Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
  • G05F3/02—Regulating voltage or current
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/16—Constructional details or arrangements
  • G06F1/20—Cooling means
  • G06F1/206—Cooling means comprising thermal management
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• the disclosure relates to thermal management for power management integrated circuits (PMIC's).
• PMIC power management integrated circuits
• PMIC Power management integrated circuits
• a PMIC may process the raw voltage from a power supply, such as a battery, and in turn supply regulated voltages to drive a plurality of off-chip power consumption entities separate from the PMIC.
• Modern PMIC's are becoming increasingly integrated due to greater system complexity.
• a typical PMIC may include many high-power on-chip modules for driving off-chip power consumption entities, such as switched-mode battery chargers (SMBC's), back light display drivers (WLED's), buck regulators, audio amplifiers, and flash LED drivers.
• SMBC's switched-mode battery chargers
• WLED's back light display drivers
• buck regulators audio amplifiers
• flash LED drivers flash LED drivers
• concurrent use scenarios for the power consumption entities may rapidly drive up the power dissipation of the PMIC, and in turn cause the temperature of the chip to exceed the thermal limits (e.g., 150° C) of the silicon and the package.
• thermal limits e.g. 150° C
• maximum power dissipation can be up to 8 Watts if all power consumption entities operate concurrently.
• the maximum allowable power dissipation on the die may be closer to 2 Watts, assuming a typical package theta-JA and up to 85° C ambient temperature.
• prior art techniques may call for monitoring and software control of the PMIC by a separate entity, e.g., a separate microprocessor coupled to the PMIC through the external pins of the PMIC. It will be appreciated that this approach to thermal management of the PMIC may cause significant latency, as a microprocessor would need to communicate with the PMIC over an interface, and such latency could undesirably result in thermal shutdown of the PMIC for certain concurrent use cases.
• prior art techniques may include performing coarse temperature monitoring and module control on the PMIC itself. However, such coarse techniques may not provide the flexibility and control of more sophisticated algorithms that may be implemented using a separate microprocessor.
• An aspect of the present disclosure provides an apparatus comprising: a plurality of modules, each module configured to process power to or from a corresponding off- chip power entity; a temperature sensor configured to sense a temperature of an integrated circuit on which the plurality of modules is provided; a thermal controller configured to adjust a maximum power processed by each of said plurality of modules in response to the sensed temperature; wherein the thermal controller and the plurality of modules are provided on a single integrated circuit.
• Another aspect of the present disclosure provides a method comprising: sensing a temperature of a power management integrated circuit (PMIC) on which a plurality of modules is provided, each module module configured to process power to or from a corresponding power entity off-chip from the PMIC; adjusting a maximum power delivered by each of said plurality of modules in response to the sensed temperature, wherein the adjusting is performed by a thermal controller provided on the PMIC.
• PMIC power management integrated circuit
• Yet another aspect of the present disclosure provides an apparatus comprising: means for processing power to or from at least one corresponding off-chip power entity; means for sensing a temperature of an integrated circuit on which the means for processing power is provided; means for adjusting a power processed by each of said plurality of modules in response to the sensed temperature, wherein the means for adjusting and the means for processing power are provided on a single integrated circuit.
• Yet another aspect of the present disclosure provides a computer program product storing code for causing a computer to manage the temperature of an integrated circuit, the code comprising: code for causing a computer to assign priorities to a plurality of modules processing power to or from at least one corresponding off-chip power entity; code for causing a computer to determine the temperature of an integrated circuit on which the plurality of modules is provided; and code for causing a computer to adjust a power processed by each of said plurality of modules in response to the determined temperature; wherein the code for causing the computer to adjust the power is provided in a memory integrated on a single chip with the code for causing a computer to assign priorities.
• FIG 1 illustrates an example of a baseline system utilizing a power management integrated circuit (PMIC).
• PMIC power management integrated circuit
• FIG 2 illustrates a temperature profile of the PMIC, in which the PMIC may coarsely manage the modules on the PMIC to self -protect the PMIC from over-heating.
• FIG 3 illustrates an exemplary embodiment of a PMIC according to the present disclosure.
• FIG 4 illustrates an exemplary embodiment of a thermal controller according to the present disclosure.
• FIG 5 illustrates an exemplary instance of operations performed by the thermal sequencer upon activation.
• FIG 6 illustrates an exemplary temperature profile of the PMIC resulting from thermal management by the autonomous controller described herein.
• FIG 1 illustrates an example of a baseline system 100 utilizing a power management integrated circuit (PMIC) 101.
• PMIC power management integrated circuit
• FIG 1 is shown for illustrative purposes only, and is not meant to limit the scope of the present disclosure only to systems or entities explicitly shown in FIG 1.
• the system 100 may be any electrical system containing entities whose power is managed or processed by modules on the PMIC. These may include, e.g., a power supply entity from which the PMIC receives power, as well as off-chip power consumption entities to which the PMIC delivers power.
• a “power entity” denotes both power supply entities and power consumption entities coupled to the PMIC, while an “off-chip power entity” denotes that such power entity is not provided on the same integrated circuit as the PMIC.
• a “module” denotes a functional block of a PMIC designed to interface with a corresponding power entity coupled to the PMIC. In cases wherein a module is coupled to a power consumption entity, then the module may be configured to source current to the power consumption entity.
• a PMIC 101 includes a supply processing module 116 coupled to a battery 136, which supplies a raw voltage to the PMIC 101.
• the PMIC 101 may also receive power from other power sources (not shown), including, e.g., an external charger, an adapter, etc. Using the raw voltage received from the battery 136 or other power source, the PMIC 101 may generate regulated and controlled voltages for powering various power consumption entities off-chip from the PMIC 101.
• the PMIC 101 may also monitor the voltages provided to the power consumption entities, and may vary the supplied voltages over time depending on, e.g., acceptable operating limits, thermal conditions, etc.
• Power consumption entities illustrated in FIG 1 include a microprocessor 150,
• LED's 134 an audio output unit 138, and other power consumption entities 140 not explicitly enumerated herein.
• One of ordinary skill in the art will appreciate that the techniques of the present disclosure may be readily applied to entities not explicitly shown in FIG 1 or mentioned herein, including, e.g., other user interface entities, digital signal processors, modem circuitry, etc.
• LED's 134 are coupled to on-chip LED drivers 114 in
• the LED's 134 may include, e.g., back light displays utilizing white LED's, flash LED's, etc.
• the PMIC 101 further includes an audio driver 118 coupled to control the audio signal power delivered to the audio output unit 138.
• the audio output unit 138 may include, e.g., speakers, stereo or mono headphones, etc.
• the PMIC 101 may further include voltage regulators 120 coupled to other power consumption entities 140 requiring supply voltages.
• a microprocessor 150 Further coupled to the PMIC 101 is a microprocessor 150.
• the microprocessor 150 Further coupled to the PMIC 101 is a microprocessor 150.
• the microprocessor 150 Further coupled to the PMIC 101 is a microprocessor 150.
• the microprocessor 150 Further coupled to the PMIC 101 is a microprocessor 150.
• the microprocessor 150 Further coupled to the PMIC 101 is a microprocessor 150.
• the microprocessor 150 Further coupled to the PMIC 101 is a microprocessor 150.
• the microprocessor 150 Further
• the module 112 on the PMIC 101 may be configured to communicate with the microprocessor 150 using a serial bus interface (SBI).
• SBI serial bus interface
• the microprocessor 150 may communicate with the PMIC 101 to manage, in real time, current supplied to the various power entities coupled to the PMIC 101.
• the module 112 may further supply power to the microprocessor 150.
• temperature sensors 110 are provided on the PMIC 101 to monitor the junction temperature on the die.
• the temperature sensors 110 are further configured to report the measurements via the microprocessor interface 112 to the microprocessor 150.
• the microprocessor 150 may manage the various modules on the PMIC 101 over the interface 132 in real time, in response to the measurements made by the temperature sensors 110, to ensure that the junction temperature on the PMIC 101 does not exceed operating limits.
• certain power management devices may include on-chip temperature sensors, and may include self-protection circuitry to coarsely monitor and shut down modules when certain temperature thresholds are exceeded.
• FIG 2 illustrates a temperature profile of the PMIC in which the PMIC 101 coarsely manages in real time the modules on the PMIC 101 to self -protect the device.
• an exemplary profile 201 is illustrated depicting a hypothetical variation of the measured temperature versus time.
• the different stages represent exemplary temperature regimes, in which the PMIC 101 may take different actions to manage the die junction temperature. Note the enumeration of various stages and temperature limits in FIG 2 are shown for illustrative purposes only, and are not meant to limit the scope of the present disclosure.
• Stage 0 may correspond to a normal operating temperature range for the
• Stage 1 may correspond to a condition wherein the junction temperature is elevated, e.g., between Tl and T2.
• Stage 2 may correspond to a temperature range, e.g., between T2 and T3, PMIC 101 may begin to automatically shut off modules for supplying power to certain user interface (UI) power consumption entities, as such user interface entities may typically consume the most power.
• UI user interface
• the LED drivers 114 and the audio driver 118 on the PMIC 101 may be instructed to shut off power to the LED's 134 and the audio output 138, respectively, to prevent the junction temperature from further increasing.
• Other exemplary user interface modules may include back light, Class D amplifiers, and a vibrator motor driver.
• automatic hardware control on the PMIC 101 may be programmed to completely shut down high-power user interface modules when the junction temperature exceeds the minimum Stage 2 threshold.
• Stage 3 may correspond to a temperature range, e.g., between T2 and T3, wherein the PMIC 101 is instructed to fully shut down.
• the temperature sensors 110 may provide an indication of the detected temperature range, e.g., an independent signal indicating the detection of Stage 2 temperatures, etc.
• the temperature sensors 110 may provide a simple temperature reading, and the microprocessor 150 or PMIC 101 may use the temperature reading to determine the corresponding temperature stage.
• the temperature of the PMIC 101 may cool down from Stage 3 back to Stage 0.
• the PMIC 101 may be allowed to resume normal operation. Note if the PMIC 101 shuts down in Stage 3, then it may shut down all the regulated supply voltages used by the PMIC 101 and other chips, including the microprocessor 150.
• a power-on trigger such as a power button press may be utilized.
• the microprocessor 150 may be provided with software instructing the PMIC 101 to adjust the module current settings in response to the detected junction temperatures. Thermal management of the PMIC 101 would thus require close monitoring and software interaction with the microprocessor 150. However, implementing the thermal management features in software generally results in greater latency, as the measured temperature and microprocessor instructions to the PMIC 101 must be communicated back and forth over the interface 132. Furthermore, in certain scenarios wherein the microprocessor 150 is "locked up" due to, e.g., software malfunction, or otherwise has a slow response time, the junction temperature of the PMIC 101 may inadvertently be allowed to rise beyond the acceptable level.
• an autonomous thermal controller directly integrated with the PMIC.
• Such an autonomous thermal controller may be provided with diverse functionality, and may directly manage power modules on the PMIC based on the measured junction temperature, thereby reducing the latency associated with communicating thermal management data and instructions with a separate off-chip microprocessor.
• FIG 3 illustrates an exemplary embodiment of a PMIC 301 according to the present disclosure.
• a thermal controller 320 is integrated with the PMIC 301, i.e., provided on the same integrated circuit die as the rest of the PMIC 301.
• the thermal controller 320 may also be denoted herein as an "autonomous" thermal controller, as it is integrated with the PMIC 301 and therefore does not require real-time control by an off- chip entity such as the microprocessor 150 of FIG 1.
• the thermal controller 320 receives measurements of the junction temperature of the PMIC 301 from temperature sensors 310.
• the thermal controller 320 may exert fine control over the various modules 330.1 through 330.N on the PMIC 301, to process the power delivered by a power source to the PMIC 101, as well as the power delivered to the various off-chip power consumption entities by the PMIC 301.
• the functionality of the thermal controller 320 may be executed by, e.g., an embedded microcontroller (not shown in FIG 3) of the PMIC 301.
• the embedded microcontroller may be native to the PMIC 301, and software for implementing the functionality of the autonomous thermal controller may be stored on non-volatile memory accessible to the embedded microcontroller.
• the embedded microcontroller may be provided with a limited instruction set that can, e.g., execute a series of reads and writes to different registers within the PMIC as part of a predefined sequence that can be stored in one-time- programmable (OTP), non- volatile memory on the PMIC.
• OTP one-time- programmable
• the microcontroller may also function as a programmable boot sequencer (PBS), which may be designed to allow the device to be programmed to perform different operations in sequence during power-up (e.g., turning on regulators in a predefined order, or doing SBI register writes to pre-configure the PMIC without direction from the microprocessor upon boot up, etc.).
• PBS programmable boot sequencer
• FIG 4 illustrates an exemplary embodiment 320.1 of a thermal controller 320 according to the present disclosure. Note the exemplary embodiment 320.1 is shown for illustrative purposes only, and is not meant to limit the scope of the present disclosure to autonomous thermal controllers necessarily having the specific functionality disclosed in FIG 4.
• the junction temperature may exceed a first predetermined temperature threshold.
• a thermal sequencer 450 within the thermal controller 320.1 may be activated when the temperature exceeds the first threshold.
• the thermal sequencer 450 or “sequencer” (as distinguished herein from “programmable boot sequencer”), may sequentially scale down currents processed by the plurality of modules in response to the temperature exceeding the predetermined threshold.
• a programmable priority assignment may determine the order in which current reduction is performed across the modules. For example, current received or sourced by a first higher-priority module may be reduced prior to current received or sourced by a second lower-priority module being reduced, etc.
• the term "high-priority" may denote that a module's current should be reduced first in sequence, prior to reducing other "lower- priority" modules' currents.
• the thermal controller may include a plurality of thermal priority registers 410.1 through 410. N. Each priority register stores a programmable priority value assigned to a corresponding module.
• the thermal controller may be programmed to specify the order according to which the modules' currents are to be reduced. For example, modules corresponding to the highest power consumption entities, such as a switched-mode battery charger (SMBC), may be assigned a highest priority using the thermal priority registers, and conversely, modules corresponding to entities causing lower power dissipation, such as the flash LED, WLED, and audio amplifier, may be assigned successively lower priorities.
• the priority assignments are programmable so that they can be set, e.g., using software from a microprocessor 150, based on user requirements. Alternatively, they may be hard-coded into NV memory.
• the thermal controller may also include a bank of minimum scaling factor (SF) registers 420.1 through 420.N.
• each SF register may be programmed with a minimum scaling factor (minSF) corresponding to each module.
• the SF registers may set the minimum current that the sequencer will reduce each module to during a thermal event before moving on to reducing the current scaling factor of the next priority module.
• the minimum scaling factor for charging current to the battery provided by the SMBC module could be set to scale a full 2- Amp default current down to no less than 500 mA, after which the thermal controller 320.1 should proceed to reduce the current sourced by the next lower priority module, as specified by the thermal priority registers 410.
• the sequencer may stop reducing the module currents, and latch in the appropriate current scaling factors to registers (not shown) in the thermal controller.
• the current scaling factor may be a measure of the maximum amount of current that is processed by (e.g., received from or sourced by) a module on the PMIC corresponding to an off-chip power entity. It is contemplated that the techniques of the present disclosure are also applicable to controlling power consumption parameters other than the current scaling factor of each module.
• any or all of the entities' average current consumption, average power consumption, peak-to- average power consumption, amplifier gain (in the case of the audio amplifier), switching frequency of a regulator in a module may be monitored, adjusted, and/or controlled according to the techniques of the present disclosure.
• FIG 5 illustrates an exemplary instance of operations that may be performed by the thermal sequencer upon activation. Note FIG 5 is shown for illustrative purposes only, and is not meant to limit the scope of the present disclosure to any particular thermal sequencer scheme shown. Modifications to the scheme shown in FIG 5 may readily be made by one of ordinary skill in the art in light of the principles disclosed herein, and such alternative exemplary embodiments are contemplated to be within the scope of the present disclosure.
• all stored scaling factor (SF) values may be set according to predetermined default values, e.g., values corresponding to full-scale current for all power entities.
• the thermal sequencer is activated, and it is checked whether the temperature T is less than TRES, at block 504. If yes, then it may be determined that the thermal sequencer need not be activated, and thus operation returns to block 501. If no, then operation proceeds to block 505.
• TRES then all the latched SF values may be restored to their original default values. In this manner, if the device temperature returns to the ambient temperature, or to any temperature significantly below a TO threshold by, e.g., 10° or 20° C, the modules can be automatically returned to their full performance capabilities. The thermal controller would then be disabled along with the reset until, e.g., another thermal event pushes the die junction temperature above Tl again. In an exemplary embodiment, TRES may be less than TO.
• the current scaling factor for a first module SF(1) may be decremented by a step size.
• the step size may be predetermined and set to a fixed value, or the step size may be programmable via software control.
• the thermal sequencer may continue to block 512. If no, the sequencer may continue to block 510. It will be appreciated that the threshold TO may be chosen to correspond to the upper range of a normal operating temperature range, wherein if T ⁇ TO, then no further current scaling factor reduction needs to be performed. Therefore, if T ⁇ TO, then at block 512, the thermal sequencer latches in the existing current scaling factor values, e.g., to a plurality of registers in the thermal controller for subsequent use.
• SF(1) is greater than or equal to a minimum scaling factor for the first module minSF(l). If yes, the sequencer returns to block 506. If no, the sequencer proceeds to processing for the next module, e.g., module 2 (the processing of which is not explicitly shown in FIG 5). It will be appreciated the minimum scaling factor for a given module may be chosen to correspond to the minimum level to which the current scaling factor may be reduced.
• the sequencer will not reduce SF(1) any further at that time, and will instead move on to reducing the current scaling factor for a next module (e.g., cycling through SF(n), wherein n is an index from 1 to N denoting all the modules of the PMIC) if the temperature remains elevated.
• a next module e.g., cycling through SF(n), wherein n is an index from 1 to N denoting all the modules of the PMIC
• the ordering of the modules 1 to N may be as prescribed by the registers 410.1 through 410.N as described with reference to FIG 4.
• processing for all modules n from 1 to N may proceed analogously to what is described with reference to module 1, e.g., analogous blocks to blocks 504 through 510 for module 1 may be provided for all modules n from 1 to N.
• FIG 5 the processing for modules 2 through N-l is not illustrated for simplicity, and is instead represented by ellipses between blocks 510 and 514, as well as ellipses between blocks 522 and 504.
• module-specific parameters may be provided for all module-specific processing blocks, e.g., each module may have a different associated scaling factor SF(n) as well as a different minimum scaling factor minSF(n). In an exemplary embodiment, these values may be set by programming the registers 410 and 420 as earlier described hereinabove with reference to FIG 4.
• Blocks 514 through 520 represent the processing for module N, corresponding to the lowest-priority module, e.g., as specified using priority registers 410.1 through 410.N in FIG 4.
• T is greater than a threshold temperature T2 greater than Tl. If no, then the sequencer continues checking. If yes, then the sequencer proceeds to block 540, at which a self-protection scheme may be applied wherein modules of the PMIC are selectively shut down. It will be appreciated that the temperature T being greater than T2 may indicate that the temperature is increasing despite the actions taken by the thermal controller to reduce the module current scaling factors, in which case the self-protection scheme may need to be undertaken.
• T is greater than a threshold temperature T3 greater than T2. If no, then the sequencer continues checking. If yes, then the entire PMIC may be shut down at block 560. Note if the entire PMIC is shut down by the thermal controller for self-protection, it may need to receive a power-on trigger, e.g., from a power button or charger insertion, to be re-activated.
• a power-on trigger e.g., from a power button or charger insertion
• thermal sequencer schemes for reducing the PMIC temperature other than that shown in FIG 5.
• alternative exemplary embodiments of thermal sequencers may or may not incorporate hysteresis, and/or alternative module prioritization schemes (e.g., wherein the scaling factors for all modules are simultaneously reduced in lockstep, with each module having a different step size), fewer or more temperature thresholds than shown, etc.
• various temperature checks not explicitly shown in FIG 5 may be performed in alternative exemplary embodiments.
• the temperature check at block 504 need not be performed.
• Such alternative exemplary embodiments are contemplated to be within the scope of the present disclosure.
• FIG 6 illustrates an exemplary temperature profile of the PMIC resulting from thermal management by the autonomous controller 320.1.
• the temperature variables TO, Tl, etc. need not correspond to the same variables as described earlier herein with reference to FIG 2.
• an exemplary profile 601 is illustrated depicting a hypothetical variation of PMIC temperature versus time. From time tO to tl, the measured temperature is seen to increase from TO to Tl. At time tl, when the measured temperature exceeds the first threshold Tl, the thermal sequencer is activated. In an exemplary embodiment, the thermal sequencer may perform operations as described hereinabove with reference to FIG 5.
• the rate of temperature change is seen to decrease between times tl to t3 due to actions performed by the thermal sequencer, e.g., as described hereinabove with reference to FIG 5.
• the temperature is seen to return to below Tl, while at time t3, the temperature returns to below TO.
• the temperature reduction schemes applied by the thermal sequencer may incorporate hysteresis, e.g., current scaling factors of modules may be reduced once the temperature exceeds Tl, and may continue to be reduced as long as the temperature remains above TO which is lower than Tl.
• DSP Digital Signal Processor
• ASIC Application Specific Integrated Circuit
• FPGA Field Programmable Gate Array
• a general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
• a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
• a software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
• An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
• the storage medium may be integral to the processor.
• the processor and the storage medium may reside in an ASIC.
• the ASIC may reside in a user terminal.
• the processor and the storage medium may reside as discrete components in a user terminal.
• the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
• Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
• a storage media may be any available media that can be accessed by a computer.
• such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
• any connection is properly termed a computer-readable medium.
• the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
• the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.
• Disk and disc includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• Human Computer Interaction (AREA)
• Electromagnetism (AREA)
• Radar, Positioning & Navigation (AREA)
• Automation & Control Theory (AREA)
• Semiconductor Integrated Circuits (AREA)
• Power Sources (AREA)
• Control Of El Displays (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=48948537

Family Applications (1)

Country Status (5)

Cited By (1)

Families Citing this family (49)

Citations (3)

Family Cites Families (12)

• 2012
  • 2012-07-26 US US13/559,030 patent/US9285818B2/en active Active
• 2013
  • 2013-07-26 CN CN202111004461.2A patent/CN113703555B/zh active Active
  • 2013-07-26 JP JP2015524492A patent/JP5973074B2/ja not_active Expired - Fee Related
  • 2013-07-26 EP EP13745974.9A patent/EP2877907B1/en active Active
  • 2013-07-26 WO PCT/US2013/052413 patent/WO2014018941A1/en not_active Ceased
  • 2013-07-26 CN CN201380039339.6A patent/CN104487911A/zh active Pending

Patent Citations (3)

Also Published As

Similar Documents

Legal Events