WO2014015603A1 - Sensor and method for manufacturing same - Google Patents

Sensor and method for manufacturing same Download PDF

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Publication number
WO2014015603A1
WO2014015603A1 PCT/CN2012/085689 CN2012085689W WO2014015603A1 WO 2014015603 A1 WO2014015603 A1 WO 2014015603A1 CN 2012085689 W CN2012085689 W CN 2012085689W WO 2014015603 A1 WO2014015603 A1 WO 2014015603A1
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WIPO (PCT)
Prior art keywords
pattern
electrode
layer
photodiode
bias
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PCT/CN2012/085689
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French (fr)
Chinese (zh)
Inventor
徐少颖
谢振宇
陈旭
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北京京东方光电科技有限公司
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Publication of WO2014015603A1 publication Critical patent/WO2014015603A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14603Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate to a sensor and a method of fabricating the same. Background technique
  • CT computed tomography
  • the sensor 12 includes a plurality of scan lines 15, a plurality of data lines 16, and a plurality of sensing units, each of which includes a photodiode 13 and a field effect transistor ( Field Effect Transistor (FET) 14, the gate of the field effect transistor 14 is connected to a corresponding scan line 15 in the sensor 12, the drain of the field effect transistor 14 and the corresponding data line in the sensor 12 (Data Line) 16
  • FET Field Effect Transistor
  • the photodiode 13 is connected to the source of the field effect transistor 14.
  • One end of these data lines 16 is connected to the data readout circuit 18 via a connection pin 17.
  • the above sensor operates on the principle that the sensor 12 applies a drive scan signal through the scan line 15 to control the switching state of the field effect transistor 14 of each sense unit.
  • the photocurrent signal generated by the photodiode 13 is sequentially output through the data line 16 connected to the field effect transistor 14 and the data readout circuit 18, by controlling the timing of the signal on the scan line 15 and the data line 16.
  • the collecting function of the photocurrent signal is realized, that is, the control effect of the photocurrent signal generation generated by the photodiode 13 is realized by controlling the switching state of the FET 14.
  • the senor usually adopts a thin film transistor (TFT) flat plate structure, and the sensor may have multiple layers in a cross section.
  • each sensing unit includes: a substrate, a gate layer, a gate insulating layer, Active layer, source and drain layers, passivation layer, PIN junction and transparent electrode window layer of PIN photosensor, and bias line layer and light barrier layer.
  • TFT thin film transistor
  • each sensing unit includes: a substrate, a gate layer, a gate insulating layer, Active layer, source and drain layers, passivation layer, PIN junction and transparent electrode window layer of PIN photosensor, and bias line layer and light barrier layer.
  • the specific layers on the cross-section are not exactly the same due to the difference in specific structures.
  • Each layer of the sensor is typically formed by a patterning process, and each patterning process typically includes steps such as masking, exposure, development, etching, and stripping. That is, in order to achieve multiple sensors Layers require multiple patterning processes.
  • the above-mentioned sensor having a plurality of layers usually requires 9 to 11 patterning processes at the time of manufacture, so that 9 to 11 mask masks are required correspondingly, thereby making the manufacturing cost of the sensor high, and the manufacturing process is relatively high. Complex, and the production capacity is difficult to upgrade. Summary of the invention
  • a sensor comprising: a substrate substrate, a set of gate lines and a set of data lines arranged in a cross, an array defined by the set of gate lines and a set of data lines a plurality of sensing units arranged in a row, and a set of bias lines extending through each of the sensing units, each sensing unit comprising at least one sensing subunit composed of a thin film transistor device and a photodiode sensing device, wherein
  • the thin film transistor device includes: a gate electrode over the substrate substrate and connected to an adjacent gate line; a gate insulating layer over the gate and covering the substrate substrate; An active layer above the gate insulating layer, above the gate; an ohmic layer over the active layer; a source and a drain over the ohmic layer and oppositely forming a channel, The drain is connected to an adjacent data line;
  • the photodiode sensor device includes: a receiving electrode connected to the source, a photodiode over the receiving electrode, a transparent electrode over the photodiode, and a bias on the transparent electrode a pressure electrode, the bias electrode being connected to an adjacent bias line.
  • a method of manufacturing a sensor comprising: forming a pattern of a gate line, a pattern of a gate connected to the gate line by a patterning process on a substrate;
  • a gate insulating layer covering the base substrate, and forming a pattern of an active layer above the gate, a pattern of an ohmic layer over the active layer, located at a location by a first patterning process a pattern of a source and a drain formed above the ohmic layer and oppositely formed, a pattern of a data line connected to the drain, a pattern of a receiving electrode connected to the source, and a receiving electrode a pattern of the photodiode above, a pattern of transparent electrodes on the photodiode; a pattern of the first passivation layer formed by the second patterning process, the first passivation layer not covering the bias electrode And the zone i of the bias line; and Forming a pattern of a bias electrode over the transparent electrode, a pattern of a bias line connected to the bias electrode, and a location over the source, drain, and channel by a third patterning process The pattern of the light barrier.
  • the thin film transistor device of the sensor according to the embodiment of the invention is of a bottom gate type, and the manufacturing of the sensor can be formed by using a lesser number of patterning processes. Compared with the prior art, the number of masks used is reduced, and the number of masks is reduced. Manufacturing costs simplify the production process and greatly increase the equipment capacity and product yield.
  • FIG. 1 is a schematic perspective view of a conventional sensor
  • FIG. 2 is a top plan view of one of the sensing units of the sensor according to the embodiment of the present invention.
  • FIG. 3 is a top plan view of a plurality of sensing units arranged in an array of sensors according to an embodiment of the present invention
  • FIG. 4 is a cross-sectional view of the sensing unit along the line A-A of FIG. 2 after the first patterning process according to an embodiment of the present invention
  • FIG. 5 is a cross-sectional view of the sensing unit along line B-B of FIG. 2 after the first patterning process according to an embodiment of the present invention
  • FIG. 6 is a cross-sectional view of the sensing unit along the line A-A of FIG. 2 after the second patterning process according to an embodiment of the present invention
  • FIG. 7 is a cross-sectional view of the sensing unit along line B-B of FIG. 2 after the second patterning process according to an embodiment of the present invention
  • FIG. 8 is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along line A-A of FIG. 2 after the third patterning process;
  • FIG. 9 is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along the line B-B of FIG. 2 after the third patterning process;
  • 10 is a cross-sectional view of the sensing unit along line AA of FIG. 2 after the fourth patterning process according to an embodiment of the present invention
  • 11 is a cross-sectional view of the sensing unit along line BB of FIG. 2 after the fourth patterning process according to an embodiment of the present invention
  • FIG. 12 is a cross-sectional view of the sensing unit taken along line A-A of FIG. 2 after the fifth patterning process according to an embodiment of the present invention
  • Figure 13 is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along the line B-B of Figure 2 after the fifth patterning process.
  • the senor may be an X-ray sensor or other type of sensor, such as a sensor that transmits by photoelectric conversion.
  • a sensor that transmits by photoelectric conversion may be formed identically.
  • the embodiment of the present invention provides a sensor and a manufacturing method thereof.
  • the sensor includes: a substrate substrate 32, a set of gate lines 30 and a set of data lines 31 arranged in a cross, a set of gate lines 30 and a set of data a plurality of sensing units arranged in an array defined by line 31, and a set of bias lines 42b extending through each of the sensing units, each sensing unit comprising at least one of a thin film transistor device and a photodiode sensor device Sensing subunit, wherein
  • the thin film transistor device includes: a gate electrode 38 over the substrate substrate 32 and connected to the adjacent gate line 30; a gate insulating layer 37 over the gate electrode 38 and covering the substrate; and the gate insulating layer 37 Above, an active layer 36 over the gate 38; an ohmic layer 35 over the active layer 36; a source 33 and a drain 34 overlying the ohmic layer 35 and oppositely forming a channel, the drain The pole 34 is connected to the adjacent data line 31;
  • the photodiode sensor device includes: a receiving electrode 39 connected to the source 33, a photodiode 40 above the receiving electrode 39, a transparent electrode 41 above the photodiode 40, and a bias voltage over the transparent electrode 41.
  • the electrode 42a, the bias electrode 42a is connected to an adjacent bias line 42b.
  • the base substrate 32 may be a substrate of a glass substrate, a plastic substrate or other materials; the gate line 30, the gate 38, the data line 31, the source 33, the drain 34, and the receiving electrode. 39.
  • the bias electrode 42a, the bias line 42b and the light blocking strip 52 (the function of which is to reduce the influence of light on the channel) can be made of the same material, such as aluminum-niobium alloy (AlNd), aluminum (A1).
  • a single layer film of copper (Cu), molybdenum (Mo), molybdenum-tungsten alloy (MoW) or chromium (Cr) may be a composite film composed of any combination of these metal elements or alloy materials.
  • the thickness of these single or composite films is, for example, between 150 nm and 450 nm.
  • the material of the ohmic layer 35 may be a doped semiconductor (n+a-Si); the material of the active layer 36 may be a semiconductor material, such as amorphous silicon (a-Si), and the thickness is, for example,
  • the material of the gate insulating layer 37 may be silicon nitride, and the thickness is, for example, between 300 nm and 500 nm; the material of the transparent electrode 41 may be, for example, indium tin oxide (ITO) or indium oxide. Transparent conductive material such as (IZO).
  • the photodiode may be a PIN type photodiode, including: an N-type semiconductor (n+a-Si) 40a located above the receiving electrode 39, and an I-type semiconductor located above the N-type semiconductor 40a ( a-Si) 40b, and a P-type semiconductor (p+a-Si) 40c over the I-type semiconductor 40b.
  • the PIN type photodiode works by the photovoltaic principle and has the advantages of small junction capacitance, short transit time, and high sensitivity.
  • photodiodes may also utilize other types of photodiodes such as MIS type photodiodes.
  • the senor may further include: under each of the data lines 31 and the receiving electrodes 39 of each of the photodiode sensing devices, sequentially located in the gate insulating layer An active material layer 55 and an ohmic material layer 56 above 37;
  • the senor may further include:
  • first passivation layer 43 over the transparent electrode material layer 54 and the transparent electrode 41.
  • the first passivation layer 43 does not cover the bias electrode 42a and the bias line 42b;
  • a light blocking strip located above the first passivation layer 43 and located above the source 33, the drain 34 and the channel
  • FIG. 12 and FIG. 13 are cross-sectional structures of one sensing unit, and thus are located on the substrate The surrounding signal guiding area vias are not shown in the figure).
  • the materials of the data line 31, the source 33, the drain 34, and the receiving electrode 39 are preferably the same.
  • the materials of the light blocking strip 52, the bias electrode 42a, and the bias line 42b are preferably the same.
  • the photodiode material layer 53, the transparent electrode material layer 54, the active material layer 55, and the ohmic material layer 56 are respectively connected to the photodiode 40, the transparent electrode 41, the active layer 36, and the ohmic layer 35.
  • the materials are the same.
  • the purpose of this structural design is to reduce the number of patterning processes, and the photodiode material layer 53, the transparent electrode material layer 54, the active material layer 55, and the ohmic material layer 56 do not play a practical role in the sensor.
  • the first passivation layer 43 (and the second passivation layer 57 hereinafter) may be an inorganic insulating film (for example, silicon nitride or the like) or an organic insulating film (for example, a photosensitive resin material or a non-photosensitive resin material, etc.), for example, in thickness Between 150 nm and 1500 nm.
  • an inorganic insulating film for example, silicon nitride or the like
  • an organic insulating film for example, a photosensitive resin material or a non-photosensitive resin material, etc.
  • the set of gate lines 30 includes two single gate lines 30a, and a plurality of sets of double gate lines 30b between the two single gate lines 30a (adjacent two double gate lines 30b constitute A group) .
  • Each of the sensing units includes two sensing subunits, each of which includes a thin film transistor device 50 and a photodiode device 51.
  • the thin film transistor devices 50 of the two sensing subunits are diagonally distributed, and the gate of the thin film transistor device 50 is connected to an adjacent one of the single gate lines 30a or the adjacent double gate lines 30b.
  • both the gate line and the data line are arranged in a single line, and there is only one sensing unit in a region defined by two adjacent gate lines and two adjacent ones, and the sensing unit includes a thin film transistor
  • the device and a photodiode sensor device comprise only one sensing subunit. Therefore, compared with the conventional sensor, the arrangement of the double gate lines in the embodiment of the present invention doubles the total number of gate lines, but the number of data lines is reduced to half, and the cost of the gate line driving equipment is lower than the data. The cost of the line drive device, therefore, the use of this structure can further reduce the cost of the sensor.
  • the bias line 42b is located between two sensing subunits of the sensing unit, and is connected to the bias electrodes 42a of the two sensing subunits.
  • Cross-shaped which improves the uniformity of the voltage between the bias electrode and the transparent electrode compared to the conventional "in-line” bias line.
  • the thin film transistor device of the sensor is a bottom gate type, and the manufacturing of the sensor can be formed by using a five-time patterning process. Compared with the prior art, the number of masks used in the manufacturing process can be reduced, and the number of masks is reduced. Manufacturing costs simplify the production process and greatly increase the equipment capacity and product yield.
  • a method of manufacturing the above sensor comprising:
  • Step 101 A pattern of the gate line 30 and a pattern of the gate electrode 38 connected to the gate line 30 are formed on the base substrate 32 by one patterning process.
  • Figure 4 and Figure 5 for the cross-sectional structure after the first patterning process.
  • 3 and 4 are cross-sectional views of the base substrate after the first patterning process.
  • 2 and 12 and FIG. 12 are a plan view and a cross-sectional view, respectively, of the sensing unit obtained after five passes of the process. Therefore, the base substrate in FIGS. 3 and 4 is only cut along the direction of AA, line and BB shown in FIG. 2, which does not represent a cross-sectional view of the base substrate of FIG. 2.
  • FIGS. 5 to 11 are also shown in the same manner.
  • the one-time patterning process includes steps of substrate cleaning, film formation, photoresist coating, exposure, development, etching, photoresist removal, and the like.
  • Substrate cleaning includes cleaning with deionized water, organic cleaning solution, and the like.
  • the film forming process is used to form a structural layer to be patterned. For example, for a metal layer, a film is formed by physical vapor deposition (for example, magnetron sputtering), and a pattern is formed by wet etching.
  • a non-metal layer a film is formed by chemical vapor deposition, and dried. Etching forms a pattern.
  • the composition process in the following steps is the same as this, and will not be described again.
  • Step 102 forming a gate insulating layer 37 covering the substrate, and forming a pattern of the active layer 36 over the gate electrode 38, a pattern of the ohmic layer 35 over the active layer 36, in the ohmic layer 35 by one patterning process.
  • the pattern of the source 33 and the drain 34 forming the channel, the pattern of the data line 31 connected to the drain 34, the pattern of the receiving electrode 39 connected to the source 33, and the receiving electrode 39 are formed on the upper side.
  • the pattern of the photodiode 40, the pattern of the transparent electrode 41 above the photodiode 40 Please refer to Figure 6 and Figure 7 for the cross-sectional structure after the second patterning process;
  • the active layer is formed by one patterning process.
  • the pattern of 36, the pattern of the ohmic layer 35, the pattern of the source 33 and the drain 34, the pattern of the data line 31, the pattern of the receiving electrode 39, the pattern of the photodiode 40, and the pattern of the transparent electrode 41 include:
  • an active semiconductor layer depositing an active semiconductor layer, an ohmic semiconductor layer, a data line material layer, an N-type semiconductor layer, an I-type semiconductor layer, a P-type semiconductor layer, and a transparent conductive material layer;
  • the substrate Exposing the substrate with a mask having a fully transparent region, a semi-transmissive region, and an opaque region, wherein the opaque region correspondingly forms the receiving electrode 39, the PIN photodiode, the transparent electrode 41, the data line 31, and the drain a region of the pole 34 and the source 33, the semi-transmissive region corresponding to the region forming the channel;
  • the mask used in this step may be a gray tone mask or a halftone mask;
  • the substrate is etched and photoresist stripped to form a pattern of the ohmic layer 35 and a pattern of the drain 34 and the source 33, and the source 33 and the drain 34 are opposed to each other to form a channel.
  • the pattern of the transparent electrode 41 may be formed by wet etching alone or by dry etching simultaneously with the pattern of the photodiode 40.
  • Step 103 forming a pattern of the first passivation layer 43 by one patterning process, the first passivation layer 43 not covering the region where the bias electrode 42a and the bias line 42b are formed, that is, the formation of 42a and 42b is reserved. Space. This is because the bias electrode 42a and the bias line 42b formed next need to be connected to the transparent electrode 41.
  • Step 104 forming a pattern of the bias electrode 42a over the transparent electrode 41 by one patterning process, and connecting with the bias electrode 42a The pattern of the bias line 42b, and the pattern of the light blocking strips 52 above the source 33, the drain 34 and the channel.
  • the light blocking strip 52, the bias electrode 42a, and the bias line 42b are made of the same material.
  • step 104 the method further includes:
  • Step 105 forming a pattern of the second passivation layer 57 covering the substrate by one patterning process, the second passivation layer 57 has a signal guiding area via hole, and the cross-sectional structure after the fifth patterning process is shown in FIG. 13 and 14 is shown.
  • step 105 is optional because the purpose of the present invention can be achieved without performing step 105.
  • the method for fabricating a sensor may include only steps 101-104 described above.
  • the manufacturing method of the sensor of the present invention can be fabricated by using four or five patterning processes in total, which reduces the use of the mask, reduces the manufacturing cost, simplifies the production process, and greatly improves the equipment production rate compared with the prior art. And the yield of the product.

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Abstract

A sensor and a method for manufacturing same. The sensor comprises: a plurality of sensing units arranged in an array and defined by a group of gate lines and a group of data lines; and a group of bias lines passing through each sensing unit. Each sensing unit comprises at least one sensing subunit consisting of a thin film transistor element and a photodiode sensing element. The sensor is manufactured by adopting five patterning processes. Patterns of an active layer, an ohmic layer, a source, a drain, the data lines, a receiving electrode, a photodiode and a transparent electrode are formed through one patterning process.

Description

传感器及其制造方法 技术领域  Sensor and method of manufacturing the same
本发明的实施例涉及一种传感器及其制造方法。 背景技术  Embodiments of the present invention relate to a sensor and a method of fabricating the same. Background technique
由于保健的需要, 各种无损伤医疗检测方法逐渐受到人们的青睐。 在诸 多的无损伤检测方法中, 计算机断层扫描技术( CT ) 已经得到广泛的应用。 在计算机断层扫描设备中必不可缺的一个部分就是传感器。  Due to the needs of health care, various non-invasive medical detection methods are gradually favored by people. Among the many non-invasive detection methods, computed tomography (CT) has been widely used. One of the indispensable parts of a computed tomography device is the sensor.
一种传感器的基本结构如图 1所示, 该传感器 12包括多条扫描线 15、 多条数据线 16以及多个感测单元, 每个感测单元包括一个光电二极管 13和 一个场效应晶体管 (Field Effect Transistor, FET) 14, 场效应晶体管 14的栅极 与传感器 12中相应的扫描线 (Scan Line) 15连接, 场效应晶体管 14的漏极与 传感器 12中相应的数据线 (Data Line) 16连接, 光电二极管 13与场效应晶体 管 14的源极连接。这些数据线 16的一端通过连接引脚 17连接数据读出电路 18。  A basic structure of a sensor is shown in FIG. 1. The sensor 12 includes a plurality of scan lines 15, a plurality of data lines 16, and a plurality of sensing units, each of which includes a photodiode 13 and a field effect transistor ( Field Effect Transistor (FET) 14, the gate of the field effect transistor 14 is connected to a corresponding scan line 15 in the sensor 12, the drain of the field effect transistor 14 and the corresponding data line in the sensor 12 (Data Line) 16 The photodiode 13 is connected to the source of the field effect transistor 14. One end of these data lines 16 is connected to the data readout circuit 18 via a connection pin 17.
上述传感器的工作原理为: 传感器 12通过扫描线 15施加驱动扫描信号 来控制每个感测单元的场效应晶体管 14的开关状态。 当场效应晶体管 14被 打开时, 光电二极管 13产生的光电流信号依次通过与场效应晶体管 14连接 的数据线 16、 数据读出电路 18而输出, 通过控制扫描线 15与数据线 16上 的信号时序来实现光电流信号的釆集功能,即通过控制场效应管 14的开关状 态来实现对光电二极管 13产生的光电流信号釆集的控制作用。  The above sensor operates on the principle that the sensor 12 applies a drive scan signal through the scan line 15 to control the switching state of the field effect transistor 14 of each sense unit. When the field effect transistor 14 is turned on, the photocurrent signal generated by the photodiode 13 is sequentially output through the data line 16 connected to the field effect transistor 14 and the data readout circuit 18, by controlling the timing of the signal on the scan line 15 and the data line 16. The collecting function of the photocurrent signal is realized, that is, the control effect of the photocurrent signal generation generated by the photodiode 13 is realized by controlling the switching state of the FET 14.
目前, 传感器通常釆用薄膜晶体管( Thin Film Transistor, TFT )平板结 构, 这种传感器在断面上可具有多层, 例如, 每个感测单元内包括: 基板、 栅极层、 栅极绝缘层、 有源层、 源极与漏极层、 钝化层、 PIN光电传感器的 PIN结和透明电极窗口层, 以及偏压线层和挡光条层等。 当然, 不同传感器 由于具体结构的差异, 在断面上的具体图层也不完全相同。  At present, the sensor usually adopts a thin film transistor (TFT) flat plate structure, and the sensor may have multiple layers in a cross section. For example, each sensing unit includes: a substrate, a gate layer, a gate insulating layer, Active layer, source and drain layers, passivation layer, PIN junction and transparent electrode window layer of PIN photosensor, and bias line layer and light barrier layer. Of course, the specific layers on the cross-section are not exactly the same due to the difference in specific structures.
传感器的各个图层一般通过构图工艺形成, 而每一次构图工艺通常包括 掩模、 曝光、 显影、 刻蚀和剥离等步骤。 也就是说, 为了实现传感器的多个 图层, 需要釆用多次构图工艺。 例如, 上述具有多层的传感器在制造时通常 需要釆用 9至 11次构图工艺, 这样就对应的需要 9至 11张光罩掩模板, 由 此, 使传感器的制造成本较高, 制造工艺较为复杂, 且产能较难提升。 发明内容 Each layer of the sensor is typically formed by a patterning process, and each patterning process typically includes steps such as masking, exposure, development, etching, and stripping. That is, in order to achieve multiple sensors Layers require multiple patterning processes. For example, the above-mentioned sensor having a plurality of layers usually requires 9 to 11 patterning processes at the time of manufacture, so that 9 to 11 mask masks are required correspondingly, thereby making the manufacturing cost of the sensor high, and the manufacturing process is relatively high. Complex, and the production capacity is difficult to upgrade. Summary of the invention
本发明的目的是提供一种传感器及其制造方法, 用以解决现有技术中存 在的传感器的制造成本较高, 且制造工艺较为复杂, 产能较难提升的技术问 题。 根据本发明的第一方面, 提供一种传感器, 包括: 衬底基板、 呈交叉排 列的一组栅线和一组数据线、 由所述一组栅线和一组数据线所限定的呈阵列 状排布的多个感测单元, 及贯穿每一个感测单元的一组偏压线, 每个感测单 元包括至少一个由薄膜晶体管器件和光电二极管传感器件组成的感测子单 元, 其中,  It is an object of the present invention to provide a sensor and a method of manufacturing the same, which solves the technical problem of high manufacturing cost of the sensor existing in the prior art, complicated manufacturing process, and difficulty in improving production capacity. According to a first aspect of the present invention, a sensor is provided, comprising: a substrate substrate, a set of gate lines and a set of data lines arranged in a cross, an array defined by the set of gate lines and a set of data lines a plurality of sensing units arranged in a row, and a set of bias lines extending through each of the sensing units, each sensing unit comprising at least one sensing subunit composed of a thin film transistor device and a photodiode sensing device, wherein
所述薄膜晶体管器件包括: 位于所述衬底基板之上并与相邻的栅线连接 的栅极; 位于所述栅极之上并覆盖所述衬底基板的栅极绝缘层; 位于所述栅 极绝缘层之上、 栅极上方的有源层; 位于所述有源层之上的欧姆层; 位于所 述欧姆层之上并相对而置形成沟道的源极和漏极, 所述漏极与相邻的数据线 连接;  The thin film transistor device includes: a gate electrode over the substrate substrate and connected to an adjacent gate line; a gate insulating layer over the gate and covering the substrate substrate; An active layer above the gate insulating layer, above the gate; an ohmic layer over the active layer; a source and a drain over the ohmic layer and oppositely forming a channel, The drain is connected to an adjacent data line;
所述光电二极管传感器件包括: 与所述源极连接的接收电极、 位于所述 接收电极之上的光电二极管、 位于所述光电二极管之上的透明电极, 以及位 于所述透明电极之上的偏压电极, 所述偏压电极与相邻的偏压线连接。  The photodiode sensor device includes: a receiving electrode connected to the source, a photodiode over the receiving electrode, a transparent electrode over the photodiode, and a bias on the transparent electrode a pressure electrode, the bias electrode being connected to an adjacent bias line.
根据本发明的第二方面, 提供一种传感器的制造方法, 包括: 在衬底基板上通过一次构图工艺形成栅线的图形、 与所述栅线连接的栅 极的图形;  According to a second aspect of the present invention, a method of manufacturing a sensor, comprising: forming a pattern of a gate line, a pattern of a gate connected to the gate line by a patterning process on a substrate;
形成覆盖所述衬底基板的栅极绝缘层, 并通过第一次构图工艺形成位于 所述栅极上方的有源层的图形、 位于所述有源层之上的欧姆层的图形、 位于 所述欧姆层之上并相对而置形成沟道的源极和漏极的图形、 与所述漏极连接 的数据线的图形、 与所述源极连接的接收电极的图形、 位于所述接收电极之 上的光电二极管的图形、 位于所述光电二极管之上的透明电极的图形; 通过第二次构图工艺形成第一钝化层的图形, 所述第一钝化层未覆盖形 成偏压电极和偏压线的区 i或; 以及 通过第三次构图工艺形成位于所述透明电极之上的偏压电极的图形、 与 所述偏压电极连接的偏压线的图形, 以及位于所述源极、 漏极及沟道上方的 挡光条的图形。 Forming a gate insulating layer covering the base substrate, and forming a pattern of an active layer above the gate, a pattern of an ohmic layer over the active layer, located at a location by a first patterning process a pattern of a source and a drain formed above the ohmic layer and oppositely formed, a pattern of a data line connected to the drain, a pattern of a receiving electrode connected to the source, and a receiving electrode a pattern of the photodiode above, a pattern of transparent electrodes on the photodiode; a pattern of the first passivation layer formed by the second patterning process, the first passivation layer not covering the bias electrode And the zone i of the bias line; and Forming a pattern of a bias electrode over the transparent electrode, a pattern of a bias line connected to the bias electrode, and a location over the source, drain, and channel by a third patterning process The pattern of the light barrier.
根据本发明实施例所提出的传感器的薄膜晶体管器件为底栅型, 传感器 的制造可共釆用较少次数的构图工艺制作形成, 对比于现有技术, 减少了掩 模板的使用数量, 降低了制造成本, 简化了生产工艺, 大大提升了设备产能 及产品的良品率。 附图说明  The thin film transistor device of the sensor according to the embodiment of the invention is of a bottom gate type, and the manufacturing of the sensor can be formed by using a lesser number of patterning processes. Compared with the prior art, the number of masks used is reduced, and the number of masks is reduced. Manufacturing costs simplify the production process and greatly increase the equipment capacity and product yield. DRAWINGS
为了更清楚地说明本发明实施例的技术方案, 下面将对实施例的附图作 简单地介绍,显而易见地,下面描述中的附图仅仅涉及本发明的一些实施例, 而非对本发明的限制。  In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .
图 1为现有传感器的立体结构示意图;  1 is a schematic perspective view of a conventional sensor;
图 2为本发明实施例的传感器的其中一个感测单元的俯视图;  2 is a top plan view of one of the sensing units of the sensor according to the embodiment of the present invention;
图 3 为本发明实施例的传感器的呈阵列状排布的多个感测单元的俯视 图;  3 is a top plan view of a plurality of sensing units arranged in an array of sensors according to an embodiment of the present invention;
图 4为本发明实施例的感测单元在第一次构图工艺后沿图 2的 A-A, 线 的截面视图;  4 is a cross-sectional view of the sensing unit along the line A-A of FIG. 2 after the first patterning process according to an embodiment of the present invention;
图 5为本发明实施例的感测单元在第一次构图工艺后沿图 2的 B-B, 线 的截面视图;  5 is a cross-sectional view of the sensing unit along line B-B of FIG. 2 after the first patterning process according to an embodiment of the present invention;
图 6为本发明实施例的感测单元在第二次构图工艺后沿图 2的 A-A, 线 的截面视图;  6 is a cross-sectional view of the sensing unit along the line A-A of FIG. 2 after the second patterning process according to an embodiment of the present invention;
图 7为本发明实施例的感测单元在第二次构图工艺后沿图 2的 B-B, 线 的截面视图;  7 is a cross-sectional view of the sensing unit along line B-B of FIG. 2 after the second patterning process according to an embodiment of the present invention;
图 8为本发明实施例的感测单元在第三次构图工艺后沿图 2的 A-A, 线 的截面视图;  8 is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along line A-A of FIG. 2 after the third patterning process;
图 9为本发明实施例的感测单元在第三次构图工艺后沿图 2的 B-B, 线 的截面视图;  9 is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along the line B-B of FIG. 2 after the third patterning process;
图 10为本发明实施例的感测单元在第四次构图工艺后沿图 2的 A-A, 线的截面视图; 图 11为本发明实施例的感测单元在第四次构图工艺后沿图 2的 B-B,线 的截面视图; 10 is a cross-sectional view of the sensing unit along line AA of FIG. 2 after the fourth patterning process according to an embodiment of the present invention; 11 is a cross-sectional view of the sensing unit along line BB of FIG. 2 after the fourth patterning process according to an embodiment of the present invention;
图 12为本发明实施例的感测单元在第五次构图工艺后沿图 2的 A-A, 线的截面视图; 以及  12 is a cross-sectional view of the sensing unit taken along line A-A of FIG. 2 after the fifth patterning process according to an embodiment of the present invention;
图 13为本发明实施例的感测单元在第五次构图工艺后沿图 2的 B-B,线 的截面视图。  Figure 13 is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along the line B-B of Figure 2 after the fifth patterning process.
附图标记:  Reference mark:
12-传感器 13-光电二极管 14-场效应晶体管 12-sensor 13-photodiode 14-field effect transistor
15-扫描线 16-数据线 17-连接引脚 15-scan line 16-data line 17-connect pin
18-数据读出电路 30-栅线 31-数据线  18-data readout circuit 30-gate line 31-data line
32-衬底基板 33-源极 34-漏极  32-substrate substrate 33-source 34-drain
35-欧姆层 36-有源层 37-栅极绝缘层  35-ohm layer 36-active layer 37-gate insulating layer
38-栅极 39-接收电极 40-光电二极管  38-gate 39-receiving electrode 40-photodiode
41-透明电极 42a-偏压电极 40a-N型半导体  41-transparent electrode 42a-bias electrode 40a-N type semiconductor
40b-I型半导体 40c-P型半导体 43-第一钝化层  40b-I type semiconductor 40c-P type semiconductor 43-first passivation layer
30a-单栅线 30b-双栅线 50-薄膜晶体管器件 30a-single gate line 30b-double gate line 50-thin film transistor device
42b-偏压线 52-挡光条 57-第二钝化层42b-bias line 52-light barrier 57-second passivation layer
53-光电二极管材料层 54-透明电极材料层 55-有源材料层53-photodiode material layer 54-transparent electrode material layer 55-active material layer
56-欧姆材料层 具体实施方式 56-ohm material layer
为使本发明实施例的目的、 技术方案和优点更加清楚, 下面将结合本发 明实施例的附图,对本发明实施例的技术方案进行清楚、 完整地描述。显然, 所描述的实施例是本发明的一部分实施例, 而不是全部的实施例。 基于所描 述的本发明的实施例, 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例, 都属于本发明保护的范围。  The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.
除非另作定义, 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的术语 "连接" 并非限定于物理的或者机械的连接, 而是可 以包括电性的连接, 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系, 当被描述对象的绝对位置改变后, 则该 相对位置关系也相应地改变。 Unless otherwise defined, technical terms or scientific terms used herein shall be of ordinary meaning as understood by those of ordinary skill in the art to which the invention pertains. The term "connected" as used in the specification and claims of the present invention is not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "上", "下下", "左", "Right" or the like is only used to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship is also changed accordingly.
在本发明以下实施例中, 传感器可以是 X射线传感器, 也可以是其他类 型的传感器, 例如通过光电转换进行传输的传感器。 在下面的描述和图示中 针对单个感测单元进行, 其他感测单元可以同样地形成。  In the following embodiments of the invention, the sensor may be an X-ray sensor or other type of sensor, such as a sensor that transmits by photoelectric conversion. In the following description and illustration, for a single sensing unit, other sensing units may be formed identically.
针对解决现有技术中存在的传感器的制造成本较高, 且制造工艺较为复 杂的技术问题, 本发明的实施例提供了一种传感器及其制造方法。  In order to solve the technical problem that the manufacturing cost of the sensor existing in the prior art is high and the manufacturing process is complicated, the embodiment of the present invention provides a sensor and a manufacturing method thereof.
图 2示出了根据本发明一个实施例的传感器的其中一个感测单元的俯视 图。 图 12和图 13是图 2的感测单元沿 A-A, 线和 B-B, 线的截面图。 如图 2、 图 12和图 13所示, 该传感器, 包括: 衬底基板 32、 呈交叉排列的一组 栅线 30和一组数据线 31、 由所述一组栅线 30和一组数据线 31所限定的呈 阵列状排布的多个感测单元, 及贯穿每一个感测单元的一组偏压线 42b, 每 个感测单元包括至少一个由薄膜晶体管器件和光电二极管传感器件组成的感 测子单元, 其中,  2 shows a top view of one of the sensing units of the sensor in accordance with one embodiment of the present invention. 12 and 13 are cross-sectional views of the sensing unit of Fig. 2 taken along line A-A, line and B-B. As shown in FIG. 2, FIG. 12 and FIG. 13, the sensor includes: a substrate substrate 32, a set of gate lines 30 and a set of data lines 31 arranged in a cross, a set of gate lines 30 and a set of data a plurality of sensing units arranged in an array defined by line 31, and a set of bias lines 42b extending through each of the sensing units, each sensing unit comprising at least one of a thin film transistor device and a photodiode sensor device Sensing subunit, wherein
所述薄膜晶体管器件包括: 位于衬底基板 32之上并与相邻的栅线 30连 接的栅极 38; 位于栅极 38之上并覆盖基板的栅极绝缘层 37; 位于栅极绝缘 层 37之上、 栅极 38上方的有源层 36; 位于有源层 36之上的欧姆层 35; 位 于欧姆层 35之上并相对而置形成沟道的源极 33和漏极 34, 所述漏极 34与 相邻的数据线 31连接;  The thin film transistor device includes: a gate electrode 38 over the substrate substrate 32 and connected to the adjacent gate line 30; a gate insulating layer 37 over the gate electrode 38 and covering the substrate; and the gate insulating layer 37 Above, an active layer 36 over the gate 38; an ohmic layer 35 over the active layer 36; a source 33 and a drain 34 overlying the ohmic layer 35 and oppositely forming a channel, the drain The pole 34 is connected to the adjacent data line 31;
所述光电二极管传感器件包括: 与源极 33连接的接收电极 39、 位于接 收电极 39之上的光电二极管 40、位于光电二极管 40之上的透明电极 41 , 以 及位于透明电极 41之上的偏压电极 42a, 所述偏压电极 42a与相邻的偏压线 42b连接。  The photodiode sensor device includes: a receiving electrode 39 connected to the source 33, a photodiode 40 above the receiving electrode 39, a transparent electrode 41 above the photodiode 40, and a bias voltage over the transparent electrode 41. The electrode 42a, the bias electrode 42a is connected to an adjacent bias line 42b.
本发明的实施例中,所述衬底基板 32可以为玻璃基板、塑料基板或其他 材料的基板; 所述栅线 30、 栅极 38、 数据线 31、 源极 33、 漏极 34、 接收电 极 39、 偏压电极 42a、 偏压线 42b和挡光条 52 (其作用是为减少光线对沟道 的影响)可以釆用相同的材质,例如为铝钕合金 ( AlNd )、铝( A1 )、铜( Cu )、 钼 (Mo ) 、 钼钨合金 ( MoW )或铬(Cr ) 的单层膜, 也可以为这些金属单 质或合金材料任意组合所构成的复合膜。 这些单层或复合膜的厚度例如在 150纳米至 450纳米之间。 本发明的实施例中, 欧姆层 35的材质可以为掺杂质半导体(n+a-Si ) ; 有源层 36 的材质可以为半导体材料, 例如非晶硅(a-Si ) , 厚度例如在 30 纳米至 250纳米之间; 栅极绝缘层 37的材质可以为氮化硅, 厚度例如在 300 纳米至 500纳米之间; 透明电极 41的材质可以为诸如氧化铟锡( ITO )或氧 化铟辞(IZO )等的透明导电材料。 In the embodiment of the present invention, the base substrate 32 may be a substrate of a glass substrate, a plastic substrate or other materials; the gate line 30, the gate 38, the data line 31, the source 33, the drain 34, and the receiving electrode. 39. The bias electrode 42a, the bias line 42b and the light blocking strip 52 (the function of which is to reduce the influence of light on the channel) can be made of the same material, such as aluminum-niobium alloy (AlNd), aluminum (A1). A single layer film of copper (Cu), molybdenum (Mo), molybdenum-tungsten alloy (MoW) or chromium (Cr) may be a composite film composed of any combination of these metal elements or alloy materials. The thickness of these single or composite films is, for example, between 150 nm and 450 nm. In the embodiment of the present invention, the material of the ohmic layer 35 may be a doped semiconductor (n+a-Si); the material of the active layer 36 may be a semiconductor material, such as amorphous silicon (a-Si), and the thickness is, for example, The material of the gate insulating layer 37 may be silicon nitride, and the thickness is, for example, between 300 nm and 500 nm; the material of the transparent electrode 41 may be, for example, indium tin oxide (ITO) or indium oxide. Transparent conductive material such as (IZO).
本发明实施例中, 所述光电二极管可以为 PIN型光电二极管, 包括: 位 于接收电极 39之上的 N型半导体(n+a-Si ) 40a, 位于 N型半导体 40a之上 的 I型半导体( a-Si )40b,以及位于 I型半导体 40b之上的 P型半导体( p+a-Si ) 40c。 PIN型光电二极管利用光生伏特原理工作,具有结电容小、渡越时间短、 灵敏度高等优点。 其结构相当于在 PN结中间插入较厚的本征非晶硅层, 其 中 P型材料由本征材料掺入提供空穴的杂质形成, N型材料由本征材料掺入 提供电子的杂质形成。 在本发明的其它实施例中, 光电二极管还可以釆用诸 如 MIS型光电二极管的其他类型光电二极管。  In the embodiment of the present invention, the photodiode may be a PIN type photodiode, including: an N-type semiconductor (n+a-Si) 40a located above the receiving electrode 39, and an I-type semiconductor located above the N-type semiconductor 40a ( a-Si) 40b, and a P-type semiconductor (p+a-Si) 40c over the I-type semiconductor 40b. The PIN type photodiode works by the photovoltaic principle and has the advantages of small junction capacitance, short transit time, and high sensitivity. The structure is equivalent to inserting a thicker intrinsic amorphous silicon layer in the middle of the PN junction, wherein the P-type material is formed by intrinsic material doping impurities which provide holes, and the N-type material is formed by intrinsic material doping impurities which provide electrons. In other embodiments of the invention, photodiodes may also utilize other types of photodiodes such as MIS type photodiodes.
继续参照图 12和图 13所示,在一个实施例中, 所述传感器,还可包括: 在每条数据线 31和每个光电二极管传感器件的接收电极 39的下方, 依次位 于栅极绝缘层 37之上的有源材料层 55和欧姆材料层 56;  Continuing to refer to FIG. 12 and FIG. 13, in one embodiment, the sensor may further include: under each of the data lines 31 and the receiving electrodes 39 of each of the photodiode sensing devices, sequentially located in the gate insulating layer An active material layer 55 and an ohmic material layer 56 above 37;
位于一组数据线 31和每个薄膜晶体管器件的源极 33和漏极 34之上的光 电二极管材料层 53、 位于光电二极管材料层 53之上的透明电极材料层 54。  A layer of photodiode material 53 overlying a set of data lines 31 and a source 33 and a drain 34 of each thin film transistor device, a layer 54 of transparent electrode material over the layer of photodiode material 53.
在一个实施例中, 该传感器还可进一步包括:  In an embodiment, the sensor may further include:
位于透明电极材料层 54和透明电极 41之上的第一钝化层 43,所述第一 钝化层 43未覆盖偏压电极 42a和偏压线 42b;  a first passivation layer 43 over the transparent electrode material layer 54 and the transparent electrode 41. The first passivation layer 43 does not cover the bias electrode 42a and the bias line 42b;
位于第一钝化层 43之上, 并位于源极 33、 漏极 34及沟道上方的挡光条 a light blocking strip located above the first passivation layer 43 and located above the source 33, the drain 34 and the channel
52; 52;
位于挡光条 52之上并覆盖基板的第二钝化层 57,所述第二钝化层 57具 有信号引导区过孔(图 12和图 13为一个感测单元的截面结构, 因此位于基 板周边的信号引导区过孔未在图中示出) 。  a second passivation layer 57 located above the light blocking strip 52 and covering the substrate, the second passivation layer 57 having a signal guiding area via hole (FIG. 12 and FIG. 13 are cross-sectional structures of one sensing unit, and thus are located on the substrate The surrounding signal guiding area vias are not shown in the figure).
在本发明实施例中, 所述数据线 31、 源极 33、 漏极 34和接收电极 39 的材质优选为相同。 所述挡光条 52、 偏压电极 42a和偏压线 42b的材质优选 为相同。 所述光电二极管材料层 53、 透明电极材料层 54、 有源材料层 55和 欧姆材料层 56分别与光电二极管 40、 透明电极 41、 有源层 36和欧姆层 35 的材质相同。 该结构设计的目的是为了减少构图工艺的次数, 光电二极管材 料层 53、透明电极材料层 54、有源材料层 55和欧姆材料层 56在传感器中并 未起到实际作用。 第一钝化层 43 (以及下文的第二钝化层 57 )可以釆用无机 绝缘膜 (例如氮化硅等)或有机绝缘膜 (例如感光树脂材料或者非感光树脂 材料等) , 厚度例如在 150纳米至 1500纳米之间。 In the embodiment of the present invention, the materials of the data line 31, the source 33, the drain 34, and the receiving electrode 39 are preferably the same. The materials of the light blocking strip 52, the bias electrode 42a, and the bias line 42b are preferably the same. The photodiode material layer 53, the transparent electrode material layer 54, the active material layer 55, and the ohmic material layer 56 are respectively connected to the photodiode 40, the transparent electrode 41, the active layer 36, and the ohmic layer 35. The materials are the same. The purpose of this structural design is to reduce the number of patterning processes, and the photodiode material layer 53, the transparent electrode material layer 54, the active material layer 55, and the ohmic material layer 56 do not play a practical role in the sensor. The first passivation layer 43 (and the second passivation layer 57 hereinafter) may be an inorganic insulating film (for example, silicon nitride or the like) or an organic insulating film (for example, a photosensitive resin material or a non-photosensitive resin material, etc.), for example, in thickness Between 150 nm and 1500 nm.
图 3示出了根据本发明实施例的传感器的多个感测单元的俯视图。 如图 3所示, 所述一组栅线 30, 包括两根单栅线 30a, 以及位于两根单栅线 30a 之间的多组双栅线 30b (相邻的两根双栅线 30b构成一组) 。 所述每个感测 单元包括两个感测子单元,每个感测子单元包括一个薄膜晶体管器件 50和一 个光电二极管器件 51。 两个感测子单元的薄膜晶体管器件 50呈对角分布, 且薄膜晶体管器件 50的栅极与相邻的单栅线 30a或者相邻的双栅线 30b中距 离较近的一根连接。 在传统的传感器中, 栅线与数据线均为单线排布, 在由 相邻两条栅线和相邻两条所限定的区域内仅有一个感测单元, 该感测单元包 含一个薄膜晶体管器件和一个光电二极管传感器件, 即只包含一个感测子单 元。 因此, 对比于传统的传感器, 本发明实施例中的双栅线的排布方式使得 栅线总数量增加一倍, 但数据线数量却降低至一半, 而栅线驱动设备的成本 要低于数据线驱动设备的成本, 因此, 釆用该结构可进一步降低传感器的成 本。  3 shows a top view of a plurality of sensing units of a sensor in accordance with an embodiment of the present invention. As shown in FIG. 3, the set of gate lines 30 includes two single gate lines 30a, and a plurality of sets of double gate lines 30b between the two single gate lines 30a (adjacent two double gate lines 30b constitute A group) . Each of the sensing units includes two sensing subunits, each of which includes a thin film transistor device 50 and a photodiode device 51. The thin film transistor devices 50 of the two sensing subunits are diagonally distributed, and the gate of the thin film transistor device 50 is connected to an adjacent one of the single gate lines 30a or the adjacent double gate lines 30b. In a conventional sensor, both the gate line and the data line are arranged in a single line, and there is only one sensing unit in a region defined by two adjacent gate lines and two adjacent ones, and the sensing unit includes a thin film transistor The device and a photodiode sensor device comprise only one sensing subunit. Therefore, compared with the conventional sensor, the arrangement of the double gate lines in the embodiment of the present invention doubles the total number of gate lines, but the number of data lines is reduced to half, and the cost of the gate line driving equipment is lower than the data. The cost of the line drive device, therefore, the use of this structure can further reduce the cost of the sensor.
此外, 如图 2所示, 该实施例中, 所述偏压线 42b位于感测单元的两个 感测子单元之间, 与两个感测子单元的偏压电极 42a交叉相连, 呈 "十字交 叉形" , 对比于传统的 "一字形" 偏压线, 该结构可提高偏压电极和透明电 极之间电压的均一性。  In addition, as shown in FIG. 2, in the embodiment, the bias line 42b is located between two sensing subunits of the sensing unit, and is connected to the bias electrodes 42a of the two sensing subunits. "Cross-shaped", which improves the uniformity of the voltage between the bias electrode and the transparent electrode compared to the conventional "in-line" bias line.
在本发明实施例中, 传感器的薄膜晶体管器件为底栅型, 传感器的制造 可共釆用五次构图工艺制作形成, 对比于现有技术, 可减少制造过程中掩模 板的使用数量, 降低了制造成本, 简化了生产工艺, 大大提升了设备产能及 产品的良品率。  In the embodiment of the invention, the thin film transistor device of the sensor is a bottom gate type, and the manufacturing of the sensor can be formed by using a five-time patterning process. Compared with the prior art, the number of masks used in the manufacturing process can be reduced, and the number of masks is reduced. Manufacturing costs simplify the production process and greatly increase the equipment capacity and product yield.
根据本发明的另一个实施例, 制造上述传感器的方法, 包括:  According to another embodiment of the present invention, a method of manufacturing the above sensor, comprising:
步骤 101、 在衬底基板 32上通过一次构图工艺形成栅线 30的图形、 与 栅线 30连接的栅极 38的图形。 第一次构图工艺后的截面结构请参照图 4和 图 5所示。 图 3和图 4为衬底基板在第一次构图工艺后的截面图。 图 2和图 12、 图 12分别是最终经过五次工艺后得到的感测单元的俯视图和剖面图。 因此, 图 3和图 4中的衬底基板只是按图 2示出的 A-A, 线及 B-B, 线的方向被切开, 其并不代表图 2的衬底基板的剖面图。 同样, 图 5至图 11也是按相同方式示 出。 Step 101: A pattern of the gate line 30 and a pattern of the gate electrode 38 connected to the gate line 30 are formed on the base substrate 32 by one patterning process. Please refer to Figure 4 and Figure 5 for the cross-sectional structure after the first patterning process. 3 and 4 are cross-sectional views of the base substrate after the first patterning process. 2 and 12 and FIG. 12 are a plan view and a cross-sectional view, respectively, of the sensing unit obtained after five passes of the process. Therefore, the base substrate in FIGS. 3 and 4 is only cut along the direction of AA, line and BB shown in FIG. 2, which does not represent a cross-sectional view of the base substrate of FIG. 2. Also, FIGS. 5 to 11 are also shown in the same manner.
一次构图工艺依次包括基板清洗、 成膜、 光刻胶涂覆、 曝光、 显影、 刻 蚀、 光刻胶去除等步骤。 基板清洗包括使用去离子水、 有机清洗液进行清洗 等。 成膜工艺用于形成将被构图的结构层。 例如, 对于金属层通常釆用物理 气相沉积方式(例如磁控溅射法)成膜, 并通过湿法刻蚀形成图形; 而对于 非金属层通常釆用化学气相沉积方式成膜, 并通过干法刻蚀形成图形。 以下 步骤中的构图工艺与此相同, 不再赘述。  The one-time patterning process includes steps of substrate cleaning, film formation, photoresist coating, exposure, development, etching, photoresist removal, and the like. Substrate cleaning includes cleaning with deionized water, organic cleaning solution, and the like. The film forming process is used to form a structural layer to be patterned. For example, for a metal layer, a film is formed by physical vapor deposition (for example, magnetron sputtering), and a pattern is formed by wet etching. For a non-metal layer, a film is formed by chemical vapor deposition, and dried. Etching forms a pattern. The composition process in the following steps is the same as this, and will not be described again.
步骤 102、 形成覆盖基板的栅极绝缘层 37 , 并通过一次构图工艺形成位 于栅极 38上方的有源层 36的图形、位于有源层 36之上的欧姆层 35的图形、 位于欧姆层 35之上并相对而置形成沟道的源极 33和漏极 34的图形、与漏极 34连接的数据线 31的图形、 与源极 33连接的接收电极 39的图形、 位于接 收电极 39之上的光电二极管 40的图形、位于光电二极管 40之上的透明电极 41的图形。 第二次构图工艺后的截面结构请参照图 6和图 7所示;  Step 102, forming a gate insulating layer 37 covering the substrate, and forming a pattern of the active layer 36 over the gate electrode 38, a pattern of the ohmic layer 35 over the active layer 36, in the ohmic layer 35 by one patterning process. The pattern of the source 33 and the drain 34 forming the channel, the pattern of the data line 31 connected to the drain 34, the pattern of the receiving electrode 39 connected to the source 33, and the receiving electrode 39 are formed on the upper side. The pattern of the photodiode 40, the pattern of the transparent electrode 41 above the photodiode 40. Please refer to Figure 6 and Figure 7 for the cross-sectional structure after the second patterning process;
在一个实施例中, 当光电二极管 40为 PIN型光电二极管, 所述数据线 31、 源极 33、 漏极 34和接收电极 39的材质相同时, 步骤 102中, 通过一次 构图工艺形成有源层 36的图形、 欧姆层 35的图形、 源极 33和漏极 34的图 形、数据线 31的图形、接收电极 39的图形、 光电二极管 40的图形和透明电 极 41的图形, 包括:  In one embodiment, when the photodiode 40 is a PIN photodiode, and the materials of the data line 31, the source 33, the drain 34, and the receiving electrode 39 are the same, in step 102, the active layer is formed by one patterning process. The pattern of 36, the pattern of the ohmic layer 35, the pattern of the source 33 and the drain 34, the pattern of the data line 31, the pattern of the receiving electrode 39, the pattern of the photodiode 40, and the pattern of the transparent electrode 41 include:
依次沉积有源半导体层、 欧姆半导体层、数据线材料层、 N型半导体层、 I型半导体层、 P型半导体层和透明导电材料层;  Depositing an active semiconductor layer, an ohmic semiconductor layer, a data line material layer, an N-type semiconductor layer, an I-type semiconductor layer, a P-type semiconductor layer, and a transparent conductive material layer;
涂覆光刻胶;  Coating a photoresist;
釆用具有全透光区、 半透光区和不透光区的掩模板对基板进行曝光, 其 中, 不透光区对应形成接收电极 39、 PIN光电二极管、 透明电极 41、 数据线 31、 漏极 34和源极 33的区域, 半透光区对应形成沟道的区域; 该步骤所釆 用的掩模板可以为灰色调掩模板或者半色调掩模板等;  基板 Exposing the substrate with a mask having a fully transparent region, a semi-transmissive region, and an opaque region, wherein the opaque region correspondingly forms the receiving electrode 39, the PIN photodiode, the transparent electrode 41, the data line 31, and the drain a region of the pole 34 and the source 33, the semi-transmissive region corresponding to the region forming the channel; the mask used in this step may be a gray tone mask or a halftone mask;
显影, 去除全透光区对应区域的光刻胶; 对基板进行刻蚀, 形成接收电极 39的图形、 PIN光电二极管的图形、 透 明电极 41的图形、 数据线 31的图形和有源层 36的图形; Developing, removing the photoresist in the corresponding region of the entire transparent region; Etching the substrate to form a pattern of the receiving electrode 39, a pattern of the PIN photodiode, a pattern of the transparent electrode 41, a pattern of the data line 31, and a pattern of the active layer 36;
对基板进行灰化, 去除半透光区对应区域的光刻胶;  Ashing the substrate to remove the photoresist in the corresponding region of the semi-transmissive region;
对基板进行刻蚀和光刻胶剥离, 形成欧姆层 35的图形及漏极 34和源极 33的图形, 所述源极 33和漏极 34相对而置形成沟道。  The substrate is etched and photoresist stripped to form a pattern of the ohmic layer 35 and a pattern of the drain 34 and the source 33, and the source 33 and the drain 34 are opposed to each other to form a channel.
在该次构图工艺中,透明电极 41图形可以单独釆用湿法刻蚀形成,也可 以与光电二极管 40的图形同时通过干法刻蚀形成。  In the patterning process, the pattern of the transparent electrode 41 may be formed by wet etching alone or by dry etching simultaneously with the pattern of the photodiode 40.
步骤 103、 通过一次构图工艺形成第一钝化层 43的图形, 所述第一钝化 层 43未覆盖形成偏压电极 42a和偏压线 42b的区域, 即预留出要形成 42a 和 42b的空间。 这是因为下一步形成的偏压电极 42a和偏压线 42b需要与透 明电极 41连接。 第三次构图工艺后的截面结构请参照图 8和图 9所示; 步骤 104、 通过一次构图工艺形成位于透明电极 41之上的偏压电极 42a 的图形、 与偏压电极 42a连接的偏压线 42b的图形, 以及位于源极 33、 漏极 34及沟道上方的挡光条 52的图形。 第四次构图工艺后的截面结构请参照图 10和图 11所示。 在一个实施例中, 所述挡光条 52、 偏压电极 42a和偏压线 42b的材质相同。  Step 103, forming a pattern of the first passivation layer 43 by one patterning process, the first passivation layer 43 not covering the region where the bias electrode 42a and the bias line 42b are formed, that is, the formation of 42a and 42b is reserved. Space. This is because the bias electrode 42a and the bias line 42b formed next need to be connected to the transparent electrode 41. Referring to FIG. 8 and FIG. 9 for the cross-sectional structure after the third patterning process; Step 104, forming a pattern of the bias electrode 42a over the transparent electrode 41 by one patterning process, and connecting with the bias electrode 42a The pattern of the bias line 42b, and the pattern of the light blocking strips 52 above the source 33, the drain 34 and the channel. Refer to Figure 10 and Figure 11 for the cross-sectional structure after the fourth patterning process. In one embodiment, the light blocking strip 52, the bias electrode 42a, and the bias line 42b are made of the same material.
此外, 在步骤 104之后, 还进一步包括:  In addition, after step 104, the method further includes:
步骤 105、 通过一次构图工艺形成覆盖基板的第二钝化层 57的图形, 所 述第二钝化层 57具有信号引导区过孔,第五次构图工艺后的截面结构请参照 图 13和图 14所示。  Step 105, forming a pattern of the second passivation layer 57 covering the substrate by one patterning process, the second passivation layer 57 has a signal guiding area via hole, and the cross-sectional structure after the fifth patterning process is shown in FIG. 13 and 14 is shown.
该步骤 105为可选的, 因为在不执行步骤 105的情况下, 同样可以实现 本发明的目的。 因此, 在一个实施例中, 用于制造传感器的方法可仅包括上 述步骤 101~104。  This step 105 is optional because the purpose of the present invention can be achieved without performing step 105. Thus, in one embodiment, the method for fabricating a sensor may include only steps 101-104 described above.
可见, 本发明传感器的制造方法可共釆用四次或五次构图工艺制作, 对 比于现有技术, 减少了掩模板的使用数量, 降低了制造成本, 简化了生产工 艺, 大大提升了设备产能及产品的良品率。  It can be seen that the manufacturing method of the sensor of the present invention can be fabricated by using four or five patterning processes in total, which reduces the use of the mask, reduces the manufacturing cost, simplifies the production process, and greatly improves the equipment production rate compared with the prior art. And the yield of the product.
以上所述仅是本发明的示范性实施方式, 而非用于限制本发明的保护范 围, 本发明的保护范围由所附的权利要求确定。  The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

权利要求书 claims
1、一种传感器, 包括:衬底基板、呈交叉排列的一组栅线和一组数据线、 由所述一组栅线和一组数据线所限定的呈阵列状排布的多个感测单元, 及贯 穿每一个感测单元的一组偏压线, 每个感测单元包括至少一个由薄膜晶体管 器件和光电二极管传感器件组成的感测子单元, 其中, 1. A sensor, comprising: a substrate, a set of gate lines and a set of data lines arranged in a crosswise manner, and a plurality of sensors arranged in an array defined by the set of gate lines and a set of data lines. A sensing unit, and a set of bias lines running through each sensing unit, each sensing unit including at least one sensing subunit composed of a thin film transistor device and a photodiode sensing device, wherein,
所述薄膜晶体管器件包括: 位于所述衬底基板之上并与相邻的栅线连接 的栅极; 位于所述栅极之上并覆盖所述衬底基板的栅极绝缘层; 位于所述栅 极绝缘层之上、 栅极上方的有源层; 位于所述有源层之上的欧姆层; 位于所 述欧姆层之上并相对而置形成沟道的源极和漏极, 所述漏极与相邻的数据线 连接; The thin film transistor device includes: a gate located on the base substrate and connected to an adjacent gate line; a gate insulating layer located on the gate electrode and covering the base substrate; The active layer above the gate insulating layer and above the gate; the ohmic layer located above the active layer; the source and drain located above the ohmic layer and facing each other to form a channel, the The drain is connected to the adjacent data line;
所述光电二极管传感器件包括: 与所述源极连接的接收电极、 位于所述 接收电极之上的光电二极管、 位于所述光电二极管之上的透明电极, 以及位 于所述透明电极之上的偏压电极, 所述偏压电极与相邻的偏压线连接。 The photodiode sensing device includes: a receiving electrode connected to the source, a photodiode located above the receiving electrode, a transparent electrode located above the photodiode, and a bias electrode located above the transparent electrode. A piezoelectric electrode, the bias electrode is connected to an adjacent bias line.
2、 如权利要求 1所述的传感器, 其中, 所述一组栅线包括两根单栅线, 以及位于两根单栅线之间的多组双栅线, 2. The sensor of claim 1, wherein the set of gate lines includes two single gate lines, and a plurality of sets of double gate lines located between the two single gate lines,
所述每个感测单元包括两个感测子单元, 两个感测子单元的薄膜晶体管 器件呈对角分布, 且薄膜晶体管器件的栅极与相邻的单栅线或者相邻的双栅 线中距离较近的一根连接。 Each of the sensing units includes two sensing sub-units, the thin film transistor devices of the two sensing sub-units are distributed diagonally, and the gates of the thin film transistor devices are connected to adjacent single gate lines or adjacent double gates. The closer one of the wires is connected.
3、如权利要求 2所述的传感器, 其中, 所述偏压线位于感测单元的两个 感测子单元之间 , 与两个感测子单元的偏压电极交叉相连。 3. The sensor according to claim 2, wherein the bias line is located between two sensing sub-units of the sensing unit and is cross-connected with the bias electrodes of the two sensing sub-units.
4、 如权利要求 1-3中任一项所述的传感器, 还包括: 4. The sensor according to any one of claims 1-3, further comprising:
在每条数据线和每个光电二极管传感器件的接收电极的下方, 依次位于 栅极绝缘层之上的有源材料层和欧姆材料层; Below each data line and the receiving electrode of each photodiode sensing device, there are active material layers and ohmic material layers located above the gate insulating layer;
位于一组数据线和每个薄膜晶体管器件的源极和漏极之上的光电二极管 材料层、 位于光电二极管材料层之上的透明电极材料层。 A layer of photodiode material located over a set of data lines and the source and drain electrodes of each thin film transistor device. A layer of transparent electrode material located over the layer of photodiode material.
5、 如权利要求 1-4中任一项所述的传感器, 还包括: 5. The sensor according to any one of claims 1-4, further comprising:
位于透明电极材料层和透明电极之上的第一钝化层, 所述第一钝化层未 覆盖偏压电极和偏压线; A first passivation layer located on the transparent electrode material layer and the transparent electrode, the first passivation layer does not cover the bias electrode and bias line;
位于第一钝化层之上, 并位于源极、 漏极及沟道上方的挡光条; 位于挡光条之上并覆盖衬底基板的第二钝化层, 所述第二钝化层具有信 号引导区过孔。 A light blocking strip located above the first passivation layer and above the source, drain and channel; A second passivation layer is located above the light blocking strip and covers the base substrate, and the second passivation layer has a signal guide area via hole.
6、 如权利要求 1-5中任一项所述的传感器, 其中, 所述数据线、 源极、 漏极和接收电极的材质相同。 6. The sensor according to any one of claims 1 to 5, wherein the data line, source electrode, drain electrode and receiving electrode are made of the same material.
7、 如权利要求 5或 6所述的传感器, 其中, 所述挡光条、 偏压电极和偏 压线的材质相同; 7. The sensor according to claim 5 or 6, wherein the light blocking strip, bias electrode and bias line are made of the same material;
8、 如权利要求 4-7中任一项所述的传感器, 其中, 所述光电二极管材料 层、 透明电极材料层、 有源材料层和欧姆材料层分别与光电二极管、 透明电 极、 有源层和欧姆层的材质相同。 8. The sensor according to any one of claims 4 to 7, wherein the photodiode material layer, transparent electrode material layer, active material layer and ohmic material layer are respectively in contact with the photodiode, transparent electrode and active layer. The same material as the ohmic layer.
9、 如权利要求 1-8 中任一项所述的传感器, 其中, 所述光电二极管为 9. The sensor according to any one of claims 1-8, wherein the photodiode is
PIN型光电二极管, 包括: 位于接收电极之上的 N型半导体, 位于 N型半导 体之上的 I型半导体, 以及位于 I型半导体之上的 P型半导体。 PIN-type photodiodes include: N-type semiconductor located on the receiving electrode, I-type semiconductor located on the N-type semiconductor, and P-type semiconductor located on the I-type semiconductor.
10、 一种传感器的制造方法, 包括: 10. A method of manufacturing a sensor, including:
在衬底基板上通过一次构图工艺形成栅线的图形、 与所述栅线连接的栅 极的图形; Forming a pattern of gate lines and a pattern of gate electrodes connected to the gate lines on the base substrate through a patterning process;
形成覆盖所述衬底基板的栅极绝缘层, 并通过第一次构图工艺形成位于 所述栅极上方的有源层的图形、 位于所述有源层之上的欧姆层的图形、 位于 所述欧姆层之上并相对而置形成沟道的源极和漏极的图形、 与所述漏极连接 的数据线的图形、 与所述源极连接的接收电极的图形、 位于所述接收电极之 上的光电二极管的图形、 位于所述光电二极管之上的透明电极的图形; A gate insulating layer covering the base substrate is formed, and through a first patterning process, the pattern of the active layer located above the gate, the pattern of the ohmic layer located above the active layer, and the pattern of the ohmic layer located above the active layer are formed through the first patterning process. Patterns of source and drain electrodes forming a channel on the ohmic layer and facing each other, patterns of data lines connected to the drain electrodes, patterns of receiving electrodes connected to the source electrodes, and patterns located on the receiving electrodes. The pattern of the photodiode above, the pattern of the transparent electrode located above the photodiode;
通过第二次构图工艺形成第一钝化层的图形, 所述第一钝化层未覆盖形 成偏压电极和偏压线的区 i或; 以及 The pattern of the first passivation layer is formed through a second patterning process, and the first passivation layer does not cover the area where the bias electrode and the bias line are formed; and
通过第三次构图工艺形成位于所述透明电极之上的偏压电极的图形、 与 所述偏压电极连接的偏压线的图形, 以及位于所述源极、 漏极及沟道上方的 挡光条的图形。 Through the third patterning process, the pattern of the bias electrode located above the transparent electrode, the pattern of the bias line connected to the bias electrode, and the pattern located above the source electrode, drain electrode and channel are formed. Graphics of light bars.
11、 如权利要求 10所述的制造方法, 其中, 在形成偏压电极的图形、 偏 压线的图形和挡光条的图形之后, 进一步包括: 11. The manufacturing method according to claim 10, wherein after forming the pattern of the bias electrode, the pattern of the bias line and the pattern of the light blocking strip, further comprising:
通过第四次构图工艺形成覆盖衬底基板的第二钝化层的图形, 所述第二 钝化层具有信号引导区过孔。 A pattern of the second passivation layer covering the base substrate is formed through a fourth patterning process, and the second passivation layer has a signal guide area via hole.
12、如权利要求 10或 11所述的制造方法,其中,所述光电二极管为 PIN 型光电二极管, 包括 N型半导体、 I型半导体和 P型半导体。 12. The manufacturing method according to claim 10 or 11, wherein the photodiode is a PIN Type photodiodes include N-type semiconductors, I-type semiconductors and P-type semiconductors.
13、 如权利要求 10-12中任一项所述的制造方法, 其中, 所述数据线、 源极、 漏极和接收电极的材质相同; 所述挡光条、 偏压电极和偏压线的材质 相同。 13. The manufacturing method according to any one of claims 10 to 12, wherein the data line, source electrode, drain electrode and receiving electrode are made of the same material; the light blocking strip, bias electrode and bias voltage The threads are made of the same material.
14、 如权利要求 10-12中任一项所述的制造方法, 其中, 所述通过一次 构图工艺形成有源层的图形、 欧姆层的图形、 源极和漏极的图形、 数据线的 图形、 接收电极的图形、 光电二极管的图形和透明电极的图形, 包括: 14. The manufacturing method according to any one of claims 10 to 12, wherein the pattern of the active layer, the pattern of the ohmic layer, the pattern of the source electrode and the drain electrode, and the pattern of the data line are formed through one patterning process. , the pattern of the receiving electrode, the pattern of the photodiode and the pattern of the transparent electrode, including:
依次沉积有源半导体层、 欧姆半导体层、数据线材料层、 N型半导体层、 I型半导体层、 P型半导体层和透明导电材料层, 并在透明导电材料层之上涂 覆光刻胶; Deposit the active semiconductor layer, the ohmic semiconductor layer, the data line material layer, the N-type semiconductor layer, the I-type semiconductor layer, the P-type semiconductor layer and the transparent conductive material layer in sequence, and coat the photoresist on the transparent conductive material layer;
釆用具有全透光区、半透光区和不透光区的掩模板对衬底基板进行曝光, 其中, 不透光区对应形成接收电极、 PIN光电二极管、 透明电极、 数据线、 漏极和源极的区域, 半透光区对应形成沟道的区域; The substrate is exposed using a mask plate having a fully transparent area, a semi-transparent area and an opaque area, wherein the opaque area corresponds to the receiving electrode, PIN photodiode, transparent electrode, data line and drain electrode. and the source area, the semi-transparent area corresponds to the area where the channel is formed;
对衬底基板进行显影、 刻蚀, 形成接收电极的图形、 PIN光电二极管的 图形、 透明电极的图形、 数据线的图形和有源层的图形; Develop and etch the base substrate to form the pattern of the receiving electrode, the pattern of the PIN photodiode, the pattern of the transparent electrode, the pattern of the data line and the pattern of the active layer;
对衬底基板进行灰化、 刻蚀和光刻胶剥离, 形成欧姆层的图形及漏极和 源极的图形, 所述源极和漏极相对而置形成沟道。 The base substrate is ashed, etched, and photoresist stripped to form the pattern of the ohmic layer and the patterns of the drain and source electrodes. The source electrode and the drain electrode are placed opposite to form a channel.
15、 如权利要求 10-14中任一项所述的制造方法, 其中, 所述透明电极 的图形通过湿法刻蚀形成, 或者, 所述透明电极的图形与光电二极管的图形 同时通过干法刻蚀形成。 15. The manufacturing method according to any one of claims 10 to 14, wherein the pattern of the transparent electrode is formed by wet etching, or the pattern of the transparent electrode and the pattern of the photodiode are formed by dry etching at the same time. Formed by etching.
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