WO2013185308A1 - 一种对频率锁定的方法、一种压控振荡器以及频率产生单元 - Google Patents

一种对频率锁定的方法、一种压控振荡器以及频率产生单元 Download PDF

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Publication number
WO2013185308A1
WO2013185308A1 PCT/CN2012/076855 CN2012076855W WO2013185308A1 WO 2013185308 A1 WO2013185308 A1 WO 2013185308A1 CN 2012076855 W CN2012076855 W CN 2012076855W WO 2013185308 A1 WO2013185308 A1 WO 2013185308A1
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WIPO (PCT)
Prior art keywords
voltage
frequency
circuit
controlled oscillator
varactor
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Ceased
Application number
PCT/CN2012/076855
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English (en)
French (fr)
Inventor
冷鹏
童伟
黄成富
朱敏
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Hytera Communications Corp Ltd
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Hytera Communications Corp Ltd
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Priority to PCT/CN2012/076855 priority Critical patent/WO2013185308A1/zh
Publication of WO2013185308A1 publication Critical patent/WO2013185308A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1203—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier being a single transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1231—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/124—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
    • H03B5/1243—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance the means comprising voltage variable capacitance diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Definitions

  • the present invention relates to the field of communication technologies, and in particular, to a method for frequency locking, a voltage controlled oscillator, and a frequency generating unit.
  • Frequency generation units are important in modern communication systems and information processing systems.
  • the performance index of the frequency generation unit directly affects the '1' performance index of the RF communication system and the digital signal processing system.
  • the lock time of the frequency generating unit becomes one of the key indicators of the design. The shorter the lock time of the frequency generating unit, the faster the frequency is converted and the faster the data transfer rate.
  • the frequency generating unit mainly includes a voltage-controlled oscillator (VC0), a loop filter (LPF), a phase-locked loop integrated circuit (PLL IC), a VC0 to PLL IC feedback band pass (BPF), and a phase lock. Ring reference crystal.
  • VC0 voltage-controlled oscillator
  • LPF loop filter
  • PLL IC phase-locked loop integrated circuit
  • BPF PLL IC feedback band pass
  • a phase lock. Ring reference crystal a phase lock. Ring reference crystal.
  • the voltage controlled oscillator is one of the important components of the frequency generating unit, and its main function is to output the corresponding oscillation frequency according to the input voltage.
  • the frequency generation unit has a longer frequency lock time and a slower frequency conversion speed, which affects the data transmission rate.
  • the technical problem to be solved by the present invention is to provide a method for locking a frequency, a voltage controlled oscillator and a frequency generating unit, which can achieve a shorter locking time and a locking speed when the frequency is locked with corresponding reasonable parameters. fast.
  • the present invention provides a voltage controlled oscillator comprising a frequency selective network circuit and an active device circuit.
  • the frequency selective network circuit has a control voltage input and an auxiliary control voltage input, wherein a change trend of the auxiliary control voltage is the same as a change trend of a target oscillation frequency of the frequency selective network circuit, and the auxiliary control voltage causes the
  • the equivalent capacitance value of the frequency selective network circuit changes C1
  • the control voltage causes the equivalent capacitance value of the frequency selective network circuit to change C2
  • the sum of C1 and C2 is C3
  • the C3 is
  • the frequency selective network circuit is configured to generate a signal whose oscillation frequency changes according to the control voltage and the auxiliary control voltage according to the control voltage and the auxiliary control voltage.
  • the active device circuit is operative to provide energy to the frequency selective network circuit that produces an oscillating frequency.
  • the auxiliary control voltage is input to the frequency selective network circuit prior to a control voltage.
  • the frequency selective network circuit comprises: first, second, third and fourth inductances, first, second, third, fourth, fifth, sixth, seventh, eighth and ninth Capacitor, first, second, third and fourth varactors and a magnetic bead.
  • the first varactor set includes at least one varactor in parallel.
  • the second varactor set includes at least one varactor in parallel.
  • the third varactor set includes at least one varactor in parallel.
  • the fourth varactor set includes at least one varactor in parallel.
  • first, second, third, eighth, and ninth capacitors an anode of all of the varactors in the first and fourth varactors, and the third and fourth inductors
  • the first end is connected to the ground voltage.
  • the second end of the first capacitor and the first end of the first inductor are connected to a control voltage.
  • a second end of the first inductor, a first end of the fourth and fifth capacitors, and a cathode of all of the varactors in the third varactor group are connected to all of the varactors in the fourth varactor group negative electrode.
  • the first end of the magnetic bead and the second end of the second capacitor are connected to an auxiliary control voltage.
  • a second end of the magnetic bead and a second end of the third capacitor are coupled to a first end of the second inductor.
  • a second end of the second inductor, a negative pole of all varactors in the first varactor group, and a second end of the fourth and fifth capacitors are connected to all of the second varactor group The negative pole of the varactor.
  • the positive poles of all the varactors in the second varactor group, the positive poles of all varactors in the third varactor group, and the first ends of the sixth and seventh capacitors are connected to the third The second end of the inductor.
  • the first varactor set comprises a first varactor.
  • the second varactor set includes a second varactor having the same voltage capacity characteristics as the first varactor.
  • the second varactor set includes third and fourth varactors having the same voltage capacitance characteristics in parallel.
  • the third varactor set includes fifth and sixth varactors having the same voltage capacitance characteristics in parallel.
  • the auxiliary control voltage is provided by a digital to analog conversion circuit or a voltage divider circuit controlled by a switch.
  • the present invention also provides a method for frequency locking, the method comprising:
  • the control unit generates an auxiliary voltage corresponding to the target oscillation frequency according to a relationship between the preset frequency and the control voltage, and inputs the auxiliary voltage to the voltage controlled oscillator provided by the present invention as an auxiliary control voltage of the voltage controlled oscillator;
  • the path filter inputs a control voltage to the voltage controlled oscillator.
  • the auxiliary control voltage causes an equivalent capacitance value of the frequency selective network circuit in the voltage controlled oscillator to change by C1, and the control voltage causes the equivalent capacitance value of the frequency selective network circuit to change by C2.
  • the frequency output by the voltage controlled oscillator is taken as the locked frequency after the time when the method is executed reaches the preset lock time.
  • C3 is a capacitance value of the equivalent capacitance value of the frequency selective network circuit when the frequency of the signal generated by the frequency selective network circuit changes from the current frequency to the target oscillation frequency.
  • the absolute value of C 3 is greater than the absolute value of C2.
  • the method further includes:
  • the control unit applies a preset voltage output by the voltage pre-configuration circuit to the loop filter for charging the capacitor in the loop filter during a first period of time;
  • the voltage pre-configuration circuit includes a forward voltage drop with temperature A raised and lowered diode for outputting a preset voltage that increases with increasing temperature.
  • the control unit cuts off the preset voltage provided by the voltage pre-configuration circuit for the loop filter after the first period of time.
  • the method further includes:
  • the control unit turns on the fast lock function of the phase locked loop circuit, and sends a fast lock signal generated by the phase locked loop circuit to the loop filter in a second time period after the first time period.
  • the present invention also provides a frequency generating unit, characterized in that the frequency generating unit comprises: a control unit, a phase locked loop circuit, a loop filter, and a voltage controlled oscillator provided by the present invention.
  • the control unit is configured to generate a frequency setting signal according to the target oscillation frequency, and send the frequency setting signal to the phase locked loop circuit, and generate an auxiliary voltage corresponding to the target oscillation frequency according to a preset relationship between the frequency and the control voltage. And inputting an auxiliary voltage as an auxiliary control voltage to the voltage controlled oscillator; the auxiliary control voltage causes an equivalent capacitance value of the frequency selective network circuit in the voltage controlled oscillator to change by Cl.
  • the phase-locked loop circuit obtains a comparison signal according to the output signal of the voltage-controlled oscillator and the frequency setting signal, and obtains an error voltage signal reflecting a phase difference between the comparison signal and the reference signal according to the comparison signal and the reference signal, and Outputting the error voltage signal to a loop filter, and the error voltage signal is filtered by the loop filter and input to the voltage controlled oscillator as a control voltage of the voltage controlled oscillator;
  • the equivalent capacitance value change C2 of the frequency selective network circuit is used to be used to the frequency selective network circuit.
  • the voltage controlled oscillator sends a signal generated by the voltage controlled oscillator to the phase locked loop circuit.
  • the sum of C1 and C2 is C3, and the C3 is a capacitance value of the equivalent capacitance value of the frequency selective network circuit when the frequency of the signal generated by the frequency selective network circuit changes from the current frequency to the target oscillation frequency.
  • the absolute value of C3 is greater than the absolute value of C2.
  • control unit includes a digital-to-analog conversion circuit; the digital-to-analog conversion circuit is configured to generate an auxiliary voltage corresponding to the target oscillation frequency according to a preset relationship between the frequency and the control voltage, and use the auxiliary voltage as an auxiliary A control voltage is input to the voltage controlled oscillator.
  • control unit includes a switch-controlled voltage dividing circuit; the voltage dividing circuit is configured to generate an auxiliary voltage corresponding to the target oscillation frequency according to a preset relationship between the frequency and the control voltage, and use the auxiliary voltage as An auxiliary control voltage is input to the voltage controlled oscillator.
  • the frequency generating unit further comprises: a voltage pre-configuration circuit comprising a diode whose forward voltage drop decreases as the temperature rises, for outputting a preset voltage that increases with an increase in temperature.
  • a voltage pre-configuration circuit comprising a diode whose forward voltage drop decreases as the temperature rises, for outputting a preset voltage that increases with an increase in temperature.
  • the control unit is further configured to apply a preset voltage output by the voltage pre-configuration circuit to the loop filter, charge a capacitor in the loop filter, and at the first After the time period, the voltage pre-configuration circuit is turned off to provide a preset voltage for the loop filter.
  • the frequency generating unit further includes a first switch and a second switch.
  • the control unit is further configured to enable a fast lock function of the phase locked loop circuit.
  • a first switch connected between the voltage pre-configuration circuit and the loop filter for connection And receiving the pre-configured control signal sent by the control unit in the first time period, and applying a preset voltage provided by the voltage pre-configuration circuit to the loop filter.
  • a second switch connected between the fast lock control end of the phase locked loop circuit and the loop filter, configured to send the control unit in a second time period after the first time period After the lock control signal is turned on, the fast lock signal generated by the phase locked loop circuit is sent to the loop filter.
  • the auxiliary control voltage generated by the control unit causes the equivalent capacitance value of the frequency selective network circuit in the voltage controlled oscillator to change C 1
  • the control voltage causes the equivalent capacitance value of the frequency selective network circuit to change C2.
  • the sum of C1 and C2 is C3, and the C3 is a capacitance of the equivalent capacitance value of the frequency selective network circuit when the frequency of the signal generated by the frequency selective network circuit changes from the current frequency to the target oscillation frequency. Value; the absolute value of C 3 is greater than the absolute value of C2.
  • the control voltage only needs to change the equivalent capacitance value of the frequency selective network circuit by C2, compared to the case where there is no auxiliary control voltage, that is, the equivalent capacitance value of the frequency selective network circuit needs to be changed compared to the control voltage.
  • the variation range of the control voltage is smaller in the present invention, and since the ambient factor of the voltage controlled oscillator is the same, the frequency locking time depends on the variation range of the control voltage, and therefore, the frequency generating unit realized by the present invention The difference in the control voltage variation is reduced when the ambient factors of the voltage controlled oscillator are the same and the oscillation frequency of the voltage controlled oscillator output is constant, thereby achieving a faster speed locking and a shorter locking time.
  • Figure 1 is a phase diagram of the frequency locking process
  • FIG. 3 is a system structural diagram of a voltage controlled oscillator provided by the present invention.
  • FIG. 4 is a specific circuit diagram of a voltage controlled oscillator provided by the present invention.
  • Figure 5 is a relationship between the reverse voltage of the varactor and the reverse circuit
  • Figure 6 is a graph showing the relationship between the reverse voltage of the varactor and the resistance
  • FIG. 8 is a structural diagram of a frequency generating unit provided by the present invention.
  • Figure 9 is a structural diagram of a system including a frequency generating unit
  • Figure 10 is a circuit diagram of the system shown in Figure 8;
  • Figure 11 is a flow chart showing the operation of the system shown in Figure 8.
  • Tl Capture Phase: Due to the switching of frequency points, the frequency changes from stable to unstable, the phase difference between the output frequency and the phase-detection frequency of the reference clock is very large, and the phase-locked loop is in an unlocked state, requiring a large amount of Pump current to capture the target frequency.
  • T2 Track Phase: The phase difference between the output frequency and the reference clock phase-detection frequency is small.
  • the phase-locked loop tracks the output frequency, which belongs to the stage of loop self-adjustment.
  • T3 Stable Phase: The phase difference between the output frequency and the reference clock phase is very small, and the phase locked loop is locked. When the frequency deviation is less than ⁇ 100Hz, the phase-locked loop enters a steady state.
  • the locking time of the target frequency is mainly determined by the T1 and T2 phases.
  • the time of T2 is mainly determined by the parameters of the loop itself.
  • the phase difference is already small, and the T3 can be quickly entered by the adjustment of the phase-locked loop itself.
  • the time consumed by the Tl capture phase has a direct impact on the overall lock time.
  • the present invention therefore primarily reduces the overall lock time by reducing the time consumed by the T1 capture phase.
  • the present invention provides a voltage controlled oscillator comprising a frequency selective network circuit 301 and an active device circuit 302.
  • the frequency selective network circuit 301 has a control voltage input and an auxiliary control voltage input, wherein a change trend of the auxiliary control voltage is the same as a change trend of a target oscillation frequency of the frequency selective network circuit, and the auxiliary control voltage makes The equivalent capacitance value change C1 of the frequency selective network circuit, the control voltage is such that the equivalent capacitance value of the frequency selective network circuit changes C2, the sum of C1 and C2 is C3, and the C3 is generated by the frequency selective network circuit.
  • the capacitance value of the equivalent capacitance value of the frequency selective network circuit changes; the absolute value of C3 is greater than the absolute value of C2, that is,
  • the frequency selective network circuit 301 is configured to generate a signal whose oscillation frequency changes according to the control voltage and the auxiliary control voltage according to the control voltage and the auxiliary control voltage. energy.
  • auxiliary control voltage and control voltage mentioned in the present invention are two different control voltages.
  • the difference C1, C2, and C3 of the capacitance change are vectors. If the equivalent capacitance value of the frequency selective network circuit increases, the difference of the capacitance change is a negative number, and the equivalent capacitance value is When decreasing, the difference in capacitance change is a positive number. If the equivalent capacitance value of the frequency selective network circuit decreases, the difference in capacitance change is a positive number, and when the equivalent capacitance value increases, the difference in capacitance change is a negative number.
  • the target oscillation frequency that is, the oscillation frequency to be obtained.
  • the oscillation frequency to be obtained is used as the voltage controlled oscillation.
  • the target oscillation frequency can be determined according to the actual situation.
  • the auxiliary control voltage may be input to the frequency selective network circuit 301 prior to the control voltage.
  • the auxiliary control voltage can be provided by a digital to analog conversion circuit (DAC).
  • DAC digital to analog conversion circuit
  • the auxiliary control voltage can also be provided by a voltage controlled circuit controlled by a switch.
  • the specific form may be: dividing the output frequency of the voltage controlled oscillator into a plurality of frequency intervals, each frequency interval corresponding to a unique auxiliary control voltage, and the voltage value of the specific auxiliary control voltage corresponding to the frequency interval is determined according to an actual circuit.
  • the trend of the auxiliary control voltage is the same as the overall trend of the target oscillation frequency, and therefore, it is the same as the overall trend of the frequency interval.
  • the switch of the voltage dividing circuit is turned off, the auxiliary control voltage is 2V, and the target oscillation frequency of the voltage controlled oscillator is within the range of 435-470 MHz, the partial voltage The circuit's switch is closed and the auxiliary control voltage is 4V.
  • the voltage controlled oscillator provided by the present invention shown in FIG. 3 has a voltage controlled oscillator as shown in FIG. Fast conversion speed.
  • the control voltage of the voltage controlled oscillator shown in 2 is required to reduce the equivalent capacitance of the voltage controlled oscillator by 6pF. Therefore, the control voltage of the voltage controlled oscillator shown in FIG. 3 is smaller than the control voltage of the voltage controlled oscillator shown in FIG. 2, and the time of the frequency conversion of the voltage controlled oscillator shown in FIG. short.
  • the frequency selective network circuit includes: a first inductor L2033, Second inductor L2043, third inductor L2035, fourth inductor L2034, first capacitor C2090, second capacitor C2139, third capacitor C2137, fourth capacitor C2135, fifth capacitor C2133, sixth capacitor C2084, seventh capacitor C2088, The eighth capacitor C2092, the ninth capacitor C2091, the first, second, third and fourth varactor groups and a magnetic bead L2053.
  • the first varactor tube set includes a first varactor tube D2021, and the second varactor tube group includes a second varactor tube
  • the voltage capacitance characteristics of D2020, D2021 and D2020 are the same.
  • the third varactor group includes a third varactor D2011 and a fourth varactor D2012 having the same voltage capacitance characteristics in parallel.
  • the fourth varactor group includes a parallel fifth varactor D2013 and a sixth varactor D2014 having the same voltage capacity characteristics.
  • the same voltage capacitance characteristics mean that the voltage capacitance characteristic curves are the same or similar, that is, when the same input voltage is used, the capacitance values of the varactors are equal or similar.
  • the second end of the first capacitor C2090 and the first end of the first inductor L2033 are connected to a control voltage.
  • the second end of the first inductor L2033, the first end of the fourth capacitor C2135 and the fifth capacitor C2133, and the cathodes of all the varactors D2011 and D2012 in the third varactor group are connected to the fourth varactor The negative poles of all varactors D2013 and D2014 in the group.
  • the first end of the magnetic bead L2053 and the second end of the second capacitor C2139 are connected to an auxiliary control voltage.
  • the second end of the magnetic bead L 2053 and the second end of the third capacitor C2137 are connected to the first end of the second inductor.
  • the second end of the second inductor L2043, the negative ends of all the varactors D2021 in the first varactor group, the second ends of the fourth capacitor C2135 and the fifth capacitor C2133 are connected to the second change The negative poles of all varactors D2020 in the volume group.
  • the positive poles of all the varactors D2020 in the second varactor group, the anodes of all the varactors D2011 and D2012, the sixth capacitor C2084 and the seventh capacitor C2088 in the third varactor group The end is connected to the second end of the third inductor L2035.
  • the sixth capacitor C2084, the seventh capacitor C2088, the eighth capacitor C2092, the second end of the ninth capacitor C2091, and the second end of the fourth inductor L2034 are connected to the active device circuit.
  • the active device circuit is operative to provide energy to the frequency selective network circuit that produces an oscillating frequency.
  • the first varactor set includes a first varactor D2021
  • the second varactor set includes a second varactor D2020 having the same voltage capacitance characteristics as the first varactor D2021.
  • the third varactor group includes a third varactor D201 1 and a fourth varactor D201 2 having the same voltage capacitance characteristics in parallel.
  • the fourth variable capacitor group includes a fifth varactor D201 3 and a sixth varactor D2014 having the same voltage capacitance characteristics in parallel.
  • the first varactor tube set includes at least one varactor tube in parallel; the second varactor tube group includes at least one varactor tube in parallel; and the third varactor tube group includes at least one varactor tube in parallel
  • the fourth varactor set includes at least one varactor in parallel.
  • the auxiliary control voltage is obtained based on the target oscillation frequency and a relationship between the preset frequency and the control voltage.
  • the design principle of the relationship between the preset frequency and the control voltage is such that when the frequency of the output changes constantly, the range of variation of the control voltage is reduced.
  • the change trend of the auxiliary control voltage is the same as the change trend of the target oscillation frequency of the frequency selective network circuit, and the auxiliary control voltage causes the equivalent capacitance value of the frequency selective network circuit to change C1, and the control voltage makes the
  • the sum of the equivalent capacitance values of the frequency selective network circuit C2, the sum of C1 and C2 is C3, and the C3 is the frequency of the signal generated by the frequency selective network circuit from the current frequency to the destination oscillation frequency,
  • the capacitance value of the equivalent capacitance value of the frequency selective network circuit; the absolute value of C 3 is greater than the absolute value of C2.
  • the auxiliary control voltage may be input to the frequency selective network circuit prior to the control voltage.
  • the auxiliary control voltage can be provided by a digital to analog conversion circuit (DAC) or a voltage division circuit controlled by a switch.
  • DAC digital to analog conversion circuit
  • the voltage controlled oscillator has two control voltage inputs, and a reasonable auxiliary control voltage input can be designed according to the output oscillation frequency, so that when the output oscillation frequency changes the same, the control voltage is The range of variation is smaller, thereby increasing the lock time of the frequency generating unit.
  • the oscillation frequency of the voltage controlled oscillator output shown in Figure 1 varies from 400MHz to 470MHz. Its control voltage input varies from 1 to 4V.
  • the oscillation frequency of the voltage controlled oscillator output provided by the present invention is changed from 400 MHz to 470 MHz, the target variation range of the control voltage input is
  • the voltage controlled oscillator provided by the present invention has a relatively fast frequency conversion speed.
  • the structure of the voltage controlled oscillator shown in 4 discusses the magnitude of its phase noise.
  • the diode can change the width of the space charge region by applying a reverse voltage, thereby changing the size of the barrier capacitance.
  • a varactor diode, a varactor, is a special ⁇ junction diode made with this characteristic.
  • the voltage controlled oscillator shown in Figure 4 introduces the reverse current of the varactor.
  • Figure 5 shows the relationship between the reverse voltage of the varactor and the reverse current. It can be seen that the reverse current of the varactor is small, so the voltage controlled oscillator shown in Figure 4 does not cause additional current during application.
  • Figure 6 shows the relationship between the internal resistance of the varactor and the reverse voltage.
  • the control voltage of the voltage-controlled oscillator shown in Figure 2 is 400-470 ⁇ . The control voltage varies from 1-4V.
  • the voltage-controlled oscillation shown in Figure 4 5 ⁇ 3. 5V, and as can be seen from Figure 6, with Figure 4, the auxiliary control voltage obtained by the design of the voltage curve can be achieved when the signal of the same frequency is output.
  • the control voltage of the voltage controlled oscillator is increased, the internal resistance of the varactor is greatly reduced, and the lower the internal resistance of the varactor, the higher the Q value of the circuit, plus the external voltage applied to the varactor Above, due to the presence of the access capacitor, the Q value of the voltage controlled oscillator is not greatly reduced by the external voltage. Therefore, the voltage controlled oscillator shown in Figure 4 is realized by its high Q value. Optimization of phase noise.
  • the voltage controlled oscillator shown in Figure 4 can increase the frequency variation range to a certain extent, and can appropriately reduce the voltage control sensitivity (KV) value within the range of acceptable lock time, and can also reduce the phase noise thereof.
  • the voltage controlled oscillator shown in FIG. 4 can achieve faster frequency conversion speed and achieve smaller phase noise by using an auxiliary control voltage obtained by a preset relationship between the frequency and the control voltage.
  • the present invention also provides a method for frequency locking.
  • the method includes: S701: The control unit generates an auxiliary voltage corresponding to the target oscillation frequency according to a preset relationship between the frequency and the control voltage.
  • the auxiliary voltage is input to the voltage controlled oscillator provided by the present invention as an auxiliary control voltage of the voltage controlled oscillator; the auxiliary control voltage causes an equivalent capacitance value of the frequency selective network circuit in the voltage controlled oscillator to change Cl.
  • S702 The loop filter inputs a control voltage to the voltage controlled oscillator, and the control voltage changes an equivalent capacitance value of the frequency selective network circuit by C2.
  • the frequency output by the voltage controlled oscillator is taken as the locked frequency after the time when the method is executed reaches the preset lock time.
  • steps S702 and S701 are not limited, and a preferred execution order is that S701 is executed prior to S702.
  • C3 is a capacitance value of the equivalent capacitance value of the frequency selective network circuit when the frequency of the signal generated by the frequency selective network circuit changes from the current frequency to the target oscillation frequency;
  • the absolute value is greater than the absolute value of C2.
  • the relationship between the preset frequency and the control voltage is set such that when the oscillation frequency of the voltage controlled oscillator is changed, the variation range of the control voltage becomes small.
  • the auxiliary control voltage can be provided by a DAC circuit or a switch-controlled voltage dividing circuit.
  • the reference signal may be provided by a reference crystal capable of producing a certain oscillation frequency.
  • control voltage can be generated by the following steps:
  • the control unit generates a frequency setting signal based on the destination oscillation frequency and transmits the frequency setting signal to the phase locked loop circuit.
  • the phase-locked loop circuit After receiving the frequency setting signal, the phase-locked loop circuit obtains a comparison signal according to the output signal of the voltage controlled oscillator and the frequency setting signal, and obtains the contrast signal and the reference signal according to the comparison signal and the reference signal.
  • the phase difference error voltage signal is output to the loop filter.
  • the loop filter performs filtering processing on the error voltage signal as a control voltage.
  • the phase locked loop circuit obtains a comparison signal according to the output signal of the voltage controlled oscillator and the frequency setting signal, according to the comparison
  • the signal and the reference signal obtain an error voltage signal reflecting a phase difference between the comparison signal and the reference signal, and output the error voltage signal to a loop filter.
  • the frequency setting signal may be a frequency dividing ratio
  • the phase locked loop circuit obtains a comparison signal according to the output signal of the voltage controlled oscillator and the frequency setting signal, including: the phase locked loop circuit controls the voltage according to the frequency dividing ratio The output signal of the oscillator is divided, and the divided signal is used as a comparison signal.
  • the voltage controlled oscillator provided by the present invention is used. Therefore, by designing a reasonable auxiliary control voltage, the oscillation frequency of the voltage controlled oscillator is changed to a certain value, and the frequency locking is shorter. Lock time and faster lock speed.
  • the method further includes: the control unit applies a preset voltage output by the voltage pre-configuration circuit to the loop filter to charge the capacitor in the loop filter in a first period of time;
  • the configuration circuit includes a diode whose forward voltage drop decreases with increasing temperature for outputting a preset voltage that increases with increasing temperature.
  • the control unit cuts off the preset voltage provided by the voltage pre-configuration circuit for the loop filter after the first period of time.
  • the method further includes:
  • the control unit turns on the fast lock function of the phase locked loop circuit, and sends a fast lock signal generated by the phase locked loop circuit to the loop filter in a second time period after the first time period.
  • the present invention also provides a frequency generating unit comprising: a control unit 801, a phase locked loop circuit 802, a loop filter 803, and a voltage controlled oscillator 804 provided by the present invention.
  • the control unit 801 is configured to generate a frequency setting signal according to the target oscillation frequency, and send the frequency setting signal to the phase locked loop circuit 802, and generate an auxiliary corresponding to the target oscillation frequency according to a relationship between the preset frequency and the control voltage.
  • a voltage, and the auxiliary voltage is input to the voltage controlled oscillator 804 as an auxiliary control voltage; the auxiliary control voltage causes an equivalent capacitance value of the frequency selective network circuit in the voltage controlled oscillator 804 to change by Cl.
  • the phase-locked loop circuit 802 obtains a comparison signal according to the output signal of the voltage-controlled oscillator 804 and the frequency setting signal, and obtains an error voltage signal reflecting a phase difference between the comparison signal and the reference signal according to the comparison signal and the reference signal.
  • the voltage controlled oscillator 804 sends an output signal generated by the voltage controlled oscillator 804 to the phase locked loop circuit 802.
  • the signal generated by the voltage controlled oscillator 804 having a certain oscillation frequency is the frequency signal generated by the frequency generating unit provided in this embodiment.
  • C3 is a capacitance value of the equivalent capacitance value of the frequency selective network circuit when the frequency of the signal generated by the frequency selective network circuit changes from the current frequency to the target oscillation frequency.
  • the absolute value of C3 is greater than the absolute value of C2.
  • the control unit may include a digital-to-analog conversion circuit, and the digital-to-analog conversion circuit is configured to generate an auxiliary voltage corresponding to the target oscillation frequency according to a preset relationship between the frequency and the control voltage, and use the auxiliary voltage as the auxiliary control voltage. Input to the voltage controlled oscillator.
  • the control unit may include a switch-controlled voltage dividing circuit; the voltage dividing circuit is configured to generate an auxiliary voltage corresponding to the target oscillation frequency according to a preset relationship between the frequency and the control voltage, and use the auxiliary voltage as an auxiliary control A voltage is input to the voltage controlled oscillator.
  • the control unit can include a CPU.
  • the frequency setting signal may be a frequency dividing ratio
  • the phase-locked loop circuit 802 obtains a comparison signal according to the output signal of the voltage-controlled oscillator 804 and the frequency setting signal, including: the phase-locked loop circuit 802 is divided into The frequency ratio divides the output signal of the voltage controlled oscillator 804, and the divided signal is used as a comparison signal.
  • the phase-locked loop circuit can be a phase-locked loop integrated chip, and the phase detector and the frequency divider are integrated.
  • the reference signal may be provided by a reference crystal capable of producing a certain oscillation frequency.
  • the voltage controlled oscillator and the phase locked loop circuit can be connected through a feedback circuit.
  • the auxiliary control voltage In the case of meeting all the requirements of the frequency generating unit, the auxiliary control voltage
  • the design principle is to minimize the range of control voltage variations.
  • the indicator requirements here can be set manually according to the requirements of the system.
  • the frequency generating unit further comprises: a voltage pre-configuration circuit comprising a diode whose forward voltage drop decreases with an increase in temperature, for outputting a preset voltage that increases with an increase in temperature.
  • a voltage pre-configuration circuit comprising a diode whose forward voltage drop decreases with an increase in temperature, for outputting a preset voltage that increases with an increase in temperature.
  • the control unit is further configured to apply a preset voltage output by the voltage pre-configuration circuit to the loop filter, charge the capacitor in the loop filter, and in the first period After a period of time, the voltage pre-configuration circuit is turned off to provide a preset voltage for the loop filter.
  • the frequency generating unit further includes a first switch and a second switch;
  • the control unit is further configured to enable a fast lock function of the phase locked loop circuit.
  • a first switch connected between the voltage pre-configuration circuit and the loop filter, configured to be turned on after receiving the pre-configured control signal sent by the control unit in a first time period, and the voltage is turned on A preset voltage provided by the pre-configuration circuit is applied to the loop filter.
  • a second switch connected between the fast lock control end of the phase locked loop circuit and the loop filter, configured to send the control unit in a second time period after the first time period After the lock control signal is turned on, the fast lock signal generated by the phase locked loop circuit is sent to the loop filter.
  • FIG. 9 is a structural diagram of a system including a frequency generating unit, which mainly includes: a CPU (OMAP) 901, a phase locked loop circuit (PLL IC) Sky72310 902, a loop filter (LPF) 903, and a voltage controlled oscillator ( VCO) 904, VCO to PLL IC feedback circuit (BPF) 905, buffer circuit (Buffer) 906, digital to analog conversion circuit (DAC) 907, phase locked loop reference crystal (VC_TCXO) 908, voltage switch 1 (Swithl) 909 , voltage switch 2 (Swith2) 910 and voltage pre-configuration circuit (Pre-Setup - CV) 911.
  • VCO904 is the VCO provided by the present invention
  • DAC907 provides auxiliary control voltage for VCO904.
  • Figure 10 is a circuit connection diagram of the Sky72310 902, LPF903, BPF905, and VC-TCXO908 in the system shown in Figure 9.
  • FIG. 11 is a flow chart showing the operation of the system shown in Figure 9. Specifically include:
  • S1101 When the device is powered on or switches channels, the DAC first outputs the corresponding auxiliary control voltage to the VCO according to the frequency information, which is usually short.
  • S1102 The PLPIC is configured with the frequency information required for locking, and the fast lock function of the PLLIC is turned on at the same time, but due to the isolation of the switch 2, the fast lock function is not applied to the loop filter.
  • S1103 Turn on the preset voltage switch 1 for tl time and preset a fixed voltage to the loop filter.
  • S1104 Turn off the voltage switch 1 and turn on the switch 2 for t2 time. At this time, the fast lock function of the PLL acts on the loop filter to speed up the lock.
  • S1106 Switch the fast lock mode of the PLL to the lock detection mode to make the system shown in Figure 9 lock normally.
  • the length of the tl time and the length of the t2 directly determine the overcharge of the loop filter and the lock time. Therefore, it is necessary to control the length of time t1 and t2 according to the final lock time to reduce the overshoot.
  • the voltage preset by the preset voltage circuit depends on the range of CV variation.
  • the preset voltage is selected as the intermediate value of CV.
  • the preset voltage is selected as 2.5V.
  • the specific voltage of the preset voltage can be appropriately adjusted. value.
  • Table 1 shows the frequency lock time, phase noise, and phase margin at different temperatures when the system shown in Fig. 9 is used and the frequency lock operation process shown in Fig. 11 is used, in which the system
  • the voltage controlled oscillator is the voltage controlled oscillator shown in FIG.
  • Table 2 shows the frequency locking time at different temperatures when the system structure shown in Fig. 9 is used and the frequency locking operation process shown in Fig. 11 is used, wherein the voltage controlled oscillator used in the system is as shown in Fig. 2. Voltage controlled oscillator.
  • Table 3 shows the structure of the system shown in Figure 9, but the phase-locked loop integrated circuit does not have the fast lock function, the frequency lock time at different temperatures, and the voltage-controlled oscillator used in the frequency generating unit is Figure 2.

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Description

一种对频率锁定的方法、 一种压控振荡器以及频率产生单元
技术领域
本发明涉及通信技术领域， 尤其是涉及一种对频率锁定的方法、 一种 压控振荡器以及频率产生单元。
背景技术
频率产生单元在现代通信系统和信息处理系统中十分重要。 作为射频 通信系统发射接收机的本地振荡源和数字信号处理系统的时钟源， 频率产 生单元的性能指标直接影响到了射频通信系统以及数字信号处理系统的 ' 1·生 能指标。 目前， 随着数据传输速度的提高， 频率产生单元的锁定时间成为 设计的关键指标之一。 频率产生单元的锁定时间越短， 则频率的转换速度 越快， 从而数据的传输速率也就越快。
频率产生单元主要包括压控振荡器 （ voltage-controlled oscillator， VC0 )、 环路滤波器 （LPF )、 锁相环集成电路（PLL IC )、 VC0至 PLL IC 的反馈带通 （BPF ) 以及锁相环参考晶体。 其中， 压控振荡器是频率产生 单元的重要组成部分之一，主要作用是根据输入电压输出相应的振荡频率。 目前， 频率产生单元的频率锁定时间较长， 频率转换速度较慢， 影响了数 据的传输速率。
发明内容
本发明解决的技术问题在于提供一种对频率的锁定方法、 一种压控振 荡器以及频率产生单元， 在具有相应合理参数的情况下能够实现对频率锁 定时的锁定时间更短， 锁定速度更快。
为此， 本发明提供了一种压控振荡器， 所述压控振荡器包括选频网络电 路和有源器件电路。
所述选频网络电路具有控制电压输入和辅助控制电压输入， 其中， 所述辅 助控制电压的变化趋势与所述选频网络电路的目的振荡频率的变化趋势相同， 所述辅助控制电压使得所述选频网络电路的等效电容值变化 C1 , 控制电压使 得所述选频网络电路的等效电容值变化 C2 , C1与 C2之和为 C3 , 所述 C3为所 述选频网络电路产生的信号的频率从当前频率转变到目的振荡频率时，所述选 频网络电路的等效电容值变化的电容值； C3的绝对值大于 C2的绝对值。
所述选频网络电路用于根据控制电压和辅助控制电压产生振荡频率按照 控制电压和辅助控制电压而变化的信号。
所述有源器件电路用于向所述选频网络电路提供产生振荡频率的能量。 优选地， 所述辅助控制电压先于控制电压输入至所述选频网络电路。 优选地， 所述选频网络电路包括： 第一、 第二、 第三和第四电感、 第一、 第二、 第三、 第四、 第五、 第六、 第七、 第八和第九电容、 第一、 第二、 第三 和第四变容管组以及一磁珠。
所述第一变容管组包括并联的至少一个变容管。
所述第二变容管组包括并联的至少一个变容管。
所述第三变容管组包括并联的至少一个变容管。
所述第四变容管组包括并联的至少一个变容管。
所述第一、 第二、 第三、 第八和第九电容的第一端、 所述第一和第四变容 管组中全部变容管的正极以及所述第三和第四电感的第一端连接到地电压。
所述第一电容的第二端以及第一电感的第一端连接到控制电压。
所述第一电感的第二端、第四和第五电容的第一端以及第三变容管组中全 部变容管的负极连接到所述第四变容管组中全部变容管的负极。
所述磁珠的第一端以及所述第二电容的第二端连接到辅助控制电压。 所述磁珠的第二端以及所述第三电容的第二端连接到所述第二电感的第 一端。
所述第二电感的第二端、所述第一变容管组中全部变容管的负极以及所述 第四和第五电容的第二端连接到所述第二变容管组中全部变容管的负极。
所述第二变容管组中全部变容管的正极、所述第三变容管组中全部变容管 的正极以及所述第六和第七电容的第一端连接到所述第三电感的第二端。
所述第六、 第七、第八和第九电容的第二端以及所述第四电感的第二端连 接到所述有源器件电路。 优选地， 所述第一变容管组包括第一变容管。
所述第二变容管组包括与第一变容管电压容值特性相同的第二变容管。 所述第二变容管组包括并联的电压容值特性相同的第三和第四变容管。 所述第三变容管组包括并联的电压容值特性相同的第五和第六变容管。 优选地， 所述辅助控制电压由数模转换电路或开关控制的分压电路提供。 本发明还提供了一种对频率锁定的方法， 所述方法包括：
控制单元根据预先设置的频率和控制电压的关系曲线，生成目的振荡频率 对应的辅助电压， 将辅助电压输入至本发明提供的压控振荡器，作为所述压控 振荡器的辅助控制电压； 环路滤波器将控制电压输入至所述压控振荡器。
所述辅助控制电压使得所述压控振荡器中的选频网络电路的等效电容值 变化 C1 , 控制电压使得所述选频网络电路的等效电容值变化 C2。
在所述方法执行的时间到达预设的锁定时间后将所述压控振荡器输出的 频率作为锁定后的频率。
C1与 C2之和为 C 3 , 所述 C 3为所述选频网络电路产生的信号的频率从当 前频率转变到目的振荡频率时， 所述选频网络电路的等效电容值变化的电容 值； C 3的绝对值大于 C2的绝对值。
优选地， 所述方法还包括：
控制单元在第一时间段内将电压预配置电路输出的预置电压施加到环路 滤波器， 为所述环路滤波器中的电容充电； 所述电压预配置电路包括正向压降 随温度升高而降低的二极管， 用于输出随温度升高而增加的预置电压。
控制单元在所述第一时间段后切断电压预配置电路为环路滤波器提供的 预置电压。
优选地， 所述方法还包括：
所述控制单元开启所述锁相环电路的快锁功能，并在第一时间段后的第二 时间段将所述锁相环电路产生的快锁信号发送给所述环路滤波器。
本发明还提供了一种频率产生单元，其特征在于，所述频率产生单元包括： 控制单元、 锁相环电路、 环路滤波器以及本发明提供的压控振荡器。 所述控制单元用于根据目的振荡频率生成频率设置信号，并向锁相环电路 发送所述频率设置信号， 以及根据预先设置的频率和控制电压的关系曲线， 生 成目的振荡频率对应的辅助电压，并将辅助电压作为辅助控制电压输入至所述 压控振荡器；所述辅助控制电压使得所述压控振荡器中的选频网络电路的等效 电容值变化 Cl。
所述锁相环电路根据压控振荡器的输出信号和所述频率设置信号得到对 比信号，根据所述对比信号和参考信号得到反映所述对比信号和参考信号的相 位差的误差电压信号， 并输出所述误差电压信号至环路滤波器， 所述误差电压 信号经所述环路滤波器滤波处理后输入所述压控振荡器，作为所述压控振荡器 的控制电压； 控制电压使得所述选频网络电路的等效电容值变化 C2。
所述压控振荡器将所述压控振荡器产生的信号发送至所述锁相环电路。 其中， C1和 C2之和为 C3 , 所述 C3为所述选频网络电路产生的信号的频 率从当前频率转变到目的振荡频率时，所述选频网络电路的等效电容值变化的 电容值； C3的绝对值大于 C2的绝对值。
优选地， 所述控制单元包括数模转换电路； 所述数模转换电路用于根据预 先设置的频率和控制电压的关系曲线， 生成目的振荡频率对应的辅助电压， 并 将所述辅助电压作为辅助控制电压输入至所述压控振荡器。
优选地， 所述控制单元包括开关控制的分压电路； 所述分压电路用于根据 预先设置的频率和控制电压的关系曲线， 生成目的振荡频率对应的辅助电压， 并将所述辅助电压作为辅助控制电压输入至所述压控振荡器。
优选地， 所述频率产生单元还包括： 电压预配置电路， 包括正向压降随温 度升高而降低的二极管， 用于输出随温度升高而增加的预置电压。
所述控制单元还用于在第一时间段内将电压预配置电路输出的预置电压 施加到所述环路滤波器， 为所述环路滤波器中的电容充电， 以及在所述第一时 间段后切断电压预配置电路为环路滤波器提供的预置电压。
优选地， 所述频率产生单元还包括第一开关和第二开关。
所述控制单元还用于开启所述锁相环电路的快锁功能。
第一开关， 连接在所述电压预配置电路和所述环路滤波器之间， 用于在接 收所述控制单元在第一时间段内发送的预配置控制信号后接通，将所述电压预 配置电路提供的预置电压施加给所述环路滤波器。
第二开关， 连接在所述锁相环电路的快锁控制端和所述环路滤波器之间， 用于在接收所述控制单元在第一时间段后的第二时间段内发送的快锁控制信 号后接通， 将所述锁相环电路产生的快锁信号发送给所述环路滤波器。
由上述技术方案可以看出， 控制单元生成的辅助控制电压使得压控振荡 器中选频网络电路的等效电容值变化 C 1 , 而控制电压使得所述选频网络电路 的等效电容值变化 C2 , C1与 C2之和为 C 3 , 所述 C 3为所述选频网络电路产生 的信号的频率从当前频率转变到目的振荡频率时，所述选频网络电路的等效电 容值变化的电容值； C 3的绝对值大于 C2的绝对值。 可见控制电压只需使得所 述选频网络电路的等效电容值变化 C2 , 相比于没有辅助控制电压的情况， 即 相比于控制电压需使得所述选频网络电路的等效电容值变化 C 3时， 本发明中 控制电压的变化范围更小， 又由于在压控振荡器的周围环境因素相同时， 频率 锁定的时间取决于控制电压的变化范围， 因此， 本发明实现的频率产生单元 能够使得在压控振荡器的周围环境因素相同并且压控振荡器输出的振荡频 率变化一定时， 控制电压变化的差值减小， 从而实现对频率锁定的速度更 快， 锁定时间更短。
附图说明
图 1为频率锁定过程阶段图；
图 2为现有技术中的压控振荡器；
图 3为本发明提供的压控振荡器的系统结构图
图 4为本发明提供的压控振荡器的一具体电路图；
图 5为变容管反向电压与反向电路的关系曲线；
图 6为变容管反向电压与电阻的关系曲线；
图 7为本发明提供的频率锁定方法的流程图；
图 8为本发明提供的频率产生单元的结构图；
图 9为包括频率产生单元的系统的结构图；
图 10为图 8所示的系统的电路图； 图 11为图 8所示的系统的工作流程图。
具体实施方式
请参阅图 1 , 频率锁定过程分为三个阶段：
Tl : Capture Phase (捕获阶段)： 由于频点的切换， 频率从稳定到不稳 定的急剧变化， 输出频率与参考时钟的鉴相频率相位差非常大， 锁相环处 于失锁状态， 需要大量的泵电流来捕获目标频率。
T2 : Track Phase (跟踪阶段)：输出频率与参考时钟鉴相频率相位差较 小， 锁相环对输出频率进行跟踪， 属于环路自身调节的阶段。
T3 : Stable Phase (稳定阶段)：输出频率与参考时钟鉴相频率相位差非 常小， 锁相环处于锁定的状态。 当频率偏差小于 ± 100Hz 时， 锁相环进入 稳定状态。
可以看出， 锁定过程的三个阶段中， 主要是由 T1和 T2阶段决定目标 频率的锁定时间。 而 T2的时间主要是由于环路自身的参数决定。 T2时， 相位差已经比较小了， 靠锁相环自身的调节可以很快进入 T3。 Tl捕获阶段 所消耗的时间， 对整体锁定时间起直接的影响。 因此本发明主要通过减少 T1捕获阶段所消耗的时间， 从而减小整体锁定时间。
图 2为一种常用的压控振荡器， 由于当变容管两端的电压值发生变化 时其电容值也发生变化， 因此当控制电压 （Control Voltage , CV ) 的值改 变时， 其 LC谐振回路电容值也发生改变， 根据/ = 1/27Γ , 可见其输出 的振荡频率也发生相应的变化。 因此， 压控振荡器输出的振荡频率的值由 其输入的控制电压决定， 振荡频率转换的差值一定时， 输入的控制电压的 差值也确定。 其中， f为压控振荡器产生的信号的频率， L为压控振荡器的 等效电感值， C为压控振荡器的等效电容值。 设 为电容上的初始电压值， 为电容最终可充电或放电得到的 电压值， 电容两端的 电压值到达 t 所需的时间 为 t , 则有 Vt = V0 + (VI - 0) X [1 - Qxp(-t I RQ] ? ? t = RCx ln[( VI - V0) l{V\ - Vt)] ? 如上 可见， 在 不变以及其它条件相同时， 电容两端的电压值到达 W时所需 的时间 t由控制电压的差值 AC = V \ - V0决定。 由此可见，压控振荡器的 控制电压变化时， 输出稳定的输出频率所需的时间由控制电压的差值 AC 决定。
综上可见， 釆用图 2所示的压控振荡器实现对频率锁定时， 其它条件 确定时， 压控振荡器产生的振荡频率变化一定时， 需输入的控制电压的变 化也一定， 因此频率转换所需的时间也是确定的， 即对频率锁定的锁定时 间确定。 其它条件指的是压控振荡器的周围环境因素， 包括温度等。
请参阅图 3 , 本发明提供了一种压控振荡器， 所述压控振荡器包括选频 网络电路 301和有源器件电路 302。
所述选频网络电路 301具有控制电压输入和辅助控制电压输入， 其中， 所 述辅助控制电压的变化趋势与所述选频网络电路的目的振荡频率的变化趋势 相同， 所述辅助控制电压使得所述选频网络电路的等效电容值变化 C1 , 控制 电压使得所述选频网络电路的等效电容值变化 C2 , C1与 C2之和为 C3 , 所述 C3 为所述选频网络电路产生的信号的频率从当前频率转变到目的振荡频率 时， 所述选频网络电路的等效电容值变化的电容值； C3的绝对值大于 C2的绝 对值， 即 | C3 | > | C2 |。
所述选频网络电路 301 用于根据控制电压和辅助控制电压产生振荡频率 按照控制电压和辅助控制电压而变化的信号。 能量。
本发明中提到的辅助控制电压与控制电压是两种不同的控制电压。
并且在该实施例中， 电容变化的差值 Cl、 C2和 C3均为矢量， 若选频网络 电路的等效电容值增大时，电容变化的差值为负数，则在该等效电容值减小时， 电容变化的差值为正数。 若选频网络电路的等效电容值减小时， 电容变化的差 值为正数， 则在该等效电容值增大时， 电容变化的差值为负数。
其中， 目的振荡频率， 即所要获得的振荡频率。 在压控振荡器的具体应用 中， 为产生具有一定的振荡频率的信号，将需要获得的振荡频率作为压控振荡 器中的选频网络电路的目的振荡频率。 目的振荡频率可根据实际情况确定。 所述辅助控制电压可以先于控制电压输入至所述选频网络电路 301。
其中， 所述辅助控制电压可以由数模转换电路（DAC )提供。
所述辅助控制电压也可以由开关控制的分压电路提供。具体提供形式可以 为： 将压控振荡器输出频率分为若干个频率区间，每个频率区间对应唯一的辅 助控制电压，而频率区间对应的具体的辅助控制电压的电压值根据实际电路确 定。 并且， 辅助控制电压的变化趋势与目的振荡频率的整体趋势相同， 因此， 与频率区间的整体趋势相同。例如，压控振荡器的目的振荡频率在 400-435MHZ 区间内时， 分压电路的开关断开， 辅助控制电压为 2V , 压控振荡器的目的振 荡频率在 435-470MHZ区间内时， 分压电路的开关闭合， 辅助控制电压为 4V。
下面举例说明在压控振荡器的周围环境因素相同时，釆用图 3所示的本发 明提供的压控振荡器相比图 2所示的压控振荡器， 在频率转换一定时， 具有更 快的转换速度。
釆用图 1所示的压控振荡器， 当前频率为 400MHz时， 压控振荡器的等效 电容值为 20pF , 当目的振荡频率为 470MHz时， 压控振荡器的等效电容值需减 小 6pF , 即则图 2所示的压控振荡器的控制电压的变化需使得压控振荡器的等 效电容值从减小 6pF。 当釆用图 3所示的压控振荡器时， 压控振荡器当前频率 为 400MHz 时， 压控振荡器的等效电容值为 20pF , 当目的振荡频率为 470MHz 时， 压控振荡器的等效电容值需减小 6pF , 即 C3=-6Pf。 而图 3所示的压控振 荡器的辅助控制电压可以使得压控振荡器的等效电容值从减小 5pF , 即 Cl=-5Pf , 控制电压只需使得压控振荡器的等效电容值减小 l pF 即可， 即 C2=-lPf。 从而可以看出， 当压控振荡器的输出频率从 400MHz变化到 470MHz 时， 图 3所示的压控振荡器的控制电压只需使得压控振荡器的等效电容减小 1 pF , 而图 2 所示的压控振荡器的控制电压需使得压控振荡器的等效电容减小 6pF。 因此， 图 3所示压控振荡器的控制电压相比于图 2所示的压控振荡器的 控制电压， 变化范围更小， 则图 3所示的压控振荡器频率转换时的时间更短。
图 4为本发明提供的压控振荡器的具体实施例的电路连接图，该实施例包 括选频网络电路和有源器件电路。其中，选频网络电路包括： 第一电感 L2033、 第二电感 L2043、 第三电感 L2035、 第四电感 L2034、 第一电容 C2090、 第二 电容 C2139, 第三电容 C2137, 第四电容 C2135, 第五电容 C2133, 第六电容 C2084, 第七电容 C2088、 第八电容 C2092、 第九电容 C2091、 第一、 第二、 第 三和第四变容管组以及一磁珠 L2053。
第一变容管组包括第一变容管 D2021, 第二变容管组包括第二变容管
D2020, D2021和 D2020的电压容值特性相同。 第三变容管组包括并联的电压 容值特性相同的第三变容管 D2011和第四变容管 D2012。 第四变容管组包括并 联的电压容值特性相同的第五变容管 D2013和第六变容管 D2014。 电压容值特 性相同指的是电压容值特性曲线相同或相近， 即在具有相同输入电压时， 变容 管的电容值相等或相近。
所述第一电容 C2090、 第二电容 C2139、 第三电容 C2137、 第八电容 C2092 和第九电容 C2091的第一端、 所述第一和第四变容管组中全部变容管 D2021、 D2013以及 D2014的正极以及所述第三电感 L2035和第四电感 L2034的第一端 连接到地电压。
所述第一电容 C2090的第二端以及第一电感 L2033的第一端连接到控制电 压。
所述第一电感 L2033的第二端、第四电容 C2135和第五电容 C2133的第一 端以及第三变容管组中全部变容管 D2011和 D2012的负极连接到所述第四变容 管组中全部变容管 D2013和 D2014的负极。
所述磁珠 L2053的第一端以及所述第二电容 C2139的第二端连接到辅助控 制电压。
所述磁珠 L 2053的第二端以及所述第三电容 C2137的第二端连接到所述第 二电感的第一端。
所述第二电感 L2043 的第二端、 所述第一变容管组中全部变容管 D2021 的负极、所述第四电容 C2135和第五电容 C2133的第二端连接到所述第二变容 管组中全部变容管 D2020的负极。
所述第二变容管组中全部变容管 D2020的正极、所述第三变容管组中全部 变容管 D2011和 D2012的正极、所述第六电容 C2084和第七电容 C2088的第一 端连接到所述第三电感 L2035的第二端。
所述第六电容 C2084、 第七电容 C2088、 第八电容 C2092、 第九电容 C2091 的第二端以及所述第四电感 L2034的第二端连接到所述有源器件电路。
所述有源器件电路用于向所述选频网络电路提供产生振荡频率的能量。 在该实施例中， 第一变容管组包括第一变容管 D2021 , 第二变容管组包括 与第一变容管 D2021电压容值特性相同的第二变容管 D2020。 第三变容管组包 括并联的电压容值特性相同的第三变容管 D201 1和第四变容管 D201 2。 第四变 容管组包括并联的电压容值特性相同的第五变容管 D201 3 和第六变容管 D2014。 在其它实施例中， 第一变容管组包括并联的至少一个变容管； 第二变 容管组包括并联的至少一个变容管； 第三变容管组包括并联的至少一个变容 管； 所述第四变容管组包括并联的至少一个变容管。
辅助控制电压根据目的振荡频率以及预先设置的频率和控制电压的关系 曲线获得。 其中，预先设置的频率和控制电压的关系曲线的设计原则为使得输 出的频率变化一定时， 控制电压的变化范围减小。
其中，所述辅助控制电压的变化趋势与所述选频网络电路的目的振荡频率 的变化趋势相同，所述辅助控制电压使得所述选频网络电路的等效电容值变化 C1 , 控制电压使得所述选频网络电路的等效电容值变化 C2 , C1 与 C2之和为 C 3 , 所述 C 3为所述选频网络电路产生的信号的频率从当前频率转变到目的振 荡频率时， 所述选频网络电路的等效电容值变化的电容值； C 3 的绝对值大于 C2的绝对值。
所述辅助控制电压可以先于控制电压输入至所述选频网络电路。
其中， 所述辅助控制电压可以由数模转换电路（DAC )或开关控制的分压 电路提供。
可以看出。 图 3和图 4所示的实施例中，压控振荡器具有两个控制电压输 入， 可根据输出的振荡频率设计出合理的辅助控制电压输入，使得输出的振荡 频率变化相同时，控制电压的变化范围更小，从而提高频率产生单元的锁定时 间。
例如， 图 1 所示的压控振荡器输出的振荡频率从 400MHz 变化到 470MHz 时， 其控制电压输入的变化范围为 1_4V。 设置本发明提供的压控振荡器输出 的振荡频率从 400MHz 变化到 470MHz 时， 其控制电压输入的目标变化范围为
2. 5V-3. 5V, 根据控制电压的目标变化范围设计辅助控制电压与输出频率相关 的电压曲线， 预先设置的使得根据该设计好的电压曲线得到的辅助控制电压， 使得控制电压的变化范围为 2. 5V到 3. 5就能实现输出的振荡频率从 400MHz 变化到 470MHz。 根据公式 =
Figure imgf000013_0001
0) /(Π— 可知， 控制电压的变 化范围越小， 其锁定的时间越短。 因此， 在本发明提供的压控振荡器中， 根 据该设计好的电压曲线得到的辅助控制电压， 能够减小控制电压的变化范围， 从而实现本发明提供的压控振荡器的频率转换的速度更快。其中，设计好的电 压曲线可以线性， 也可以为非线性的。 这里， 设计好的电压曲线为本发明中提 到的预先设置的频率和控制电压的关系曲线。
综上可见本发明提供的压控振荡器具有较快的频率转换速度，下面根据图
4所示的压控振荡器的结构讨论其相位噪声的大小。
二极管通过外加反向电压可以改变空间电荷区的宽度，从而改变势垒电容 的大小。 变容二极管， 即变容管， 就是利用这种特性制成的特殊的 ΡΝ结二极 管。 图 4所示的压控振荡器引入的是变容管的反向电流。
图 5为变容管的反向电压与反向电流的关系。可以看出， 变容管的反向电 流很小， 因此图 4所示的压控振荡器在应用过程中不会造成额外的电流。 图 6 为变容管的内阻与反向电压的关系， 而图 2 所示的压控振荡器中输出 400-470ΜΗΖ时的控制电压变化范围为 1-4V, 图 4所示的压控振荡器中， 通过 设计好的电压曲线得到的辅助控制电压，能够实现输出相同频率的信号时的控 制电压变化范围为 2. 5V到 3. 5V, 而从图 6中可以看出， 随着图 4所示的压控 振荡器的控制电压的增大， 变容管的内阻大幅降低， 而由于变容管内阻越低， 则电路的 Q值越高， 再加上外部电压加在变容管上， 由于接入电容的存在， 压 控振荡器的 Q值不会因为外部电压的接入而大幅降低， 因此， 图 4所示的压控 振荡器通过其具有的较高的 Q值实现了对相位噪声的优化。
此外， 图 4所示的压控振荡器在一定程度上可以提高其频率变化范围， 可 以在能够接受的锁定时间的范围内， 适当降低压控灵敏度（KV )值， 同样可以 减小其相位噪声。 综上， 图 4所示的压控振荡器， 通过预先设置的频率和控制电压的关系 曲线得到的辅助控制电压，能够实现更快的频率转换速度以及实现更小的相位 噪声。
本发明还提供了一种对频率锁定的方法， 请参阅图 7 , 所述方法包括： S701 : 控制单元根据预先设置的频率和控制电压的关系曲线， 生成目的振 荡频率对应的辅助电压， 将所述辅助电压输入至本发明提供的压控振荡器，作 为所述压控振荡器的辅助控制电压；所述辅助控制电压使得所述压控振荡器中 的选频网络电路的等效电容值变化 Cl。
S702: 环路滤波器将控制电压输入至所述压控振荡器， 该控制电压使得所 述选频网络电路的等效电容值变化 C2。
在所述方法执行的时间到达预设的锁定时间后将所述压控振荡器输出的 频率作为锁定后的频率。
步骤 S702和 S701的执行顺序不受限定， 一种较优的执行顺序是 S701先 于 S702执行。
C1与 C2之和为 C3 , 所述 C3为所述选频网络电路产生的信号的频率从当 前频率转变到目的振荡频率时， 所述选频网络电路的等效电容值变化的电容 值； C3的绝对值大于 C2的绝对值。
其中，所述预先设置的频率和控制电压的关系曲线的设置目的是使得压控 振荡器的振荡频率转变一定时， 控制电压的变化范围变小。
辅助控制电压可以由一 DAC电路或一开关控制的分压电路提供。
所述参考信号可以由能够产生一定的振荡频率的参考晶体提供。
而在该实施例中， 控制电压可以通过以下步骤生成：
控制单元根据目的振荡频率生成频率设置信号并将所述频率设置信号发 送至锁相环电路。
所述锁相环电路接收到所述频率设置信号后， 根据压控振荡器的输出信 号和所述频率设置信号得到对比信号，根据所述对比信号和参考信号得到反映 所述对比信号和参考信号的相位差的误差电压信号，并将所述误差电压信号输 出至环路滤波器。 所述环路滤波器将所述误差电压信号进行滤波处理后作为控制电压。
并且将通过以上步骤生成的控制电压输入至所述压控振荡器后， 返回执 行：锁相环电路根据所述压控振荡器的输出信号和所述频率设置信号得到对比 信号，根据所述对比信号和参考信号得到反映所述对比信号和参考信号的相位 差的误差电压信号， 并将所述误差电压信号输出至环路滤波器。
其中， 所述频率设置信号可以为分频比， 则锁相环电路根据所述压控振荡 器的输出信号和所述频率设置信号得到对比信号包括：锁相环电路根据分频比 对压控振荡器的输出信号进行分频， 将分频后信号作为对比信号。
图 7所示的对频率锁定的方法中，使用了本发明提供的压控振荡器， 因此 通过设计合理的辅助控制电压，使得压控振荡器的振荡频率改变一定时， 实现 对频率锁定更短的锁定时间和更快的锁定速度。
优选地， 所述方法还包括： 控制单元在第一时间段内将电压预配置电路输 出的预置电压施加到环路滤波器， 为所述环路滤波器中的电容充电； 所述电压 预配置电路包括正向压降随温度升高而降低的二极管，用于输出随温度升高而 增加的预置电压。
控制单元在所述第一时间段后切断电压预配置电路为环路滤波器提供的 预置电压。
优选地， 所述方法还包括：
所述控制单元开启所述锁相环电路的快锁功能，并在第一时间段后的第二 时间段将所述锁相环电路产生的快锁信号发送给所述环路滤波器。
请参阅图 8 ,本发明还提供了一种频率产生单元，所述频率产生单元包括： 控制单元 801、 锁相环电路 802、 环路滤波器 803以及本发明提供的压控振荡 器 804。
所述控制单元 801用于根据目的振荡频率生成频率设置信号，并向锁相环 电路 802发送所述频率设置信号，以及根据预先设置的频率和控制电压的关系 曲线， 生成目的振荡频率对应的辅助电压， 并将所述辅助电压作为辅助控制电 压输入至所述压控振荡器 804 ; 所述辅助控制电压使得所述压控振荡器 804中 的选频网络电路的等效电容值变化 Cl。 所述锁相环电路 802根据压控振荡器 804的输出信号和所述频率设置信号 得到对比信号，根据所述对比信号和参考信号得到反映所述对比信号和参考信 号的相位差的误差电压信号， 并输出所述误差电压信号至环路滤波器 803 , 所 述误差电压信号经所述环路滤波器滤波处理后输入所述压控振荡器 804 , 作为 所述压控振荡器 804的控制电压；控制电压使得所述选频网络电路的等效电容 值变化 C2。
所述压控振荡器 804将所述压控振荡器 804产生的输出信号发送至所述锁 相环电路 802。
所述压控振荡器 804 产生的具有一定振荡频率的信号为该实施例提供的 频率产生单元所产生的频率信号。
其中， C1与 C2之和为 C3 , 所述 C3为所述选频网络电路产生的信号的频 率从当前频率转变到目的振荡频率时，所述选频网络电路的等效电容值变化的 电容值； C3的绝对值大于 C2的绝对值。
所述控制单元可以包括数模转换电路；所述数模转换电路用于根据预先设 置的频率和控制电压的关系曲线， 生成目的振荡频率对应的辅助电压， 并将所 述辅助电压作为辅助控制电压输入至所述压控振荡器。
所述控制单元可以包括开关控制的分压电路；所述分压电路用于根据预先 设置的频率和控制电压的关系曲线， 生成目的振荡频率对应的辅助电压， 并将 所述辅助电压作为辅助控制电压输入至所述压控振荡器。
控制单元可以包括 CPU。
其中， 所述频率设置信号可以为分频比， 则所述锁相环电路 802根据压控 振荡器 804的输出信号和所述频率设置信号得到对比信号包括：所述锁相环电 路 802根据分频比对压控振荡器 804的输出信号进行分频，将分频后信号作为 对比信号。
其中， 锁相环电路可以为锁相环集成芯片， 集成了鉴相器和分频器。 所述参考信号可以由能够产生一定的振荡频率的参考晶体提供。
压控振荡器和锁相环电路之间可通过反馈电路连接。
其中， 在满足频率产生单元所有指标要求的情况下， 辅助控制电压的 设计原则是使得控制电压变化范围尽量减小。 这里指标要求可以根据系统 的要求人为设定。
优选地， 所述频率产生单元还包括： 电压预配置电路， 包括正向压降随 温度升高而降低的二极管， 用于输出随温度升高而增加的预置电压。
则所述控制单元还用于在第一时间段内将电压预配置电路输出的预置电 压施加到所述环路滤波器， 为所述环路滤波器中的电容充电， 以及在所述第一 时间段后切断电压预配置电路为环路滤波器提供的预置电压。
优选地， 所述频率产生单元还包括第一开关和第二开关；
所述控制单元还用于开启所述锁相环电路的快锁功能。
第一开关， 连接在所述电压预配置电路和所述环路滤波器之间， 用于在接 收所述控制单元在第一时间段内发送的预配置控制信号后接通，将所述电压预 配置电路提供的预置电压施加给所述环路滤波器。
第二开关， 连接在所述锁相环电路的快锁控制端和所述环路滤波器之间， 用于在接收所述控制单元在第一时间段后的第二时间段内发送的快锁控制信 号后接通， 将所述锁相环电路产生的快锁信号发送给所述环路滤波器。
图 9为包括频率产生单元的系统的结构图， 该系统中主要包括： CPU ( OMAP ) 901 , 锁相环电路 ( PLL IC ) Sky72310 902、 环路滤波器 （ LPF ) 903、 压控振荡器 （VCO ) 904、 VCO至 PLL IC的反馈电路（ BPF ) 905、 緩冲电路 （Buffer ) 906、 数模转换电路 （ DAC ) 907、 锁相环参考晶体 (VC_TCXO)908、 电压开关 1 ( Swithl ) 909、 电压开关 2 ( Swith2 ) 910以 及电压预配置电路（Pre— Setup— CV ) 911。 其中， VCO904为本发明提供的 VCO, DAC907为 VCO904提供辅助控制电压。
图 10 为图 9 所示的系统中的 Sky72310 902、 LPF903、 BPF905、 VC— TCXO908的电路连接图。
其中 LPF903输出的电压作为控制电压发送至本发明提供的 VCO。 图 11为图 9所示的系统工作时的流程图。 具体包括：
S1101 : 当设备上电或者切换信道时， 首先 DAC根据频点信息给 VCO 输出相应的辅助控制电压， 这个时间通常 短。 S1102: 给 PLLIC配置锁定所需的频点信息， 同时打开 PLLIC的快锁 功能， 但是由于开关 2隔离， 快锁功能未加到环路滤波器上。
S1103: 打开预置电压开关 1 并持续 tl 时间， 给环路滤波器预置一个 固定电压。
S1104: 关闭电压开关 1 并打开开关 2, 使其持续 t2时间， 此时 PLL 的快锁功能作用到环路滤波器， 加快了锁定。
S1105: 关闭电压开关 2
S1106: 将 PLL的快锁模式切换为锁定检测模式， 使图 9所示的系统 实现正常锁定。
在整个过程中， tl时间长度和 t2时间长度直接决定环路滤波器的过充 与否以及锁定时间， 所以需要根据最终锁定时间控制 tl和 t2的时间长度， 以减弱过冲。
这里， 预置电压电路所预置的电压根据 CV 变化范围而定。 通常预置 电压选取的是 CV的中间值， 如 CV为 1V~4V, 则预置电压选取为 2.5V 考虑到环路滤波器的过冲和欠充情况，可适当调整预置电压的具体电压值。
表 1为通过实验测出的， 釆用图 9所示的系统并且釆用图 11所示的频 率锁定工作过程时， 在不同温度下的频率锁定时间、 相位噪声以及相位余 度， 其中系统中的压控振荡器为图 4所示的压控振荡器。
表 1
频率. (MHz) 至 /STL -30°C 80°C
2.71 3.73 3.06 锁定时间 2.75 3.82 2.53
(ms) 180->218 2.58
218->180 2.31
336 -117
相位噪声 396 -117.5
(dBc/Hz) 180 -119 336 35。
相位余度 396 35。
(。 ) 180 36。
218 36。
表 2为釆用图 9所示的系统结构并且釆用图 11所示的频率锁定工作过 程时， 在不同温度下的频率锁定时间， 其中系统中釆用的压控振荡器为图 2所示的压控振荡器。
表 2
Figure imgf000019_0001
表 3为釆用图 9所示的系统的结构， 但锁相环集成电路不具有快速锁 定功能， 在不同温度下的频率锁定时间， 其中频率产生单元中釆用的压控 振荡器为图 2所示的压控振荡器。
表 3
Figure imgf000019_0002
由表 1、 表 2以及表 3可以看出， 釆用图 9所示的系统结构并且釆用图 11所示的频率锁定工作过程时， 系统釆用的压控振荡器为图 4所示的压控 振荡器时， 输出频率转换一定时其所耗费的时间越短， 即锁定频率的速度 越快。 并且， 从表 1 可以看出， 釆用图 4所示的压控振荡器时， 具有较好 的相位噪声和相位余度。
以上所述仅是本发明的优选实施方式， 应当指出， 对于本技术领域的 普通技术人员来说， 在不脱离本发明原理的前提下， 还可以作出若干改进 和润饰， 这些改进和润饰也应视为本发明的保护范围。

Claims

权 利 要 求
1、 一种压控振荡器， 其特征在于， 所述压控振荡器包括选频网络电路和 有源器件电路；
所述选频网络电路具有控制电压输入和辅助控制电压输入， 其中， 所述辅 助控制电压的变化趋势与所述选频网络电路的目的振荡频率的变化趋势相同， 所述辅助控制电压使得所述选频网络电路的等效电容值变化 C1 , 控制电压使 得所述选频网络电路的等效电容值变化 C2 , C1与 C2之和为 C3 , 所述 C3为所 述选频网络电路产生的信号的频率从当前频率转变到目的振荡频率时，所述选 频网络电路的等效电容值变化的电容值； C3的绝对值大于 C2的绝对值；
所述选频网络电路用于根据控制电压和辅助控制电压产生振荡频率按照 控制电压和辅助控制电压而变化的信号；
所述有源器件电路用于向所述选频网络电路提供产生振荡频率的能量。
1、 根据权利要求 1所述的压控振荡器， 其特征在于， 其中， 所述辅助控 制电压先于控制电压输入至所述选频网络电路。
3、 根据权利要求 1所述的压控振荡器， 其特征在于， 所述选频网络电路 包括： 第一、 第二、 第三和第四电感、 第一、 第二、 第三、 第四、 第五、 第六、 第七、 第八和第九电容、 第一、 第二、 第三和第四变容管组以及一磁珠；
所述第一变容管组包括并联的至少一个变容管；
所述第二变容管组包括并联的至少一个变容管；
所述第三变容管组包括并联的至少一个变容管；
所述第四变容管组包括并联的至少一个变容管；
所述第一、 第二、 第三、 第八和第九电容的第一端、 所述第一和第四变容 管组中全部变容管的正极以及所述第三和第四电感的第一端连接到地电压； 所述第一电容的第二端以及第一电感的第一端连接到控制电压；
所述第一电感的第二端、第四和第五电容的第一端以及第三变容管组中全 部变容管的负极连接到所述第四变容管组中全部变容管的负极；
所述磁珠的第一端以及所述第二电容的第二端连接到辅助控制电压； 所述磁珠的第二端以及所述第三电容的第二端连接到所述第二电感的第 一端；
所述第二电感的第二端、所述第一变容管组中全部变容管的负极以及所述 第四和第五电容的第二端连接到所述第二变容管组中全部变容管的负极； 所述第二变容管组中全部变容管的正极、所述第三变容管组中全部变容管 的正极以及所述第六和第七电容的第一端连接到所述第三电感的第二端； 所述第六、 第七、第八和第九电容的第二端以及所述第四电感的第二端连 接到所述有源器件电路。
4、 根据权利要求 3所述的压控振荡器， 其特征在于，
所述第一变容管组包括第一变容管；
所述第二变容管组包括与第一变容管电压容值特性相同的第二变容管； 所述第二变容管组包括并联的电压容值特性相同的第三和第四变容管； 所述第三变容管组包括并联的电压容值特性相同的第五和第六变容管。
5、 根据权利要求 1所述的压控振荡器， 其特征在于， 所述辅助控制电压 由数模转换电路或开关控制的分压电路提供。
6、 一种对频率锁定的方法， 其特征在于， 所述方法包括：
控制单元根据预先设置的频率和控制电压的关系曲线，生成目的振荡频率 对应的辅助电压，将辅助电压输入至如权利要求 1至 5任意一项所述的压控振 荡器，作为所述压控振荡器的辅助控制电压； 环路滤波器将控制电压输入至所 述压控振荡器；
所述辅助控制电压使得所述压控振荡器中的选频网络电路的等效电容值 变化 C1 , 控制电压使得所述选频网络电路的等效电容值变化 C2 ;
在所述方法执行的时间到达预设的锁定时间后将所述压控振荡器输出的 频率作为锁定后的频率； C1与 C2之和为 C 3 , 所述 C 3为所述选频网络电路产生的信号的频率从当 前频率转变到目的振荡频率时， 所述选频网络电路的等效电容值变化的电容 值； C 3的绝对值大于 C2的绝对值。 7、 根据权利要求 6所述的方法， 其特征在于， 所述方法还包括： 控制单元在第一时间段内将电压预配置电路输出的预置电压施加到环路 滤波器， 为所述环路滤波器中的电容充电； 所述电压预配置电路包括正向压降 随温度升高而降低的二极管， 用于输出随温度升高而增加的预置电压；
控制单元在所述第一时间段后切断电压预配置电路为环路滤波器提供的 预置电压。
8、 根据权利要求 7所述方法， 其特征在于， 所述方法还包括：
所述控制单元开启所述锁相环电路的快锁功能，并在第一时间段后的第二 时间段将所述锁相环电路产生的快锁信号发送给所述环路滤波器。
9、 一种频率产生单元， 其特征在于， 所述频率产生单元包括： 控制单元、 锁相环电路、环路滤波器以及如权利要求 1至 5中任意一项所述的压控振荡器； 所述控制单元用于根据目的振荡频率生成频率设置信号，并向锁相环电路 发送所述频率设置信号， 以及根据预先设置的频率和控制电压的关系曲线， 生 成目的振荡频率对应的辅助电压，并将辅助电压作为辅助控制电压输入至所述 压控振荡器；所述辅助控制电压使得所述压控振荡器中的选频网络电路的等效 电容值变化 C 1 ;
所述锁相环电路根据压控振荡器的输出信号和所述频率设置信号得到对 比信号，根据所述对比信号和参考信号得到反映所述对比信号和参考信号的相 位差的误差电压信号， 并输出所述误差电压信号至环路滤波器， 所述误差电压 信号经所述环路滤波器滤波处理后输入所述压控振荡器，作为所述压控振荡器 的控制电压； 控制电压使得所述选频网络电路的等效电容值变化 C2 ;
所述压控振荡器将所述压控振荡器产生的信号发送至所述锁相环电路； 其中， C1和 C2之和为 C 3 , 所述 C 3为所述选频网络电路产生的信号的频 率从当前频率转变到目的振荡频率时，所述选频网络电路的等效电容值变化的 电容值； C 3的绝对值大于 C2的绝对值。
1 0、 根据权利要求 9所述的频率产生单元， 其特征在于， 所述控制单元包 括数模转换电路；所述数模转换电路用于根据预先设置的频率和控制电压的关 系曲线， 生成目的振荡频率对应的辅助电压， 并将所述辅助电压作为辅助控制 电压输入至所述压控振荡器。
11、 根据权利要求 9所述的频率产生单元， 其特征在于， 所述控制单元包 括开关控制的分压电路；所述分压电路用于根据预先设置的频率和控制电压的 关系曲线， 生成目的振荡频率对应的辅助电压， 并将所述辅助电压作为辅助控 制电压输入至所述压控振荡器。
12、 根据权利要求 9所述的频率产生单元， 其特征在于， 所述频率产生单 元还包括： 电压预配置电路， 包括正向压降随温度升高而降低的二极管， 用于 输出随温度升高而增加的预置电压；
所述控制单元还用于在第一时间段内将电压预配置电路输出的预置电压 施加到所述环路滤波器， 为所述环路滤波器中的电容充电， 以及在所述第一时 间段后切断电压预配置电路为环路滤波器提供的预置电压。
1 3、 根据权利要求 12所述的频率产生单元， 其特征在于， 所述频率产生 单元还包括第一开关和第二开关；
所述控制单元还用于开启所述锁相环电路的快锁功能；
第一开关， 连接在所述电压预配置电路和所述环路滤波器之间， 用于在接 收所述控制单元在第一时间段内发送的预配置控制信号后接通，将所述电压预 配置电路提供的预置电压施加给所述环路滤波器；
第二开关， 连接在所述锁相环电路的快锁控制端和所述环路滤波器之间， 用于在接收所述控制单元在第一时间段后的第二时间段内发送的快锁控制信 号后接通， 将所述锁相环电路产生的快锁信号发送给所述环路滤波器。
PCT/CN2012/076855 2012-06-13 2012-06-13 一种对频率锁定的方法、一种压控振荡器以及频率产生单元 Ceased WO2013185308A1 (zh)

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CN101783677A (zh) * 2010-03-26 2010-07-21 海能达通信股份有限公司 一种锁相环的锁定方法及锁定电路
CN102710257A (zh) * 2012-06-13 2012-10-03 海能达通信股份有限公司 一种对频率锁定的方法、一种压控振荡器以及频率产生单元

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