WO2013178078A1 - 图像传感器与晶体管的制作方法 - Google Patents

图像传感器与晶体管的制作方法 Download PDF

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Publication number
WO2013178078A1
WO2013178078A1 PCT/CN2013/076473 CN2013076473W WO2013178078A1 WO 2013178078 A1 WO2013178078 A1 WO 2013178078A1 CN 2013076473 W CN2013076473 W CN 2013076473W WO 2013178078 A1 WO2013178078 A1 WO 2013178078A1
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conductivity type
type
layer
conductive
doped layer
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PCT/CN2013/076473
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English (en)
French (fr)
Inventor
赵立新
李文强
蒋珂玮
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格科微电子（上海）有限公司
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Publication of WO2013178078A1 publication Critical patent/WO2013178078A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient

Definitions

  • the present invention relates to the field of semiconductor technology, and more particularly to an image sensor and a method of fabricating the same. Background technique
  • CCD Charge Coupled Device
  • CMOS complementary metal oxide semiconductor
  • CMOS image sensors typically use a 3T or 4T pixel structure.
  • 1 shows a 4T pixel structure of a conventional CMOS image sensor including a photodiode 11, a transfer transistor 12, a reset transistor 13, a source follower transistor 14, and a row selection transistor 15.
  • the photodiode 11 is used to sense a change in light intensity to form a corresponding image charge signal.
  • the transfer transistor 12 is configured to receive the transfer control signal TX, and under the control of the transfer control signal , the transfer transistor 12 is turned on or off correspondingly, so that the image charge signal induced by the photodiode 11 is read out to the transfer transistor 12 A drain-coupled floating diffusion, which in turn stores an image charge signal.
  • the reset transistor 13 is for receiving a reset control signal RST, and under the control of the reset control signal RST, the reset transistor 13 is turned on or off correspondingly, thereby providing a reset signal to the gate of the source follower transistor 14.
  • the source follower transistor 14 is for converting the image charge signal obtained by the transfer transistor 12 into a voltage signal, and the voltage signal can be outputted to the bit line BL through the row selection transistor 15.
  • the voltage signal output by the conventional CMOS image sensor tends to have large flicker noise, especially when the light is weak.
  • the flicker noise in the voltage signal can significantly degrade the image quality.
  • CMOS image sensors often use surface channel transistors as source follower transistors.
  • the conductive channel is on the surface of the substrate and is adjacent to the gate oxide layer on the substrate.
  • the interface between the substrate and the gate oxide layer is susceptible to forming an interface state that randomly traps or releases carriers, thereby causing a change in channel current, thereby introducing flicker noise into the voltage signal output from the source follower transistor.
  • an image sensor includes a pixel array, and one or more pixel units in the pixel array includes a source follower transistor, and the source follower transistor is a junction field effect transistor comprising: a first conductivity type substrate; a second conductivity type a well, located in the first conductivity type substrate; a second conductivity type deposition doping layer located outside the surface of the first conductivity type substrate and at least partially on the second conductivity type well; a type source region, located in the second conductivity type well; a first conductivity type drain region, located in the first conductivity type substrate and/or in the second conductivity type well; a layer, at least partially between the second conductivity type well and the second conductivity type deposition doping layer, such that the first conductivity type source region is electrically connected to the first conductivity type drain region, and Forming a PN junction between it and the second conductivity type well and between the second conductivity type deposition doping layer
  • the carrier in the conductive channel is avoided due to the interface state at the oxide-semiconductor bottom interface. It is randomly captured or dried, thereby effectively reducing the flicker noise in the output voltage signal, thereby improving the image quality of the image sensor.
  • the PN junction on one side of the conduction channel is a first conductivity type doped layer deposited by a second conductivity type located outside the surface of the first conductivity type substrate The formation of the hetero layer.
  • the second conductivity type deposition doping layer comprises a doped polysilicon layer or an amorphous silicon layer.
  • the doped polysilicon or amorphous silicon may be formed outside the surface of the first conductive type substrate by chemical vapor deposition or other suitable deposition method without being formed in the first conductive type substrate by ion implantation. This can reduce one ion implantation, thereby reducing the manufacturing cost of the image sensor.
  • the source follower transistor does not need to make a deep isolation trench in the first conductive type substrate outside its conductive channel to isolate adjacent regions, which can reduce the manufacturing process difficulty and reduce the area of the image sensor.
  • the second conductive type well and the second conductive type deposited doped layer at least partially overlap each other outside the first conductive type doped layer such that the second conductive type well
  • the doped layers are deposited electrically connected to the second conductivity type.
  • the first conductive type drain region and/or the first conductive type doped layer is at least partially located outside the second conductive type well to obtain the first conductive type drain region and The first conductivity type substrate is electrically connected.
  • the edge of the second conductivity type deposited doped layer is on the dielectric layer of the surface of the first conductivity type substrate or on the isolation trench in the first conductivity type substrate.
  • the dielectric layer between the edge and the first conductive type substrate may cause the etching of the second conductive type doped layer to stop on the dielectric layer or the isolation trench On the slot, thereby avoiding damage to the first conductivity type substrate and the resulting transistor damage.
  • a method of fabricating a transistor comprising the steps of: providing a first conductivity type substrate, wherein the first conductivity type substrate is doped with a second conductivity type well; Forming a first conductive type doped layer in the first conductive type substrate and/or the second conductive type well; forming a second conductive type deposited doped layer, the first conductive type being located Outside the surface of the substrate and at least partially on the doped layer of the first conductivity type, such that a PN junction is formed between the deposition layer of the second conductivity type and the first conductivity type dopant layer; Forming a first conductivity type source region in the second conductivity type well, and forming a first guide in the second conductivity type well and/or the first conductivity type substrate An electrical type drain region such that the first conductivity type source region is electrically connected to the first conductivity type drain region.
  • the edge of the second conductivity type deposition doped layer is on the dielectric layer of the first conductivity type substrate bottom surface or on the isolation trench in the first conductivity type substrate.
  • the method before the step of forming the doped second conductivity type deposition doped layer, the method further includes: forming the dielectric layer on the bottom surface of the first conductivity type and/or at the first Forming an isolation trench in the conductive type substrate; and the step of forming the second conductive type deposition doped layer further comprises: partially etching the dielectric layer such that the first conductive type doped layer is at least partially Exposing a doped polysilicon or amorphous silicon on the exposed first conductive type doped layer to form the second conductive type deposited doped layer; and partially etching the second conductive type The doped layer is deposited such that the etched second conductivity type deposited doped layer edge is on the dielectric layer and/or the isolation trench.
  • the step of partially etching the dielectric layer further comprises: partially etching the dielectric layer such that the first conductive type doped layer and the second conductive type well are at least partially exposed .
  • the step of depositing doped polysilicon or amorphous silicon further comprises: performing the polysilicon or amorphous silicon deposited while the polysilicon or amorphous silicon is deposited, or After the deposition of the polysilicon or amorphous silicon, the deposited polysilicon or amorphous silicon is doped.
  • Figure 1 shows a 4T pixel structure of a conventional CMOS image sensor
  • Figure 2 shows an image sensor 200 in accordance with one embodiment of the present invention
  • Figure 3a shows an example of a source follower transistor of image sensor 200 of Figure 2.
  • Fig. 3b shows another example of the source follower transistor of the image sensor 200 of Fig. 2
  • Fig. 4a shows another example of the source follower transistor of the image sensor 200 of Fig. 2.
  • Figure 4b is a cross-sectional view of the source follower transistor of Figure 4a taken along the line AA';
  • Figure 5a shows a method 500 for fabricating a transistor according to an embodiment of the present invention
  • Figures 5b through 5e show schematic cross-sectional views of the fabrication method 500 of Figure 5a. detailed description
  • the image sensor 200 includes an array of pixels. Each pixel unit in the pixel array includes: a photodiode 201 for sensing a change in light intensity to generate a corresponding image. An image charge signal; a transfer transistor 202 for transferring an image charge signal; and a source follower transistor 204 for generating a voltage signal based on the transferred image charge signal, wherein the read source follower transistor 204 is a junction field effect transistor.
  • a plurality of pixel units in a pixel array may have one source follower transistor 204, for example, two adjacent, four or more pixel units may share one source follower transistor 204 for output. Voltage signal.
  • the source follower transistor 204 is a P-type field effect transistor.
  • the source follower transistor 204 can also be an N-type field effect transistor.
  • the photodiode 201 is coupled to the reference potential line VSS, such as a ground or negative power supply potential, and the source of the transfer transistor 202 for sensing a change in light intensity to form a corresponding image charge signal.
  • the drain of the transfer transistor 202 is connected to the gate of the source follower transistor 204.
  • the gate of the transfer transistor 202 is used to receive the transfer control signal TX. Under the control of the transfer control signal TX, the transfer transistor 202 is turned on or off accordingly.
  • Photodiode The image charge signal induced by 201 is read out to a floating diffusion region coupled to the drain of the transfer transistor 202, and the image charge signal is stored by the floating diffusion region.
  • the source follower transistor 204 is coupled between the reference potential line VSS and the bias current source 205, the drain thereof is coupled to the reference potential line VSS, the source thereof is coupled to the bias current source 205 and is used for outputting a voltage signal.
  • the gate is coupled to the drain of the transfer transistor 202, that is, coupled to the floating diffusion region to obtain an image charge signal transferred by the transfer transistor 202.
  • the voltage of the source of the source follower transistor 204 varies with the change in the image charge signal acquired by its gate, with a voltage gain close to 1
  • the source follows the transistor
  • the source of 204 is further coupled to a bit line (not shown) via a row select transistor (not shown) and provides the voltage signal to a signal processing circuit of the image sensor.
  • the image sensor further includes a reset transistor 203 having a drain for receiving a reset signal RSG, the source of which is coupled to the drain of the transfer transistor 202 and the gate of the source follower transistor 204.
  • the gate of the reset transistor 203 is for receiving a reset control signal RST. Under the control of the reset control signal RST, the reset transistor 203 is turned on or off correspondingly, thereby providing a reset signal to the gate of the source follower transistor 204.
  • the transfer transistor 202 and the reset transistor 203 are both NMQS transistors. It can be understood that in other embodiments, the transfer transistor 202 and the reset transistor 203 can also adopt other types of transistors, such as a PMOS transistor or a junction field. Effect tube.
  • the amplification unit 215 amplifies the voltage difference between the two capacitors, and supplies the amplified output voltage to the subsequent processing circuit. .
  • Figure 3a shows an example 300 of a source follower transistor of image sensor 200 of Figure 2, wherein the source follower transistor is a P-type field effect transistor.
  • the source follower transistor is an N-type field effect transistor.
  • the read source follower transistor includes:
  • N-well 303 which is located in the P-type bottom 301;
  • An N-type deposited doped layer 305 is disposed outside the surface of the P-type substrate 301 and at least partially on the N-type well 303;
  • P-type source region 307 which is located in N-well 303;
  • P-type drain region 309 which is located in P-type substrate 301 and / or N-well 303;
  • a P-type doped layer 311 is at least partially interposed between the N-type well 303 and the N-type deposited doped layer 305 such that the P-type source region 307 is electrically connected to the P-type drain region 309, and the P-type source region 307 is caused.
  • the P-type drain region 309 is electrically connected, and a PN junction is formed between the P-type doping layer 311 and the N-type well 303, and between the P-type doped layer 311 and the N-type deposited doping layer 305, respectively.
  • the P-type substrate 301 may be a P-type doped semiconductor wafer, or a P-type doped silicon-on-insulator (SOI), or a P-type well region in an N-type doped semiconductor wafer, or other Similar to a substrate or well region.
  • SOI silicon-on-insulator
  • the P-type source regions 307 are all located in the N-well 303.
  • the N-well 303 makes the P-type source region
  • the 307 is isolated from the P-type substrate 301. Since source region 307 is used to output a voltage signal, it may have a higher potential, while P-type substrate 301 is typically coupled to a reference potential line, such as ground. Therefore, the source region 307 and the P-type substrate 301 are isolated from each other to avoid substrate punch-through to ensure normal operation of the source follower transistor.
  • the P-type drain regions 309 may all be located in the P-type substrate 301 outside the N-type well 303; or all of them in the N-type well 303; or a portion may be located in the N-type well 303, and The other portion is located in the P-type substrate 301 outside the N-well 303.
  • the P-type drain regions 309 are all located in the N-type well 303, and thus they are electrically connected to the P-type source region 307 through the P-type doping layer 311 in the N-type well 303.
  • the P-type source region 307 and the P-type drain region 309 are partially overlapped with the P-type doped layer 311, respectively, to achieve electrical connection therebetween.
  • the N-type deposited doping layer 305 may also be located wholly or partially on the N-type well 303 and between the source region 307 and the drain region 309.
  • the layout of the N-type deposited trim layer 305 is all located within the layout of the N-well 303.
  • the P-type doped layer 311 is located between the N-type well 303 and the N-type deposited doping layer 305, and is electrically connected to the P-type source region 307 and the P-type drain region 309.
  • the P-type doped layer 311 is at least partially located in the N-type well 303, the P-type doped layer 311 is in contact with the N-type well 303, thereby forming a PN junction of the junction field effect transistor near its contact interface. Further, the P-type doped layer 311 is also at least partially in contact with the N-type deposited doping layer 305 located thereon, thereby forming another PN junction of the junction field effect transistor in the vicinity of its contact interface. This causes the N-type well 303 and the N-type deposited doping layer 305 to act as the gate of the germanium source follower transistor, and the region between the two PN junctions is the conductive channel region of the source follower transistor 300.
  • the difference in voltage difference between the N-type deposited doping layer 305 (and the N-well 303) and the source region 307 and the drain region 309 causes the junction space charge region of the two PN junctions.
  • the change in width changes the thickness of the conductive channel of the junction field effect transistor, which in turn changes the channel current.
  • the interface state defects at the contact surface position are much smaller than those of the oxide-substrate interface. Interface state defects.
  • the channel current is in the P-type doped layer 311 away from the surface of the P-type substrate 301, it is substantially not affected by the interface state of the surface oxide-substrate interface of the P-type substrate 301, thereby greatly reducing the interface state.
  • the probability of random trapping or releasing carriers of the defect thereby effectively reducing the flicker noise in the output voltage signal of the source follower transistor.
  • electrical contact between the N-type deposited doped layer 305 and the P-type doped layer 311 can be achieved by removing the dielectric layer 304, such as an oxide layer, on the surface of the P-type substrate 301, ie, The surface of the P-type substrate 301 is usually formed with an oxide layer, and the oxide layer above the P-type doped layer 311 may be partially removed to expose the P-type doped layer 311 from the surface of the P-type substrate 301; For example, etched polysilicon or amorphous silicon is deposited on the P-type substrate 301 to form the N-type deposited doped layer 305.
  • the dielectric layer 304 may be formed in advance on the surface of the P-type substrate 301.
  • the N-type deposited doping layer 305 is only in contact with the P-type doped layer 311 and constitutes a PN junction without being in electrical contact with the P-type source region 307 and the P-type drain region 309.
  • the doped polysilicon layer or the amorphous silicon layer may be doped with the polysilicon or amorphous silicon when deposited, that is, a gas having doped ions is added to the deposited reaction chamber. . This eliminates the need to dope by ion implantation to form the N-type deposition doping layer 305, which can reduce one-time ion implantation, thereby reducing the fabrication cost of the image sensor.
  • the N-type deposited doped layer 305 can also be formed by first depositing polysilicon or amorphous silicon, and then doping the deposited polysilicon or amorphous silicon, for example, by ion implantation. Or doping in a diffusion mode.
  • the N-type deposited doping layer 305 can be controlled by, for example, dry etching, and its outline is easily controlled, so that the image sensor 300 using the read junction type field effect transistor is highly reliable.
  • the edge of the N-type deposited doped layer 305 is on the dielectric layer 304.
  • Dielectric layer 304 isolates the edge of N-type deposited doped layer 305 from P-type substrate 301.
  • the dielectric layer 304 between the edge and the P-type substrate 301 may cause the etching of the N-type deposited doping layer 305 to stop on the dielectric layer 304.
  • the portion of the N-type deposited dopant layer 305 that is in contact with the P-type substrate 301 is located within the window of the dielectric layer 304, the edges of which extend beyond the edge of the window of the dielectric layer 304, such as 5 nm, 10 nm. , 50 nanometers, and so on.
  • the N-type well 303 and the N-type deposited doped layer 305 may overlap each other outside the P-type doped layer 311 such that the N-type well 303 and the N-type deposited doped layer 305 are electrically connected to each other. This eliminates the need to make additional vias or other structures in the N-well 303 to extract the N-well 303, thereby reducing manufacturing costs. It will be appreciated that in other examples, the N-type well 303 and the N-type deposited doped layer 305 may not be in direct contact with each other, but may be electrically connected through vias in the dielectric layer 304.
  • Figure 3b shows another example of the source follower transistor of image sensor 200 of Figure 2.
  • a photodiode of image sensor 200 is also shown, which is composed of a P-type substrate 301 and an N-type doped region 321 outside the N-type well 303.
  • the P-type substrate 301 further includes an isolation trench 323 located outside the N-type well 303, that is, between the N-type doping region 321 and the N-type well 303.
  • the isolation trench 323 is formed of an insulating material such as silicon oxide or silicon nitride, and thus has a good electrical isolation effect.
  • the isolation trench 323 in the P-type substrate 301 isolates the N-type doping region 321 from the N-type well 303, which can effectively avoid short-circuit (ie, punch-through) between the negative electrode of the photodiode and the gate of the source-following transistor. Affect the operation of the image sensor.
  • the profile of the conductive channel is easy to control due to the reduction of one ion implantation, and it is not caused by too many annealing times. Causes a deeper knot. Therefore, the image sensor does not need to make a deep isolation trench in the P-type substrate 301 outside the conductive channel to isolate adjacent regions, that is, the isolation trench 323 can adopt a shallow trench isolation structure (Shallow Trench Isolation), which occupies The chip area is relatively small, so that the area of the image sensor can be effectively reduced.
  • Shallow Trench Isolation Shallow Trench Isolation
  • the isolation trench 323 can be adjacent to the germanium source region 307 and/or the germanium dopant region 321 which can further reduce the area of the image sensor, thereby increasing chip integration.
  • the isolation trench 323 is adjacent to the N-type well 303 and the P-type source region 307, which reduces the contact area between the N-type well 303 and the P-type substrate 301, thereby being effective The parasitic capacitance between the N-well 303 and the P-type substrate 301 is reduced.
  • the N-well 303 is coupled to the floating diffusion region of the image sensor.
  • the isolation trench 323 adjacent to the N-well 303 and the P-type source region 307 can further improve the sensitivity of the image sensor.
  • the edge of the N-type deposited doped layer 305 may also be located on the isolation trench 323.
  • the isolation trench 323 isolates the edge of the N-type deposited erase layer 305 from the P-type substrate 301.
  • the isolation trench 323 between the edge and the P-type substrate 301 may cause the etching of the N-type deposited doping layer 305 to stop on the isolation trench 323. Thereby, damage of the P-type substrate 301 and the resulting transistor damage are avoided.
  • 4a and 4b show another example 400 of the source follower transistor of image sensor 200 of Fig. 2.
  • 4b is a schematic cross-sectional view of the source follower transistor in the direction of AA in FIG. 4a.
  • the source follower transistor has a similar structure to the source follower transistor of Figure 3a.
  • the drain region 409 of the source follower transistor is located in the P-type substrate 401 outside the N-type well 403, which electrically connects the P-doped drain region 409 to the P-type substrate 401.
  • the drain region 409 and the P-type substrate 401 are both coupled to the reference potential line, for example, so that there is no voltage difference therebetween, so that no current is formed between the drain region 409 and the P-type substrate 401. .
  • the P-type dopant layer 411 extends at least partially from the N-well 403 to the P-type substrate.
  • the germanium substrate 401 and the germanium-type dopant layer 411 are electrically connected to the source region 407 and the drain region 409.
  • the channel current can flow from the drain region 409 through the germanium substrate 401 and the germanium-type dopant layer 411 to the source region 407.
  • image sensor 200 it typically has a plurality of pixel cells, each having a source follower transistor.
  • each source follower transistor For the drain region 409 of these source follower transistors, there may be some or all of the drain regions 409 at least partially outside the ⁇ -type well 403
  • the ground ⁇ -type substrate 401 are equal in potential so that they have equal potentials with each other.
  • this can improve the grounding effect without increasing the chip area, for example, the ground can be shared by the ⁇ -type substrate 401, which avoids the inconsistent ground potential of different pixel units, thereby further improving the performance of the image sensor.
  • the germanium well 403 and the germanium-type deposition doped layer 405 at least partially overlap each other outside the germanium-doped layer 411, thereby electrically interconnecting the germanium-type well 403 and the germanium-type deposition doped layer 405. This eliminates the need to make additional vias in the germanium well 403 to extract the germanium well 403, thereby reducing manufacturing costs.
  • Figure 5a illustrates a method 500 of fabricating a transistor in accordance with one embodiment of the present invention. As shown in FIG. 5a, the manufacturing method 500 includes:
  • Step S501 providing a first conductivity type substrate, wherein the first conductivity type substrate is doped with a second conductivity type well;
  • Step S503 forming a first conductive type doping layer in the first conductive type substrate and/or the second conductive type well;
  • Step S505 forming a second conductivity type deposition doping layer, which is located outside the surface of the first conductivity type substrate and at least partially on the first conductivity type doping layer, so that the second conductivity type deposits the doped layer and Forming a PN junction between the doped layers of the first conductivity type;
  • Step S507 forming a first conductivity type source region in the second conductivity type well, and forming a first conductivity type drain region in the second conductivity type well and/or the first conductivity type substrate to make the first conductive
  • the type source region is electrically connected to the first conductivity type drain region.
  • the method 500 of fabricating the transistor can be used to fabricate a source follower transistor in an image sensor.
  • the process of fabricating an image sensor further includes forming an image.
  • the steps of the photodiode in the sensor pixel unit, and other transistors, such as a transfer transistor, a reset transistor, and a row select transistor, are not described herein.
  • the edge of the second conductivity type deposition doped layer is on the dielectric layer of the surface of the first conductivity type substrate or on the isolation trench in the first conductivity type substrate.
  • the dielectric layer or isolation trench between the edge and the first conductivity type substrate may cause etching of the doped layer of the second conductivity type deposition layer Stopping on the dielectric layer or isolation trenches avoids etch damage of the first conductivity type substrate and the resulting transistor damage.
  • the method further includes: forming a dielectric layer on the surface of the first conductive type substrate and/or forming an isolation trench in the first conductive type substrate; and forming a second conductive type deposition doping
  • the step of the impurity layer further includes: partially etching the dielectric layer such that the first conductive type doped layer is at least partially exposed; depositing doped polysilicon or amorphous silicon on the exposed first conductive type doped layer to form Depositing a doped layer with a second conductivity type; and partially etching the second conductivity type deposition doped layer and causing the etched second conductivity type deposition doped layer edge to be on the dielectric layer and/or isolation trench on.
  • the step of partially etching the dielectric layer further comprises: partially etching the dielectric layer such that the first conductive type doped layer and the second conductive type well are at least partially exposed. Therefore, it is necessary to deposit doped polysilicon or amorphous silicon on the exposed first conductive type doped layer and the second conductive type well to form a second conductive type deposited doped layer.
  • the second conductive type electrode doped layer directly formed on the second conductive type well may be in electrical contact with the second conductive type well underneath, so that the second conductive type well can be electrically extracted without making through holes or other electricity
  • a connection structure is used to extract the second conductivity type well.
  • Figures 5b through 5e illustrate cross-sectional views of the fabrication method 500 of Figure 5a.
  • the transistor formed by the fabrication method 500 is a P-type field effect transistor.
  • the principles of operation are equally applicable to the case where the transistor is an N-type field effect transistor.
  • an embodiment of the method 500 for fabricating an image sensor will be described in detail with reference to Figs. 5a to 5e.
  • a P-type substrate 501 is provided, and a photodiode region 502 and an N-type well 503 are formed in the read P-type substrate 501.
  • the N-well 503 and the photodiode region 502 pass The P-type substrates 501 in between are separated from each other.
  • a P-type doped layer 511 is formed which is at least partially located in the N-type well 503.
  • the P-type doping layer 511 is entirely located in the N-well 503.
  • an N-type well 503 and a P-type doped layer 511 located therein constitute a PN junction of the transistor.
  • the P-type doping layer 511 may also be partially located in the P-type substrate 501, and partially located in the N-type well 503. It should be noted that the P-type doping layer 511 and the N-type are formed.
  • the step of the well 503 is usually carried out by ion implantation. After each ion implantation, the P-type substrate 501 is also subjected to an annealing treatment, such as a rapid annealing treatment, to activate ions and reduce lattice defects caused by the implantation.
  • a dielectric layer 504 is formed on the surface of the P-type substrate 501.
  • the dielectric layer 504 is, for example, hafnium oxide or other dielectric material, which may be formed by, for example, an oxidation process or a deposition process.
  • an isolation trench (not shown) may also be formed in the P-type substrate 501, which is typically located outside of the N-well 511.
  • an N-type deposition doping layer 505 is formed, which is located outside the surface of the P-type substrate 501 and at least partially located on the N-type well 503, so that the N-type deposition doping layer 505 and the N-type A PN junction is formed between the P-type doped layers 511 in the well 503.
  • the read N-type deposited doped layer 505 can be formed by: first, partially etching the dielectric layer 504 to form a window on the P-type substrate 501, the window making the P-type doped layer 511 at least Partially exposed; then, doped polysilicon or amorphous silicon is deposited on the exposed P-type doped layer 511 to form an N-type deposited doped layer 505; thereafter, the N-type deposited doped layer 505 is partially etched and The edge of the N-type deposited doping layer 505 is placed on the dielectric layer 504, or the edge of the N-type deposited doping layer 505 is located on the isolation trench, such that the edge of the N-type deposited doping layer 505 is not directly It is located on the P-type substrate 501.
  • polysilicon or amorphous silicon may be deposited by a chemical vapor deposition process, and P-type ions, such as phosphorus or arsenic ions, may be doped while depositing the polysilicon or amorphous silicon to form doped polysilicon. Or amorphous silicon.
  • P-type ions such as phosphorus or arsenic ions
  • polysilicon or amorphous silicon may be deposited by a chemical vapor deposition process, followed by doping P-type ions in the deposited polysilicon or amorphous silicon, for example by diffusion or ion implantation. .
  • the polysilicon or amorphous silicon may be deposited by a chemical vapor deposition process, followed by partial etching of the deposited polysilicon or amorphous silicon, and then The etched polysilicon or amorphous silicon is ion-implanted to dope the impurity ions before or after the source and drain regions are formed.
  • the N-type deposited doped layer 505 is also formed directly on the N-well 503. Accordingly, the dielectric layer 504 is etched such that the P-type doped layer 511 and the N-type well 503 are at least partially exposed, and doped polysilicon is deposited on the exposed P-type doped layer 511 and the N-type well 503 or Amorphous silicon is used to form an N-type deposited doped layer.
  • the polysilicon deposited can be in direct contact with the underlying P-doped layer 511 through the Ion house window to form a PN junction on the other side of the junction field of the junction field effect transistor.
  • This PN junction together with the PN junction between the P-type doped layer 511 and the N-type well 503 collectively defines the conductive channel of the junction field effect transistor, and the N-type well 503 and the N-type deposited doping layer 505 together serve as The two gates of the junction field effect transistor.
  • a P-type source region 507 and a P-type drain region 509 are formed in the N-type well 503, and the P-type source region 507 and the P-type drain region 509 are electrically connected to each other.
  • the P-type source region 507 and the P-type drain region 509 are electrically connected by a P-type doping layer 511 therebetween.
  • the P-type drain region 509 can also be formed on the P-type substrate 501 outside the N-type well 503, and the P-type drain region 509 can pass through the P-line between the N-type well 503 and the N-type well 503.
  • the bottom 501 is electrically connected to the N-well 503 and further electrically connected to the P-type source region 507 through the P-type doping layer 511.
  • the N-type deposited doping layer 505 can be formed by a deposition process, it is not required to be formed in the P-type substrate 501 by ion implantation. This reduces the number of ion implantation and annealing processes, thereby reducing the fabrication cost of the transistor.
  • the ion implantation is reduced once, the profile of the conductive channel is easy to control and does not cause a deeper junction depth due to too many annealing times. Therefore, the junction field effect transistor does not need to make a deep isolation trench in the P-type 501 outside the conductive channel to isolate adjacent regions, such as between the N-well 503 and the photodiode region 502, which can reduce the fabrication process. Difficulty and reduce the area of the transistor.

Abstract

提供一种图像传感器（200）与晶体管（204，300）的制作方法。图像传感器（200）包括像素阵列，像素阵列的一个或多个像素单元包括一个源跟随晶体管（204，300）。源跟随晶体管（204，300）是结型场效应晶体管，包括：第一导电类型衬底（301）；第二导电类型阱（303），位于第一导电类型衬底（301）中；第二导电类型淀积掺杂层（305），位于第一导电类型衬底（301）表面外并至少部分位于第二导电类型阱（303）上；第一导电类型源区（307），位于第二导电类型阱（303）中；第一导电类型漏区（309），位于第一导电类型衬底（301）中和/或第二导电类型阱（303）中；第一导电类型掺杂层（311），至少部分位于第二导电类型阱（303）与第二导电类型淀积掺杂层（305）之间，以使得第一导电类型源区（307）与第一导电类型漏区（309）电连接，并在其与第二导电类型阱（303）之间以及其与第二导电类型淀积掺杂层（305）之间分别形成PN结。

Description

图像传感器与晶体管的制作方法 技术领域
本发明涉及半导体技术领域， 更具体地， 本发明涉及一种图像传感 器以及一种晶体管的制作方法。 背景技术
传统的图像传感器通常可以分为两类： 电荷耦合器件 （Charge Coupled Device, CCD ) 图像传感器和互补金属氧化物半导体（ CMOS ) 图像传感器。 其中， CMOS图像传感器具有体积小、 功耗低、 生产成本 低等优点， 因此， CMOS图像传感器易于集成在例如手机、笔记本电脑、 平板电脑等便携电子设备中， 作为提供数字成像功能的摄像模组使用。
CMOS图像传感器通常采用 3T或 4T的像素结构。图 1即示出了一 种传统 CMOS图像传感器的 4T像素结构， 包括光电二极管 11、转移晶 体管 12、复位晶体管 13、源跟随晶体管 14以及行选择晶体管 15。其中， 光电二极管 11用于感应光强变化而形成相应的图像电荷信号。 转移晶 体管 12用于接收转移控制信号 TX， 在转移控制信号 ΤΧ的控制下， 转 移晶体管 12相应导通或关断，从而使得光电二极管 11所感应的图像电 荷信号被读出到与该转移晶体管 12 漏极耦接的浮动扩散区 （floating diffusion ) , 进而由该浮动扩散区存储图像电荷信号。 复位晶体管 13用 于接收复位控制信号 RST, 在该复位控制信号 RST的控制下， 复位晶 体管 13相应导通或关断，从而向源跟随晶体管 14的栅极提供复位信号。 源跟随晶体管 14用于将转移晶体管 12获得的图像电荷信号转换为电压 信号， 并且兹电压信号可以通过行选择晶体管 15输出到位线 BL上。
然而， 传统 CMOS 图像传感器输出的电压信号中往往具有较大的 闪烁噪声， 特别在光线较弱时， 这种闪烁噪声更为明显。 电压信号中的 闪烁噪声会显著地降低图像质量。 发明内容
因此， 需要提供一种具有较低闪烁噪声的图像传感器。
发明人经过研究发现， 传统的 CMOS 图像传感器往往采用表面沟 道晶体管来作为源跟随晶体管。 在这种源跟随晶体管中， 导电沟道位于 衬底表面， 并靠近衬底上的栅氧化层。 然而， 衬底与栅氧化层的界面容 易形成界面态， 该界面态会随机地俘获或释放载流子， 从而引起沟道电 流的变化， 进而在源跟随晶体管输出的电压信号中引入闪烁噪声。
为了解决上述问题，根据本发明的一个方面， 提供了一种图像传感 器。 该图像传感器包括像素阵列， 兹像素阵列中的一个或多个像素单元 包括一个源跟随晶体管， 所述源跟随晶体管是结型场效应晶体管， 其包 括： 第一导电类型村底； 第二导电类型阱， 位于所述第一导电类型衬底 中； 第二导电类型淀积掺杂层， 位于所述第一导电类型衬底表面外并至 少部分位于所述第二导电类型阱上； 第一导电类型源区， 位于所述第二 导电类型阱中； 第一导电类型漏区， 位于所述第一导电类型衬底中和 / 或位于所述第二导电类型阱中； 笫一导电类型掺杂层， 至少部分位于所 述第二导电类型阱与所述第二导电类型淀积掺杂层之间，以使得所述第 一导电类型源区与所述第一导电类型漏区电连接，并在其与所述第二导 电类型阱之间以及其与所述第二导电类型淀积掺杂层之间分别形成 PN 结
相比于现有技术的图像传感器， 由于采用了结型场效应晶体管替代 表面沟道 MOS晶体管作为源跟随晶体管， 这避免了导电沟道中的载流 子因氧化层-半导体村底界面处的界面态而被随机俘获或幹放， 从而有 效减少了输出的电压信号中的闪烁噪声，进而提高了图像传感器的成像 质量。 此外， 在该结型场效应晶体管中， 导电沟道一侧的 PN结是通过 位于第一导电类型衬底表面外的第二导电类型淀积掺杂层以及与其相 接触的第一导电类型掺杂层形成的。由于第二导电类型淀积捧杂层的边 缘可以通过例如干法刻蚀来形成， 其轮廓易于控制， 因此采用兹结型场 效应晶体管的图像传感器可靠性较高，并且不同像素单元之间的性能差 异较小。 在一个实施例中，所述第二导电类型淀积掺杂层包括掺杂的多晶硅 层或非晶硅层。该撩杂的多晶硅或非晶硅可以通过化学气相淀积方式或 其他适合的淀积方式形成在第一导电类型衬底表面外，而无需通过离子 注入方式形成在第一导电类型衬底中。 这可以減少一次离子注入， 从而 降低了图像传感器的制作成本。 此外， 由于减少了一次离子注入， 因而 源跟随晶体管中导电沟道的轮廓易于控制，并且不会由于退火次数过多 而造成较深的结深而影响其性能。 因此， 该源跟随晶体管无需在其导电 沟道外的第一导电类型村底中制作较深的隔离槽来隔离相邻区域，这可 以降低制作工艺难度， 并减少图像传感器的面积。
在一个实施例中，所述第二导电类型阱与所述第二导电类型淀积掺 杂层在所述第一导电类型摻杂层外至少部分相互重叠，以使得所述第二 导电类型阱与所迷第二导电类型淀积掺杂层相互电连接。
在一个实施例中， 所述第一导电类型漏区和 /或第一导电类型捧杂 层至少部分位于所迷第二导电类型阱外，以 4吏得所述第一导电类型漏区 与所述第一导电类型衬底电连接。
在一个实施例中，所述第二导电类型淀积撿杂层的边缘位于笫一导 电类型衬底表面的介电层上或者位于第一导电类型衬底中的隔离沟槽 上。在刻蚀第二导电类型掺杂层的过程中， 其边缘与第一导电类型衬底 之间的介电层可以使得第二导电类型掺杂层的刻蚀停止在介电层上或 隔离沟槽上，从而避免第一导电类型衬底的损伤以及由此带来的晶体管 损伤。
根据本发明的另一方面， 还提供了一种晶体管的制作方法， 包括下 述步骤： 提供第一导电类型衬底， 所述第一导电类型衬底中掺杂形成有 第二导电类型阱； 在所述第一导电类型衬底和 /或所述第二导电类型阱 中換杂形成第一导电类型掺杂层； 形成第二导电类型淀积掺杂层， 其位 于所述第一导电类型衬底表面外并至少部分位于所述第一导电类型掺 杂层上，以使得所迷第二导电类型淀积捧杂层与所述第一导电类型捧杂 层之间形成 PN结； 在所述第二导电类型阱中形成第一导电类型源区， 并在所述第二导电类型阱中和 /或所述第一导电类型衬底中形成第一导 电类型漏区，以使得所述第一导电类型源区与所述第一导电类型漏区电 连接。
在一个实施例中，所述第二导电类型淀积掺杂层的边缘位于第一导 电类型村底表面的介电层上或者位于第一导电类型衬底中的隔离沟槽 上。
在一个实施例中， 在形成所迷笫二导电类型淀积摻杂层的步骤之 前， 还包括： 在所述笫一导电类型村底表面形成所述介电层和 /或在所 述第一导电类型衬底中形成隔离沟槽；并且所述形成第二导电类型淀积 掺杂层的步骤进一步包括： 部分刻蚀所述介电层， 以使得所述第一导电 类型掺杂层至少部分露出；在所述露出的第一导电类型掺杂层上淀积掺 杂的多晶硅或非晶硅以形成所述第二导电类型淀积掺杂层； 以及部分刻 蚀所述第二导电类型淀积掺杂层并使得被刻蚀的第二导电类型淀积掺 杂层边缘位于所述介电层上和 /或所述隔离沟槽上。
在一个实施例中， 所述部分刻蚀介电层的步骤进一步包括： 部分刻 蚀所述介电层， 以使得所述第一导电类型掺杂层与所述第二导电类型阱 至少部分露出。
在一个实施例中，所述淀积掺杂的多晶硅或非晶硅的步骤进一步包 括：在淀积所述多晶硅或非晶硅的同时对所淀积的多晶硅或非晶硅进行 惨杂， 或者在淀积所述多晶硅或非晶硅之后， 对所淀积的多晶硅或非晶 硅进行掺杂。
本发明的以上特性及其他特性将在下文中的实施例部分进行明确 地阐述。 附图说明
通过参照附图阅读以下所作的对非限制性实施例的详细描述，能够 更容易地理解本发明的特征、 目的和优点。 其中， 相同或相似的附图标 记代表相同或相似的装置。
图 1示出了一种传统 CMOS图像传感器的 4T像素结构； 图 2示出了根据本发明一个实施例的图像传感器 200; 图 3a示出了图 2 中图像传感器 200 的源跟随晶体管的一个例子
300;
图 3b示出了图 2中图像传感器 200的源跟随晶体管的另一例子； 图 4a示出了图 2 中图像传感器 200 的源跟随晶体管的另一例子
400;
图 4b示出了图 4a的源跟随晶体管沿 AA'方向的剖面示意图； 图 5a示出了才艮据本发明一个实施例的晶体管的制作方法 500;
图 5b至图 5e示出了图 5a中的制作方法 500的剖面示意图。 具体实施方式
下面详细讨论实施例的实施和使用。 然而， 应当理解， 所讨论的具 体实施例仅仅示范性地说明实施和使用本发明的特定方式，而非限制本 发明的范围。
参考图 2， 示出了根据本发明一个实施例的图像传感器 200, 该图 像传感器 200包括像素阵列， 该像素阵列中的每个像素单元包括： 光电 二极管 201 , 用于感应光强变化而生成相应的图像电荷信号； 转移晶体 管 202， 用于转移图像电荷信号； 以及源跟随晶体管 204, 用于基于所 转移的图像电荷信号生成电压信号， 其中， 读源跟随晶体管 204是结型 场效应晶体管。
需要说明的是， 在一些例子中， 像素阵列中的多个像素单元可以具 有一个源跟随晶体管 204, 例如相邻的 2个、 4个或更多个像素单元可 以共用一个源跟随晶体管 204以输出电压信号。 此外， 在本实施例中， 源跟随晶体管 204是 P型场效应晶体管。 本领域技术人员可以理解， 在 其他的实施例中， 源跟随晶体管 204亦可为 N型场效应晶体管。
具体地， 光电二极管 201耦接于参考电位线 VSS, 例如地或负电源 电位， 与转移晶体管 202的源极之间， 用于感应光强变化而形成相应的 图像电荷信号。转移晶体管 202的漏极与源跟随晶体管 204的柵极相连， 该转移晶体管 202的栅极用于接收转移控制信号 TX, 在转移控制信号 TX的控制下， 转移晶体管 202相应导通或关断， 从而使得光电二极管 201所感应的图像电荷信号被读出到耦接在谅转移晶体管 202的漏极的 浮动扩散区， 并由 i亥浮动扩散区存储图像电荷信号。
源跟随晶体管 204耦接在参考电位线 VSS与偏置电流源 205之间， 其漏极耦接至参考电位线 VSS,其源极耦接至该偏置电流源 205并用于 输出电压信号， 其栅极耦接至转移晶体管 202的漏极， 即耦接到浮动扩 散区，以获取转移晶体管 202所转移的图像电荷信号。在偏置电流源 205 的偏置下，源跟随晶体管 204源极的电压跟随着其栅极所获取的图像电 荷信号变化而变化， 其电压增益接近于 1„ 在一个实施例中， 源跟随晶 体管 204的源极进一步通过行选择晶体管（图中未示出）耦接到位线（图 中未示出） ， 并将该电压信号提供给图像传感器的信号处理电路。
在一个实施例中， 谅图像传感器还包括复位晶体管 203, 谊复位晶 体管 203的漏极用于接收复位信号 RSG, 其源极耦接到转移晶体管 202 的漏极与源跟随晶体管 204的栅极。该复位晶体管 203的栅极用于接收 复位控制信号 RST,在该复位控制信号 RST的控制下， 复位晶体管 203 相应导通或关断， 从而向源跟随晶体管 204的栅极提供复位信号。 在该 实施例中， 转移晶体管 202与复位晶体管 203均为 NMQS晶体管， 可 以理解， 在其他的实施例中， 转移晶体管 202与复位晶体管 203亦可采 用其他类型的晶体管， 例如 PMOS晶体管或结型场效应管。
由于采用了结型场效座晶体管替代表面沟道 MOS晶体管作为源跟 随晶体管 204,这避免了导电沟道中的载流子因氧化层-半导体村底界面 处的界面态而被随机俘获或锋放，从而有效减少了输出的电压信号中的 闪烁噪声， 进而提高了图像传感器 200的成像质量。
在复位电容 213与图像电容 211分别存储对应于复位信号与图像电 荷信号的电荷之后， 放大单元 215对这两个电容上的电压差进行放大， 并将经过放大的输出电压提供给后续的处理电路。
图 3a示出了图 2 中图像传感器 200 的源跟随晶体管的一个例子 300， 其中该源跟随晶体管为 P型场效应晶体管。 本领域普通技术人员 应当理解，其工作原理同样适用于源跟随晶体管为 N型场效应晶体管的 情形。 如图 3a所示， 读源跟随晶体管包括：
P型衬底 301 ;
N型阱 303, 其位于 P型村底 301中；
N型淀积掺杂层 305, 其位于 P型衬底 301表面外， 并至少部分位 于 N型阱 303上；
P型源区 307, 其位于 N型阱 303中；
P型漏区 309, 其位于 P型衬底 301中和 /或 N型阱 303中；
P型掺杂层 311 ,其至少部分位于 N型阱 303与 N型淀积掺杂层 305 之间， 以使得 P型源区 307与 P型漏区 309电连接，并且使得 P型源区 307与 P型漏区 309电连接， 并在 P型捧杂层 311与 N型阱 303之间， 以及在谊 P型掺杂层 311与 N型淀积掺杂层 305之间分别形成 PN结。
具体地， P型衬底 301可以是 P型掺杂的半导体晶片， 或者是 P型 掺杂的绝缘体上硅（SOI ) , 或者是 N型掺杂的半导体晶片中的 P型阱 区， 或者其他类似衬底或阱区。
P型源区 307全部位于 N型阱 303中。该 N型阱 303使得 P型源区
307与 P型衬底 301相互隔离。 由于源区 307用于输出电压信号， 其可 能具有较高的电位， 而 P型衬底 301通常耦接到参考电位线， 例如地。 因此， 源区 307与 P型衬底 301相互隔离可以避免衬底穿通， 以保证源 跟随晶体管的正常工作。
4艮据具体实施例的不同，谊 P型漏区 309可以全部位于 N型阱 303 外的 P型村底 301中；或者全部位于 N型阱 303中； 或者一部分位于 N 型阱 303内， 而另一部分位于 N型阱 303外的 P型衬底 301中。 在图 3a所示的例子 300中， P型漏区 309全部位于 N型阱 303中， 因而其与 P型源区 307通过 N型阱 303内的 P型掺杂层 311相互电连接。在实际 应用中，该 P型源区 307以及 P型漏区 309分别与 P型摻杂层 311相互 部分重叠（overlap ) 以实现其间的电连接。 与 P型掺杂层 311对应， N 型淀积捧杂层 305也可以全部或部分地位于 N型阱 303上，并位于源区 307与漏区 309之间。 在图 3a的例子 300中， 该 N型淀积換杂层 305 的布图 （layout )全部位于 N型阱 303的布图内。 P型掺杂层 311位于 N型阱 303与 N型淀积捧杂层 305之间，并电 连接 P型源区 307与 P型漏区 309。 由于 P型掺杂层 311至少部分位于 N型阱 303中， 因而该 P型掺杂层 311与 N型阱 303接触，从而在其接 触界面附近形成了结型场效应管的一个 PN结。 此外， P型掺杂层 311 还与位于其上的 N型淀积掺杂层 305至少部分相互接触，从而在其接触 界面附近形成了结型场效应管的另一个 PN结。这使得 N型阱 303与 N 型淀积掺杂层 305作用为钹源跟随晶体管的栅极， 而两个 PN结之间的 区域即为源跟随晶体管 300的导电沟道区。 当源跟随晶体管工作时， N 型淀积掺杂层 305 (以及 N型阱 303 )与源区 307以及漏区 309之间的 电压差的不同会引起这两个 PN结的结空间电荷区的宽度变化， 即改变 了结型场效应管的导电沟道厚度， 进而改变了沟道电流的大小。 需要说 明的是， 由于 P型掺杂层 311与 N型淀积換杂层 305采用相同的材料， 即由硅构成， 因而其接触面位置的界面态缺陷远少于氧化层-衬底界面 的界面态缺陷。由于沟道电流处于远离 P型衬底 301表面的 P型掺杂层 311内，其基本上不会受到 P型衬底 301表面氧化层 -衬底界面的界面态 作用， 从而大大降低了界面态缺陷随机俘荻或释放载流子的几率， 进而 有效减少了源跟随晶体管输出电压信号中的闪烁噪声。
在一些实施例中， N型淀积掺杂层 305与 P型掺杂层 311之间的电 接触可以通过移除 P型村底 301表面的介电层 304，例如氧化层，实现， 即： P型衬底 301表面通常形成有一层氧化层， 可以将 P型掺杂层 311 上方的氧化层部分移除以将该 P型掺杂层 311从 P型衬底 301表面露出； 之后，再在 P型衬底 301上淀积例如擦杂的多晶硅或非晶硅以形成该 N 型淀积掺杂层 305。 谊介电层 304可以预先形成在 P型衬底 301表面。 由于介电层 304的隔离， N型淀积掺杂层 305仅与 P型掺杂层 311接触 并构成 PN结， 而不会与 P型源区 307以及 P型漏区 309电接触。 在一 些例子中，掺杂的多晶硅层或非晶硅层可以在被淀积时一并对该多晶硅 或非晶硅进行摻杂， 即在淀积的反应腔体中加入具有掺杂离子的气体。 这就不需要再以离子注入的方式来掺杂形成 N型淀积掺杂层 305,这可 以减少一次离子注入， 从而降低图像传感器的制作成本。 可以理解， 在 一些其他的例子中， N型淀积摻杂层 305也可以通过下述方式形成： 先 淀积多晶硅或非晶硅， 再对所淀积的多晶硅或非晶硅进行掺杂， 例如以 离子注入或扩散方式掺杂。
此外， N型淀积掺杂层 305可以采用例如干法刻蚀来控制， 其轮廓 易于控制， 因此采用读结型场效应管的图像传感器 300可靠性较高。 优 选地， 在图 3a所示的实施例中， N型淀积掺杂层 305的边缘位于介电 层 304上。兹介电层 304使得 N型淀积掺杂层 305边缘与 P型衬底 301 隔离。 在刻蚀 N型淀积摻杂层 305的过程中， 其边缘与 P型衬底 301 之间的介电层 304可以使得 N型淀积掺杂层 305的刻蚀停止在介电层 304上， 从而避免 P型衬底 301的损伤以及由此带来的晶体管损伤。 在 一些例子中， N型淀积換杂层 305与 P型衬底 301接触的部分位于介电 层 304的窗口内， 其边缘超出谅介电层 304窗口边缘一定长度， 例如 5 纳米、 10纳米、 50纳米， 等等。
在一些例子中，N型阱 303与 N型淀积掺杂层 305可以在 P型摻杂 层 311外部分相互重叠， 从而使得 N型阱 303与 N型淀积掺杂层 305 相互电连接。这就不需要在 N型阱 303中制作额外的通孔或其他结构来 引出 N型阱 303 , 从而降低了制作成本。 可以理解， 在另一些例子中， N型阱 303与 N型淀积掺杂层 305也可以不相互直接接触，而是通过介 电层 304中的通孔来电连接。
图 3b示出了图 2中图像传感器 200的源跟随晶体管的另一例子。 在图 3b中，还示出了图像传感器 200的光电二极管，其由 P型衬底 301 以及位于 N型阱 303外的 N型摻杂区 321构成。
如图 3b所示， P型衬底 301中还包括隔离沟槽 323，其位于 N型阱 303外， 即位于 N型掺杂区 321与 N型阱 303之间。 隔离沟槽 323采用 绝缘材料， 例如氧化硅、 氮化硅形成， 因而具有较好的电学隔离效果。 P型衬底 301中的隔离沟槽 323使得 N型掺杂区 321与 N型阱 303相互 隔离 ,其可以有效避免光电二极管的负极与源跟随晶体管的栅极之间发 生短路（即穿通）而影响图像传感器的运行。 可以看出， 由于减少了一 次离子注入， 导电沟道的轮廓易于控制， 并且不会由于退火次数过多而 造成较深的结深。 因此， 该图像传感器无需在导电沟道外的 P型衬底 301中制作较深的隔离槽来隔离相邻区域， 即隔离沟槽 323可以采用浅 沟槽隔离结构（ Shallow Trench Isolation ) ,其占用的芯片面积相对较小， 因而能够有效减少图像传感器的面积。
在一个优选的实施例中，隔离沟槽 323可以与 Ρ型源区 307和 /或 Ν 型捧杂区 321相邻， 这可以进一步减少图像传感器的面积， 从而提高芯 片集成度。特別地，在图 3b所示的例子中， 隔离沟槽 323与 N型阱 303 以及 P型源区 307相邻， 这使得 N型阱 303与 P型衬底 301的接触面 积减小， 从而有效减少了 N型阱 303与 P型衬底 301之间的寄生电容。 在图像传感器中， N型阱 303会被耦接到图像传感器的浮动扩散区。 可 以理解， N型阱 303与 P型衬底 301之间的寄生电容越小， 图像传感器 的灵敏度也越高。 因此，与 N型阱 303以及 P型源区 307相邻的隔离沟 槽 323能够进一步提高图像传感器的灵敏度。
此外， 在一些实施例中， N型淀积掺杂层 305的边缘也可以位于隔 离沟槽 323上。该隔离沟槽 323使得 N型淀积擦杂层 305边缘与 P型衬 底 301隔离。在刻蚀 N型淀积掺杂层 305的过程中，其边缘与 P型衬底 301之间的隔离沟槽 323可以使得 N型淀积掺杂层 305的刻蚀停止在隔 离沟槽 323上，从而避免 P型衬底 301的损伤以及由此带来的晶体管损 伤。
图 4a与图 4b示出了图 2中图像传感器 200的源跟随晶体管的另一 例子 400。 其中， 图 4b是图 4a中源跟随晶体管沿 AA，方向的剖面示意 图。
如图 4a与图 4b所示, 该源跟随晶体管具有与图 3a中的源跟随晶 体管类似的结构。 但是， 该源跟随晶体管的漏区 409位于 N型阱 403 外的 P型衬底 401中，这使得 P型掺杂的漏区 409与 P型衬底 401电连 接。 在实际应用中， 该漏区 409与 P型衬底 401均耦接至参考电位线， 例如地， 因此其间不具有电压差， 从而不会在漏区 409与 P型衬底 401 之间形成电流。
相应地， P型捧杂层 411至少部分地由 N型阱 403延伸至 P型衬底 401中， 以使得该 Ρ型衬底 401与 Ρ型捧杂层 411共同电连接源区 407 与漏区 409。这样， 当读源跟随晶体管导通时，沟道电流能够由漏区 409 经过该 Ρ型衬底 401以及 Ρ型捧杂层 411而流向源区 407。
特别地， 对于图像传感器 200而言， 其通常具有多个像素单元， 而 每个像素单元均具有源跟随晶体管。对于这些源跟随晶体管的漏区 409, 可以有部分或全部漏区 409均至少部分地位于 Ν型阱 403外的 Ρ型村底
401相等的电位， 从而其相互之间具有相等的电位。 因而， 这可以使得 在不增加芯片面积的情况下提高了接地的效果，例如可以通过 Ρ型衬底 401来共享接地， 这就避免不同像素单元接地电位不一致， 从而进一步 提高了图像传感器的性能。
参考图 ½, Ν型阱 403与 Ν型淀积掺杂层 405在 Ρ型掺杂层 411 外至少部分相互重叠， 从而使得 Ν型阱 403与 Ν型淀积掺杂层 405相 互电连接。 这就不需要在 Ν型阱 403中制作额外的通孔来引出 Ν型阱 403 , 从而降低了制作成本。
图 5a示出了才艮据本发明一个实施例的晶体管的制作方法 500。 如图 5a所示， 该制作方法 500包括：
执行步骤 S501 , 提供第一导电类型衬底， 该笫一导电类型衬底中 掺杂形成有第二导电类型阱；
执行步骤 S503 , 在第一导电类型衬底和 /或第二导电类型阱中捧杂 形成第一导电类型捧杂层；
执行步骤 S505, 形成第二导电类型淀积掺杂层， 其位于第一导电 类型衬底表面外并至少部分位于第一导电类型捧杂层上，以使得第二导 电类型淀积掺杂层与第一导电类型掺杂层之间形成 PN结；
执行步驟 S507, 在第二导电类型阱中形成第一导电类型源区， 并 在第二导电类型阱中和 /或第一导电类型衬底中形成第一导电类型漏 区， 以使得第一导电类型源区与第一导电类型漏区电连接。
可以理解，该晶体管的制作方法 500可以用于制作图像传感器中的 源跟随晶体管。 在实际应用中， 制作图像传感器的工艺还包括形成图像 传感器像素单元中的光电二极管、 以及其他晶体管， 例如转移晶体管、 复位晶体管、 行选择晶体管的步骤， 在此不再赘述。
在一些例子中，第二导电类型淀积掺杂层的边缘位于第一导电类型 衬底表面的介电层上， 或者位于第一导电类型衬底中的隔离沟槽上。在 刻蚀第二导电类型淀积掺杂层的过程中，其边缘与第一导电类型衬底之 间的介电层或隔离沟槽可以使得第二导电类型淀积掺杂层的刻蚀自停 止在介电层或隔离沟槽上，从而避免第一导电类型衬底的刻蚀损伤以及 由此带来的晶体管损伤。
在一些例子中， 在步骤 S505之前， 还包括： 在第一导电类型衬底 表面形成介电层和 /或在第一导电类型衬底中形成隔离沟槽； 并且形成 第二导电类型淀积掺杂层的步骤进一步包括： 部分刻蚀介电层， 以使得 第一导电类型摻杂层至少部分露出；在露出的第一导电类型掺杂层上淀 积掺杂的多晶硅或非晶硅以形成第二导电类型淀积掺杂层； 以及部分刻 蚀第二导电类型淀积掺杂层并使得被刻蚀的第二导电类型淀积掺杂层 边缘位于介电层上和 /或隔离沟槽上。
在一个实施例中， 部分刻蚀介电层的步骤进一步包括： 部分刻蚀介 电层以使得第一导电类型掺杂层与第二导电类型阱至少部分露出。 因 而，需要在露出的笫一导电类型掺杂层与第二导电类型阱上淀积掺杂的 多晶硅或非晶硅以形成第二导电类型淀积捧杂层。直接形成在第二导电 类型阱上的第二导电类型电极掺杂层可以与其下的第二导电类型阱电 接触， 从而可以将该第二导电类型阱电引出， 而无需制作通孔或其他电 连接结构来引出该第二导电类型阱。
图 5b至图 5e示出了图 5a的制作方法 500的剖面示意图。 其中， 该制作方法 500形成的晶体管为 P型场效应晶体管。本领域普通技术人 员应当理解， 其工作原理同样适用于晶体管为 N型场效应晶体管的情 形。 接下来， 参考图 5a至图 5e, 对用于制作图像传感器的该晶体管的 制作方法 500的一个实施例进行详迷。
如图 5b所示， 提供 P型衬底 501， 读 P型衬底 501中形成有光电 二极管区 502以及 N型阱 503。该 N型阱 503与光电二极管区 502通过 其间的 P型衬底 501相互分离。
之后， 如图 5c所示， 形成 P型掺杂层 511 , 其至少部分位于 N型 阱 503中。 在图 5c中， P型捧杂层 511全部位于 N型阱 503中。 此外， N型阱 503与位于其中的 P型掺杂层 511之间构成了晶体管的一个 PN 结。 在一些其他的实施例中， P型捧杂层 511也可以部分地位于 P型村 底 501中， 并且部分地位于 N型阱 503中 需要说明的是， 形成 P型掺 杂层 511以及 N型阱 503的步骤通常采用离子注入实现，在每次离子注 入之后， 还需要对该 P型衬底 501进行退火处理， 例如快速退火处理， 以激活离子并减少注入引起的晶格缺陷。
接着， 在 P型衬底 501表面形成介电层 504。 该介电层 504例如为 氧化珪或其他介材料，可以通过例如氧化工艺或淀积工艺形成该介电层 504。 可选地， 在一些例子中， 还可以在 P型衬底 501中形成隔离沟槽 (图中未示出） ， 该隔离沟槽通常位于 N型阱 511之外。
然后， 如图 5d所示， 形成 N型淀积掺杂层 505, 其位于 P型村底 501表面外并至少部分位于 N型阱 503上， 以使得 N型淀积摻杂层 505 与 N型阱 503中的 P型掺杂层 511之间形成 PN结。
具体地， 读 N型淀积掺杂层 505可以通过下述步骤形成： 首先， 部 分刻蚀介电层 504， 以在 P型衬底 501上形成窗口， 该窗口使得 P型掺 杂层 511至少部分露出； 接着， 在露出的 P型掺杂层 511上淀积掺杂的 多晶硅或非晶硅以形成 N型淀积捧杂层 505;之后，部分刻蚀 N型淀积 掺杂层 505并使得 N型淀积捧杂层 505边缘位于介电层 504上，或者使 得 N型淀积掺杂层 505的边缘位于隔离沟槽上， 即使得该 N型淀积掺 杂层 505的边缘不直接位于 P型衬底 501上。在一些例子中， 可以通过 化学气相淀积工艺淀积多晶硅或非晶硅，并在淀积该多晶硅或非晶硅的 同时掺杂 P型离子， 例如磷或砷离子， 以形成掺杂的多晶硅或非晶硅。 在另一些例子中， 可以通过化学气相淀积工艺淀积多晶硅或非晶硅， 之 后， 在所淀积的多晶硅或非晶硅中掺杂 P型离子， 例如通过扩散或离子 注入的方式摻杂。 在还有一些例子中， 可以先通过化学气相淀积工艺淀 积多晶硅或非晶硅，接着部分刻蚀所淀积的多晶硅或非晶硅， 之后再在 形成源区与漏区之前或之后对被刻蚀的多晶硅或非晶硅进行离子注入 来掺杂杂质离子。
在一个优选的实施例中， N型淀积掺杂层 505还直接形成在 N型阱 503上。相应地，介电层 504被刻蚀为使得 P型掺杂层 511与 N型阱 503 至少部分露出，并且在露出的 P型掺杂层 511与 N型阱 503上淀积掺杂 的多晶硅或非晶硅来形成 N型淀积摻杂层。
可以看出， 通过谊介电屋窗口， 所淀积的多晶硅能够与其下的 P型 掺杂层 511 直接接触， 从而形成结型场效应晶体管导电沟道另一侧的 PN结。 这个 PN结连同 P型掺杂层 511与 N型阱 503之间的 PN结共 同限定该结型场效应晶体管的导电沟道， 而 N型阱 503与 N型淀积掺 杂层 505则共同作为结型场效应晶体管的两个栅极。
接着， 如图 5e所示， 在 N型阱 503中形成 P型源区 507以及 P型 漏区 509, 并使得该 P型源区 507以及 P型漏区 509相互电连接。 在图 5e的例子中， P型源区 507与 P型漏区 509通过其间的 P型掺杂层 511 电连接。 可以理解， 在一些实施例中， P型漏区 509亦可形成在 N型阱 503外的 P型衬底 501 , 兹 P型漏区 509可以通过其与 N型阱 503之间 的 P型衬底 501来电连接到 N型阱 503, 并进一步地通过 P型掺杂层 511电连接到 P型源区 507。
可以看出， 由于该 N型淀积掺杂层 505可以通过淀积工艺形成， 而 无需通过离子注入方式形成在 P型衬底 501中。这可以减少一次离子注 入与退火处理， 从而降低了晶体管的制作成本。 此外， 由于减少了一次 离子注入， 导电沟道的轮廓易于控制， 并且不会由于退火次数过多而造 成较深的结深。 因此， 该结型场效应晶体管无需在导电沟道外的 P型村 底 501中制作较深的隔离槽来隔离相邻区域，例如 N型阱 503与光电二 极管区 502之间， 这可以降低制作工艺难度， 并减少晶体管的面积。
尽管在附图和前述的描迷中详细阐明和描述了本发明，应认为该阐 明和描述是说明性的和示例性的， 而不是限制性的； 本发明不限于所上 述实施方式。
那些本技术领域的一般技术人员可以通过研究说明书、公开的内容 及附图和所附的权利要求书， 理解和实施对披露的实施方式的其他改 变。 在权利要求中， 措词 "包括" 不排除其他的元素和步骤， 并且措辞 "一个" 不排除复数。 在发明的实际应用中， 一个零件可能执行权利要 求中所引用的多个技术特征的功能。权利要求中的任何附图标记不应理 解为对范围的限制。

Claims

权 利 要 求 书
1. 一种图像传感器， 其特征在于， 包括像素阵列， 所述像素阵 列中的一个或多个像素单元包括一个源跟随晶体管， 所述源跟随晶 体管是结型场效应晶体管， 其包括：
第一导电类型衬底；
笫二导电类型阱， 位于所述第一导电类型衬底中；
第二导电类型淀积掺杂层， 位于所述第一导电类型衬底表面外 并至少部分位于所述第二导电类型阱上；
第一导电类型源区， 位于所述第二导电类型阱中；
第一导电类型漏区， 位于所述第一导电类型衬底中和 /或位于所 迷第二导电类型阱中；
第一导电类型掺杂层， 至少部分位于所述第二导电类型阱与所 述第二导电类型淀积掺杂层之间， 以使得所述第一导电类型源区与 所述第一导电类型漏区电连接， 并在其与所述第二导电类型阱之间 以及其与所述第二导电类型淀积掺杂层之间分别形成 PN结。
2. 根据权利要求 1所述的图像传感器， 其特征在于， 所迷第二 导电类型淀积掺杂层包括掺杂的多晶硅层或非晶硅层。
3. 根据权利要求 1所述的图像传感器， 其特征在于， 所述第二 导电类型阱与所述第二导电类型淀积摻杂层在所述第一导电类型掺 杂层外至少部分相互重叠， 以使得所述第二导电类型阱与所迷第二 导电类型淀积掺杂层相互电连接。
4. 根据权利要求 1所述的图像传感器， 其特征在于， 所述第一 导电类型漏区和 /或所述第一导电类型掺杂层至少部分位于所述第二 导电类型阱外， 以使得所迷第一导电类型漏区与第一导电类型衬底 电连接。
5. 根据权利要求 1所述的图像传感器， 其特征在于， 所迷第二 导电类型淀积掺杂层的边缘位于第一导电类型衬底表面的介电层上 或者位于第一导电类型村底中的隔离沟槽上。
6. 一种晶体管的制作方法， 其特征在于， 包括下述步骤： 提供第一导电类型衬底， 所述第一导电类型衬底中掺杂形成有 第二导电类型阱；
在所述第一导电类型衬底和 /或所述第二导电类型阱中掺杂形成 第一导电类型掺杂层；
形成第二导电类型淀积掺杂层， 其位于所述第一导电类型衬底 表面外并至少部分位于所述第一导电类型掺杂层上， 以使得所述第 二导电类型淀积捧杂层与所述第一导电类型掺杂层之间形成 PN结； 在所述第二导电类型阱中形成第一导电类型源区， 并在所述第 二导电类型阱中和 /或所述笫一导电类型衬底中形成第一导电类型漏 区， 以使得所述笫一导电类型源区与所述笫一导电类型漏区电连接。
7. 根据权利要求 6所述的制作方法， 其特征在于， 所述第二导 电类型淀积掺杂层的边缘位于第一导电类型衬底表面的介电层上或 者位于第一导电类型村底中的隔离沟槽上。
8. 根据权利要求 7所述的制作方法， 其特征在于，
在形成所述第二导电类型淀积掺杂层的步骤之前， 还包括： 在 所述第一导电类型衬底表面形成所述介电层和 /或在所述第一导电类 型衬底中形成隔离沟槽；
并且所述形成第二导电类型淀积摻杂层的步骒进一步包括： 部分刻蚀所述介电层， 以使得所述第一导电类型掺杂层至少部 分露出；
在所述露出的第一导电类型掺杂层上淀积掺杂的多晶硅或非晶 硅以形成所述第二导电类型淀积掺杂层； 以及
部分刻蚀所述第二导电类型淀积摻杂层并使得被刻蚀的第二导 电类型淀积掺杂层边缘位于所迷介电层上和 /或所述隔离沟槽上。
9. 才 据权利要求 8所述的制作方法， 其特征在于， 所迷部分刻 蚀介电层的步脒进一步包括： 部分刻蚀所述介电层， 以使得所述第 一导电类型摻杂层与所述第二导电类型阱至少部分露出。
10. 根据权利要求 8所述的制作方法， 其特征在于， 所述淀积掺 杂的多晶硅或非晶硅的步骤进一步包括： 在淀积所述多晶硅或非晶 硅的同时对所淀积的多晶硅或非晶硅进行掺杂， 或者在淀积所述多 晶硅或非晶硅之后， 对所淀积的多晶硅或非晶硅进行掺杂。
PCT/CN2013/076473 2012-06-01 2013-05-30 图像传感器与晶体管的制作方法 WO2013178078A1 (zh)

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CN105304665A (zh) * 2015-10-29 2016-02-03 上海华力微电子有限公司 改善像素单元满阱容量的cmos图像传感器
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