WO2013170657A1 - 像素结构、双栅像素结构及显示装置 - Google Patents

像素结构、双栅像素结构及显示装置 Download PDF

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Publication number
WO2013170657A1
WO2013170657A1 PCT/CN2013/072762 CN2013072762W WO2013170657A1 WO 2013170657 A1 WO2013170657 A1 WO 2013170657A1 CN 2013072762 W CN2013072762 W CN 2013072762W WO 2013170657 A1 WO2013170657 A1 WO 2013170657A1
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layer
gate
pixel electrode
electrode
drain
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English (en)
French (fr)
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王世君
薛海林
车春城
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Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US13/995,455 priority Critical patent/US9401374B2/en
Publication of WO2013170657A1 publication Critical patent/WO2013170657A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • Pixel structure, double gate pixel structure and display device
  • the present disclosure relates to a pixel structure, a dual gate pixel structure, and a display device. Background technique
  • the aperture ratio is the ratio of the effective light transmission area of a pixel to the total area of the entire pixel.
  • the resolution of mobile phone products is getting higher and higher, the pixel size (Pixel pitch) is getting smaller and smaller, and the aperture ratio of Twisted Nematic ( ⁇ ) type products becomes a bottleneck.
  • the ⁇ type product In order to prevent the occurrence of flicker, the ⁇ type product must ensure the size of the storage capacitor Cst, so the aperture ratio is limited by 4 ⁇ . For double-gate LCD panels, the aperture ratio is lower.
  • FIG. 1 is a schematic diagram of a pixel structure of a conventional TN type liquid crystal panel, in which an insulating layer 5 (PVX) and a gate insulating layer 6 (GI) are interposed between the pixel electrode 7 and the common voltage line 8 (Vcom).
  • PVX insulating layer 5
  • GI gate insulating layer 6
  • Vcom common voltage line 8
  • one of the objects of the present disclosure is to provide a pixel structure, a dual gate pixel structure, and a display device for solving the technical problem of low aperture ratio of a conventional double gate pixel structure.
  • a pixel structure includes: a thin film transistor including a gate electrode, a gate insulating layer, an active layer, and a source and drain layer, which are sequentially stacked, the source and drain layers including a source and a drain, the gate insulating layer extending to a region of the pixel structure outside the thin film transistor; a passivation layer overlying the thin film transistor and extending to the pixel structure a region other than the thin film transistor; a lower pixel electrode located under the gate insulating layer; an upper pixel electrode located above the passivation layer, wherein the lower pixel electrode and the upper pixel electrode are connected by a via hole And the lower pixel electrode and the upper pixel electrode to One of the less is connected to the drain of the source and drain layers; and a common voltage line between the gate insulating layer and the passivation layer, and separated by the gate insulating layer and the blunt The layer overlaps at least partially with the lower pixel electrode and the upper pixel electrode to form a storage
  • the upper pixel electrode is connected to the lower pixel electrode through a via hole penetrating the passivation layer and the gate insulating film.
  • the thin film transistor is a bottom gate structure, the gate, the gate insulating layer, the active layer, and the source and drain layers are sequentially stacked from bottom to top; and the lower layer pixel
  • the electrodes are on the same layer as the gate.
  • the upper pixel electrode is connected to the drain by a via that passes through the passivation layer.
  • the common voltage line is in the same layer as the source and drain layers and is formed of the same metal material.
  • the thin film transistor is a top gate structure, the source drain layer, the active layer, the gate insulating layer, and the gate are sequentially stacked from bottom to top; and the lower layer pixel
  • the electrode is in the same layer as the source and drain layers.
  • a drain in the source drain layer is located on a side adjacent to the lower pixel electrode, and the lower pixel electrode is directly connected to the drain.
  • the common voltage line and the gate are in the same layer.
  • only the passivation layer is between the upper pixel electrode and the common voltage line; and only the gate insulating layer is between the lower pixel electrode and the common voltage line.
  • Another embodiment of the present disclosure provides a dual gate pixel structure including two sub-pixel structures, wherein each sub-pixel structure may be any of the pixel structures described above, and sources of thin film transistors in the two sub-pixel structures The electrodes are electrically connected to each other.
  • Still another embodiment of the present disclosure provides a display device including any of the above pixel structures or double gate pixel structures.
  • the present disclosure uses two upper and lower pixel electrode layers to form a storage capacitor with a common voltage line, increasing the overlap area between the pixel electrode layer and the common voltage line.
  • the thickness of the intermediate layer between the lines is reduced and the overlap area is increased, so that the storage capacitance can be increased.
  • the capacity of the storage capacitor is constant In this case, with the technical solution of the present disclosure, the width of the common voltage line can be reduced, thereby effectively increasing the aperture ratio.
  • FIG. 1 is a schematic diagram of a conventional twisted nematic double gate pixel structure
  • FIG. 2 is a plan view of a liquid crystal panel of a pixel structure according to an embodiment of the present disclosure
  • FIG. 3 is a schematic view of a pixel structure substantially cut along the AB direction of FIG. 2 according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a pixel structure cut along the CD direction of FIG. 2 according to an embodiment of the present disclosure. detailed description
  • FIG. 2 is a top view of a liquid crystal panel using a dual gate pixel structure according to an embodiment of the present disclosure.
  • the upper and lower pixel electrodes of each sub-pixel unit are connected through vias 9, two sub-pixel units HA and 11B.
  • the pixel electrodes overlap the common voltage line 8, respectively.
  • a row of sub-pixel arrays needs to be driven by two rows of gate lines.
  • a row of pixels between gate line 1A and gate line 1B needs to be simultaneously driven by gate line 1A and gate line 1B, and one data line 10 is connected to two columns of sub-pixel units ( For example, it is connected to the source of the thin film transistor of the sub-pixel unit).
  • FIG. 2 is only a schematic diagram showing a pixel structure according to an embodiment of the present disclosure. The dimensional ratios of the various parts shown in the figures are not necessarily drawn to scale in actual dimensions.
  • FIG. 3 is a schematic diagram of a pixel structure substantially cut along the AB direction of FIG. 2 according to an embodiment of the present disclosure.
  • the pixel structure includes: a gate 1 at a bottom layer; a lower pixel electrode 7A in the same layer as the gate 1; a gate insulating layer 6 overlying the gate 1 and the lower pixel electrode 7A; and a source 2 and a drain a drain 3 (source drain layer); an insulating layer 5 overlying the source 2 and the drain 3; an upper pixel electrode 7B electrically connected to the drain 3 and the lower pixel electrode 7A; and a semiconductor layer 4 at the gate Above the insulating layer 6, under the source 2, the drain 3, and connected to the source 2 and the drain 3; the insulating layer 5 covering the source 2 and the drain 3; the common voltage line 8, located Between the upper pixel electrode 7B and the lower pixel electrode 7A, an insulating material is filled between the common voltage line 8 and the upper pixel electrode 7B and the lower pixel electrode to ensure that the upper
  • the gate electrode 1, the gate insulating layer 6, the semiconductor layer 4, and the source and drain layers 2 and 3 constitute a thin film transistor (TFT).
  • TFT thin film transistor
  • the thin film transistor of the pixel structure may be located at a corner of the area where the pixel structure is located, but the present invention does not specifically limit the specific position of the thin film transistor in the pixel structure.
  • the gate insulating layer 6 of the thin film transistor may extend beyond the thin film transistor, for example, may extend to the entire area of the pixel structure.
  • the above insulating layer 5 can be used as a passivation layer which can be extended beyond the thin film transistor, for example, can be laid over the entire area of the pixel structure after forming the thin film transistor.
  • the material of the insulating layer may be any suitable insulating material, and the present disclosure is not particularly limited thereto.
  • the upper pixel electrode 7B may be located above the insulating layer 5, and the lower pixel electrode 7A may be located under the gate insulating layer 6.
  • the upper pixel electrode 7B and the lower pixel electrode 7A may be located outside the thin film transistor.
  • a small portion may overlap with the drain to achieve electrical connection with the drain.
  • the common voltage line 8 may be located between the insulating layer 5 and the gate insulating layer 6.
  • the common voltage line can be located between each column of pixels in the pixel array, and thus, the common voltage line can at least partially overlap the edge portions of the pixel electrodes 7A and 7B.
  • the common voltage line 8 overlaps at least a portion of the lower pixel electrode 7A and the upper pixel electrode 7B via the gate insulating layer 6 and the insulating layer 5, respectively, to form a storage capacitor Cst.
  • the upper layer pixel electrode 7B and the lower layer pixel electrode 7A may be completely opposed, that is, the upper layer pixel electrode 7B and the lower layer pixel electrode 7A are aligned in the vertical direction.
  • the upper pixel electrode 7B and the lower pixel electrode 7A are electrically connected through the via hole 9.
  • the via 9 can pass through the insulating layer 5 and the gate insulating layer 6.
  • the upper pixel electrode 7B and the lower pixel electrode 7A may also partially overlap.
  • the common voltage line 8 can at least partially overlap the upper pixel electrode 7B and the lower pixel electrode 7A to ensure that the upper and lower pixel electrodes and the common voltage line 8 together form the storage capacitor Cst.
  • the gate insulating layer 6 is interposed between the common voltage line 8 and the lower pixel electrode 7A, and the insulating layer 5 is interposed between the upper pixel electrode 7B and the common voltage line 8.
  • the common voltage line 8 and the source and drain layers 2 and 3 are respectively located on both sides of the via 9.
  • the common voltage line 8 overlaps the portion of the upper pixel electrode 7B and the lower pixel electrode 7A in the vertical direction, and the upper pixel electrode 7B and the lower pixel electrode 7A form a storage capacitor Cst with the common voltage line 8.
  • the upper pixel electrode 7B and/or the lower pixel electrode 7A cover the area of all the common voltage lines 8 to collectively form the storage capacitor Cst.
  • the storage capacitor Cst is formed by the upper and lower pixel electrodes together with the common voltage line 8, the overlap area is increased, so that the storage capacitor Cst can be increased.
  • the common voltage line 8 and the source 2 and drain 3 may be formed of the same metal layer or the same metal material.
  • the common voltage line can be formed in the same patterning process as the source and drain metal layers for forming the source 2 and the drain 3 and the source 2 and the drain 3.
  • the present disclosure is not limited thereto, and the common voltage line may be formed separately, or a different material may be used from the source 2 and the drain 3.
  • the pixel structure according to the present disclosure can have a larger storage capacitance than the prior art. Based on the above design, in the case where the capacity of the required storage capacitor Cst is constant, the technical solution of the present disclosure can effectively increase the aperture ratio by reducing the width of the common voltage line 8 (Vcom).
  • the material of the upper and lower pixel electrodes is indium tin oxide. It will be understood by those skilled in the art that in addition to using indium tin oxide as the pixel electrode, other conductive high transmittance materials can be used as the pixel electrode (transmittance is at least 97% or more), and the present disclosure is no longer used. --for example.
  • the positional relationship and the connection relationship between the gate electrode 1, the gate insulating layer 6, the semiconductor layer 4, and the source/drain layer in the above thin film transistor may be any manner known in the art, here No longer described in detail.
  • FIG. 3 only a bottom gate type thin film transistor has been described as an example.
  • the gate 1, the gate insulating layer 6, the semiconductor layer 4, and the source and drain layers are sequentially stacked from bottom to top.
  • the upper pixel electrode 7B is connected to the drain through a via hole penetrating through the insulating layer 5.
  • the present invention can also employ a thin film transistor of a top gate structure. In the thin film transistor of the top gate structure, the source and drain layers 2 and 3, the semiconductor layer 4, the gate insulating layer 6, and the gate electrode 1 are sequentially stacked from bottom to top.
  • the lower pixel electrode 7A may be located in the same layer as the source and drain layers 2 and 3.
  • the drain 3 in the source/drain layer may be located on the side close to the lower pixel electrode 7A and directly connected to the lower pixel electrode, and the above-mentioned insulating through the upper layer pixel electrode 7B and the drain as described above is no longer required.
  • the common voltage line 8 may be in the same layer as the gate 1.
  • other configurations of the pixel structure having the top gate structure thin film transistor may be the same as the above-described pixel structure having the bottom gate structure, and are not described herein again.
  • each pixel structure may include two sub-pixel structures, each of which may be described above for each pixel structure.
  • the source electrodes of the thin film transistors in the two sub-pixel structures are electrically connected to each other.
  • the source electrodes of the thin film transistors in the two sub-pixel structures may each be connected to the same data line on the substrate to thereby electrically connect to each other.
  • the electrical connection can also be implemented in any other suitable manner.
  • the embodiment of the present disclosure further correspondingly provides a mask production process of the pixel structure provided by the embodiment of the present disclosure, which is divided into the following five mask processing steps:
  • Step 1 Perform a mask processing process of the gate line 1;
  • the second step performing a mask processing process of the lower pixel electrode layer 7A;
  • the third step after depositing the gate insulating layer 6, the same metal layer is used to generate the source 2, the drain 3 and the common voltage line 8 through a mask process;
  • the fourth step performing a mask processing process of the insulating layer 5;
  • a mask processing process of the upper pixel electrode layer 7B is performed.
  • the lower pixel electrode layer 7A and the upper pixel electrode layer 7B can share the same mask, and The four-mask process of the conventional liquid crystal panel does not increase in cost.

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Description

像素结构、 双栅像素结构及显示装置 技术领域
本公开涉及一种像素结构、 双栅 ( Dual Gate )像素结构及显示装置。 背景技术
液晶显示器中有一个很重要的性能指标就是亮度， 而决定亮度最重要的 因素就是开口率， 开口率是指一个像素的有效透光区域占整个像素全部面积 的比例。
目前手机产品的分辨率越来越高， 像素尺寸（ Pixel pitch )越来越小， 扭 曲向列 （ Twisted Nematic , ΤΝ )型产品的开口率成为了一个瓶颈。 ΤΝ型产 品为防止闪烁（flicker )的产生， 必须保证存储电容 Cst的大小， 因此开口率 受到了 4艮大的限制。 对于双栅液晶面板来说， 开口率则更低。
图 1为传统的 TN型液晶面板的像素结构示意图， 其中像素电极 7与公 共电压线 8 ( Vcom )之间有绝缘层 5 ( PVX )和栅极绝缘层 6 ( GI ) 两层绝 缘层。 为保证存储电容 Cst必须有较大的正对面积， 需要将公共电压线 8 ( Vcom )的面积 #文的比较大。 然而， 公共电压线 8 ( Vcom )的面积增大后， 会使开口率降低。 发明内容
有鉴于此， 本公开的目的之一在于提供一种像素结构、 双栅像素结构及 显示装置， 用于解决传统的双栅像素结构的开口率低的技术问题。
根据本公开的一个实施例提供一种像素结构， 包括： 薄膜晶体管， 该薄 膜晶体管包括依次堆叠的栅极、 栅极绝缘层、 有源层、 以及源漏极层， 所述 源漏极层包括源极和漏极， 所述栅极绝缘层延伸到所述像素结构的在所述薄 膜晶体管之外的区域； 钝化层， 覆盖在所述薄膜晶体管上方， 并且延伸到所 述像素结构的在所述薄膜晶体管之外的区域； 下层像素电极， 位于所述栅极 绝缘层下方； 上层像素电极， 位于所述钝化层上方， 所述下层像素电极和所 述上层像素电极通过过孔相连， 且所述下层像素电极和所述上层像素电极至 少之一与所述源漏极层的漏极相连； 以及公共电压线， 位于所述栅极绝缘层 和所述钝化层之间， 且分别隔着所述栅极绝缘层和所述钝化层与所述下层像 素电极和所述上层像素电极至少部分交叠以形成存储电容。
在一个示例中， 所述上层像素电极通过穿过所述钝化层和所述栅极绝缘 膜的过孔与所述下层像素电极相连。
在一个示例中， 所述薄膜晶体管为底栅极结构， 所述栅极、 所述栅极绝 缘层、 所述有源层和所述源漏极层从下至上依次堆叠； 以及所述下层像素电 极与所述栅极位于同一层。
在一个示例中， 所述上层像素电极通过穿过所述钝化层的过孔与所述漏 极相连。
在一个示例中， 所述公共电压线与所述源漏极层位于同一层， 且由相同 的金属材料形成。
在一个示例中， 所述薄膜晶体管为顶栅极结构， 所述源漏极层、 所述有 源层、 所述栅极绝缘层和所述栅极从下至上依次堆叠； 以及所述下层像素电 极与所述源漏极层位于同一层。
在一个示例中， 所述源漏极层中的漏极位于靠近所述下层像素电极的一 侧， 且所述下层像素电极与所述漏极直接相连。
在一个示例中， 所述公共电压线和所述栅极位于同一层。
在一个示例中， 所述上层像素电极与所述公共电压线之间只有所述钝化 层； 且所述下层像素电极与所述公共电压线之间只有所述栅极绝缘层。
本公开的另一个实施例提供一种双栅像素结构， 包括两个子像素结构， 其中每个子像素结构可以为以上所述的任何像素结构， 且所述两个子像素结 构中的薄膜晶体管的源极电极彼此电连接。
本公开的再一个实施例提供一种显示装置， 包括以上所述任一像素结构 或双栅像素结构。
本公开采用上下两层像素电极层来与公共电压线形成存储电容， 增大像 素电极层与公共电压线之间的交叠面积。 下层像素电极和公共电压线之间只 有栅极绝缘层， 上层像素电极和公共电压线之间只有钝化层， 两层像素电极 和公共电压线之间的距离减小， 由于像素电极和公共电压线之间的中间层厚 度减小且交叠面积增加， 因而可以增大存储电容。 在存储电容的容量一定的 情况下， 采用本公开的技术方案， 可以减小公共电压线的宽度， 从而有效地 增加开口率。
附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为传统扭曲向列型双栅像素结构示意图；
图 2为采用本公开实施例提供的像素结构的液晶面板的俯视图； 图 3为本公开实施例提供的大致沿图 2的 AB方向切割后的像素结构示 意图；
图 4为本公开实施例提供的大致沿图 2的 CD方向切割后的像素结构示 意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
图 2为采用本公开实施例提供的双栅像素结构的液晶面板的俯视图， 从 图 2可以看出， 每个子像素单元的上下两层像素电极通过过孔 9连接， 两个 子像素单元 HA和 11B的像素电极分别与公共电压线 8交叠。一行子像素阵 列需要由两行栅线来驱动，例如在栅线 1A和栅线 1B之间的一行像素需要由 栅线 1A和栅线 1B同时驱动，一条数据线 10与两列子像素单元连接（例如， 与子像素单元的薄膜晶体管的源极相连） 。 另外， 图 2仅仅是示意性地示出 根据本公开实施例的像素结构。 图中所示各部分的尺寸比例并不一定是按实 际的尺寸比例绘制。
图 3为本公开实施例提供的大致沿图 2的 AB方向切割后的像素结构示 意图。 该像素结构包括： 栅极 1 , 位于最底层； 下层像素电极 7A, 与栅极 1位 于同一层； 栅极绝缘层 6, 覆盖于栅极 1和下层像素电极 7A之上； 源极 2 和漏极 3 (源漏极层）； 绝缘层 5, 覆盖于源极 2和漏极 3之上； 上层像素电 极 7B, 与漏极 3和下层像素电极 7A电性相连； 半导体层 4, 位于栅极绝缘 层 6之上，位于源极 2、漏极 3之下，并且与源极 2和漏极 3相连；绝缘层 5 , 覆盖在源极 2和漏极 3的上方；公共电压线 8,位于上层像素电极 7B与下层 像素电极 7A之间，公共电压线 8与上层像素电极 7B和下层像素电极之间分 别填充绝缘材料， 以保证上下两层像素电极与公共电压线 8共同形成存储电 容 Cst。
上述栅极 1、栅极绝缘层 6、半导体层 4以及源漏极层 2和 3构成薄膜晶 体管 （TFT ) 。 像素结构的薄膜晶体管可以位于该像素结构所在区域的一个 角落处， 但本发明对于该薄膜晶体管在该像素结构中的具体位置不作具体限 制。 另外， 该薄膜晶体管的栅极绝缘层 6可以延伸到薄膜晶体管之外， 例如， 可以延伸到像素结构的整个区域。
另外， 上述绝缘层 5可以用作钝化层， 其可以延伸到薄膜晶体管之外， 例如， 可以在形成薄膜晶体管之后铺设在像素结构的整个区域上。 对于该绝 缘层的材料， 可以为任何合适的绝缘材料， 本公开对此不作特别限制。
例如，上层像素电极 7B可以位于绝缘层 5上方， 下层像素电极 7A可以 位于栅极绝缘层 6下方。 例如， 对于平面位置， 上层像素电极 7B和下层像 素电极 7A大部分可以位于薄膜晶体管之外， 当然， 也可以有一小部分与漏 极重叠， 以实现与漏极的电连接。
例如， 公共电压线 8可以位于绝缘层 5和栅极绝缘层 6之间。 例如， 对 于平面位置， 公共电压线可以位于像素阵列中每列像素之间， 因此， 公共电 压线可以至少部分地与像素电极 7A和 7B 的边缘部分重叠。 公共电压线 8 分别隔着栅极绝缘层 6和绝缘层 5与下层像素电极 7A和上层像素电极 7B至 少部分交叠以形成存储电容 Cst。
在本公开优选实施例中， 在垂直方向 （各层的堆叠方向）上， 上层像素 电极 7B与下层像素电极 7A可以完全相对， 也就是上层像素电极 7B和下层 像素电极 7A在垂直方向上对齐。 上层像素电极 7B与下层像素电极 7A通过 过孔 9电性相连。 过孔 9可以穿过绝缘层 5和栅极绝缘层 6。 当然， 在一个 示例中，上层像素电极 7B与下层像素电极 7A也可以部分交叠。公共电压线 8可与上层像素电极 7B和下层像素电极 7A均至少部分交叠， 以保证上下两 层像素电极与公共电压线 8共同形成存储电容 Cst。 在图 3所示的实施例中， 栅极绝缘层 6插设在公共电压线 8与下层像素电极 7A之间， 绝缘层 5插设 在上层像素电极 7B和公共电压线 8之间。
在如图 2所示的沿栅极线 1A延伸的方向上，公共电压线 8与源漏极层 2 和 3分别位于过孔 9的两侧。公共电压线 8在垂直方向上与上层像素电极 7B 和下层像素电极 7A的部分交叠， 上层像素电极 7B和下层像素电极 7A与公 共电压线 8形成存储电容 Cst。 当然， 也可以是上层像素电极 7B和 /或下层 像素电极 7A覆盖全部的公共电压线 8的面积， 以共同形成存储电容 Cst。 与 现有技术相比， 由于是由上下两层像素电极与公共电压线 8共同形成存储电 容 Cst, 增加了交叠面积， 因此可以增大存储电容 Cst。
在一个实施例中， 公共电压线 8与源极 2和漏极 3可以由同一层金属层 或相同的金属材料形成。 例如， 公共电压线可以利用用于形成源极 2和漏极 3的源漏金属层与源极 2和漏极 3在同一构图工艺中形成。 然而， 本公开并 不限制于此， 公共电压线也可以单独形成， 或者可以与源极 2和漏极 3使用 不同的材料。
在一个实施例中， 如图 3所示， 上层像素电极 7B与公共电压线 8之间 只有绝缘层 5; 下层像素电极 7A与公共电压线 8之间只有栅极绝缘层 6。 与 现有技术相比， 由于上下层像素电极与公共电压线 8之间只有一层绝缘层， 因此减小了距离， 从而可以增大存储电容 Cst。
从以上描述可以知道， 如果公共电压线 8的宽度相同， 则与现有技术相 比， 根据本公开的像素结构能够具有较大的存储电容。 基于上述设计， 在所 需存储电容 Cst的容量一定的情况下， 本公开的技术方案可以通过减小公共 电压线 8 ( Vcom ) 的宽度的方式， 有效地增加开口率。
例如， 上下层像素电极的材质为铟锡氧化物。 本领域一般技术人员可以 理解， 除使用铟锡氧化物作为像素电极外， 还可使用其他可导电的透过率高 的材料作为像素电极（透过率至少在 97%以上），本公开不再——举例说明。
另夕卜， 上述薄膜晶体管中的栅极 1、栅极绝缘层 6、半导体层 4以及源漏 极层之间的位置关系和连接关系可以采用本领域中所熟知的任何方式， 这里 不再具体描述。 例如， 图 3中仅仅以底栅极型薄膜晶体管为例进行了描述。 如图 3所示， 在底栅极薄膜晶体管中， 栅极 1、 栅极绝缘层 6、 半导体层 4 以及源漏极层从下至上依次堆叠。 上层像素电极 7B通过穿过绝缘层 5的过 孔与漏极相连。 然而， 本发明也可以采用顶栅极结构的薄膜晶体管。 在顶栅 极结构的薄膜晶体管中， 源漏极层 2和 3、半导体层 4、栅极绝缘层 6和栅极 1从下至上依次堆叠。
例如， 在顶栅极结构的薄膜晶体管的情况下， 下层像素电极 7A可以与 源漏极层 2和 3位于同一层。 例如， 源漏极层中的漏极 3可以位于靠近下层 像素电极 7A的一侧， 且与下层像素电极直接连接， 而不再需要以上所述的 连接上层像素电极 7B和漏极的穿过绝缘层的过孔。 例如， 在顶栅极结构的 薄膜晶体管的情况下， 公共电压线 8可以与栅极 1位于同一层。 另外， 具有 顶栅极结构薄膜晶体管的像素结构的其他构造可以与上述具有底栅极结构的 像素结构相同， 这里不再赘述。
图 4为本公开实施例提供的大致沿图 2的 CD方向切割后的像素结构示 意图， 从该结构示意图中可以看出， 位于两行子像素电极之间有两条栅线， 即由图 4的像素结构构成面板中， 每行子像素通过两条栅线驱动。 在根据本 公开实施例的双栅像素结构中， 每个像素结构可以包括两个子像素结构， 每 个子像素结构可以为以上描述各个像素结构。 在这两个子像素结构中的薄膜 晶体管的源极电极彼此电连接。 例如， 两个子像素结构中的薄膜晶体管的源 极电极可以均连接到基板上的同一条数据线， 从而实现彼此电连接。 当然， 也可以采用其他任何合适的方式实现电连接。
本公开实施例还相应给出了本公开实施例所提供的像素结构的掩模生产 流程， 共分为以下五个掩模处理步骤：
第一步： 进行栅线 1的掩模处理过程；
第二步： 进行下层像素电极层 7A的掩模处理过程；
第三步： 沉积栅极绝缘层 6后， 采用同一金属层通过一次掩模处理过程 生成源极 2、 漏极 3及公共电压线 8;
第四步： 进行绝缘层 5的掩模处理过程；
第五步： 进行上层像素电极层 7B的掩模处理过程。
其中， 下层像素电极层 7A和上层像素电极层 7B可以共用同一掩模， 与 传统液晶面板的四次掩模工艺相比在成本上并没有增加。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种像素结构， 包括：
薄膜晶体管， 该薄膜晶体管包括依次堆叠的栅极、栅极绝缘层、有源层、 以及源漏极层， 所述源漏极层包括源极和漏极， 所述栅极绝缘层延伸到所述 像素结构的在所述薄膜晶体管之外的区域；
钝化层， 覆盖在所述薄膜晶体管上方， 并且延伸到所述像素结构的在所 述薄膜晶体管之外的区域；
下层像素电极， 位于所述栅极绝缘层下方；
上层像素电极， 位于所述钝化层上方， 所述下层像素电极和所述上层像 素电极通过过孔相连， 且所述下层像素电极和所述上层像素电极至少之一与 所述源漏极层的漏极相连； 以及
公共电压线， 位于所述栅极绝缘层和所述钝化层之间， 且分别隔着所述 栅极绝缘层和所述钝化层与所述下层像素电极和所述上层像素电极至少部分 交叠以形成存储电容。
2、 根据权利要求 1所述的像素结构， 其中，
所述上层像素电极通过穿过所述钝化层和所述栅极绝缘膜的过孔与所述 下层像素电极相连。
3、 根据权利要求 1所述的像素结构， 其中，
所述薄膜晶体管为底栅极结构， 所述栅极、 所述栅极绝缘层、 所述有源 层和所述源漏极层从下至上依次堆叠； 以及
所述下层像素电极与所述栅极位于同一层。
4、 根据权利要求 3所述的像素结构， 其中，
所述上层像素电极通过穿过所述钝化层的过孔与所述漏极相连。
5、 根据权利要求 3所述的像素结构， 其中，
所述公共电压线与所述源漏极层位于同一层，且由相同的金属材料形成。
6、 根据权利要求 1所述的像素结构， 其中，
所述薄膜晶体管为顶栅极结构， 所述源漏极层、 所述有源层、 所述栅极 绝缘层和所述栅极从下至上依次堆叠； 以及
所述下层像素电极与所述源漏极层位于同一层。
7、 根据权利要求 6所述的像素结构， 其中，
所述源漏极层中的漏极位于靠近所述下层像素电极的一侧， 且所述下层 像素电极与所述漏极直接相连。
8、 根据权利要求 6所述的像素结构， 其中，
所述公共电压线和所述栅极位于同一层。
9、 根据权利要求 1所述的像素结构， 其中，
所述上层像素电极与所述公共电压线之间只有所述钝化层； 且
所述下层像素电极与所述公共电压线之间只有所述栅极绝缘层。
10、 一种双栅像素结构， 包括两个子像素结构，
其中每个子像素结构包括：
薄膜晶体管， 该薄膜晶体管包括依次堆叠的栅极、栅极绝缘层、有源层、 以及源漏极层， 所述源漏极层包括源极和漏极， 所述栅极绝缘层延伸到所述 子像素结构的在所述薄膜晶体管之外的区域；
钝化层， 覆盖在所述薄膜晶体管上方， 并且延伸到所述子像素结构的在 所述薄膜晶体管之外的区域；
下层像素电极， 位于所述栅极绝缘层下方；
上层像素电极， 位于所述钝化层上方， 所述下层像素电极和所述上层像 素电极通过过孔相连， 且所述下层像素电极和所述上层像素电极至少之一与 所述源漏极层的漏极相连； 以及
公共电压线， 位于所述栅极绝缘层和所述钝化层之间， 且分别隔着所述 栅极绝缘层和所述钝化层与所述下层像素电极和所述上层像素电极至少部分 交叠以形成存储电容，
其中所述两个子像素结构中的薄膜晶体管的源极电极彼此电连接。
11、 根据权利要求 10所述的双栅像素结构， 其中，
所述上层像素电极通过穿过所述钝化层和所述栅极绝缘膜的过孔与所述 下层像素电极相连。
12、 根据权利要求 10所述的双栅像素结构， 其中，
所述薄膜晶体管为底栅极结构， 所述栅极、 所述栅极绝缘层、 所述有源 层和所述源漏极层从下至上依次堆叠； 以及
所述下层像素电极与所述栅极位于同一层。
13、 根据权利要求 12所述的双栅像素结构， 其中，
所述上层像素电极通过穿过所述钝化层的过孔与所述漏极相连。
14、 根据权利要求 12所述的双栅像素结构， 其中，
所述公共电压线与所述源漏极层位于同一层，且由相同的金属材料形成。
15、 根据权利要求 10所述的双栅像素结构， 其中，
所述薄膜晶体管为顶栅极结构， 所述源漏极层、 所述有源层、 所述栅极 绝缘层和所述栅极从下至上依次堆叠； 以及
所述下层像素电极与所述源漏极层位于同一层。
16、 根据权利要求 15所述的双栅像素结构， 其中，
所述源漏极层中的漏极位于靠近所述下层像素电极的一侧， 且所述下层 像素电极与所述漏极直接相连。
17、 根据权利要求 15所述的双栅像素结构， 其中，
所述公共电压线和所述栅极位于同一层。
18、 根据权利要求 10所述的双栅像素结构， 其中，
所述上层像素电极与所述公共电压线之间只有所述钝化层； 且
所述下层像素电极与所述公共电压线之间只有所述栅极绝缘层。
19、 一种显示装置， 包括如权利要求 1所述的像素结构。
PCT/CN2013/072762 2012-05-17 2013-03-15 像素结构、双栅像素结构及显示装置 Ceased WO2013170657A1 (zh)

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