WO2013152658A1 - Triple-junction solar cell and preparation method therefor - Google Patents

Abstract

Provided are a triple-junction solar cell and a preparation method therefor. The method comprises: providing a p-type Si substrate (110) above which a first subcell (100) is formed through diffusion and is provided with a first band gap; a GaAs_xP_1-x graded buffer layer (500) with graded components epitaxially growing above the first subcell (100), and being provided with a second band gap which is greater than the first band gap; a GaAsP second subcell (200) being formed above the graded buffer layer (500), and being provided with a third band gap which is greater than the first band gap; and an InGaP third subcell (300) being formed above the second subcell (200), being provided with a fourth band gap which is greater than the third band gap, and having a lattice constant which matches the second subcell (200). By simultaneously regulating the components x and y of As and P in the GaAs_xP_1-x second subcell (200) and the In_yGa_1-yP third subcell (300), it can be achieved that a double-junction cell has various band gap combinations under the condition of lattice matching, and the selection space of multi-junction solar cells can be greatly widened.

Description

 Three-junction solar cell and preparation method thereof

The present application claims priority to Chinese Patent Application No. 201210104646.5 , entitled " Three-junction Solar Cell and Its Preparation Method ", filed on April 11, 2012, the entire contents of in.

 Technical field

The invention relates to a three-junction solar cell and a manufacturing method thereof, and belongs to the technical field of semiconductor materials.

 Background technique

Due to the gradual depletion of non-renewable energy sources such as coal and oil and the resulting environmental degradation, human beings urgently need to use green energy to solve the huge problems they face. Solar cells manufactured by photoelectric conversion technology can directly convert solar energy into electrical energy, which greatly reduces the dependence of people's production and life on coal, oil and natural gas, and becomes one of the most effective ways to use green energy. Although silicon-based solar cells dominate in large-scale applications and industrial production, single-junction solar cells can only absorb sunlight in a specific spectral range, and their conversion efficiency is not high. If different band gaps are used Eg materials are prepared as multi-junction solar cells and these materials are pressed Eg The size is superposed from top to bottom to form a multi-junction solar cell. By allowing them to selectively absorb and convert different sub-domains of the solar spectrum, the photoelectric conversion efficiency of the solar cell can be greatly improved.

III - The V-group compound semiconductor-based multi-junction solar cell has long been a mainstream technology for space photovoltaic power sources because of its advantages of high temperature resistance, strong radiation resistance, and good temperature characteristics.

However, currently used for III - The substrate materials of the V-group compound semiconductor solar cells are mainly monolithic wafers and gallium arsenide single wafers, which are expensive and rare materials, which greatly affect the cost of the concentrating solar cell and restrict the raw materials. Its large-scale application. Therefore, in order to make multi-junction solar cells compete with the first and second generation solar cells, and even with traditional energy sources, it is necessary to develop new multi-junction solar cells with low cost and high efficiency. Adopted in this case The replacement of a Ge substrate by a Si substrate enables the realization of a low-cost, high-efficiency solar cell. Due to the abundant raw materials of Si and mature production technology, Si is used. The substrate not only greatly reduces the raw material cost of the multi-junction solar cell (the price of a 6-inch Ge substrate is about 10 times that of a Si substrate of the same size); at the same time, the multi-junction solar cell and the relatively mature Si processing technology is combined; in addition, the density of Si is small, which can reduce the weight of the entire battery, and will be beneficial to aerospace applications of multi-junction solar cells.

Summary of the invention

The present invention is directed to an efficient triple junction solar cell using a Si substrate and a method of fabricating the same. Using Si The substrate not only greatly reduces the raw material cost of multi-junction solar cells, but also combines multi-junction solar cells with relatively mature Si processing technology for III- The application and promotion of V-group compound semiconductor-based multi-junction solar cells is of great significance.

According to an aspect of the invention, a method for fabricating a three-junction solar cell, the specific steps of which include:

 1) providing a p-type Si substrate for semiconductor epitaxial growth;

 2) forming a diffusion method over the Si substrate a type region, as an emitter region, the substrate itself as a base region, thereby forming a first subcell having a first band gap;

3) epitaxially growing a GaAs _x P _1-x graded buffer layer over the first subcell, which is a layered multilayer structure, x varies from 0.05 to 0.95, and has a second larger than the first band gap Bandgap;

4) forming a GaAsP second subcell having a third band gap greater than the first band gap, the lattice constant of which matches the termination layer of the graded buffer layer, over the GaAs _x P _1-x graded buffer layer ;

 5) forming InGaP above the second sub-cell A third subcell having a fourth band gap greater than a third band gap, the lattice constant of which matches the second subcell.

According to another aspect of the present invention, a triple junction solar cell includes: a first subcell composed of a Si-based battery having a first band gap; and a GaAs _x P _1-x graded buffer layer formed on Above the first sub-cell, which is a layered multilayer structure, x varies from 0.05 to 0.95, has a second band gap greater than the first band gap; and a second subcell is formed on the GaAs _x P ₁ Above the _-x gradient buffer layer, which is composed of GaAsP, has a third band gap larger than the first band gap, and the lattice constant is matched with the GaAs _x P _1-x graded buffer layer termination layer; the third subcell is formed in Above the second sub-cell, which is composed of InGaP, has a fourth band gap greater than the third band gap, and the lattice constant is matched with the second sub-cell.

The above GaAs _x P _1-x graded buffer layer has a lattice constant a _{GaAsP as a function of} As composition in accordance with Vergard's theorem. The calculation formula is as follows (unit Å ): a _GaAsP =5.4505 + 0.20275x _As .

In the present invention, the band gap of the first subcell is preferably 1.11 eV. The lattice constant of the GaAs _x P _1-x graded buffer layer ranges from 5.43 to 5.51 Å, and the band gap varies from 1.54 to 2.62 eV, including a GaAs _x P _1-x lattice gradation layer, a GaAs stress balance layer, and GaAs _x P _1-x target lattice layer. Wherein the As component in the GaAs _x P _1-x lattice gradation layer varies from 0.05 to 0.95 and gradually increases; the GaAs stress balance layer is located above the GaAs _x P _1-x lattice gradation layer; GaAs _{The x} P _1-x target lattice layer is a termination layer of a GaAs _x P _1-x graded buffer layer over the GaAs stress balance layer and having a lower lattice constant than the GaAs stress balance layer. The second sub-cell is composed of GaAsP, and the band gap is adjusted to 1.40~1.60 eV by the As composition change, and the lattice constant is matched with the GaAs _x P _1-x graded buffer stop layer, but smaller than the GaAs crystal. Grid constant. The third sub-cell is composed of In _y Ga _1-y P, and the band gap is adjusted to 1.90-2.20 eV by the change of the In composition, and the lattice constant thereof is matched with the second sub-cell.

The innovations of the present invention are: 1) The replacement of expensive Ge or GaAs substrates with Si substrates greatly reduces battery cost. 2) Using GaAs _x P _1-x material as the graded buffer layer can overcome the lattice mismatch between the bottom cell Si (5.4309 Å) and the middle cell GaAsP (5.43~5.51Å: according to different As and P ratios). Effectively reduces the dislocation density. In particular, in the present invention, the GaAs _x P _1-x graded buffer layer has a multilayer structure, and the range of x varies from 0.05 to 0.95, the lattice constant ranges from 5.43 to 5.51 Å, and the band gap varies from 1.54 to 2.62 eV. By increasing the composition, the lattice constant is gradually increased, and the sub-terminating layer is a GaAs stress-balancing layer, and the stress is slowly released, overcoming the lattice mismatch between the first two sub-cells. 3) By simultaneously adjusting the components x and y of As and P in the GaAs _x P _1-x second sub-cell and the In _y Ga _1-y P third sub-cell, the two-junction cell can be realized in the case of lattice matching. The diversity of the bandgap combination (the black solid line range in Figure 1 is the bandgap range of the second and third sub-cells) greatly expands the choice of multi-junction solar cells, and can be selected according to actual needs (ground or space). Gap combination to obtain a current matching high efficiency solar cell.

Other features and advantages of the invention will be set forth in the description which follows, The objectives and other advantages of the invention may be realized and obtained by means of the structure particularly pointed in the appended claims.

While the invention will be described in conjunction with the exemplary embodiments and the methods of the invention, it is understood that the invention is not intended to limit the invention. Rather, the invention is to cover all alternatives, modifications, and equivalents of the scope of the invention as defined by the appended claims.

DRAWINGS

The drawings are intended to provide a further understanding of the invention, and are intended to be a In addition, the drawing figures are a summary of the description and are not drawn to scale.

Figure 1 is a plot of the lattice constant and band gap of a semiconductor material.

2 is a schematic structural view of a triple junction solar cell in accordance with a preferred embodiment of the present invention.

Figure 3 is a three-junction solar cell shown in Figure 2. GaAs _x P _1-x  Schematic diagram of the gradient buffer layer.

The numbers in the figure indicate:

100: first sub-battery; 110: p-type Si substrate; 120: first sub-cell window layer; 200: second sub-cell (GaAsP sub-cell); 210: second sub-battery back-field layer; 220: second Subcell base; 230: second subcell emitting region; 240: second subcell window layer; 300: third subcell (InGaP subcell); 310: third subcell backfield layer; 320: third sub Battery base; 330: third sub-cell emitting region; 340: third sub-cell window layer; 401: first and second sub-cell tunneling junctions; 402: second and third sub-cell tunneling junctions; 500: GaAs _x P _1-x graded buffer layer; 510: GaAs _x P _1-x lattice graded layer; 520: GaAs stress balance layer; 530: GaAs _x P _1-x target lattice layer; 600: highly doped cap layer.

 detailed description

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and embodiments, in which the present invention can be applied to the technical problems, and the implementation of the technical effects can be fully understood and implemented. It should be noted that the various embodiments of the present invention and the various features of the various embodiments may be combined with each other, and the technical solutions formed are all within the scope of the present invention.

A method for preparing a three-junction solar cell, comprising the following steps:

First, in the MOCVD system, a p-type Si substrate 110 having a doping concentration of 2 × 10 ¹⁷ cm ^-3 to 5 × 10 ¹⁷ cm ^{-3 is selected} as the first sub-cell base region. An n-type emitter region is obtained by diffusion method on the surface of the substrate to obtain a first subcell having a band gap of 1.11 eV and a thickness of the emitter region of preferably 100 nm; and an n-type InGaP window layer 110 is grown on the emitter region, the thickness of which is At 25 nm, the doping concentration is around 1 × 10 ¹⁸ cm ^-3 .

Next, a GaAs _x P _1-x graded buffer layer 500 is epitaxially grown on the first sub-cell 100. The details are as follows: First, a series of GaAs _x P _1-x material layers with increasing As composition are deposited as GaAs _x P _1-x lattice grading layer 510 with a variation range of 0.05-0.95; then a layer of GaAs material is deposited as a layer. The stress balance layer 520 has a thickness greater than the thickness of the front graded layer; finally, a layer of GaAs _x P _1-x material is deposited as the GaAs _x P _1-x target lattice layer 530, and the lattice constant of the layer is smaller than that of the GaAs crystal. The grid constant, the thickness can be the same as the thickness of the previous gradient layer.

Next, a heavily doped p++/n++-InGaP tunneling junction 401 is grown over the GaAs _x P _1-x graded buffer layer 500 with a total thickness of 50 nm and a doping concentration of up to 2 × 10 ¹⁹ cm ^-3 .

Next, a second sub-cell 200 is formed over the tunnel junction 401. Specific process: First, a p-AlGaInP material layer is epitaxially grown as a back field layer 210 over the tunneling junction 401, having a thickness of 50 nm, a doping concentration of 1 to 2 × 10 ¹⁸ cm ^-3 , and then, in the back field layer 210 The p-GaAs _0.90 P _0.10 material layer is grown as the base region 220, the band gap is 1.60 eV, the thickness is 3 micrometers, and the gradient doping method is used, the concentration is 1~5 × 10 ¹⁷ cm ^-3 ; then, above the base region 220 The n+-GaAs _0.90 P _0.10 material layer is grown as an emitter region 230 having a thickness of 100 nm and a doping concentration of about 2 × 10 ¹⁸ cm ^-3 . Finally, an n-type InAlP material layer is grown on the emitter region 230 as a window layer 240. The thickness is 25 nm and the doping concentration is about 1 × 10 ¹⁸ cm ^-3 .

Next, a heavily doped P++/n++-InGaAsP tunneling junction 402 is grown over the second subcell 200 with a thickness of 50 nm and a doping concentration of up to 2 × 10 ¹⁹ cm ^-3 .

Next, a third sub-cell 300 is epitaxially grown over the tunnel junction 402. Specific process: first, at the tunnel junction 402 The p+-AlInP material layer is epitaxially grown as a back field layer 310 with a thickness of 40 nm and a doping concentration of about 1 × 10¹⁸Cm^-3 Next, growing above the back field layer 310 p+-In_0.37Ga_0.63The P material layer serves as the base region 320, has a thickness of 2 μm, and has a doping concentration of 5 × 10¹⁷Cm^-3 Then, growing above the base 320 n+-In_0.37Ga_0.63The P material layer serves as the emitter region 330 with a thickness of 200 nm and a doping concentration of up to 2 × 10¹⁸Cm^-3 Finally, an n-type InAlP material layer is grown over the emitter region 330 as a window layer 340 having a thickness of 25 Nm, doping concentration is 1 × 10¹⁸Cm^-3 about.

Next, a layer of heavily doped n++-InGaP capping layer 600 is overlying the third subcell 300. , thickness is 1000 nm, doping concentration is 1 × 10¹⁹Cm^-3 .

After the epitaxial end of the sample, the surface of the sample is subjected to anti-reflection vapor deposition, preparation of a metal electrode, and the like, to complete the required solar cell.

As shown in FIG. 2, a three-junction solar cell prepared according to the above method includes: a Si-based first sub-cell 100, GaAsP second sub-cell 200, InGaP third sub-cell 300 and GaAs _x P _1-x  Gradient buffer layer 500, each subcell passes through a tunnel junction 401, 402 connect them.

Wherein, the Si-based first sub-cell 100 is formed on the p-type Si substrate, and an n-type region is formed as an emission region over the substrate by a diffusion method, and has a band gap of 1.11 eV. The GaAs _x P _1-x graded buffer layer 500 is located between the Si-based subcell and the GaAsP subcell to overcome the lattice mismatch between the two junction cells. The GaAs _x P _1-x graded buffer layer 500 is a layered multilayer structure with a lattice constant ranging from 5.43 to 5.51 Å and a band gap variation range of 1.54 to 2.62 eV, which is close to the end of the Si cell and consists of a series of The As-component gradually increasing GaAs _x P _1-x lattice grading layer 510 is composed of a range of 0.05 to 0.95; above the lattice-grading layer 510 is a GaAs stress-balancing layer 520 having a thickness of about 500 nm in GaAs. Above the stress balance layer 520 is a GaAs _x P _1-x target lattice layer 530 having a lattice constant smaller than the GaAs lattice constant as a termination layer of the graded buffer layer 500. The GaAs stress balancing layer 520 balances the stress generated by the stack of upper and lower materials. In a preferred embodiment of the present invention, as shown in FIG. 3, the GaAs _x P _1-x graded buffer layer 500 has a total of 8 layers, respectively GaAs _0.15 P _0.85 , GaAs _0.30 P _0.70 , GaAs _0.40 P _0.60 , GaAs _{0.55 .} P _0.45 , GaAs _0.70 P _0.30 , GaAs _0.85 P _0.15 , GaAs , GaAs _0.90 P _0.10 , doping concentration is about 1 × 10 ¹⁸ cm ^-3 . The first 6 layers are GaAs _x P _1-x lattice grading layer 510, each layer has a thickness of 250 nm, and the seventh layer is GaAs stress balance layer 520, the thickness of which is preferably 500 nm, and the eighth layer is GaAs _x P _1-x target lattice layer 530. The GaAsP subcell 200 is adjusted by the As composition to adjust the band gap to 1.40 to 1.60 eV, and the lattice constant is matched with the GaAs _x P _1-x graded buffer layer termination layer. The InGaP subcell 300 is adjusted to have a band gap of 1.90 to 2.20 eV by a change in In composition, and the lattice constant is matched with the GaAsP subcell 200. In a preferred embodiment of the present invention, GaAs _0.90 P _{0.10 is selected} as the material of the second sub-cell PN junction, the band gap is 1.60 eV, and In _0.37 Ga _0.63 P is selected as the material of the third sub-cell PN junction.

By simultaneously adjusting the components x and y of As and P in the GaAs _x P _1-x second sub-cell and the In _y Ga _1-y P third sub-cell, the two-junction cell can be realized in the case of lattice matching. The diversity of gap combinations. The solid line range of Figure 1 is the bandgap range of the second and third sub-cells. In practical applications, the band gap of the second sub-cell is generally 1.40~1.60 eV, and the band gap of the third sub-cell is 1.90~2.20 eV.

It is apparent that the description of the present invention should not be construed as being limited to the above-described embodiments, but rather to all embodiments that utilize the inventive concept.

Claims (12)

1.  A method for preparing a three-junction solar cell, comprising the steps of:

   Providing a p-type Si substrate for semiconductor epitaxial growth;

   Forming by diffusion method over the Si substrate a type region, as an emitter region, the substrate itself as a base region, thereby forming a first subcell having a first band gap;

   Extending a GaAs _x P _1-x graded buffer layer over the first subcell, which is a compositionally graded multilayer structure, x varies from 0.05 to 0.95, and has a second band gap greater than the first band gap ;

   Forming a GaAsP second subcell above the GaAs _x P _1-x graded buffer layer, having a third band gap greater than the first band gap, the lattice constant of which matches the termination layer of the graded buffer layer;

   Forming InGaP above the second subcell A third subcell having a fourth band gap greater than a third band gap, the lattice constant of which matches the second subcell.
2. The method of fabricating a three-junction solar cell according to claim 1, wherein the first subcell has a band gap of 1.11 eV. .
3. The method of fabricating a three-junction solar cell according to claim 1, wherein said GaAs _x P _1-x graded buffer layer comprises a GaAs _x P _1-x lattice graded layer, a GaAs stress balance layer, and GaAs _x P _{a 1-x} x target lattice layer, wherein the As component in the GaAs _x P _1-x lattice gradation layer varies from 0.05 to 0.95 and gradually increases; a GaAs stress balance layer is located in the GaAs _x P ₁ Above the _-x lattice gradient layer; the GaAs _x P _1-x target lattice layer is a termination layer of a GaAs _x P _1-x graded buffer layer over the GaAs stress balance layer and having a lattice constant less than the GaAs Stress balance layer.
4. A method of fabricating a three-junction solar cell according to claim 3, wherein: GaAs_xP_1-x The lattice constant of the target lattice layer determines the thickness of the GaAs stress balancing layer.
5. A method of fabricating a three-junction solar cell according to claim 1, wherein said second subcell is composed of GaAsP, and the band gap is adjusted to 1.40 to 1.60 eV by a change in As composition, and a lattice constant thereof is compared with said GaAs _x P _{1 The -x} gradient buffer terminates layer matching, but is smaller than the lattice constant of GaAs.
6. The method of manufacturing a three-junction solar cell according to claim 1, wherein the third sub-cell is composed of In _y Ga _1-y P, and the band gap is adjusted to 1.90 to 2.20 eV by a change in In composition, and a lattice constant thereof is obtained. Matches the second sub-cell.
7. A triple junction solar cell comprising:

   a first sub-battery composed of a Si-based battery having a first band gap;

   GaAs _x P _1-x graded buffer layer formed over the first subcell, which is a component of the graded multilayer structure, x ranges from 0.05 to 0.95, having a second bandgap greater than the first bandgap ;

   a second subcell formed over the GaAs _x P _1-x graded buffer layer, which is composed of GaAsP, having a third band gap greater than the first band gap, a lattice constant and the GaAs _x P _1-x gradient Buffer layer termination layer matching;

   a third sub-battery formed over the second sub-cell, which is composed of InGaP Constructed to have a fourth band gap greater than the third band gap, the lattice constant being matched to the second sub-cell.
8. A three-junction solar cell according to claim 7, wherein: GaAs _x P _1-x  The lattice constant of the graded buffer layer varies from 5.43 to 5.51 Å. The band gap varies from 1.54 to 2.62 eV.
9. The triple junction solar cell according to claim 7, wherein said GaAs _x P _1-x graded buffer layer comprises a GaAs _x P _1-x lattice graded layer, a GaAs stress balance layer, and GaAs _x P _1-x x a target lattice layer, wherein the As component in the GaAs _x P _1-x lattice gradation layer varies from 0.05 to 0.95 and gradually increases; the GaAs stress balance layer is located in the GaAs _x P _1-x crystal Above the lattice gradient layer; the GaAs _x P _1-x x target lattice layer is a termination layer of the GaAs _x P _1-x graded buffer layer, which is located above the GaAs stress balance layer, and has a lattice constant smaller than the GaAs stress balance Floor.
10. The triple junction solar cell according to claim 8, wherein the thickness of said GaAs stress balance layer is adjusted in accordance with the lattice constant of the GaAs _x P _1-x target lattice layer.
11. The triple junction solar cell according to claim 7, wherein the second subcell has a band gap ranging from 1.40 to 1.60 eV. .
12. The three-junction solar cell according to claim 7, wherein the third sub-cell InGaP is formed, and the band gap ranges from 1.90 to 2.20. eV.

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