WO2013151390A1 - Procédé de fabrication de structure de dispositif à semi-conducteur - Google Patents

Procédé de fabrication de structure de dispositif à semi-conducteur Download PDF

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Publication number
WO2013151390A1
WO2013151390A1 PCT/KR2013/002882 KR2013002882W WO2013151390A1 WO 2013151390 A1 WO2013151390 A1 WO 2013151390A1 KR 2013002882 W KR2013002882 W KR 2013002882W WO 2013151390 A1 WO2013151390 A1 WO 2013151390A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
encapsulant
semiconductor
light
device structure
Prior art date
Application number
PCT/KR2013/002882
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English (en)
Korean (ko)
Inventor
김창태
고재성
이창훈
Original Assignee
주식회사 씨티랩
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority claimed from KR1020120036182A external-priority patent/KR101291092B1/ko
Priority claimed from KR1020120093201A external-priority patent/KR101461153B1/ko
Priority claimed from KR1020120093213A external-priority patent/KR101300463B1/ko
Priority claimed from KR1020120093193A external-priority patent/KR20140026154A/ko
Priority claimed from KR1020120093187A external-priority patent/KR101299563B1/ko
Application filed by 주식회사 씨티랩 filed Critical 주식회사 씨티랩
Publication of WO2013151390A1 publication Critical patent/WO2013151390A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates generally to a method of manufacturing a semiconductor device structure, and more particularly, to a method of manufacturing a semiconductor device structure that is simple to manufacture.
  • the semiconductor device includes a semiconductor light emitting device (for example, a laser diode), a semiconductor light receiving device (for example, a photodiode), a pn junction diode electric device, a semiconductor transistor, and the like, and typically includes a group III nitride semiconductor light emitting device.
  • the group III nitride semiconductor light emitting device includes a compound semiconductor layer of Al (x) Ga (y) In (1-xy) N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1). It means a light emitting device such as a light emitting diode, and does not exclude the inclusion of a material or a semiconductor layer of these materials with elements of other groups such as SiC, SiN, SiCN, CN.
  • the semiconductor light emitting device is a substrate 100, a buffer layer 200 on the substrate 100, a first semiconductor layer having a first conductivity ( 300), an active layer 400 that generates light through recombination of electrons and holes, and a second semiconductor layer 500 having a second conductivity different from the first conductivity are sequentially deposited, and translucent thereon for current diffusion thereon.
  • the conductive film 600 and the electrode 700 serving as the bonding pad are formed, and the electrode 800 serving as the bonding pad is formed on the etched and exposed first semiconductor layer 300.
  • the substrate 100 side when the substrate 100 side is placed in the package, it functions as a mounting surface.
  • FIG. 2 is a diagram illustrating another example of a conventional semiconductor light emitting device, wherein the semiconductor light emitting device includes a substrate 100 (eg, a sapphire substrate) and a first semiconductor layer having a first conductivity on the substrate 100. 300; for example, an n-type GaN layer), an active layer 400 for generating light through recombination of electrons and holes; for example, InGaN / (In) GaN MQWs), a second semiconductor layer having a second conductivity different from the first conductivity (500; e.g., p-type GaN layer) are sequentially deposited, and an electrode film 901 (e.g., Ag reflecting film) formed of three layers for reflecting light toward the substrate 100 side thereon; : An Ni diffusion barrier layer and an electrode film 903 (eg, Au bonding layer), and are formed on the first semiconductor layer 300 which is etched and exposed, and serves as a bonding pad 800 (eg, Cr / Ni / Au).
  • a bonding pad 800
  • Laminated metal pads are formed.
  • the electrode film 903 side when the electrode film 903 side is placed in the package, it functions as a mounting surface.
  • a flip chip or junction down type chip shown in FIG. 2 is superior in heat dissipation efficiency to the lateral chip shown in FIG. 1. While the lateral chip must emit heat to the outside through the sapphire substrate 100 having a thickness of 80 to 180 ⁇ m, the flip chip transmits heat through the metal electrodes 901, 902, 903 positioned close to the active layer 400. Because it can release.
  • the semiconductor light emitting device package is a vertical semiconductor light emitting device (in the lead frame 110, 120, mold 130, and cavity 140) 150, a vertical type light-emitting chip is provided, and the cavity 140 is filled with an encapsulant 170 containing the phosphor 160.
  • a lower surface of the vertical semiconductor light emitting device 150 is electrically connected to the lead frame 110, and an upper surface of the vertical semiconductor light emitting device 150 is electrically connected to the lead frame 120 by a wire 180.
  • the mold 130, the encapsulant 170, or the lead frames 110, 120, the mold 130, and the encapsulant 170 carry the vertical semiconductor light emitting element, and thus, a carrier (ie, a carrier ( Carrier)
  • a method of manufacturing a semiconductor device structure positioning a semiconductor device on a plate, wherein the semiconductor device is a flip chip type semiconductor light emitting device. Positioning two electrodes of the semiconductor device toward the plate (defined in the vertical direction in the vertical direction and the horizontal direction in the horizontal direction in the path of the light generated in the semiconductor light emitting device); And covering the semiconductor device with an encapsulant, and before or after the separating step, forming an optical path conversion surface on at least one outer surface of the encapsulant.
  • FIG. 1 is a view showing an example of a conventional semiconductor light emitting device (Lateral Chip),
  • FIG. 2 is a view showing another example (flip chip) of a conventional semiconductor light emitting device
  • FIG. 3 illustrates an example of a method of manufacturing a semiconductor device structure according to the present disclosure
  • FIG. 5 illustrates another example of a method of manufacturing a semiconductor device structure according to the present disclosure
  • FIG. 6 is a diagram illustrating an example of a semiconductor device structure according to the present disclosure.
  • FIG. 7 illustrates another example of a method of manufacturing a semiconductor device structure according to the present disclosure
  • FIG. 8 illustrates another example of a semiconductor device structure according to the present disclosure
  • FIG. 10 illustrates another example of a method of manufacturing a semiconductor device structure according to the present disclosure
  • FIG. 11 illustrates another example of a semiconductor device structure according to the present disclosure
  • FIG. 12 illustrates another example of a semiconductor device structure according to the present disclosure
  • FIG. 13 illustrates another example of a semiconductor device structure according to the present disclosure
  • 15 is a view showing an example of a conventional semiconductor light emitting device package or semiconductor light emitting device structure
  • FIG. 16 illustrates another example of a semiconductor device structure according to the present disclosure
  • FIG. 17 is a diagram illustrating an example of a method of manufacturing the semiconductor device structure illustrated in FIG. 16;
  • 22 is a view showing an example of an entire shape of an encapsulant according to the present disclosure.
  • FIG. 25 is a diagram illustrating an example of a method of manufacturing a semiconductor device structure shown in FIG. 24;
  • FIG. 26 illustrates another example of a method of manufacturing the semiconductor device structure illustrated in FIG. 24;
  • FIG. 27 is a diagram illustrating an example of a process of curing an encapsulant in a process of manufacturing the semiconductor device structure illustrated in FIG. 24.
  • FIG. 30 illustrates another example of a semiconductor device structure according to the present disclosure
  • FIG. 31 illustrates another example of a semiconductor device structure according to the present disclosure
  • FIG. 32 is a view illustrating an example of arrangement of electrodes, external electrodes, and heat dissipation pads when the semiconductor device structure illustrated in FIG. 31 is viewed from below;
  • FIG. 33 is a view showing another example of arrangement of electrodes, external electrodes, and heat dissipation pads when the semiconductor element structure shown in FIG. 31 is viewed from below;
  • 34 to 36 illustrate an example of a method of manufacturing the semiconductor device structure illustrated in FIG. 11;
  • 39 to 41 are views illustrating an example of a method of manufacturing the semiconductor device structure illustrated in FIG. 12;
  • FIG. 3 is a view illustrating an example of a method of manufacturing a semiconductor device structure according to the present disclosure.
  • the semiconductor device 2 including the two electrodes 80 and 90 is bonded to the adhesive 3. Fix the position on the plate (1).
  • the encapsulating material (encapsulating material) 4 is used to wrap the semiconductor element 2.
  • the plate 1 and the semiconductor element 2 are separated.
  • the material constituting the plate 1 is not particularly limited, and a material such as sapphire may be used, or a flat structure such as metal or glass may be used. By using a rigid plate such as metal or glass, the process can be stabilized as compared with the use of a plate (plate) having a ductility such as blue tape.
  • the material constituting the adhesive 3 is not particularly limited, and any adhesive may be used as long as the semiconductor element 2 can be fixed to the plate 1.
  • the material of the encapsulant 3 silicone epoxy and silicone resin, which are conventionally used in LED packages, may be used.
  • the semiconductor element 2 and the plate 1 can be separated by applying heat or light that can melt the adhesive 3 or by using a solvent that can melt the adhesive 3. Do. It is also possible to use heat or light with a solvent. It is also possible to use an adhesive tape.
  • the encapsulant 4 may be formed by a conventional method such as dispensing, screen printing, molding, spin coating, stencil, and the like, which is formed by applying light to a photocurable resin (UV curable resin) and then irradiating with light. It is also possible. In the case where a translucent plate such as sapphire is used as the plate 1, it is also possible to irradiate light from the plate 1 side.
  • a translucent plate such as sapphire
  • the process can be performed with the plurality of semiconductor elements 2 placed on the plate 1.
  • the semiconductor element 2 has been described as having two electrodes 80 and 90, the number is not particularly limited. For example, in the case of a transistor, it may have three electrodes.
  • the semiconductor light emitting device includes a substrate 100 (eg, a sapphire substrate), a first semiconductor layer 300 having a first conductivity (eg, an n-type GaN layer), electrons, and holes on the substrate 100.
  • a substrate 100 eg, a sapphire substrate
  • a first semiconductor layer 300 having a first conductivity eg, an n-type GaN layer
  • electrons and holes on the substrate 100.
  • the active layer 400 (eg, InGaN / (In) GaN MQWs) that generates light through recombination of the second semiconductor layer 500 (eg, p-type GaN layer) having a second conductivity different from the first conductivity
  • a three-layer electrode film 901 e.g., Ag reflecting film
  • an electrode film 902 e.g., Ni diffusion barrier film
  • an electrode 800 eg, Cr / Ni / Au laminated metal pad serving as a bonding pad may be formed on the etched and exposed first semiconductor layer 300.
  • the semiconductor device 2 has two electrodes 80 and 90, and the electrode 90 may have the same configuration as the electrodes 901, 902 and 903 of FIG.
  • the electrode 80 and the electrode 90 are electrically insulated by an insulating film 5 such as SiO 2 .
  • the subsequent procedure is the same, and the semiconductor element 2 is wrapped using an encapsulating material (encapsulating material 4). Next, the semiconductor element 2 is separated from the plate 1 and the adhesive agent 3.
  • FIG. 5 shows another example of a method for manufacturing a semiconductor device structure according to the present disclosure, in which a plurality of semiconductor devices 2, 2 are integrally covered with an encapsulant 4 on a plate 1. After removing the plate 1, it becomes easy to package one semiconductor element 2, 2 integrally. The electrical connection method of the semiconductor element 2 and the semiconductor element 2 is mentioned later. It is also possible to separate them into individual semiconductor elements 2 as in FIG. This is possible by separating the plurality of semiconductor elements 2 and 2 from the plate 1 and then individualizing them through a process such as sawing. By using the sealing agent 4 which has softness after hardening, the bond with a flexible circuit board can be heightened further.
  • FIG. 6 is a view illustrating an example of a semiconductor device structure according to the present disclosure, and is formed such that the side surface 4a of the encapsulant 4 is inclined.
  • the encapsulant 4 has various angled outer surfaces, and the light extraction efficiency to the outside of the package is increased.
  • the screen partition wall is formed to be inclined, so that the side surface 4a can be formed, and when sawing, the side surface 4a can be formed by using a pointed cutter.
  • FIG. 7 is a view showing another example of a method of manufacturing a semiconductor device structure according to the present disclosure.
  • an insulating film 6, such as SiO 2 is formed on the electrode 80 and the electrode 90. It is provided in the state which exposed.
  • the external electrode 81 is connected to the electrode 80, and the external electrode 91 is formed on the electrode 90 to form a structure similar to a conventional package.
  • the external electrodes 81 and 91 may correspond to lead frames of a conventional package.
  • the external electrodes 81 and 91 may be widely spread and deposited so as to function as reflective films.
  • the insulating film 6 may merely serve as an insulating function, or may form an alternate stacked structure of SiO 2 / TiO 2 or form a DBR to reduce light absorption by the external electrodes 81 and 91. As shown in FIG. 4, when the semiconductor device 2 includes the insulating film 5, the insulating film 6 may be omitted.
  • the deposition process and the photolithography process used to form the insulating film 6 and the external electrodes 81 and 91 are common in the semiconductor chip process and are very familiar to those skilled in the art. By providing the external electrodes 81 and 91, mounting to the PCB, COB, etc. can be made easier. If necessary, it is also possible to provide only the insulating film 6 without the external electrodes 81 and 91.
  • the insulating film 6 can be formed of a white material so that the insulating film 6 can function as a reflective film.
  • a white PSR Photo Sloder Regist
  • a white PSR can be screen printed or spin coated and then patterned through a common photolithography process.
  • FIG. 8 is a diagram illustrating another example of a semiconductor device structure according to the present disclosure, and includes a semiconductor device 2A and a semiconductor device 2B electrically connected in series. This configuration is made possible by connecting the negative electrode 80A of the semiconductor element 2A and the positive electrode 90B of the semiconductor element 2B through the external electrode 89.
  • Reference numeral 4 is an encapsulant
  • 6 is an insulating film
  • 90A is a positive electrode of the semiconductor element 2A
  • 80B is a negative electrode of the semiconductor element 2B.
  • This configuration makes it possible to form an electrical connection between the integrated semiconductor elements 2A and 2B through the encapsulant 4 without the use of a monolithic substrate.
  • the structure of the semiconductor element thereon is the same, but according to the method of the present disclosure, the semiconductor element 2A and the semiconductor element 2B need not be elements having the same function. It goes without saying that the semiconductor elements 2A and 2B can be connected in parallel.
  • the side surface 4a of the encapsulant 4 may be formed to be inclined as shown in FIG. 6, and this configuration enables a high-voltage semiconductor light emitting device package or a semiconductor light emitting device structure that could not be previously imagined. .
  • FIG. 9 is a view illustrating an example of the use of a semiconductor device structure according to the present disclosure.
  • a conductive line 7a of the printed circuit board 7 and electrodes 80 and 90 are directly connected to each other.
  • the element 2D is connected through the conductive line 7b and the external electrodes 81 and 91.
  • the printed circuit board 7 may be a flexible circuit board.
  • FIG. 10 is a view showing another example of a method of manufacturing a semiconductor device structure according to the present disclosure, in which a semiconductor device 2 as shown in FIG. 2 is provided, and the semiconductor device 2 includes a substrate 100.
  • a first semiconductor layer 300 having a first conductivity, an active layer 400 that generates light through recombination of electrons and holes, and a second semiconductor layer having a second conductivity different from the first conductivity. 500 is grown, and electrodes 80 and 90 are formed.
  • the semiconductor element 2 is attached to the plate 1 with an adhesive 3, and then, prior to covering with the encapsulant 4, the substrate 100 is removed, and preferably a rough surface ( 301 is formed. The subsequent process is the same.
  • the substrate 100 may be removed by a process such as laser lift-off, and the rough surface 301 may be through dry etching such as an inductively coupled plasma (ICP). This enables chip level laser lift off.
  • ICP inductively coupled plasma
  • FIG. 11 is a view showing another example of a semiconductor device structure according to the present disclosure, in which an encapsulant 4 includes phosphors.
  • YAG, Silicate, Nitride phosphors and the like can emit light of a desired color.
  • FIG. 12 is a view showing another example of a semiconductor device structure according to the present disclosure, in which the phosphor layer 8 is formed in the encapsulant 4 or under the encapsulant 4. It is also possible to form the phosphor layer 8 on the encapsulant 4. This can be formed by precipitating the phosphor in the encapsulant 4, or spin coating separately, or by applying a phosphor contained in a volatile liquid, followed by volatilization, leaving only the phosphor and then covering it with the encapsulant 4. If necessary, a plurality of phosphor layers 8 can be formed.
  • FIG. 13 is a view showing still another example of the semiconductor device structure according to the present disclosure, in which the encapsulant 4 is provided with a rough surface or unevenness 4g for increasing light extraction efficiency.
  • the rough surface 4g can be formed by pressing, forming a nanoimprint, or the like.
  • After applying the bead material it is also possible to form through etching, sandblasting and the like.
  • the rough surface 4g may be formed before or after separation of the plate 1.
  • FIG. 14 is a view showing still another example of the semiconductor device structure according to the present disclosure, in which a lens 4c is formed on the encapsulant 4.
  • the lens 4c is formed integrally with the encapsulant.
  • Such an integrated lens 4c can be formed by a compression molding method or the like.
  • FIG. 16 is a view showing another example of a semiconductor device structure according to the present disclosure, in which the semiconductor device 2 is a flip chip type semiconductor light emitting device as shown in FIG. 4, and the side surface 4a of the encapsulant 4.
  • the light reflection surface 4b may be formed in the whole side surface 4a, and may be formed in one part. Preferably, it is formed under the side surface 4a in which the semiconductor element 2 is located.
  • the upper portion 4e of the side surface 4a on which the light reflecting surface 4b is not formed preferably has a predetermined height or more.
  • the upper portion 4e may have a direction perpendicular to the flat upper surface 4d, and an example of the overall shape thereof is illustrated in FIG. 22.
  • the semiconductor device structure may be used as a light source of a beam projector without a separate lens.
  • the light reflecting surface 4b is curved, and another example of the light reflecting surface 4b is shown in FIGS. 18 and 19.
  • the linear inclined surfaces 4b1 and 4b2 having two different inclinations form the reflective surfaces.
  • the side surface 4a in which the staircase 4b3 was formed on the inclined surface 4b1 is provided. It is also possible to introduce the inclined surface 4b1 and the stairs 4b3 a plurality of times.
  • the principle of the light reflecting surface 4b will be described with reference to FIGS. 20 and 21.
  • the side surface 4a shown in FIG. 6 can also be viewed as one of the reflective surfaces. Description of the same reference numerals is omitted.
  • the phosphor 8 is not necessarily provided, and may be conformal coated as shown in FIG. 16, may be contained in the entire encapsulant 4 as shown in FIG. 11, and only a part of the encapsulant 4. It may be provided. In the case where the insulating film 6 and the external electrodes 81 and 91 are provided, they are formed on the entire surface of the encapsulant 4 on the electrodes 80 and 90 side, and then removed in the sawing process by the blade 41 described later. It may be in the form, or may not be formed in the region where the light reflection surface 4b is formed in advance.
  • FIG. 17 is a diagram illustrating an example of a method of manufacturing the semiconductor device structure illustrated in FIG. 16, and is basically the same as the process described with reference to FIGS. 4 to 6, but the semiconductor devices 2c and 2d may be separated or sided ( In the process of forming 4a, the side surface 4a is formed at the same time as the semiconductor element 2 is separated by using a saw blade 41 having the shape of the light reflecting surface 4b and the upper portion 4e. It becomes possible.
  • the inclined surfaces 4b1 and 4b2 shown in FIG. 18 can be formed by using two different blades, and the inclined surfaces 4b1 and the stairs 4b3 shown in FIG. 19 correspond to the steps 4b3. It is possible to form by using the blade and the blade corresponding to the inclined surface 4b1.
  • the side surface 4a or the light reflecting surface 4b can be accurately formed in a desired shape. This is almost impossible in the case of dispensing the encapsulant 170, as shown in Figure 15, at the level of um or more (for example, when dispensing the encapsulant in COB), the present disclosure According to the method according to this, this becomes easy. Further, in the conventional package, a mold is required to have the shape of the lens 4c as shown in FIG. 14, but according to the method according to the present disclosure, the light reflecting surface 4b can be formed without the help of such a mold.
  • the light L1 has a critical angle.
  • the medium has a low index of refraction past the vertical side 4a, which is the boundary between the high medium (e.g. encapsulant 4) and the low index medium (e.g. air). Proceed.
  • the incident angle of the light L1 is large, it is reflected from the vertical side surface 4a to face the upper surface 4d, and likewise, the same principle is applied to the upper surface 4d.
  • the angle of incidence is smaller for the vertical side 4a, so that the triangle for the light L2 entering into the triangle C1 is smaller. It does not enter inside (C2), and it becomes possible to reflect light L2 to the upper surface 4d side.
  • the light reflecting surface 4b is a curved surface, the same principle applies at the tangent to each point in the light reflecting surface 4b.
  • the light reflecting surface 4b can be configured by straight lines, parabolas, arcs, or the like, or a combination thereof if possible to manufacture.
  • the light reflecting surface 4b can be configured to reflect all light incident on the light reflecting surface 4b to the upper surface 4d, but this is not required. More preferably, the light reflecting surface 4b is designed so that the light L2 reflected from the light reflecting surface 4b can be incident into the triangle C3 of the upper surface 4d. Such designs are well known to those skilled in the art of optics. As shown in FIG. 21, for one light L, the light reflecting surface 4b is larger than the incident angle ⁇ 1 when the light L is reflected on the vertical side surface 4a and faces the upper surface 4d. It is understood that the incident angle ⁇ 2 in the case of reflecting the light toward the upper surface 4d toward the upper surface 4d becomes smaller. The incidence angle is reduced and the probability of being emitted through the marine upper surface 4d is increased.
  • the semiconductor element 2 is a light emitting element
  • the light reflecting surface 4b and / or the white insulating film 6 by providing the light reflecting surface 4b and / or the white insulating film 6, the light extraction efficiency toward the upper surface 4d or above the semiconductor element 2 can be greatly increased.
  • a white mold 130 is used, and the mold 130 implements the shape of the entire package, provides a cavity 140, while providing light in the cavity 140. Provides the function to reflect.
  • the function of reflecting light by the white mold 130 is replaced by the light reflecting surface 4b (using the difference in refractive index between the encapsulant 4b and the outside) and the white insulating film 6 Is different from the white mold 13 in its position and function.
  • the provision of such a light reflecting surface 4b and the provision of the white insulating film 6 are attributable to the peculiar manner of the manufacturing method according to the present disclosure.
  • FIG. 23 is a view showing still another example of the semiconductor device structure according to the present disclosure, in which the semiconductor device 2a and the second semiconductor device 2b are integrally formed by the encapsulant 4.
  • a groove 4f is formed between the semiconductor device 2a and the second semiconductor device 2b, and the groove 4f may have various shapes such as a slit.
  • the groove 4f serves to integrate the semiconductor element 2a and the second semiconductor element 2b while integrating it, and prevents the function of the semiconductor element 2a and the function of the second semiconductor element 2b from being unnecessarily interfered with. It can also be used to.
  • the semiconductor element 2a and the second semiconductor element 2b need not be elements having the same function.
  • one may be a functional device and one may be a zener diode for antistatic.
  • the semiconductor element 2a and the second semiconductor element 2b are light emitting elements
  • the semiconductor element 2a and the second semiconductor element 2b may emit light of different colors, respectively.
  • the grooves 4f serve to form the light reflecting surface 4b.
  • the semiconductor elements 2a and the second semiconductor elements 2b can emit light to the respective upper surfaces 4d without interference with each other. Formation of the groove 4f is possible using a blade having a depth that does not cut the entire sealing agent 4.
  • the light reflecting surface 4b may be formed only on the semiconductor element 2a on one side.
  • FIG. 24 is a view showing still another example of the semiconductor device structure according to the present disclosure.
  • a rough surface or unevenness 4g is formed on the upper side of the encapsulant 4, and the lower side of the encapsulant 4 and the semiconductor element 2.
  • corrugated surface 4h is formed in the sealing agent 4 also in the side where the electrode 80,90 of () is located. It goes without saying that the unevenness 4g may be formed only on either side. In the case where the semiconductor element 2 is a semiconductor light emitting element, the unevenness 4g may function as a scattering surface for scattering light.
  • the unevenness 4h By the unevenness 4h, the area where the encapsulant 4 and the insulating film 6 and / or the external electrodes 81 and 91 face each other is enlarged, so that the bonding force between them can be improved. In addition, the movement toward the side can be suppressed by the unevenness 4h, so that the bonding force can be improved.
  • FIG. 25 is a view illustrating an example of a method of manufacturing the semiconductor device structure illustrated in FIG. 24.
  • the encapsulant 4 is formed by using a pressure plate 4j in a state where the semiconductor device 2 is fixed on the plate 1.
  • corrugation (4g; see FIG. 24) in is shown.
  • FIG. 26 is a view showing another example of the method of manufacturing the semiconductor device structure shown in FIG. 24.
  • the pressure plate 4k is shown.
  • corrugation 4h (refer FIG. 24) using the following is shown.
  • the pressing plate 4j may be flat as shown in FIG. 26, and may have irregularities as shown in FIG. 25. It goes without saying that the pressing plate 4k can be placed above the sealing agent 4 and the flat or uneven pressing plate 4j can be placed below the sealing agent 4.
  • FIG. 27 is a diagram illustrating an example of a process of curing an encapsulant in a process of manufacturing the semiconductor device structure illustrated in FIG. 24.
  • the encapsulant 4 is a thermosetting resin (e.g. silicone epoxy resin)
  • the uneven (4g, 4h) can follow the shape of the pressing plate (4j, 4k) as it is.
  • the unevenness 4g and 4h it is possible to form the unevenness 4g and 4h in a state in which the encapsulant 4 is placed above the glass transition temperature.
  • the hardening is performed at a high temperature at one time, the wave shape and bubbles are generated in the encapsulant 4, so that it cannot have a clean surface.
  • the encapsulant 4 can have a clean side.
  • FIG. 28 is a view showing another example of a semiconductor device structure according to the present disclosure, in which the encapsulant 4 is electrically insulated from the electrodes 80 and 90 on the opposite side of the semiconductor device 2, or
  • the heat dissipation pad 891 is electrically insulated from the 80 and 90 electrodes and the external electrodes 81 and 91 to discharge heat generated in the semiconductor element 2 to the outside.
  • the heat radiation pad 891 is formed after the insulating film 6 is formed and positioned on the insulating film 6. Through this configuration, it is possible to separate the path from which electricity is supplied to the path from which heat is released, thereby enhancing the effect of heat release.
  • the heat radiation pads 891 are deposited together.
  • FIG. 29 is a view illustrating still another example of the semiconductor device structure according to the present disclosure, in which an insulating film 6 is formed first, and then external electrodes 81 and 91 and a heat radiation pad 891 are formed. Although the same as the semiconductor element structure shown in 28, a part of the insulating film 6 is removed, so that the heat dissipation pad 891 is formed in direct contact with the semiconductor element 2. Through this configuration, the heat dissipation efficiency can be increased as compared with the interlayer insulating film 6 mainly composed of a dielectric material.
  • FIG. 30 is a view showing another example of a semiconductor device structure according to the present disclosure.
  • external electrodes 81 and 91 and a heat dissipation pad 891 are formed, followed by external electrodes 81 and 91 and heat dissipation.
  • the insulating film 6 is formed to electrically insulate the pad 891.
  • FIG. 31 is a view illustrating still another example of the semiconductor device structure according to the present disclosure, in which external electrodes 81 and 91 and heat dissipation pads 891 are formed without forming an insulating layer 6.
  • FIG. 32 is a view showing an example of arrangement of electrodes, external electrodes, and heat dissipation pads when the semiconductor device structure shown in FIG. 31 is viewed from below, with the semiconductor device 2 surrounded by the encapsulant 4 at the center thereof.
  • the external electrode 81 and the external electrode 91 are formed in each of the electrode 80 and the electrode 90, and the heat dissipation pad 891 is provided in almost the entire area except for this. Through this configuration, it is possible to maximize the heat dissipation of the semiconductor device structure by increasing the contact area with the PCB, COB, etc. to be mounted.
  • the heat dissipation pad 891 is formed on almost all of the semiconductor element 2 and the encapsulant 4, but it is not necessary to do so, and if necessary, the whole or part of the semiconductor element 2 and encapsulation.
  • the heat radiation pad 891 may be formed in all or part of the region (4).
  • FIG. 33 is a view showing another example of the arrangement of the electrode, the external electrode, and the heat dissipation pad when the semiconductor element structure shown in FIG. 31 is viewed from below, wherein the electrodes 80, 90 and 91, 81 are disposed; It is formed larger than the semiconductor device structure shown in FIG. 32, and is configured so that some heat can be released from the semiconductor device 2 via the electrodes 80 and 90 and through the external electrodes 81 and 91. .
  • the semiconductor element is a flip chip type semiconductor light emitting element
  • one of the electrodes 80 and 90 may be formed large in order to function as a reflecting plate, which may be a suitable configuration in this case.
  • the heat dissipation pad 891 not only functions for heat dissipation, but also functions as a light reflecting film when the semiconductor element is a semiconductor light emitting element.
  • the heat radiation pad 891 is preferably made of a metal such as Al, Au excellent in both heat radiation and reflectance.
  • the heat radiation pads 891, the external electrodes 81, 91, and the insulating film 6 are provided. It is completely covered by white PSR, DBR), maximizing light reflection efficiency.
  • FIG. 34 to 36 are diagrams illustrating an example of a method of manufacturing the semiconductor device structure illustrated in FIG. 11, wherein the semiconductor devices 2 and 2 are fixed to the plate 1 using the adhesive 3.
  • the sealing agent 4 containing the phosphor that is, the phosphor layer 8 is covered.
  • FIG. 35 the plate 1 is removed, and as shown in FIG. 36, the semiconductor elements 2 and 2 are separated from each other.
  • Conformal coating in this manner substitution of the conformal coating through the removal of the encapsulant 4 or the removal of the phosphor layer 8 is largely distinguished from the conformal coating which has been conventionally performed by spin coating or screen printing. do.
  • FIG. 37 is a view showing another example of a method of manufacturing a semiconductor device structure according to the present disclosure.
  • the semiconductor device 2, 2 manufactured in FIG. 36 is again used on the plate 1 by using an adhesive 3. Put it on, and apply the sealing agent 4 again.
  • easy shape control of the interface between the phosphor layer 8 and the encapsulant 4 is possible.
  • both appearance control of the phosphor layer 8 and appearance control of the encapsulant 4 covering the phosphor layer 8 can be easily performed.
  • the phosphor may be introduced into the external encapsulant 4 and the phosphor may not be introduced into the internal encapsulant 4.
  • the encapsulant 4 constituting the phosphor layer 8 and the encapsulant 4 covering the phosphor layer 8 may be the same material, but may have different properties (refractive index, hardness, light transmittance, curing rate, etc.). It may be a substance.
  • the present embodiment can be extended to a method of manufacturing a semiconductor device structure according to the present disclosure in which two or more same or different encapsulation agents are applied.
  • the semiconductor light emitting element is suitable for application to the semiconductor element, but when the phosphor is not contained, the semiconductor element need not necessarily be the semiconductor light emitting element.
  • FIG. 38 is a view illustrating another example of a method of manufacturing a semiconductor device structure according to the present disclosure.
  • the phosphor layer 8 is formed, and then the phosphor layer is not removed.
  • a part of (8) is removed to form a phosphor layer 8 conformally on each of the semiconductor elements 2 and 2. Thereafter, in the case where the process according to FIG. 37 proceeds, the use of the plate 1 can be reduced once.
  • 39 to 41 are views illustrating an example of a method of manufacturing the semiconductor device structure illustrated in FIG. 12. Unlike the method illustrated in FIG. 38, the phosphor layer 8 is not completely removed and separated. Leave it removed. Next, the semiconductor device structure is manufactured by covering the encapsulant 4 as shown in FIG. 40 and separating the semiconductor devices 2 and 2 as shown in FIG. 41.
  • the encapsulant 4 may have various shapes such as the shape shown in FIG. 13 and the shape shown in FIG. 14.
  • FIG. 42 and 43 illustrate another example of a method of manufacturing a semiconductor device structure according to the present disclosure.
  • a plate 1 is attached to an encapsulant 4 side.
  • Plate 1 may be attached to encapsulant 4 in the same manner as illustrated in FIG. 3.
  • the plate 1 may be attached to the encapsulant 4 side before or after separation of the plate 1 attached to the electrode 2 side in FIG. 3.
  • it is important that the plate 1 does not have the property of bending like a plate of a soft material.
  • FIG. 43 after the plate 1 shown in FIG.
  • the encapsulant 4 having a height of at most several mm is kept flat.
  • a rigid plate 1 The material of the plate 1 may be ceramic, glass, metal, engineering plastic, and the like, and the thickness may vary depending on the material. However, it is preferable to maintain a proper thickness to prevent bending and maintain mechanical stability. In the case of a glass substrate, 1 mm or more is enough, for example.
  • the plate 1 may be removed before or after the cutting of the two semiconductor devices 2, 2. According to another aspect of the present disclosure, for the purpose of presenting a method of manufacturing a semiconductor device structure deviating from these limitations. do.
  • a method of fabricating a semiconductor device structure comprising: positioning a semiconductor device on a plate, the method comprising: positioning the electrode of the semiconductor device to face the plate; Covering the semiconductor element with an encapsulant; And separating the semiconductor device covered with the encapsulant from the plate.
  • a method of manufacturing a semiconductor device structure comprising: positioning a semiconductor device on a plate, wherein the semiconductor device is a flip chip type semiconductor light emitting device, and positioning the two electrodes of the semiconductor device toward the plate.
  • the vertical upper direction is defined as the vertical direction and the horizontal direction is defined as the horizontal direction
  • Covering the semiconductor element with an encapsulant And separating the semiconductor device covered with the encapsulant from the plate; and before or after the separating step, forming an optical path conversion surface on at least one outer surface of the encapsulant.
  • optical path changing surface may be formed before the separation of the plate 1, as in FIG. 25, and may be formed after the separation of the plate 1, as in FIG.
  • the curved surface may be a single curved surface, a curved surface having a plurality of curvatures, a continuous surface, an intermittent curved surface, or the like.
  • the light reflecting surface may be composed of a total reflection surface.
  • a method for manufacturing a semiconductor device structure characterized in that the light path conversion surface is uneven.
  • a method for manufacturing a semiconductor device structure characterized in that the optical path conversion surface is formed on at least one of the upper side and the lower side of the encapsulant.

Abstract

La présente invention concerne un procédé de fabrication d'une structure de dispositif à semi-conducteur, comprenant les étapes de : fixation de la position d'un dispositif à semi-conducteur sur la partie supérieure d'une plaque, le dispositif à semi-conducteur étant un dispositif à semi-conducteur électroluminescent de type puce, et les positions de deux électrodes du dispositif à semi-conducteur étant fixées de façon à faire face à la plaque (une direction perpendiculaire est définie comme perpendiculaire vers le haut à partir du trajet d'une lumière produite par le dispositif électroluminescent semi-conducteur, et une direction horizontale est définie en tant qu'horizontale sur ledit trajet) ; et recouvrement du dispositif à semi-conducteur avec un matériau d'encapsulation, une étape de formation d'une surface d'altération de trajet de lumière sur au moins une surface externe du matériau d'encapsulation étant comprise avant ou après une étape de séparation.
PCT/KR2013/002882 2012-04-06 2013-04-05 Procédé de fabrication de structure de dispositif à semi-conducteur WO2013151390A1 (fr)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
KR10-2012-0036182 2012-04-06
KR1020120036182A KR101291092B1 (ko) 2012-04-06 2012-04-06 반도체 소자 구조물을 제조하는 방법
KR1020120093201A KR101461153B1 (ko) 2012-08-24 2012-08-24 반도체 소자 구조물을 제조하는 방법
KR10-2012-0093201 2012-08-24
KR10-2012-0093187 2012-08-24
KR1020120093213A KR101300463B1 (ko) 2012-08-24 2012-08-24 반도체 소자 구조물을 제조하는 방법
KR1020120093193A KR20140026154A (ko) 2012-08-24 2012-08-24 반도체 소자 구조물을 제조하는 방법
KR1020120093187A KR101299563B1 (ko) 2012-08-24 2012-08-24 반도체 소자 구조물을 제조하는 방법
KR10-2012-0093213 2012-08-24
KR10-2012-0093193 2012-08-24

Publications (1)

Publication Number Publication Date
WO2013151390A1 true WO2013151390A1 (fr) 2013-10-10

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WO (1) WO2013151390A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050116373A (ko) * 2003-03-10 2005-12-12 도요다 고세이 가부시키가이샤 고체 소자 디바이스 및 그 제조 방법
JP2006024615A (ja) * 2004-07-06 2006-01-26 Matsushita Electric Ind Co Ltd Ｌｅｄ照明光源およびその製造方法
KR20100060867A (ko) * 2008-11-28 2010-06-07 삼성전기주식회사 웨이퍼 레벨 패키지의 제조방법
JP2011258801A (ja) * 2010-06-10 2011-12-22 Citizen Electronics Co Ltd 発光ダイオード

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050116373A (ko) * 2003-03-10 2005-12-12 도요다 고세이 가부시키가이샤 고체 소자 디바이스 및 그 제조 방법
JP2006024615A (ja) * 2004-07-06 2006-01-26 Matsushita Electric Ind Co Ltd Ｌｅｄ照明光源およびその製造方法
KR20100060867A (ko) * 2008-11-28 2010-06-07 삼성전기주식회사 웨이퍼 레벨 패키지의 제조방법
JP2011258801A (ja) * 2010-06-10 2011-12-22 Citizen Electronics Co Ltd 発光ダイオード

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