WO2013143296A1 - X射线检测装置的阵列基板及其制造方法 - Google Patents

X射线检测装置的阵列基板及其制造方法 Download PDF

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Publication number
WO2013143296A1
WO2013143296A1 PCT/CN2012/084611 CN2012084611W WO2013143296A1 WO 2013143296 A1 WO2013143296 A1 WO 2013143296A1 CN 2012084611 W CN2012084611 W CN 2012084611W WO 2013143296 A1 WO2013143296 A1 WO 2013143296A1
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Prior art keywords
layer
drain
array substrate
electrode
source
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PCT/CN2012/084611
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English (en)
French (fr)
Inventor
谢振宇
张文余
徐少颖
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北京京东方光电科技有限公司
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Publication of WO2013143296A1 publication Critical patent/WO2013143296A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing

Definitions

  • Embodiments of the present invention relate to an array substrate of an X-ray detecting apparatus and a method of fabricating the same. Background technique
  • X-ray inspection is mainly for plane inspection.
  • X-ray imaging has used film to record optical images.
  • the concept of digital medical X-ray imaging has been proposed as early as the early 1970s.
  • digital medical image transmission and image storage transmission systems With the revolutionary development of digital medical image transmission and image storage transmission systems, the application of digital X-ray imaging technology has made great progress.
  • CCD Charge Coupled Device
  • CMOS Complementary Metal Oxide Semiconductor
  • the digital X-ray imaging system saves up to four times the processing time compared to traditional computer imaging systems, and with high-resolution display panels, it also improves efficiency, diagnostic accuracy, and a film-free medical environment.
  • the active matrix planar detector can be applied to non-destructive testing, and the physical or mechanical properties of the object to be tested can be detected in time without damaging the sample to be tested. It is easy to detect cracks, holes and micros such as 50 microns. Defects are therefore widely used, especially in the electronics, aerospace and automotive industries.
  • each pixel region of the array substrate of the conventional X-ray detector generally includes: a photodiode sensor device 200 and a thin film transistor device 300.
  • the main function of the photodiode sensor device is to receive light and convert the optical signal into an electrical signal through the photovoltaic effect, and the main function of the thin film transistor device is to act as an electrical signal for controlling the switch and transmitting the photovoltaic effect.
  • the existing X-ray detector operates on the principle that when the X-ray 101 is bombarded on the phosphor 102 disposed before the array substrate, the phosphor 102 generates visible light which is incident on the photodiode sensor device 200 of the array substrate.
  • the photodiode sensor device 200 converts the optical signal into an electrical signal by a photovoltaic effect, and the electrical signal is input to the control circuit of the X-ray detector through the switching control of the thin film transistor device 300.
  • the prior art requires the preparation of the above X-ray detector array substrate by using 9 masks.
  • the main process steps are as follows.
  • Step 101 forming a gate electrode 11 on the base substrate 10 by a first mask process
  • Step 102 depositing a gate insulating layer 12 on the substrate on which the step 101 is completed, and forming an active layer 13 on the array substrate by a second mask process;
  • Step 103 forming a channel barrier layer 14 by a third mask process on the substrate on which step 102 is completed;
  • Step 104 depositing an ohmic contact layer 29 and a source/drain electrode metal layer on the substrate on which step 103 is completed, and forming a source electrode 15, a drain electrode 16 and a light reflecting layer 17 through a fourth mask process;
  • Step 105 forming a N-type semiconductor 18, an I-type semiconductor 19, a P-type semiconductor 20 (ie, a portion of the PIN-type photodiode sensor device) and a transparent electrode 21 through a fifth mask process on the substrate on which the step 104 is completed;
  • Step 106 depositing a first passivation layer 22 on the substrate on which step 105 is completed, and forming a first via 23 and a second via 25 on the first passivation layer 22 through a sixth mask process;
  • Step 107 forming a pattern of the photomask 27, the bias electrode 24 and the signal line 26 through the seventh mask process on the substrate on which the step 106 is completed;
  • Step 108 depositing a second passivation layer 28 on the substrate on which the step 107 is completed, and forming a passivation layer via hole of the signal guiding region by an eighth mask process (not shown);
  • Step 109 forming a transparent electrode (not shown) of the signal guiding region through the ninth mask process on the substrate on which the step 108 is completed.
  • the above technique has a drawback in that in order to avoid affecting the uniformity of the active layer channel of the formed thin film transistor device when forming the photodiode sensing device, it is necessary to form over the active layer by a single mask process (step 103).
  • a channel barrier layer which undoubtedly increases the complexity of the array substrate manufacturing process, making the production capacity difficult to increase.
  • the technology in order to reduce the influence of channel leakage current of the thin film transistor device, the technology also needs to add a metal mask to block the light generated by the X-ray bombardment of the phosphor, which also makes the manufacturing cost cannot be further reduced. Summary of the invention
  • An embodiment of the present invention provides an array substrate of an X-ray detecting device and a manufacturing method thereof for solving the X-ray detecting device array substrate existing in the prior art, and additionally adopting a mask process to form a channel barrier layer.
  • An embodiment of the present invention provides an array substrate of an X-ray detecting apparatus, comprising: a source and a drain formed opposite to each other on a substrate, and a reflective layer connected to the drain; formed on the source and the drain An ohmic contact layer above the pole;
  • An active layer formed over the ohmic contact layer and at least partially overlapping the source and drain to form a channel;
  • a gate insulating layer formed on the active layer and the transparent electrode and covering the entire substrate;
  • a gate electrode formed over the gate insulating layer and above the active layer and a bias electrode connected to the transparent electrode through the gate insulating layer via.
  • the photodiode is a PIN type photodiode including a P-type semiconductor, an I-type semiconductor, and an N-type semiconductor, and the ohmic contact layer is an N-type semiconductor layer.
  • the gate material is a heavy metal or a heavy metal alloy.
  • the source, the drain, and the light reflecting layer are formed of the same material.
  • the gate electrode and the bias electrode are made of the same material.
  • Another embodiment of the present invention provides a method for manufacturing an array substrate of an X-ray detecting apparatus, including:
  • a relatively disposed source and drain, a reflective layer connected to the drain, an ohmic contact layer on the source and the drain, and an optoelectronic layer on the reflective layer are formed on the substrate by a first mask process. a pattern of diodes and transparent electrodes;
  • a gate electrode over the active layer and a bias electrode pattern connected to the transparent electrode through the gate insulating via are formed by a fourth mask process.
  • the first masking process is a halftone masking process, including the steps of: sequentially depositing a source/drain electrode metal layer, an N-type semiconductor layer, an I-type semiconductor layer, and a P-type on a substrate.
  • the substrate is exposed by a mask having a fully transparent region, a semi-transmissive region and an opaque region, wherein the positions of the all-transmissive regions are all exposed, and the shape is etched a channel pattern; a portion of the semi-transmissive region is partially exposed, and a source, a drain, and an ohmic contact layer pattern are formed after etching; a position corresponding to the opaque region is not exposed, and a reflective layer, a PIN photodiode is formed after etching And transparent electrode graphics.
  • the transparent electrode layer, the P-type semiconductor layer of the partially exposed region on the substrate are completely etched away, and the I-type semiconductor layer is partially etched away.
  • the opposite source and drain electrodes, the reflective layer connected to the drain, the source and the drain can be formed by the first halftone mask process.
  • the formed gate can protect the channel, which omits the mask process formation process of the prior art channel barrier layer, simplifies the manufacturing process of the array substrate, and improves the productivity; in addition, since the gate is active Above the layer, this effectively blocks the light, which greatly reduces the channel leakage current, eliminating the need for an additional mask, which further reduces the production cost while simplifying the production process.
  • FIG. 1 is a schematic cross-sectional structural view of an array substrate of a prior art X-ray detecting device
  • FIG. 2 is a schematic structural view of a prior art X-ray detecting device detecting principle
  • FIG. 3 is a schematic cross-sectional structural view of an array substrate of an X-ray detecting device of the present invention.
  • Figure 5 is a cross-sectional view of Figure 4 at A-A;
  • FIG. 6 is a cross-sectional view of the first halftone mask process of the present invention at AA after the first etching;
  • FIG. 7 is a second etching (ashing) of the first halftone mask process of the present invention. Sectional view at AA;
  • FIG. 8 is a cross-sectional view of the first halftone mask process of the present invention at AA after the third etching;
  • FIG. 9 is a cross-sectional view of the first halftone mask process of the present invention after stripping the photoresist at AA
  • Figure 10 is a top plan view of the first halftone mask process stripping photoresist of the present invention;
  • FIG. 11 is a top plan view of the second mask process after etching according to the present invention.
  • 12 is a cross-sectional view of the second mask process of the present invention after etching at AA;
  • FIG. 13 is a plan view of the third mask process after etching according to the present invention.
  • Figure 14 is a top plan view of the fourth mask process after etching according to the present invention.
  • Figure 15 is a cross-sectional view of the fourth mask process of the present invention after etching at A-A;
  • Figure 16 is a cross-sectional view showing the fifth mask process (signal guiding region connecting data line vias) after etching according to the present invention
  • 17 is a cross-sectional view showing the fifth mask process (signal guiding region connecting gate line via) after etching according to the present invention.
  • Figure 18 is a cross-sectional view of the sixth masking process (transparent electrode connecting the signal guiding region and the data line) of the present invention.
  • Figure 19 is a cross-sectional view showing the sixth mask process (transparent electrode in which the signal guiding region is connected to the gate line) of the present invention.
  • the embodiment of the present invention An array substrate of an X-ray detecting device and a method of manufacturing the same are provided.
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining a plurality of pixel units arranged in a matrix, each of the pixel units including a thin film transistor as a switching element
  • the device and the photodiode sensor device connected to the thin film transistor device.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is connected to the corresponding photodiode sensor device.
  • the following description is mainly made for a single or a plurality of pixel units, but other pixel units may be formed identically.
  • the array substrate of the X-ray detecting apparatus of the present invention includes a thin film transistor device 300. And a photodiode sensor device 200 connected to the thin film transistor device 300, and more particularly comprising: a source 55 and a drain 56 formed opposite to each other on the substrate substrate 50;
  • a light reflecting layer 57 formed on the substrate substrate 50 and connected to the drain 56;
  • An ohmic contact layer 69 formed over the source 55 and the drain 56;
  • the portion of the active layer 53 between the source 55 and the drain 56 forms a channel
  • a gate insulating layer 52 formed on the active layer 53 and the transparent electrode 61 and covering the entire substrate; formed on the gate insulating layer 52, the gate 51 above the active layer 53 and passing through the gate insulating layer A bias electrode 64 to which the hole 63 is connected to the transparent electrode 61.
  • the base substrate 50 may be a glass substrate, a plastic substrate or other substrate.
  • a portion of the active layer 53 between the source 55 and the drain 56 constitutes a channel of the thin film transistor.
  • the photodiode may be a MIS type photodiode or a PIN type photodiode or the like, preferably a PIN type photodiode, and a PIN type photodiode (P type semiconductor 60, type I semiconductor 59, N type semiconductor 58) is a PN between the two types of semiconductors.
  • P type semiconductor 60, type I semiconductor 59, N type semiconductor 58 is a PN between the two types of semiconductors.
  • PIN type photodiodes have the advantages of small junction capacitance, short transit time, and high sensitivity.
  • the ohmic contact layer 69 is disposed to reduce the resistance between the source 55, the drain 56 and the active layer 53, achieving a better ohmic contact.
  • the material of the ohmic contact layer 69 is, for example, an N-type semiconductor, that is, a doped semiconductor, and is made of the same material as the N-type semiconductor 58 of the PIN type photodiode.
  • the gate electrode 51 preferably uses a heavy metal or a heavy metal alloy which is difficult to penetrate by X-rays, such as copper, lead or copper-lead alloy.
  • the gate 51 and the bias electrode 64 are formed in the same mask process. Therefore, the source 55, the drain 56 and the reflective layer 57 can be made of the same metal material; the gate and the bias electrode can be made of the same metal material.
  • the embodiment shown in FIG. 3 further includes a passivation layer 62 formed on the gate electrode 51 and the transparent electrode 61 and covering the entire substrate; the transparent electrode 61a of the signal guiding region around the array substrate passes through the passivation layer 62.
  • the via hole on the gate insulating layer 52 is connected to the data line 55a, and passes through the passivation layer 62.
  • the upper via is connected to the gate line 51a.
  • the passivation layer may be an inorganic insulating film such as silicon nitride or the like, or an organic insulating film such as a resin material.
  • the thin film transistor device has a top gate type structure and the channel is located under the gate, the channel is not etched during the manufacturing process thereof.
  • the effect is that there is no need to additionally provide a channel barrier layer; and the gate can effectively block the light, so that the channel leakage current is greatly reduced, and there is no need to additionally provide a photomask in the preparation process, which simplifies the production process and further reduces the production cost. .
  • a phosphor which emits fluorescence when irradiated with X-rays, and the fluorescence can be detected and recorded by the photodiode photosensitive element of the corresponding pixel unit in the array substrate.
  • the array substrate of the X-ray detecting apparatus of the embodiment of the present invention can be formed by using a mask production process six times in total, and the main implementation process includes the following steps.
  • Step 201 sequentially depositing a source/drain electrode metal layer 550, an N-type semiconductor layer (n+a-Si) 580, an I-type semiconductor layer (a-Si) 590, and a P-type semiconductor layer (p+a) on the base substrate 50.
  • -Si ) 600 and a transparent electrode layer 610 then forming a relatively opposite source 55 and drain 56, a reflective layer 57 connected to the drain 56, and a source through a first mask process (halftone mask process)
  • the ohmic contact layer 69 over the pole 55 and the drain 56, the photodiode over the light reflecting layer 57, and the pattern of the transparent electrode 61.
  • step 201 is specifically described as follows.
  • Step 2011 depositing a source/drain electrode metal layer on the base substrate 50 by magnetron sputtering
  • the P-type semiconductor layer 600 is further deposited by a magnetron sputtering method.
  • the source-drain electrode metal layer 550 is used to form a source 55, a drain 56, and a light-reflecting layer 57, which may be made of aluminum-niobium alloy (AlNd), aluminum (Al), copper (Cu), molybdenum (Mo), molybdenum-tungsten alloy.
  • a single layer film of (MoW) or chromium (Cr) may be a composite film composed of any combination of these metal materials.
  • a portion of the N-type semiconductor layer 580 is used to form the ohmic contact layer 69, and a portion of the I-type semiconductor layer 590 is used to form a portion of the active layer 53.
  • the material of the transparent electrode layer 610 may be indium tin oxide or the like.
  • Step 2012 coating the substrate 100 of the completion step 2011 with the photoresist 100, and then using the mask (ie, a halftone mask) having a fully transparent region, a semi-transmissive region, and an opaque region to lithography
  • the glue 100 is exposed, and the exposed photoresist 100 is developed to obtain a photoresist pattern.
  • Full light transmission of the reticle The corresponding positions of the regions are all exposed for forming a channel pattern after further etching; the corresponding portions of the semi-transmissive regions are partially exposed for forming the pattern of the source 55, the drain 56 and the ohmic contact layer 69 after further etching.
  • the position corresponding to the opaque area is not exposed, and is used to form the pattern of the light reflecting layer 57, the PIN photodiode, and the transparent electrode 61 after further etching, as shown in FIGS. 4 and 5.
  • a practical positive photoresist is taken as an example for description, so that after development, the photoresist in the entire exposed region is completely removed, the photoresist in the partially exposed region is partially retained, and the photoresist in the unexposed region is almost completely Retained, thereby obtaining a three-dimensional photoresist pattern.
  • Step 2013 etching the base substrate of the completion step 2012, etching the transparent electrode layer 610 of all the exposed regions by a wet etching process; then, using the dry etching process, the P-type semiconductor layer 600, type I
  • the semiconductor layer 590 and the N-type semiconductor layer 580 are etched away; the source-drain electrode metal layer 550 is etched away by a wet etching process, as shown in FIG.
  • Step 2014 On the substrate of the completion step 2013, the photoresist in the partial exposure region is removed by an ashing etching process, and the thickness of the photoresist in the unexposed region is thinned and partially retained, as shown in FIG.
  • Step 2015 etching the substrate of the completion step 2014, etching the transparent electrode layer 610 of the partially exposed region by a wet etching process; then etching the P-type semiconductor layer 600 and the portion I by a dry etching process
  • the semiconductor layer 590 is as shown in FIG.
  • the I-type semiconductor layer may also be completely etched away, but it is difficult to realize in an actual production process because it is easy to etch away the ohmic contact layer portion, so it is preferable to etch away part of the I-type semiconductor layer.
  • Step 2016 The photoresist 100 on the substrate of the completed step 2015 is peeled off, as shown in Figs. 9 and 10.
  • the mask process includes, for example, substrate cleaning, photoresist coating, exposure and development, etching, photoresist stripping, and the like, which will not be described below.
  • Step 202 forming an active layer 53 pattern over the ohmic contact layer 69 and forming a channel with the source 55 and the drain 56 by a second mask process on the substrate of the step 201, as shown in FIG. 11 and Figure 12 shows.
  • the active layer 53 may be made of amorphous silicon and deposited by a dry etching process after deposition by chemical vapor deposition.
  • Step 203 depositing a gate insulating layer 52 covering the entire substrate on the substrate on which the step 202 is completed, and forming a gate insulating for connecting the bias electrode 64 and the transparent electrode 61 by a third mask process.
  • Layer via 63 as shown in FIG.
  • the gate insulating layer 52 may be made of silicon nitride, deposited by chemical vapor deposition, and formed by a dry etching process.
  • the gate insulating layer via is used to connect the bias electrode above the gate insulating layer and the transparent electrode under the gate insulating layer.
  • the connection of the bias electrode to the transparent electrode can be achieved by depositing a material forming the bias electrode into the via when the bias electrode is subsequently formed.
  • Step 204 forming a gate 51 above the active layer 53 and a pattern of the bias electrode 64 connected to the transparent electrode 61 by a fourth mask process on the substrate on which the step 203 is completed, as shown in FIGS. 14 and 15. .
  • the gate 51 and the bias electrode 64 are made of the same material as a copper-lead alloy, and are formed by a wet etching process after depositing the gate metal layer 51a by magnetron sputtering.
  • Step 205 depositing a passivation layer 62 on the substrate on which the step 204 is completed, and passing the signal on the periphery of the panel through the fifth mask process; 1: forming a passivation layer via hole in the early junction region, as shown in FIG. 16 and FIG. .
  • Step 206 Form a transparent electrode 61a of the signal guiding region around the panel by the sixth mask process on the substrate on which the step 205 is completed, as shown in FIGS. 18 and 19.
  • the array substrate of the X-ray detecting device of the present embodiment can form a relatively set source through the first halftone mask process at the time of manufacture.
  • a pattern of a pole 55 and a drain 56, a light reflecting layer 57 connected to the drain 56, an ohmic contact layer 69 over the source 55 and the drain 56, a photodiode over the light reflecting layer 57, and a transparent electrode 61 The source layer 53 is formed in a second masking process, and the channel between the source 55 and the drain 56 is no longer affected by subsequent etching, which eliminates the barrier layer of the prior art.
  • the mask process is formed.
  • the method of the embodiment can use a total of six mask processes, which simplifies the manufacturing process of the array substrate and greatly improves the productivity.

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Abstract

一种X射线检测装置的阵列基板及其制造方法，包括：形成于衬底基板（50）之上相对而置的源极（55）和漏极（56）及与漏极（56）连接的反光层（57）；形成于源极（55）和漏极（56）之上的欧姆接触层（69），形成于欧姆接触层（69）之上并与源极（55）和漏极（56）形成沟道的有源层（53）；形成于反光层（57）之上的光电二极管，及形成于光电二极管之上的透明电极（61）；形成于有源层（53）和透明电极（61）之上并覆盖整个基板（50）的栅极绝缘层（52）；形成于栅极绝缘层（52）之上，并位于有源层（53）上方的栅极（51）及通过栅极绝缘层（52）过孔与透明电极（61）连接的偏压电极。制造方法不再需要设置沟道阻挡层，简化了阵列基板的制造工艺，提高了产能。

Description

X射线检测装置的阵列基板及其制造方法 技术领域
本发明的实施例涉及一种 X射线检测装置的阵列基板及其制造方法。 背景技术
薄膜晶体管技术的快速发展， 带动了有源矩阵 X射线检测技术的应用。 X射线检测主要是平面检测，近百年来 X射线摄像都是使用软片记录光影像。 早在 20世纪 70年代初期数字医学 X射线摄像的概念已经被提出。 随着数字 医学影像传输与影像储存传输系统的革命性发展，数字 X射线摄像技术的应 用得到很大的进步。 有别于电荷耦合元件（ Charge Coupled device, CCD )与 互^卜金属 匕物半导体 ( Complementary Metal Oxide Semiconductors, CMOS ) 的数字 X射线摄像， 平面影像检测器提供大面积化检测与不占空间的优势， 有效缩短传统 X射线检测费时的流程。数字 X射线影像系统足足比传统计算 机造影系统节省 4倍的处理时间， 同时如果搭配高分辨率显示器面板， 则还 可以增进效率、 诊断精确性， 以及实现无底片的医疗环境。 有源矩阵平面检 测器可应用于非破坏性测试， 在不破坏被检测样品的情况下， 及时检测出待 测物的物理或机械性质， 可以轻易检测出如 50微米左右的裂痕， 孔洞，微缺 陷， 因此特别是在电子、 宇航和汽车工业上得到广泛的应用。
如图 1和图 2所示，现有 X射线检测器的阵列基板的每个像素区通常包 括： 光电二极管传感器件 200和薄膜晶体管器件 300。 光电二极管传感器件 的主要作用是接收光， 并通过光伏效应把光信号转换成电信号， 而薄膜晶体 管器件的主要作用是作为控制开关和传递光伏效应产生的电信号。
现有 X射线检测器的工作原理为：当 X射线 101轰击在设置在阵列基板 之前的荧光粉 102上时， 荧光粉 102产生可见光线， 该可见光入射到阵列基 板的光电二极管传感器件 200上。 光电二极管传感器件 200通过光伏效应， 将光信号转换为电信号， 而电信号通过薄膜晶体管器件 300的开关控制输入 到 X射线检测器的控制电路。
现有技术需要釆用 9次掩模完成上述 X射线检测器阵列基板的制备，其 主要工艺步骤如下。
步骤 101 , 在衬底基板 10上通过第一次掩模工艺形成栅极 11;
步骤 102, 在完成步骤 101的基板上沉积栅极绝缘层 12, 并通过第二次 掩模工艺在阵列基板上形成有源层 13;
步骤 103, 在完成步骤 102的基板上通过第三次掩模工艺形成沟道阻挡 层 14;
步骤 104,在完成步骤 103的基板上沉积欧姆接触层 29和源漏电极金属 层， 并通过第四次掩模工艺形成源极 15、 漏极 16和反光层 17；
步骤 105, 在完成步骤 104的基板上通过第五次掩模工艺形成 N型半导 体 18、 I型半导体 19、 P型半导体 20 (即 PIN型光电二极管传感器件的一部 分）和透明电极 21 ;
步骤 106, 在完成步骤 105的基板上沉积第一钝化层 22, 并通过第六次 掩模工艺形成第一钝化层 22上的第一过孔 23和第二过孔 25;
步骤 107, 在完成步骤 106的基板上通过第七次掩模工艺形成光罩 27、 偏压电极 24和信号线 26的图形；
步骤 108, 在完成步骤 107的基板上沉积第二钝化层 28, 并通过第八次 掩模工艺形成信号引导区的钝化层过孔（图中未示出） ；
步骤 109, 在完成步骤 108的基板上通过第九次掩模工艺形成信号引导 区的透明电极（图中未示出） 。
上述技术存在的缺陷在于， 为避免在形成光电二极管传感器件时影响到 已形成的薄膜晶体管器件有源层沟道的均匀性， 需要经一次掩模工艺 （步骤 103 )在有源层的上方形成一沟道阻挡层，这无疑增加了阵列基板制造工艺的 复杂性， 使得产能较难提升。 另外， 为减少薄膜晶体管器件沟道漏电流的影 响， 该技术还需要增加一金属光罩把 X射线轰击荧光粉产生的光遮挡起来， 这也使得制造成本无法进一步降低。 发明内容
本发明的实施例提供了一种 X射线检测装置的阵列基板及其制造方法， 用以解决现有技术中存在的 X射线检测装置阵列基板需另外釆用一次掩模工 艺去形成沟道阻挡层， 制造工艺繁瑣、成本较高，产能较难提升的技术问题。 本发明一个实施例提供了一种 X射线检测装置的阵列基板， 包括： 形成于衬底基板之上相对而置的源极和漏极及与漏极连接的反光层； 形成于源极和漏极之上的欧姆接触层；
形成于欧姆接触层之上并与源极和漏极至少部分重叠以构成沟道的有源 层；
形成于反光层之上的光电二极管；
形成于光电二极管之上的透明电极；
形成于有源层和透明电极之上并覆盖整个基板的栅极绝缘层；
形成于栅极绝缘层之上且位于有源层上方的栅极及通过栅极绝缘层过孔 与透明电极连接的偏压电极。
对于该阵列基板， 例如， 所述光电二极管为 PIN型光电二极管， 包括 P 型半导体、 I型半导体和 N型半导体， 所述欧姆接触层为 N型半导体层。
对于该阵列基板， 例如， 所述栅极材料为重金属或重金属合金。
对于该阵列基板， 例如， 形成所述源极、 漏极和反光层的材质相同。 对于该阵列基板， 例如， 形成所述栅极与偏压电极的材质相同。
本发明另一个实施例提供了一种 X射线检测装置阵列基板的制造方法， 包括：
在衬底基板上通过第一次掩模工艺形成相对设置的源极和漏极、 与漏极 连接的反光层、 位于源极和漏极之上的欧姆接触层、 位于反光层之上的光电 二极管和透明电极的图形；
通过第二次掩模工艺形成位于欧姆接触层之上并与源极和漏极形成沟道 的有源层图形， 然后覆盖整个衬底基板的栅极绝缘层；
通过第三次掩模工艺在栅极绝缘层中形成用于连接到透明电极的栅极绝 缘层过孔；
通过第四次掩模工艺形成位于有源层上方的栅极和通过栅极绝缘层过孔 与透明电极连接的偏压电极图形。
对于该制造方法， 例如， 所述第一次掩模工艺为半色调掩模工艺， 包括 步骤： 在衬底基板上依次沉积源漏电极金属层、 N型半导体层、 I型半导体 层、 P型半导体层和透明电极层； 釆用具有全透光区、 半透光区和不透光区 的掩模板对基板进行曝光， 其中， 全透光区对应的位置全部曝光， 刻蚀后形 成沟道图形； 半透光区对应的位置部分曝光， 刻蚀后形成源极、 漏极和欧姆 接触层图形； 不透光区对应的位置未曝光， 刻蚀后形成反光层、 PIN光电二 极管和透明电极图形。
对于该制造方法， 例如， 基板上部分曝光区域的透明电极层、 P型半导 体层被完全刻蚀掉、 I型半导体层被部分刻蚀掉。
由于本发明的实施例的 X射线检测装置的阵列基板在制造时可通过第一 次半色调掩模工艺形成相对而置的源极和漏极、 与漏极连接的反光层、 位于 源极和漏极之上的欧姆接触层、 位于反光层之上的光电二极管和透明电极的 图形， 有源层在第二次掩模工艺中形成， 因此沟道不再受到刻蚀的影响， 且 后续步骤形成的栅极可对沟道进行保护， 这省去了现有技术中沟道阻挡层的 掩模工艺形成过程， 简化了阵列基板的制造工艺， 提高了产能； 另外， 由于 栅极位于有源层的上方， 这可有效遮挡光线， 使得沟道漏电流大大减少， 无 需再另外设置光罩， 在简化生产工艺的同时， 进一步降低了生产成本。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术 X射线检测装置阵列基板剖面结构示意图；
图 2为现有技术 X射线检测装置检测原理结构示意图；
图 3为本发明 X射线检测装置阵列基板剖面结构示意图；
图 4为本发明第一次半色调掩模工艺曝光显影后俯视图；
图 5为图 4在 A-A处的截面图；
图 6为本发明第一次半色调掩模工艺第一次刻蚀后在 A-A处的截面图； 图 7为本发明第一次半色调掩模工艺第二次刻蚀（灰化）后在 A-A处的 截面图；
图 8为本发明第一次半色调掩模工艺第三次刻蚀后在 A-A处的截面图； 图 9为本发明第一次半色调掩模工艺剥离光刻胶后在 A-A处的截面图； 图 10为本发明第一次半色调掩模工艺剥离光刻胶后俯视图；
图 11为本发明第二次掩模工艺刻蚀后俯视图； 图 12为本发明第二次掩模工艺刻蚀后在 A-A处的截面图； 图 13为本发明第三次掩模工艺刻蚀后俯视图；
图 14为本发明第四次掩模工艺刻蚀后俯视图；
图 15为本发明第四次掩模工艺刻蚀后在 A-A处的截面图；
图 16为本发明第五次掩模工艺（信号引导区连接数据线过孔）刻蚀后截 面图；
图 17为本发明第五次掩模工艺（信号引导区连接栅线过孔）刻蚀后截面 图；
图 18为本发明第六次掩模工艺 （信号引导区与数据线连接的透明电极） 刻蚀后截面图；
图 19为本发明第六次掩模工艺（信号引导区与栅线连接的透明电极）刻 蚀后截面图。
附图标记说明：
10 衬底基板 11 栅极 12 栅极绝缘层
13 有源层 14 沟道阻挡层 15 源极
16 漏极 17 反光层 18 N型半导体
19 I型半导体 20 P型半导体 21 透明电极
22 第一钝化层 23 第一过孔 24 偏压电极
25 第二过孔 26 信号线 27 光罩
28 第二钝化层 29 欧姆接触层 101 X光线
102 荧光粉 200 光电二极管传感器件 300 薄膜晶体管器件
50 衬底基板 51 栅极 52 栅极绝缘层
53 有源层 69 欧姆接触层 55 源极
56 漏极 57 反光层 58 N型半导体
59 I型半导体 60 P型半导体 61 透明电极
62 钝化层 63 栅极绝缘层过孔 64 偏压电极
51a 栅线 55a 数据线
61a 信号引导区的透明电极 550 源漏电极金属层
580 N型半导体层 590 I型半导体层
600 P型半导体层 610 透明电极层 100 光刻胶 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
为了解决现有技术中存在的 X射线检测装置阵列基板需另外釆用一次掩 模工艺去形成沟道阻挡层， 制造工艺繁瑣、 成本较高， 产能较难提升的技术 问题,本发明的实施例提供了一种 X射线检测装置的阵列基板及其制造方法。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的多个像素单元， 每个像素单元包括作为 开关元件的薄膜晶体管器件和与薄膜晶体管器件相连的光电二极管传感器 件。 例如， 每个像素的薄膜晶体管的栅极与相应的栅线电连接或一体形成， 源极与相应的数据线电连接或一体形成， 漏极与相应的光电二极管传感器件 连接。 下面的描述主要针对单个或多个像素单元进行， 但是其他像素单元可 以相同地形成。
如图 3所示，本发明 X射线检测装置的阵列基板包括薄膜晶体管器件 300 和与薄膜晶体管器件 300相连的光电二极管传感器件 200, 更具体地包括： 形成于衬底基板 50之上相对而置的源极 55和漏极 56;
形成于衬底基板 50之上并与漏极 56连接的反光层 57;
形成于源极 55和漏极 56之上的欧姆接触层 69;
形成于欧姆接触层 69之上并与源极 55和漏极 56至少部分重叠的有源层
53 , 该有源层 53位于源极 55和漏极 56之间的部分构成沟道；
形成于反光层 57之上的光电二极管；
形成于光电二极管之上的透明电极 61;
形成于有源层 53和透明电极 61之上并覆盖整个基板的栅极绝缘层 52; 形成于栅极绝缘层 52之上，位于有源层 53上方的栅极 51及通过栅极绝 缘层过孔 63与透明电极 61连接的偏压电极 64。
衬底基板 50可以为玻璃基板、 塑料基板或其他基板。 有源层 53在源极 55和漏极 56之间的部分构成该薄膜晶体管的沟道。
光电二极管可以为 MIS型光电二极管或 PIN型光电二极管等，优选 PIN 型光电二极管， PIN型光电二极管 （P型半导体 60、 I型半导体 59、 N型半 导体 58 )是在两种半导体之间的 PN结， 或者半导体与金属之间的结的邻近 区域， 在 P区与 N区之间生成 I型 （本征 )层， 吸收光辐射而产生光电流的 一种光检测器。 PIN型光电二极管具有结电容小、 渡越时间短、 灵敏度高等 优点。
欧姆接触层 69的设置是为了减少源极 55、 漏极 56与有源层 53之间的 电阻， 实现较好的欧姆接触。 欧姆接触层 69的材质例如为 N型半导体， 即 掺杂质半导体， 与 PIN型光电二极管的 N型半导体 58材质相同。
栅极 51优选釆用 X射线较难穿透的重金属或重金属合金， 例如铜、 铅 或铜铅合金等。
由于源极 55、 漏极 56和反光层 57在同一次掩模工艺中形成， 栅极 51 与偏压电极 64在同一次掩模工艺中形成。 因此， 源极 55、 漏极 56和反光层 57可釆用同一金属材质； 栅极与偏压电极可釆用同一金属材质。
在图 3所示的实施例中还包括形成于栅极 51和透明电极 61之上并覆盖 整个基板的钝化层 62; 在该阵列基板周边的信号引导区的透明电极 61a通过 贯通钝化层 62、 栅极绝缘层 52上的过孔与数据线 55a连接， 通过钝化层 62 上的过孔与栅线 51a连接。 该钝化层可以釆用无机绝缘膜， 例如氮化硅等， 或有机绝缘膜， 例如树脂材料等。
在本发明的实施例的 X射线检测装置的阵列基板中， 由于薄膜晶体管器 件为顶栅型结构， 沟道位于栅极的下方， 因此， 在其制造工艺过程中沟道不 会受到刻蚀的影响， 无需另外设置沟道阻挡层； 而且栅极可有效遮挡光线， 使得沟道漏电流大大减少， 而无需在制备工艺中另外设置光罩， 这在简化生 产工艺的同时， 进一步降低了生产成本。
在本实施例的 X射线检测装置的阵列基板上方例如设置荧光粉，该荧光 粉被 X射线照射时发射荧光，该荧光可以被阵列基板中相应像素单元的光电 二极管感光元件检测并记录。
如图 4至图 19所示， 本发明的实施例的 X射线检测装置的阵列基板可 共釆用六次掩模生产工艺形成， 其主要实施过程包括如下步骤。
步骤 201 : 在衬底基板 50上依次沉积源漏电极金属层 550、 N型半导体 层（n+a-Si ) 580、 I型半导体层（ a-Si ) 590、 P型半导体层（p+a-Si ) 600和 透明电极层 610, 然后通过第一次掩模工艺 （半色调掩模工艺）形成相对而 置的源极 55和漏极 56、 与漏极 56连接的反光层 57、 位于源极 55和漏极 56 之上的欧姆接触层 69、位于反光层 57之上的光电二极管和透明电极 61的图 形。
参考图 4-9, 对步骤 201的一个示例具体说明如下。
步骤 2011: 在衬底基板 50上釆用磁控溅射的方法沉积源漏电极金属层
P型半导体层 600, 再釆用磁控溅射的方法沉积透明电极层 610。
源漏电极金属层 550用于形成源极 55、 漏极 56和反光层 57 , 其材质可 以为铝钕合金（AlNd )、 铝（Al )、 铜（Cu )、钼（Mo )、钼钨合金（MoW ) 或铬（Cr ) 的单层膜， 也可以为这些金属材料任意组合所构成的复合膜。 部 分 N型半导体层 580用于形成欧姆接触层 69,部分 I型半导体层 590用于形 成有源层 53的一部分。 透明电极层 610的材质可以为氧化铟锡等。
步骤 2012:对完成步骤 2011的衬底基板涂覆光刻胶 100,然后釆用具有 全透光区、半透光区和不透光区的掩模板（即半色调掩模板）对该光刻胶 100 进行曝光， 对曝光的光刻胶 100进行显影得到光刻胶图形。 掩模板的全透光 区对应的位置全部曝光， 用于在进一步刻蚀后形成沟道图形； 半透光区对应 的位置部分曝光， 用于在进一步刻蚀后形成源极 55、 漏极 56和欧姆接触层 69图形； 不透光区对应的位置未曝光， 用于在进一步刻蚀后形成反光层 57、 PIN光电二极管和透明电极 61图形，如图 4和图 5所示。这里以实用正性光 刻胶为例进行说明， 从而显影之后， 全部曝光区的光刻胶被全部去除， 部分 曝光区的光刻胶被部分保留， 而未曝光区的光刻胶几乎被全部保留， 由此得 到三维光刻胶图形。
步骤 2013: 对完成步骤 2012的衬底基板进行刻蚀， 用湿法刻蚀工艺将 全部曝光区的透明电极层 610刻蚀掉； 然后用干法刻蚀工艺将 P型半导体层 600、 I型半导体层 590、 N型半导体层 580刻蚀掉； 再用湿法刻蚀工艺将源 漏电极金属层 550刻蚀掉， 如图 6所示。
步骤 2014: 对完成步骤 2013的衬底基板釆用灰化刻蚀工艺去除部分曝 光区的光刻胶， 同时未曝光区的光刻胶的厚度被减薄从而部分保留， 如图 7 所示。
步骤 2015: 对完成步骤 2014的基板进行刻蚀， 用湿法刻蚀工艺将部分 曝光区的透明电极层 610刻蚀掉； 然后用干法刻蚀工艺刻蚀掉 P型半导体层 600和部分 I型半导体层 590, 如图 8所示。 这里， I型半导体层也可以被全 部刻蚀掉，但在实际生产工艺中较难实现， 因为容易刻蚀掉欧姆接触层部分， 因此优选刻蚀掉部分的 I型半导体层。
步骤 2016: 将完成步骤 2015的衬底基板上的光刻胶 100剥离， 如图 9 和图 10所示。
在本说明之中，掩模工艺例如包括基板清洗、 光刻胶涂覆、曝光和显影、 刻蚀、 光刻胶剥离等， 以下不再赘述。
步骤 202: 在完成步骤 201的衬底基板上通过第二次掩模工艺形成位于 欧姆接触层 69之上并与源极 55和漏极 56形成沟道的有源层 53图形， 如图 11和图 12所示。
有源层 53材质可以为非晶硅，在釆用化学气相沉积的方法沉积后再通过 干法刻蚀工艺形成。
步骤 203:在完成步骤 202的基板上沉积覆盖整个基板的栅极绝缘层 52, 并通过第三次掩模工艺形成用于连接偏压电极 64和透明电极 61的栅极绝缘 层过孔 63 , 如图 13所示。
栅极绝缘层 52材质可以为氮化硅，釆用化学气相沉积法沉积，通过干法 刻蚀工艺形成栅极绝缘层过孔。
本发明实施例中， 栅极绝缘层过孔用于连接位于栅绝缘层上方的偏压电 极和位于栅绝缘层下方的透明电极。 一般而言， 在后续形成偏压电极时使形 成偏压电极的材料沉积入该过孔即可实现偏压电极与透明电极的连接。
步骤 204: 在完成步骤 203的基板上通过第四次掩模工艺形成位于有源 层 53上方的栅极 51和与透明电极 61连接的偏压电极 64图形，如图 14和图 15所示。
栅极 51与偏压电极 64的材质相同， 为铜铅合金， 在釆用磁控溅射的方 法沉积栅极金属层 51a后通过一次湿法刻蚀工艺形成。
步骤 205: 在完成步骤 204的基板上沉积钝化层 62, 并通过第五次掩模 工艺在面板周边的信号; 1：早接区域形成钝化层过孔， 如图 16和图 17所示。
步骤 206: 在完成步骤 205的基板上通过第六次掩模工艺形成面板周边 信号引导区的透明电极 61a, 如图 18和图 19所示。
从本实施例的 X射线检测装置的阵列基板的生产工艺过程可以看出， 由 于本实施例的 X射线检测装置的阵列基板在制造时可通过第一次半色调掩模 工艺形成相对设置的源极 55和漏极 56、与漏极 56连接的反光层 57、位于源 极 55和漏极 56之上的欧姆接触层 69、 位于反光层 57之上的光电二极管和 透明电极 61 的图形， 有源层 53在第二次掩模工艺中形成， 其位于源极 55 和漏极 56之间的沟道不再受到后续刻蚀的影响，这就省去了现有技术中沟道 阻挡层的掩模工艺形成过程。 本实施例的方法可共釆用六次掩模工艺， 简化 了阵列基板的制造工艺， 大大提高了产能。
显然， 上面的对具体实施例的说明仅为描述性而非限制性的， 本发明的 保护范围应由所附的权利要求来限定。

Claims

权利要求书
1、 一种 X射线检测装置的阵列基板， 包括：
形成于衬底基板之上相对而置的源极和漏极及与所述漏极连接的反光 层；
形成于所述源极和漏极之上的欧姆接触层；
形成于所述欧姆接触层之上并与所述源极和漏极至少部分重叠以构成沟 道的有源层；
形成于所述反光层之上的光电二极管；
形成于所述光电二极管之上的透明电极；
形成于所述有源层和所述透明电极之上并覆盖整个衬底基板的栅极绝缘 层；
形成于所述栅极绝缘层之上并位于所述有源层上方的栅极及通过所述栅 极绝缘层中的过孔与所述透明电极连接的偏压电极。
2、 如权利要求 1所述的阵列基板， 其中， 所述光电二极管为 PIN型光 电二极管， 包括 P型半导体、 I型半导体和 N型半导体， 所述欧姆接触层为 N型半导体层。
3、如权利要求 1或 2所述的阵列基板， 其中， 所述栅极的材料为重金属 或重金属合金。
4、 如权利要求 1-3任一所述的阵列基板， 其中， 所述源极、 漏极和反光 层的材质相同。
5、 如权利要求 1-4任一所述的阵列基板， 其中， 所述栅极与偏压电极的 材质相同。
6、 一种 X射线检测装置阵列基板的制造方法， 包括步骤：
在衬底基板上通过第一次掩模工艺形成相对设置的源极和漏极、 与漏极 连接的反光层、 位于源极和漏极之上的欧姆接触层、 位于反光层之上的光电 二极管和透明电极的图形；
通过第二次掩模工艺形成位于所述欧姆接触层之上并与源极和漏极至少 部分重叠以够成沟道的有源层图形， 然后形成覆盖整个衬底基板的栅极绝缘 层； 通过第三次掩模工艺在所述栅极绝缘层中形成用于连接到所述透明电极 的栅极绝缘层过孔；
通过第四次掩模工艺形成位于所述有源层上方的栅极和通过所述栅极绝 缘层过孔与所述透明电极连接的偏压电极图形。
7、如权利要求 6所述的阵列基板的制造方法， 其中， 所述第一次掩模工 艺中形成所述源极、 漏极和反光层的材质相同。
8、如权利要求 6或 7所述的阵列基板的制造方法， 其中， 所述第四次掩 模工艺中形成所述栅极与偏压电极的材质相同。
9、 如权利要求 6-8任一所述的阵列基板的制造方法， 其中， 所述第一次 掩模工艺为半色调掩模工艺并且包括：
在所述衬底基板上依次沉积源漏电极金属层、 N型半导体层、 I型半导 体层、 P型半导体层和透明电极层；
釆用具有全透光区、 半透光区和不透光区的掩模板对基板进行曝光， 其 中， 全透光区对应的位置全部曝光， 刻蚀后形成所述沟道的图形； 半透光区 对应的位置部分曝光， 刻蚀后形成所述源极、 漏极和欧姆接触层的图形； 不 透光区对应的位置未曝光， 刻蚀后形成所述反光层、 PIN光电二极管和透明 电极的图形。
10、 如权利要求 9所述的阵列基板的制造方法， 其中， 所述衬底基板上 部分曝光区域的透明电极层、 P型半导体层被完全刻蚀掉、 I型半导体层被部 分刻蚀掉。
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