WO2013140759A1 - Switching element and device using same - Google Patents

Switching element and device using same Download PDF

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Publication number
WO2013140759A1
WO2013140759A1 PCT/JP2013/001692 JP2013001692W WO2013140759A1 WO 2013140759 A1 WO2013140759 A1 WO 2013140759A1 JP 2013001692 W JP2013001692 W JP 2013001692W WO 2013140759 A1 WO2013140759 A1 WO 2013140759A1
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WO
WIPO (PCT)
Prior art keywords
switching element
electrode
piezoelectric
film
substrate
Prior art date
Application number
PCT/JP2013/001692
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French (fr)
Japanese (ja)
Inventor
勝巳 阿部
茂樹 篠田
哲也 吉成
門澤　秀樹
Original Assignee
日本電気株式会社
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Publication of WO2013140759A1 publication Critical patent/WO2013140759A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02N—ELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
    • H02N2/00—Electric machines in general using piezoelectric effect, electrostriction or magnetostriction
    • H02N2/18—Electric machines in general using piezoelectric effect, electrostriction or magnetostriction producing electrical output from mechanical input, e.g. generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K17/964—Piezo-electric touch switches

Definitions

  • the present invention relates to a switching element in which a gate electrode of a switching transistor and an electrode of a piezoelectric element are integrated.
  • the present invention relates to a switching element that operates using an electromotive force generated by a piezoelectric element and a device to which the switching element is applied.
  • a method of shortening the start time of the sensor node as much as possible and extending the standby time is taken. While the sensor node is active, power consumption is high because various functions such as sensor devices, control microcomputers, and wireless communication modules are used, but power consumption is extremely low because most functions are not used during standby. Become. Therefore, for example, an operation flow is constructed in which the sensor node is periodically started at a frequency of once per minute, information is acquired by the sensor device, the result is transmitted by the wireless module, and then the standby state is returned. The If such an operation flow is adopted, the sensor node is activated for about ten seconds or more, and most of the activity is occupied by the standby time. Therefore, when the power consumption is averaged, the power consumption can be sufficiently reduced. Can do.
  • Patent Document 1 a device that converts light, pressure, heat, and a magnetic field into voltage is used, and a switching element such as a transistor is turned on by the voltage output from this device. Then, a method of supplying power to the sensor node has been proposed. For example, if a piezoelectric element that converts pressure into electricity is used as a weight sensor, a person can ride on the gravity sensor to generate a voltage and to conduct the switching element.
  • a vibration sensor that detects the operation of the mechanical device is used.
  • the power switch of the sensor can be turned on. That is, a switching element is formed by the vibration sensor and a power switch that operates according to the voltage from the vibration sensor, and the switching element functions as a trigger circuit.
  • a general event detection vibration sensor as described in Patent Document 2 is bonded to a detection object, and is connected to a substrate inside a sensor node by a signal cable and outputs a signal to a switching transistor. For this reason, the distance between a vibration sensor and a switching transistor is large, and there exists a subject that it becomes easy to receive to the influence of external noise.
  • the vibration sensor becomes large, and thus there is a problem that it is difficult to make the vibration sensor and the switching transistor as one device.
  • An object of the present invention is to provide a trigger circuit in which a piezoelectric element and a switching transistor are realized by one device and are not easily affected by external noise.
  • the switching element of the present invention is characterized in that the electrode of the piezoelectric element also serves as one of the electrodes of the switching transistor. More specifically, a substrate, a source region and a drain region provided on one surface of the substrate, an insulating film provided on the substrate, a first electrode layer disposed on the insulating film, The switching element includes a piezoelectric film disposed on one electrode layer and a second electrode layer disposed on the piezoelectric film.
  • the switching element of the present invention includes a substrate, a diffusion region provided on the substrate, an insulating film provided on the diffusion region, and a piezoelectric element provided on the insulating film. To do.
  • the piezoelectric element and the switching transistor can be made into one device, the influence of external noise can be suppressed, and a highly reliable trigger circuit without malfunction can be realized.
  • 1 is a cross-sectional structure diagram of a switching element according to a first embodiment of the present invention.
  • 1 is an upper plan view of a switching element according to a first embodiment of the present invention.
  • 1 is a cross-sectional structure diagram of a switching element according to a first embodiment of the present invention.
  • 1 is a cross-sectional structure diagram of a switching device according to a first embodiment of the present invention.
  • 1 is a circuit diagram according to a first embodiment of the present invention. It is a schematic diagram of the manufacturing process of the switching element which concerns on the 1st Embodiment of this invention. It is a schematic diagram of the manufacturing process of the switching element which concerns on the 1st Embodiment of this invention.
  • FIG. 6 is a cross-sectional structure diagram of a switching element according to a third embodiment of the present invention. It is sectional structure drawing of the switching element which concerns on the 4th Embodiment of this invention. It is a circuit diagram concerning a 5th embodiment of the present invention. It is sectional structure drawing of the switching element which concerns on the 5th Embodiment of this invention. It is a circuit diagram concerning a 6th embodiment of the present invention.
  • FIG. 1 shows a cross-sectional structure diagram of a switching element 1 according to a first embodiment of the present invention.
  • FIG. 1 is a cross-sectional view taken along the line A-A ′ of FIG. 2 described later.
  • FIG. 2 is a top plan view of the switching element 1 according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view taken along the line B-B ′ of FIG.
  • the switching element 1 of the first embodiment includes a piezoelectric sheet 11 (corresponding to a piezoelectric element) and a semiconductor substrate 15 (including a Pwell region) through an insulating film 17. It consists of connected laminates.
  • the piezoelectric sheet 11 has a structure in which a piezoelectric film 12 is sandwiched between electrode films 13a and 13b.
  • the piezoelectric film 12 is formed by forming a piezoelectric material into a thin plate shape.
  • piezoelectric ceramics such as BaTiO3 (barium titanate), PZT (lead zirconate titanate), ZnO (zinc oxide), or piezoelectric polymers such as polyvinylidene fluoride are suitable.
  • piezoelectric ceramics PMN (lead magnesium niobate), PZNT (lead zinc niobate titanate solid solution), or the like can also be used.
  • the piezoelectric sheet 11 is formed by pressure-bonding a conductive sheet on both sides of the piezoelectric film 12, or by connecting via a conductive material.
  • the conductive sheet corresponds to the electrode films 13a and 13b.
  • An electrode bump 16 is formed on a part of the electrode film 13 a outside the piezoelectric sheet 11 without covering the piezoelectric sheet 11, and an insulating portion 18 is provided so as to surround the electrode bump 16.
  • the semiconductor substrate 15 of the first embodiment uses a p-type semiconductor substrate and is a constituent element of the semiconductor layer 10.
  • the semiconductor layer 10 includes a channel layer 15b (part of the Pwell layer), an N + region 15a, and a buried wiring (source electrode 14a, drain electrode 14b) in which a groove formed in the N + region 15a is filled with metal. It has an electrode.
  • the electrode in which the embedded wirings are arranged at regular intervals is either the source electrode 14a or the drain electrode 14b.
  • the source electrode 14a and the drain electrode 14b are alternately arranged.
  • All the source electrodes 14a are electrically connected. Similarly, all the drain electrodes 14b are electrically connected. In addition, about the source electrode 14a and the drain electrode 14b, what is electrically connected is shown with the same code
  • connection state of the source electrode 14a and the drain electrode 14b has the configuration and positional relationship as shown in the top plan view of FIG. 2 and the cross-sectional view of FIG.
  • the electrode film 13b, the insulating film 17, the insulating portion 18, and the like are omitted.
  • part of the electrode film 13a and the piezoelectric film 12 is shown as a transmission diagram in order to clarify the shapes and positional relationships of the source electrode 14a and the drain electrode 14b.
  • the electrode film 13b of the piezoelectric sheet 11 is bonded to the surface on which the source electrode 14a and the drain electrode 14b are disposed on the semiconductor substrate 15 with the insulating film 17 interposed therebetween.
  • the electrode film 13b serves as both the gate electrode of the switching transistor and the electrode of the piezoelectric sheet 11.
  • the exposed surface of the source electrode 14 a is electrically connected to the outer electrode film 13 a of the piezoelectric sheet 11 via the electrode bump 16.
  • a resin protective film 19 is affixed to the other surface of the semiconductor substrate 15. The protective film 19 is not an essential configuration.
  • FIG. 4 shows an example of the switching device 20 on which the switching element 1 of the first embodiment is mounted.
  • the switching element 1 of the first embodiment is attached to a metal or resin support plate 23.
  • a weight 24 is mounted on the tip of the support plate 23, and the opposite end is fixed to the fixing portion 22 to form a cantilever structure.
  • the electrode bump 16 of the switching element 1 is connected to a microcomputer or the like provided outside by a wiring 25. Further, the outside of the switching device 20 is covered with a housing 21.
  • the switching element 1 When an external stress is applied to the cantilever structure, the switching element 1 is bent together with the support plate 23.
  • the piezoelectric film 12 is compressed or sheared by the bending of the switching element 1, and a potential difference is generated between the electrode films 13 a and 13 b on the front and back surfaces of the piezoelectric sheet 11.
  • the electrode film 13b which is one electrode of the piezoelectric sheet 11 also serves as a gate electrode.
  • the electrode film 13 a that is the other electrode of the piezoelectric sheet 11 is electrically connected to the source electrode 14 a of the semiconductor layer 10. Note that the electrode film 13a can be electrically connected to a back gate electrode (an electrode drawn from the Pwell layer) depending on the configuration.
  • the drain electrode 14b and the source electrode 14a of the switching element 1 can be electrically connected by external vibration.
  • FIG. 5 shows an example of a circuit diagram relating to the switching element 1 of the first embodiment of the present invention.
  • the circuit diagram of FIG. 5 is an example and does not limit the present invention.
  • the switching element 1 includes a piezoelectric element 31 and an n-type MOSFET 32.
  • the piezoelectric element 31 corresponds to the piezoelectric sheet 11 of FIG. 1 and includes the piezoelectric film 12 and the two electrode films 13a and 13b.
  • the n-type MOSFET 32 includes a source electrode 14a, a drain electrode 14b, an insulating film 17, and a channel layer 15b.
  • the N + region 15a including the source electrode 14a or the drain electrode 14b inside becomes a source region or a drain region, respectively.
  • the plurality of source electrodes 14a and the plurality of drain electrodes 14b shown in FIG. 1 are connected in parallel. Therefore, the n-type MOSFET 32 of FIG. 5 is formed by any adjacent source region / drain region.
  • the resistor 33 and the switching element 1 are connected in series between the power supply 34 and the GND 35, and the reset signal input port or the interrupt signal input port of the microcomputer 36 is an electrode on the power supply side of the switching element 1, that is, a drain electrode. 14b.
  • the resistor 33 may be provided inside the microcomputer 36.
  • the potential of the input port of the microcomputer 36 decreases from VDD to GND.
  • the microcomputer 36 can detect a change in the potential and can transition from the sleep state to the activated state. That is, in the microcomputer 36, the activation threshold is provided at a positive potential smaller than VDD.
  • the sleep state means a state in which the microcomputer 36 can react to an input signal although the CPU of the microcomputer 36 is in a stopped state.
  • the switching element 1 may be inserted into a power supply line connecting the microcomputer 36 and the power supply 34 so that power is supplied to the microcomputer 36 when the switching element 1 is turned on.
  • the switching element according to the first embodiment of the present invention is used, a piezoelectric element that generates a voltage in response to vibration or the like, and a switching transistor that conducts the transistor in accordance with an output from the piezoelectric element are combined into one device. can do. Therefore, the influence of external noise can be suppressed. Therefore, a highly reliable trigger circuit can be realized without malfunction.
  • the piezoelectric films 12 formed into a thin plate shape having a thickness of 10 to 100 ⁇ m are pressure-bonded to the electrode films 13a and 13b in which a conductive material is formed into a sheet shape through the conductive material (FIG. 6A).
  • a part of the electrode film 13b is opened without forming the piezoelectric film 12, and an electrically conductive material and an insulating resin are applied to the opening by printing or the like, and sintered, thereby electrically connecting to the semiconductor layer 10.
  • the electrode bump 16 for connection and the insulating part 18 are formed (FIG. 6B).
  • the semiconductor layer 10 can be formed by a general semiconductor process. That is, an N + region having an arbitrary pattern and a buried wiring are formed in each step by ion implantation, dry etching, vapor deposition, photolithography, or the like. In the following description, details of each process are omitted.
  • a p-type semiconductor substrate is used.
  • a portion where the diffusion layer is not formed is masked, and impurity ions are introduced into the opening by ion implantation (FIG. 6C).
  • the diffusion layer formed here is an N + region.
  • a metal to be a wiring is vapor-deposited at the location where dry etching is performed (FIG. 6E).
  • the back surface of the semiconductor wafer is mechanically and chemically ground to make the semiconductor substrate 15 have a thickness of about 10 to 100 ⁇ m (not shown).
  • an insulating material is applied on the piezoelectric sheet 11 or the semiconductor substrate 15 so as to have a thickness of about 1 ⁇ m, and the piezoelectric sheet 11 and the semiconductor substrate 15 are connected via the insulating material.
  • the protective sheet 19 is affixed on the back surface of the semiconductor substrate 15 (FIG. 6F).
  • the switching element according to the first embodiment of the present invention.
  • the switching element demonstrated after this can also be manufactured by the manufacturing method similar to 1st Embodiment.
  • FIG. 7 shows a cross-sectional structure diagram of a switching element 2 according to a second embodiment of the present invention.
  • drain electrode 54b, the source electrode 54a, and the gate electrode 54c are formed on the surface of the semiconductor substrate 55.
  • the switching element 2 is composed of a laminated body in which the piezoelectric sheet 51 and the semiconductor substrate 55 are connected via an insulating film 57 or an insulating part 58.
  • the piezoelectric sheet 51 has a structure in which a piezoelectric film 52 is sandwiched between electrode films 53a and 53b.
  • the material and forming method of the piezoelectric sheet 51 are the same as those in the first embodiment.
  • a part of the electrode on the end (outer side) of the piezoelectric sheet 51 is provided with an electrode bump 56 and an insulating part 58 surrounding the electrode bump 56 without covering the piezoelectric sheet 51.
  • a p-type semiconductor substrate is used as the semiconductor substrate 55 of the second embodiment.
  • the semiconductor substrate 55 is a component of the semiconductor layer 50.
  • the semiconductor layer 50 has a channel layer 55b (a part of the Pwell layer) and an N + region 55a inside the Pwell layer.
  • the source electrode 54a or the drain electrode 54b is formed on the surface of the N + region 55a.
  • the positional relationship and connection state between the source electrode 54a and the drain electrode 54b are the same as in the first embodiment.
  • the gate electrode 54c is located at a position facing the channel layer 55b with the insulating film 57 interposed therebetween. One surface of the gate electrode 54c is in contact with the insulating film 57, and the other surface is in contact with the electrode film 53b.
  • the insulating film 57 may be formed only between the gate electrode 54c and the channel layer 55b. In that case, it is assumed that there is an insulating portion 58 between the source electrode 54a or the drain electrode 54b and the electrode film 53b.
  • the electrode film 53b of the piezoelectric sheet 51 is bonded to the surface of the semiconductor substrate 55 on which the source electrode 54a and the drain electrode 54b are disposed with the insulating film 57 interposed therebetween.
  • the source electrode 54a, the drain electrode 54b, the channel layer 55b formed on the semiconductor substrate 55 sandwiched between the source electrode 54a and the drain electrode 54b, the insulating film 57, and the channel layer 55b of the electrode film 53b are electrically connected.
  • a switching transistor is formed by the gate electrode 54c thus formed. Since the electrode film 53b and the gate electrode 54c are electrically connected, the electrode film 53b also serves as the gate electrode 54c of the switching transistor described above and the electrode of the piezoelectric sheet 51.
  • a part of the source electrode 54 a is exposed on the surface of the semiconductor substrate 55.
  • the exposed surface of the source electrode 54 a is electrically connected to the outer electrode film 53 a of the piezoelectric sheet 51 via the electrode bump 56.
  • a resin protective film 59 is affixed to the other surface of the semiconductor substrate 55.
  • the switching element of the second embodiment does not need to form a buried wiring, a transistor can be formed by a relatively simple process.
  • FIG. 8 is a sectional structural view of a switching element 3 according to a third embodiment of the present invention.
  • a source electrode (electrode film 63b) is formed on the surface facing the piezoelectric sheet 61, and a drain electrode (electrode film 63c) is formed on the opposite surface (back surface). It is a point to form.
  • the switching element 3 includes a stacked body in which a piezoelectric sheet 61 and a semiconductor substrate 65 are connected via an insulating portion 68.
  • the piezoelectric sheet 61 has a structure in which a piezoelectric film 62 is sandwiched between electrode films 63a and 63b.
  • the material and forming method of the piezoelectric sheet 61 are the same as those in the first embodiment.
  • An n-type semiconductor substrate is used as the semiconductor substrate 65 of the third embodiment.
  • the semiconductor substrate 65 is a constituent element of the semiconductor layer 60.
  • an N + region 65a, a Pbase region (channel layer 65b), and an Nwell region (substrate 65) are formed in this order from the surface facing the piezoelectric sheet 61.
  • a groove formed by etching a part of the N + region 65a and the channel layer 65b, an oxide film (insulating film 67) covering the wall surface of the groove, and a buried wiring (gate electrode) made of a conductive material filling the inside thereof 64) is formed.
  • This buried wiring becomes a so-called gate electrode 64.
  • the gate electrode 64 is exposed at a part of the surface of the semiconductor substrate 65.
  • a part of the surface of the semiconductor substrate 65 is electrically connected to the electrode film 63 a outside the piezoelectric sheet 61 through the electrode bumps 66.
  • the switching element 1 of the first embodiment is composed of a horizontal transistor
  • the current flows in a direction parallel to the surface of the semiconductor substrate.
  • the switching element 3 of the third embodiment is composed of a vertical transistor
  • the current flows in a direction perpendicular to the surface of the semiconductor substrate. That is, in the third embodiment, since the vertical transistor structure can increase the number of carrier paths per unit area, lower on-resistance can be realized, and power loss due to the transistor can be further reduced. Can do.
  • FIG. 9 is a sectional structural view of a switching element 4 according to a fourth embodiment of the present invention.
  • an organic semiconductor is used as a semiconductor layer instead of a silicon semiconductor.
  • the piezoelectric sheet 71 includes a piezoelectric film 72 and electrode sheets 73a and 73b, as in the first embodiment.
  • One end portion of the piezoelectric sheet 71 is provided with a conductive electrode bump 76 formed so as to be electrically connected to the electrode film 73 a and an insulating portion 78 formed so as to surround the electrode bump 76.
  • An insulating film 77 is formed on the surface of the piezoelectric sheet 71 on the electrode film 73b side so that a part of the electrode bumps 76 is exposed.
  • the insulating film 77 is preferably formed by a printing process described later.
  • a metal wiring to be the source electrode 74a or the drain electrode 74b is formed by, for example, a printing method. Thereafter, an organic semiconductor is applied between the metal wirings by a printing process such as screen printing, ink jetting, or microcontact to form the semiconductor region 75.
  • the semiconductor region 75 located between the source electrode 74a and the drain electrode 74b and close to the piezoelectric sheet 71 functions as the channel layer 75a.
  • the semiconductor layer 70 is formed by the source electrode 74a, the drain electrode 74b, the semiconductor region 75, and the channel layer 75a. Further, the portion of the electrode film 73b that faces the channel layer 75a functions as a gate electrode. As described above, a transistor structure using an organic semiconductor can be formed.
  • a transistor can be directly formed on the piezoelectric sheet 71 by a printing process, instead of pasting a previously formed piezoelectric sheet and a semiconductor substrate.
  • the manufacturing cost of the switching element can be kept low by using the printing process.
  • FIG. 10 is a circuit diagram using a switching element 80 according to a fifth embodiment of the present invention.
  • a resistor 88, a Zener diode 87, and a depletion type p-type MOSFET 82 are provided inside or on the surface of the semiconductor.
  • the zener diode 87 and the depletion type p-type MOSFET 82 are connected between the piezoelectric element 81 and the gate electrode of the n-type MOSFET 83 and between the GND 85.
  • the gate electrode of the p-type MOSFET 82 and the drain electrode 94 b of the n-type MOSFET 83 are connected via a resistor 88.
  • the power supply 84 and the resistor 89 are the same as those in the first embodiment, and thus description thereof is omitted.
  • the p-type MOSFET 82 is controlled by the microcomputer 86 to hold the gate electrode of the p-type MOSFET 82 at the GND potential. Operate. As a result, charges accumulated in the gate electrodes of the piezoelectric element 81 and the n-type MOSFET 83 can be released to the GND 85. As a result, it is possible to suppress the accumulation of charge in the gate electrode of the n-type MOSFET 83 and the unstable operation.
  • FIG. 11 shows a sectional structural view of the switching element 5 according to the fifth embodiment of the present invention.
  • a p-type semiconductor substrate is used as the semiconductor substrate 95 of the fifth embodiment.
  • the semiconductor substrate 95 is a component of the semiconductor layer 90.
  • the semiconductor layer 90 includes an n-type MOSFET 83 having a channel layer 95b (a part of the Pwell layer) and an N + region 95a inside the Pwell layer.
  • a source electrode 94a or a drain electrode 94b is provided inside the N + region 95a.
  • the semiconductor layer 90 includes a p-type MOSFET 82 having an Nbase region 95c.
  • the Nbase region 95c has two P + regions 95d and 95e, an N + region 95f, and a P ⁇ region 95g.
  • the two P + regions 95d and 95e are connected by a P ⁇ region 95g serving as a channel layer.
  • One P + region 95e is in contact with the N + region 95f, and a source electrode 94d is formed therebetween.
  • a drain electrode 94c is formed in the other P + region 95d.
  • the Nbase region 95c is formed inside the Pwell layer.
  • P + regions 95d and 95e, an N + region 95f, and a P ⁇ region 95g are formed in the Nbase region 95c.
  • buried wiring is formed in the P + regions 95d and 95e and the N + region 95f, and these are used as the drain electrode 94c and the source electrode 94d.
  • gate electrodes 94e and 94f made of polysilicon are provided on the surface of the semiconductor substrate 95 via an insulating layer 97.
  • the Zener diode 87 and the resistor 88 can be formed in the semiconductor layer 90 in the process of forming the p-type MOSFET 82.
  • the resistor 88 it is not an essential configuration.
  • the piezoelectric sheet 91 has a structure in which a piezoelectric film 92 is sandwiched between an electrode film 93 and a gate electrode 94e.
  • the material and the forming method of the piezoelectric sheet 91 are the same as those in the first embodiment except that only one electrode film 93 is provided.
  • an electrode bump 96 and an insulating portion 98 surrounding the electrode bump 96 are provided on a part of the electrode on the end (outside) of the piezoelectric sheet 91 without providing the piezoelectric film 92 and the gate electrode 94e.
  • the source electrode 94d of the p-type MOSFET 82 and the gate electrode 94e of the n-type MOSFET 83 are electrically connected (not shown).
  • the gate electrode 94f is connected to the resistor 88.
  • a protective sheet 99 is provided on the surface of the semiconductor substrate 95 opposite to the surface on which the piezoelectric sheet 91 is formed.
  • the protective sheet 99 is not necessarily an essential configuration.
  • MOSFETs are formed in the switching element, but three or more MOSFETs can be formed in the same manner.
  • a diode, a resistor, or a capacitor can be formed in the semiconductor layer. Therefore, it is possible to incorporate a rectifier circuit such as a diode bridge circuit or a booster circuit such as a half wave double rectifier circuit.
  • FIG. 12 shows a circuit diagram of a wireless sensor using a switching element according to an embodiment of the present invention.
  • the wireless sensor according to the sixth embodiment shown in FIG. 12 includes a sensor device 109, a wireless module 108, a microcomputer 106, a power source 104, a switching transistor 107, and a switching element 110.
  • the resistor 103 and the switching element 110 are connected in series between the power supply 104 and the GND 105. Note that the switching transistor 107 is different from the switching transistor included in the switching element 110.
  • the sensor device 109 acquires environmental information.
  • the wireless module 108 wirelessly transmits information acquired by the sensor device 109.
  • the microcomputer 106 controls the wireless module 108.
  • the power source 104 supplies power for starting the microcomputer 106 and the wireless module 108.
  • the microcomputer 106 is connected to the electrode on the power supply 104 side of the switching element 110.
  • a switching transistor 107 that controls power supply is provided between the power source 104 and the wireless module 108 and the sensor device 109.
  • the microcomputer 106 is activated by the output from the switching element 110.
  • the switching transistor 107 When the microcomputer 106 is activated, the switching transistor 107 is turned on by the microcomputer 106 and power is supplied to the wireless module 108 and the sensor device 109.
  • the operation of the microcomputer 106 is the same as that in the first embodiment.
  • the wireless module 108 transmits the environment information acquired by the sensor device 109 to a management device of the wireless sensor network.
  • the piezoelectric element and the switching transistor can be manufactured as one device, so that a highly reliable trigger circuit without malfunction can be obtained.
  • the wireless sensor using the switching element of the present invention has been described.
  • the application of the switching element of the present invention is not limited to the wireless sensor, and can be applied to various environmental sensors. It is.
  • the piezoelectric element and the switching transistor that is turned on by the output voltage of the piezoelectric element can be realized by one device. Therefore, the influence of external noise can be suppressed, and a highly reliable trigger circuit without malfunction can be realized.
  • the present invention relates to a switching element in which a gate electrode of a switching transistor and an electrode of a piezoelectric element are integrated.
  • the present invention relates to a switching element that operates using an electromotive force generated by a piezoelectric element and a device to which the switching element is applied.
  • the switching element of the present invention can be used, for example, as a trigger circuit for an environmental sensor having a wireless function.
  • Switching element 10 Semiconductor layer 11 Piezoelectric sheet 12 Piezoelectric film 13a, 13b Electrode film 14a Source electrode 14b Drain electrode 15 Semiconductor substrate 15a N + area

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Abstract

This switching element is characterized in that the electrode of the piezoelectric element also functions as one of the electrodes of the switching transistor. More specifically, the switching element is provided with: a substrate; a source region and drain region provided to one surface of the substrate; an insulating film arranged on the substrate; a first electrode layer arranged on the insulating film; a piezoelectric film arranged on the first electrode layer; and a second electrode layer arranged on the piezoelectric film.

Description

スイッチング素子およびそれを用いたデバイスSwitching element and device using the same
　本発明は、スイッチングトランジスタのゲート電極と圧電素子の電極を一体化したスイッチング素子に関する。特に、圧電素子によって発生した起電力を利用して動作するスイッチング素子およびそれを適用したデバイスに関する。 The present invention relates to a switching element in which a gate electrode of a switching transistor and an electrode of a piezoelectric element are integrated. In particular, the present invention relates to a switching element that operates using an electromotive force generated by a piezoelectric element and a device to which the switching element is applied.
　近年、屋内外の様々な場所にセンサノードを設置し、気温、湿度、明るさ、あるいは、人の動きをセンシングデバイスで観測し、そこで得られたデータを元に、照明や空調の制御を行うことによって、エネルギー消費量を減らす技術に期待がもたれている。このようなセンサノードを無線通信で接続した無線センサネットワークは、省エネルギーだけではなく、防犯、防災などの安心・安全な社会を実現する技術の一つとして以前より普及が期待されていた。しかしながら、このような無線センサネットワークは、コストや電源供給などの問題によって、普及が妨げられていた。 In recent years, sensor nodes have been installed in various places indoors and outdoors, and temperature, humidity, brightness, or human movements are observed with sensing devices, and lighting and air conditioning are controlled based on the data obtained there. As a result, technology is expected to reduce energy consumption. Wireless sensor networks in which such sensor nodes are connected by wireless communication have been expected to spread widely as one of the technologies for realizing a safe and secure society such as crime prevention and disaster prevention as well as energy saving. However, the spread of such wireless sensor networks has been hampered by problems such as cost and power supply.
　センサノードの消費電力を抑制するためには、センサノードの起動時間を極力短くして、待機時間を長くする方法が取られる。センサノードが起動している間は、センサデバイスや制御マイコン、無線通信モジュールなど様々な機能が使われるために消費電力は大きいものの、待機時はほとんどの機能が使われないため消費電力はきわめて小さくなる。そこで、例えば、センサノードを１分間に１回といった頻度で定期的に起動した後、センサデバイスで情報を取得し、無線モジュールで結果を送信し、その後、待機状態に戻るといった動作フローが構築される。このような動作フローを取り入れると、センサノードが起動している時間は十数秒程度で済み、その活動の大部分は待機時間で占められるため、消費電力を平均化すると十分に低電力化することができる。 In order to suppress the power consumption of the sensor node, a method of shortening the start time of the sensor node as much as possible and extending the standby time is taken. While the sensor node is active, power consumption is high because various functions such as sensor devices, control microcomputers, and wireless communication modules are used, but power consumption is extremely low because most functions are not used during standby. Become. Therefore, for example, an operation flow is constructed in which the sensor node is periodically started at a frequency of once per minute, information is acquired by the sensor device, the result is transmitted by the wireless module, and then the standby state is returned. The If such an operation flow is adopted, the sensor node is activated for about ten seconds or more, and most of the activity is occupied by the standby time. Therefore, when the power consumption is averaged, the power consumption can be sufficiently reduced. Can do.
　一方、定期的な起動では問題が有る場合、例えば、人感センサのように人が接近したことを情報として送信する場合は、不定期に事象が発生するため、常時センサノードを起動しなければならなかった。 On the other hand, when there is a problem with regular activation, for example, when information indicating that a person has approached is sent as information such as a human sensor, an event occurs irregularly, so the sensor node must always be activated. did not become.
　このような問題点を解決する技術としては、例えば、特許文献１では、光、圧力、熱、磁界を電圧に変換するデバイスを用い、このデバイスから出力された電圧でトランジスタなどのスイッチング素子を導通させて、センサノードに電力を供給する方式が提案されている。例えば、圧力を電気に変換する圧電素子を重量センサとして用いれば、重力センサの上に人が乗ることで電圧を発生し、スイッチング素子を導通することが出来る。 As a technique for solving such a problem, for example, in Patent Document 1, a device that converts light, pressure, heat, and a magnetic field into voltage is used, and a switching element such as a transistor is turned on by the voltage output from this device. Then, a method of supplying power to the sensor node has been proposed. For example, if a piezoelectric element that converts pressure into electricity is used as a weight sensor, a person can ride on the gravity sensor to generate a voltage and to conduct the switching element.
　また、特許文献２に記載のセンサ装置では、機械装置の稼働を検知する振動センサを用い、機械装置の稼働により振動センサが電圧を発生することによって、センサの電源スイッチを入れることができる。すなわち、振動センサと、振動センサからの電圧によって動作する電源スイッチとによってスイッチング素子が形成され、そのスイッチング素子がトリガ回路として機能する。 In the sensor device described in Patent Document 2, a vibration sensor that detects the operation of the mechanical device is used. When the vibration sensor generates a voltage by the operation of the mechanical device, the power switch of the sensor can be turned on. That is, a switching element is formed by the vibration sensor and a power switch that operates according to the voltage from the vibration sensor, and the switching element functions as a trigger circuit.
特開２００４－３１２５０９号公報JP 2004-31509 A 特開２００８－１８６３３６号公報JP 2008-186336 A
　特許文献２に記載されたような一般的な事象検知用振動センサは、検知対象物に接着され、信号ケーブルによりセンサノード内部の基板に接続され実装されたスイッチングトランジスタに信号を出力する。このため、振動センサとスイッチングトランジスタ間の距離が大きく、外来ノイズの影響を受けやすくなるという課題がある。 A general event detection vibration sensor as described in Patent Document 2 is bonded to a detection object, and is connected to a substrate inside a sensor node by a signal cable and outputs a signal to a switching transistor. For this reason, the distance between a vibration sensor and a switching transistor is large, and there exists a subject that it becomes easy to receive to the influence of external noise.
　また、一般的に、振動センサの内部にスイッチングトランジスタを実装すると、振動センサが大きくなるため、振動センサとスイッチングトランジスタを一つのデバイスにすることが難しいという課題がある。 Also, generally, when a switching transistor is mounted inside the vibration sensor, the vibration sensor becomes large, and thus there is a problem that it is difficult to make the vibration sensor and the switching transistor as one device.
　本発明の目的は、圧電素子とスイッチングトランジスタを一つのデバイスで実現し、外来ノイズの影響を受けにくいトリガ回路を提供することにある。 An object of the present invention is to provide a trigger circuit in which a piezoelectric element and a switching transistor are realized by one device and are not easily affected by external noise.
　本発明のスイッチング素子は、圧電素子の電極がスイッチングトランジスタのいずれかの電極を兼ねることを特徴とする。より具体的には、基板と、基板の一方の面に設けられたソース領域およびドレイン領域と、基板上に設けられた絶縁膜と、絶縁膜上に配置された第１の電極層と、第１の電極層上に配置された圧電膜と、圧電膜上に配置された第２の電極層と、を備えるスイッチング素子とする。 The switching element of the present invention is characterized in that the electrode of the piezoelectric element also serves as one of the electrodes of the switching transistor. More specifically, a substrate, a source region and a drain region provided on one surface of the substrate, an insulating film provided on the substrate, a first electrode layer disposed on the insulating film, The switching element includes a piezoelectric film disposed on one electrode layer and a second electrode layer disposed on the piezoelectric film.
　また、本発明のスイッチング素子は、基板と、基板上に設けられた拡散領域と、拡散領域上に設けられた絶縁膜と、絶縁膜上に設けられた圧電素子と、を備えることを特徴とする。 The switching element of the present invention includes a substrate, a diffusion region provided on the substrate, an insulating film provided on the diffusion region, and a piezoelectric element provided on the insulating film. To do.
　本発明のスイッチング素子によれば、圧電素子とスイッチングトランジスタを一つのデバイスとすることができるため、外来ノイズの影響を抑制でき、誤動作のない信頼性の高いトリガ回路を実現することができる。 According to the switching element of the present invention, since the piezoelectric element and the switching transistor can be made into one device, the influence of external noise can be suppressed, and a highly reliable trigger circuit without malfunction can be realized.
本発明の第１の実施形態に係るスイッチング素子の断面構造図である。1 is a cross-sectional structure diagram of a switching element according to a first embodiment of the present invention. 本発明の第１の実施形態に係るスイッチング素子の上方平面図である。1 is an upper plan view of a switching element according to a first embodiment of the present invention. 本発明の第１の実施形態に係るスイッチング素子の断面構造図である。1 is a cross-sectional structure diagram of a switching element according to a first embodiment of the present invention. 本発明の第１の実施形態に係るスイッチングデバイスの断面構造図である。1 is a cross-sectional structure diagram of a switching device according to a first embodiment of the present invention. 本発明の第１の実施形態に係る回路図である。1 is a circuit diagram according to a first embodiment of the present invention. 本発明の第１の実施形態に係るスイッチング素子の製造工程の模式図である。It is a schematic diagram of the manufacturing process of the switching element which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係るスイッチング素子の製造工程の模式図である。It is a schematic diagram of the manufacturing process of the switching element which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係るスイッチング素子の製造工程の模式図である。It is a schematic diagram of the manufacturing process of the switching element which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係るスイッチング素子の製造工程の模式図である。It is a schematic diagram of the manufacturing process of the switching element which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係るスイッチング素子の製造工程の模式図である。It is a schematic diagram of the manufacturing process of the switching element which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係るスイッチング素子の製造工程の模式図である。It is a schematic diagram of the manufacturing process of the switching element which concerns on the 1st Embodiment of this invention. 本発明の第２の実施形態に係るスイッチング素子の断面構造図である。It is a sectional structure figure of a switching element concerning a 2nd embodiment of the present invention. 本発明の第３の実施形態に係るスイッチング素子の断面構造図である。FIG. 6 is a cross-sectional structure diagram of a switching element according to a third embodiment of the present invention. 本発明の第４の実施形態に係るスイッチング素子の断面構造図である。It is sectional structure drawing of the switching element which concerns on the 4th Embodiment of this invention. 本発明の第５の実施形態に係る回路図である。It is a circuit diagram concerning a 5th embodiment of the present invention. 本発明の第５の実施形態に係るスイッチング素子の断面構造図である。It is sectional structure drawing of the switching element which concerns on the 5th Embodiment of this invention. 本発明の第６の実施形態に係る回路図である。It is a circuit diagram concerning a 6th embodiment of the present invention.
　以下に、本発明を実施するための好ましい形態について図面を用いて説明する。但し、以下に述べる実施形態には、本発明を実施するために技術的に好ましい限定がされているが、発明の範囲を以下に限定するものではない。 Hereinafter, preferred embodiments for carrying out the present invention will be described with reference to the drawings. However, the preferred embodiments described below are technically preferable for carrying out the present invention, but the scope of the invention is not limited to the following.
　〔第１の実施形態〕図１に、本発明の第１の実施形態に係るスイッチング素子１の断面構造図を示す。図１は、後述する図２のＡ－Ａ’断面における断面図となる。図２には、本発明の第１の実施形態に係るスイッチング素子１の上面平面図を示す。また、図３には、図２のＢ－Ｂ’断面における断面図を示す。 First Embodiment FIG. 1 shows a cross-sectional structure diagram of a switching element 1 according to a first embodiment of the present invention. FIG. 1 is a cross-sectional view taken along the line A-A ′ of FIG. 2 described later. FIG. 2 is a top plan view of the switching element 1 according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along the line B-B ′ of FIG.
　〔スイッチング素子の構成〕図１に示す通り、第１の実施形態のスイッチング素子１は、圧電シート１１（圧電素子に相当する）と半導体基板１５（Ｐwell領域を含む）が絶縁膜１７を介して接続された積層体からなる。 [Configuration of Switching Element] As shown in FIG. 1, the switching element 1 of the first embodiment includes a piezoelectric sheet 11 (corresponding to a piezoelectric element) and a semiconductor substrate 15 (including a Pwell region) through an insulating film 17. It consists of connected laminates.
　圧電シート１１は、圧電膜１２を電極フィルム１３ａ、１３ｂで挟み込んだ構造をとる。 The piezoelectric sheet 11 has a structure in which a piezoelectric film 12 is sandwiched between electrode films 13a and 13b.
　圧電膜１２は、圧電材料を薄板状に形成したものである。 The piezoelectric film 12 is formed by forming a piezoelectric material into a thin plate shape.
　圧電膜１２の圧電材料としては、ＢａＴｉＯ3（チタン酸バリウム）、ＰＺＴ（チタン酸ジルコン酸鉛）、ＺｎＯ（酸化亜鉛）の様な圧電セラミックス、あるいは、ポリフッ化ビニリデンの様な圧電ポリマーが適している。また、圧電セラミックスとしては、ＰＭＮ（マグネシウム酸ニオブ酸鉛）、ＰＺＮＴ（亜鉛ニオブ酸チタン酸鉛固溶体）などを用いることもできる。 As the piezoelectric material of the piezoelectric film 12, piezoelectric ceramics such as BaTiO3 (barium titanate), PZT (lead zirconate titanate), ZnO (zinc oxide), or piezoelectric polymers such as polyvinylidene fluoride are suitable. . Moreover, as piezoelectric ceramics, PMN (lead magnesium niobate), PZNT (lead zinc niobate titanate solid solution), or the like can also be used.
　圧電シート１１は、圧電膜１２の両面に、導電性シートを圧着する、あるいは、導電性材料を介して接続することによって形成する。なお、導電性シートは、電極フィルム１３ａ、１３ｂに相当する。 The piezoelectric sheet 11 is formed by pressure-bonding a conductive sheet on both sides of the piezoelectric film 12, or by connecting via a conductive material. The conductive sheet corresponds to the electrode films 13a and 13b.
　以上が、圧電シート１１の構成である。 The above is the configuration of the piezoelectric sheet 11.
　圧電シート１１の外側の電極フィルム１３ａの一部には、圧電シート１１を被覆せずに電極バンプ１６が形成され、さらに電極バンプ１６を囲む様に絶縁部１８が設置されている。 An electrode bump 16 is formed on a part of the electrode film 13 a outside the piezoelectric sheet 11 without covering the piezoelectric sheet 11, and an insulating portion 18 is provided so as to surround the electrode bump 16.
　第１の実施形態の半導体基板１５は、ｐ型半導体基板を用いており、半導体層１０の構成要素となる。半導体層１０は、チャネル層１５ｂ（Ｐwell層の一部）と、Ｎ+領域１５ａと、Ｎ+領域１５ａの内部に形成した溝を金属で埋め込んだ埋め込み配線（ソース電極１４ａ、ドレイン電極１４ｂ）による電極を有する。 The semiconductor substrate 15 of the first embodiment uses a p-type semiconductor substrate and is a constituent element of the semiconductor layer 10. The semiconductor layer 10 includes a channel layer 15b (part of the Pwell layer), an N + region 15a, and a buried wiring (source electrode 14a, drain electrode 14b) in which a groove formed in the N + region 15a is filled with metal. It has an electrode.
　埋め込み配線を一定の間隔で整列させた電極は、ソース電極１４ａあるいはドレイン電極１４ｂのどちらかの電極となる。ソース電極１４ａとドレイン電極１４ｂとは、交互に配置されている。 The electrode in which the embedded wirings are arranged at regular intervals is either the source electrode 14a or the drain electrode 14b. The source electrode 14a and the drain electrode 14b are alternately arranged.
　全てのソース電極１４ａ同士は電気的に接続されている。同様に、全てのドレイン電極１４ｂは電気的に接続されている。なお、ソース電極１４ａおよびドレイン電極１４ｂについて、電気的に接続されているものについては同じ符号で示す。 All the source electrodes 14a are electrically connected. Similarly, all the drain electrodes 14b are electrically connected. In addition, about the source electrode 14a and the drain electrode 14b, what is electrically connected is shown with the same code | symbol.
　ソース電極１４ａとドレイン電極１４ｂの接続状態は、図２の上面平面図および図３の断面図に示したような構成および位置関係となる。なお、図２においては、ソース電極１４ａおよびドレイン電極１４ｂの位置関係を明らかにするため、電極フィルム１３ｂ、絶縁膜１７、絶縁部１８などは省略している。また、電極フィルム１３ａおよび圧電膜１２は、ソース電極１４ａおよびドレイン電極１４ｂの形状や位置関係を明らかにするために、一部を透過図として示した。 The connection state of the source electrode 14a and the drain electrode 14b has the configuration and positional relationship as shown in the top plan view of FIG. 2 and the cross-sectional view of FIG. In FIG. 2, in order to clarify the positional relationship between the source electrode 14a and the drain electrode 14b, the electrode film 13b, the insulating film 17, the insulating portion 18, and the like are omitted. Further, part of the electrode film 13a and the piezoelectric film 12 is shown as a transmission diagram in order to clarify the shapes and positional relationships of the source electrode 14a and the drain electrode 14b.
　圧電シート１１の電極フィルム１３ｂは、半導体基板１５上のソース電極１４ａおよびドレイン電極１４ｂが配置された面と、絶縁膜１７を挟んで接合される。ソース電極１４ａと、ドレイン電極１４ｂと、ソース電極１４ａとドレイン電極１４ｂに挟まれた半導体基板１５に形成されるチャネル層１５ｂと、絶縁膜１７と、電極フィルム１３ｂのチャネル層１５ｂと対面する部位（ゲート電極）によって、スイッチングトランジスタが形成される。なお、電極フィルム１３ｂは、前述のスイッチングトランジスタのゲート電極と、圧電シート１１の電極を兼ねることになる。 The electrode film 13b of the piezoelectric sheet 11 is bonded to the surface on which the source electrode 14a and the drain electrode 14b are disposed on the semiconductor substrate 15 with the insulating film 17 interposed therebetween. Source electrode 14a, drain electrode 14b, channel layer 15b formed on semiconductor substrate 15 sandwiched between source electrode 14a and drain electrode 14b, insulating film 17, and part facing channel layer 15b of electrode film 13b ( A switching transistor is formed by the gate electrode. The electrode film 13b serves as both the gate electrode of the switching transistor and the electrode of the piezoelectric sheet 11.
　また、ソース電極１４ａの一部は、半導体基板１５表面に露出している。ソース電極１４ａの露出面は、圧電シート１１の外側の電極フィルム１３ａと電極バンプ１６を介して電気的に接続される。半導体基板１５の他方の面には、樹脂製の保護フィルム１９が貼付されている。なお、保護フィルム１９は必須の構成ではない。 Further, a part of the source electrode 14 a is exposed on the surface of the semiconductor substrate 15. The exposed surface of the source electrode 14 a is electrically connected to the outer electrode film 13 a of the piezoelectric sheet 11 via the electrode bump 16. A resin protective film 19 is affixed to the other surface of the semiconductor substrate 15. The protective film 19 is not an essential configuration.
　〔スイッチングモジュールの構成〕図４には、第１の実施形態のスイッチング素子１を搭載したスイッチングデバイス２０の一例を示した。 [Configuration of Switching Module] FIG. 4 shows an example of the switching device 20 on which the switching element 1 of the first embodiment is mounted.
　図４に示す通り、スイッチングデバイス２０において、第１の実施形態のスイッチング素子１は、金属製あるいは樹脂製の支持板２３に貼付けられている。支持板２３の先端には、錘２４を搭載し、その反対の端部は固定部２２に固定され、片持ち梁構造を形成している。スイッチング素子１の電極バンプ１６は、配線２５によって外部に設けられたマイコンなどに接続されている。また、スイッチングデバイス２０の外側は、筐体２１で覆われている。 As shown in FIG. 4, in the switching device 20, the switching element 1 of the first embodiment is attached to a metal or resin support plate 23. A weight 24 is mounted on the tip of the support plate 23, and the opposite end is fixed to the fixing portion 22 to form a cantilever structure. The electrode bump 16 of the switching element 1 is connected to a microcomputer or the like provided outside by a wiring 25. Further, the outside of the switching device 20 is covered with a housing 21.
　片持ち梁構造部に外部応力が印加されると、支持板２３とともにスイッチング素子１が屈曲する。スイッチング素子１の屈曲により圧電膜１２は圧縮あるいはせん断変形を起こし、圧電シート１１の表裏面の電極フィルム１３ａ、１３ｂの間に電位差が生じる。 When an external stress is applied to the cantilever structure, the switching element 1 is bent together with the support plate 23. The piezoelectric film 12 is compressed or sheared by the bending of the switching element 1, and a potential difference is generated between the electrode films 13 a and 13 b on the front and back surfaces of the piezoelectric sheet 11.
　圧電シート１１の一方の電極である電極フィルム１３ｂは、ゲート電極を兼ねている。また、圧電シート１１のもう一方の電極である電極フィルム１３ａは、半導体層１０のソース電極１４ａと電気的に接続されている。なお、電極フィルム１３ａは、構成によってはバックゲート電極（Ｐwell層から引き出された電極）に電気的に接続することもできる。 The electrode film 13b which is one electrode of the piezoelectric sheet 11 also serves as a gate electrode. The electrode film 13 a that is the other electrode of the piezoelectric sheet 11 is electrically connected to the source electrode 14 a of the semiconductor layer 10. Note that the electrode film 13a can be electrically connected to a back gate electrode (an electrode drawn from the Pwell layer) depending on the configuration.
　そのため、スイッチング素子１の変形によって、ドレイン電極１４ｂとソース電極１４ａ間のゲート電極に対向したＰwell領域の一部は、チャネル層１５ｂとなり、キャリアパスが形成されて導通される。すなわち、外部からの振動によりスイッチング素子１のドレイン電極１４ｂとソース電極１４ａ間は、電気的に導通状態とすることができる。 Therefore, due to the deformation of the switching element 1, a part of the Pwell region facing the gate electrode between the drain electrode 14b and the source electrode 14a becomes the channel layer 15b, and a carrier path is formed and is conducted. In other words, the drain electrode 14b and the source electrode 14a of the switching element 1 can be electrically connected by external vibration.
　〔スイッチング素子の動作〕図５に本発明の第１の実施形態のスイッチング素子１に係る回路図の一例を示す。なお、図５の回路図は一例であり、本発明を限定するものではない。 [Operation of Switching Element] FIG. 5 shows an example of a circuit diagram relating to the switching element 1 of the first embodiment of the present invention. The circuit diagram of FIG. 5 is an example and does not limit the present invention.
　スイッチング素子１は、圧電素子３１およびｎ型ＭＯＳＦＥＴ３２を備えている。 The switching element 1 includes a piezoelectric element 31 and an n-type MOSFET 32.
　圧電素子３１は、図１の圧電シート１１に相当し、圧電膜１２および２つの電極フィルム１３ａ、１３ｂを有する。 The piezoelectric element 31 corresponds to the piezoelectric sheet 11 of FIG. 1 and includes the piezoelectric film 12 and the two electrode films 13a and 13b.
　ｎ型ＭＯＳＦＥＴ３２は、図１において、ソース電極１４ａ、ドレイン電極１４ｂ、絶縁膜１７およびチャネル層１５ｂを備える。なお、ｎ型ＭＯＳＦＥＴ３２において、ソース電極１４ａまたはドレイン電極１４ｂを内部に含むＮ+領域１５ａは、それぞれソース領域またはドレイン領域となる。また、図１に示した複数のソース電極１４ａ、複数のドレイン電極１４ｂは、それぞれ並列に接続されている。そのため、図５のｎ型ＭＯＳＦＥＴ３２は、いずれかの隣接しあうソース領域ドレイン領域によって形成される。 In FIG. 1, the n-type MOSFET 32 includes a source electrode 14a, a drain electrode 14b, an insulating film 17, and a channel layer 15b. In the n-type MOSFET 32, the N + region 15a including the source electrode 14a or the drain electrode 14b inside becomes a source region or a drain region, respectively. Further, the plurality of source electrodes 14a and the plurality of drain electrodes 14b shown in FIG. 1 are connected in parallel. Therefore, the n-type MOSFET 32 of FIG. 5 is formed by any adjacent source region / drain region.
　電源３４とＧＮＤ３５の間に、抵抗３３とスイッチング素子１が直列に接続され、マイコン３６のリセット信号用の入力ポートあるいは割り込み信号用の入力ポートがスイッチング素子１の電源側の電極、すなわち、ドレイン電極１４ｂに接続されている。なお、デバイスによっては、抵抗３３がマイコン３６の内部に設けられていてもよい。 The resistor 33 and the switching element 1 are connected in series between the power supply 34 and the GND 35, and the reset signal input port or the interrupt signal input port of the microcomputer 36 is an electrode on the power supply side of the switching element 1, that is, a drain electrode. 14b. Depending on the device, the resistor 33 may be provided inside the microcomputer 36.
　外部からの振動によりスイッチング素子１が導通状態となると、マイコン３６の入力ポートの電位は、ＶＤＤからＧＮＤに低下する。マイコン３６がスリープ状態の場合、マイコン３６はこの電位の変動を検知し、スリープ状態から起動状態に遷移することが可能である。すなわち、マイコン３６においては、ＶＤＤより小さい正の電位に起動の閾値が設けられている。なお、スリープ状態とは、マイコン３６のＣＰＵは停止状態であるが、入力信号に対してはマイコン３６が反応できる状態のことを意味する。 When the switching element 1 becomes conductive due to vibrations from the outside, the potential of the input port of the microcomputer 36 decreases from VDD to GND. When the microcomputer 36 is in the sleep state, the microcomputer 36 can detect a change in the potential and can transition from the sleep state to the activated state. That is, in the microcomputer 36, the activation threshold is provided at a positive potential smaller than VDD. Note that the sleep state means a state in which the microcomputer 36 can react to an input signal although the CPU of the microcomputer 36 is in a stopped state.
　すなわち、人の接近による振動を起点としてマイコン３６を起動、その後センサデバイスや無線モジュール等の周辺デバイスの起動を完了することができる。あるいは、スイッチング素子１をマイコン３６と電源３４を接続する電源ラインに挿入し、スイッチング素子１が導通するとマイコン３６に電力が供給されるように構成しても良い。 That is, it is possible to start the microcomputer 36 starting from vibration caused by the approach of a person, and then complete startup of peripheral devices such as sensor devices and wireless modules. Alternatively, the switching element 1 may be inserted into a power supply line connecting the microcomputer 36 and the power supply 34 so that power is supplied to the microcomputer 36 when the switching element 1 is turned on.
　本発明の第１の実施形態に係るスイッチング素子を用いれば、振動等に応答して電圧を発生する圧電素子と、圧電素子からの出力に応じてトランジスタの導通を行うスイッチングトランジスタを一つのデバイスとすることができる。そのため、外来ノイズの影響を抑制することができる。したがって、誤動作のなく信頼性の高いトリガ回路を実現することができる。 If the switching element according to the first embodiment of the present invention is used, a piezoelectric element that generates a voltage in response to vibration or the like, and a switching transistor that conducts the transistor in accordance with an output from the piezoelectric element are combined into one device. can do. Therefore, the influence of external noise can be suppressed. Therefore, a highly reliable trigger circuit can be realized without malfunction.
　〔スイッチング素子の製造方法〕図６Ａ～６Ｆを用いて、第１の実施形態に係るスイッチング素子の製造方法を説明する。 [Manufacturing Method of Switching Element] A manufacturing method of the switching element according to the first embodiment will be described with reference to FIGS. 6A to 6F.
　厚さ１０～１００μｍの薄板状に形成された圧電膜１２の表裏に、導電性材料をシート状に形成した電極フィルム１３ａ、１３ｂと、導電材料を介して圧着する（図６Ａ）。 The piezoelectric films 12 formed into a thin plate shape having a thickness of 10 to 100 μm are pressure-bonded to the electrode films 13a and 13b in which a conductive material is formed into a sheet shape through the conductive material (FIG. 6A).
　電極フィルム１３ｂの一部には圧電膜１２を形成せずに開口し、開口部に導電性材料、及び、絶縁性樹脂を印刷等で塗布、焼結することによって、半導体層１０との電気的接続用の電極バンプ１６および絶縁部１８を形成する（図６Ｂ）。 A part of the electrode film 13b is opened without forming the piezoelectric film 12, and an electrically conductive material and an insulating resin are applied to the opening by printing or the like, and sintered, thereby electrically connecting to the semiconductor layer 10. The electrode bump 16 for connection and the insulating part 18 are formed (FIG. 6B).
　一方、半導体層１０は、一般的な半導体工程によって形成することができる。すなわち、イオン注入、ドライエッチング、蒸着、及び、フォトリソグラフ等により各工程に於いて任意のパターンのＮ+領域、埋め込み配線を形成する。なお、以下の説明において、各工程の詳細は省略する。 On the other hand, the semiconductor layer 10 can be formed by a general semiconductor process. That is, an N + region having an arbitrary pattern and a buried wiring are formed in each step by ion implantation, dry etching, vapor deposition, photolithography, or the like. In the following description, details of each process are omitted.
　第１の実施形態では、ｐ型半導体基板を用いる。拡散層を形成しない部分にはマスクをし、開口部分にはイオン注入によって不純物イオンを導入する（図６Ｃ）。ここで形成した拡散層は、Ｎ+領域とする。 In the first embodiment, a p-type semiconductor substrate is used. A portion where the diffusion layer is not formed is masked, and impurity ions are introduced into the opening by ion implantation (FIG. 6C). The diffusion layer formed here is an N + region.
　次に、ソース電極１４ａまたはドレイン電極１４ｂを形成する箇所にドライエッチングを施す（図６Ｄ）。 Next, dry etching is performed on the portion where the source electrode 14a or the drain electrode 14b is formed (FIG. 6D).
　さらに、ドライエッチングを施した箇所に配線となる金属を蒸着する（図６Ｅ）。 Furthermore, a metal to be a wiring is vapor-deposited at the location where dry etching is performed (FIG. 6E).
　その後、半導体ウェハの裏面を機械的、化学的に研削し、半導体基板１５の厚さを１０～１００μｍ程度とする（図は省略）。 Thereafter, the back surface of the semiconductor wafer is mechanically and chemically ground to make the semiconductor substrate 15 have a thickness of about 10 to 100 μm (not shown).
　最後に、絶縁材料を圧電シート１１あるいは半導体基板１５上に、１μｍ程度の厚さになるように塗布し、絶縁材料を介して圧電シート１１と半導体基板１５を接続する。また、半導体基板１５の裏面に保護シート１９を貼付する（図６Ｆ）。 Finally, an insulating material is applied on the piezoelectric sheet 11 or the semiconductor substrate 15 so as to have a thickness of about 1 μm, and the piezoelectric sheet 11 and the semiconductor substrate 15 are connected via the insulating material. Moreover, the protective sheet 19 is affixed on the back surface of the semiconductor substrate 15 (FIG. 6F).
　以上が本発明の第１の実施形態に係るスイッチング素子の製造方法である。なお、これ以降で説明するスイッチング素子も、第１の実施形態と同様の製造方法によって製造することができる。 The above is the method for manufacturing the switching element according to the first embodiment of the present invention. In addition, the switching element demonstrated after this can also be manufactured by the manufacturing method similar to 1st Embodiment.
　〔第２の実施形態〕図７に、本発明の第２の実施形態に係るスイッチング素子２の断面構造図を示す。 Second Embodiment FIG. 7 shows a cross-sectional structure diagram of a switching element 2 according to a second embodiment of the present invention.
　第１の実施形態との相違点は、ドレイン電極５４ｂ、ソース電極５４ａ、ゲート電極５４ｃを半導体基板５５表面に形成したことである。 The difference from the first embodiment is that the drain electrode 54b, the source electrode 54a, and the gate electrode 54c are formed on the surface of the semiconductor substrate 55.
　図７に示す通り、第２の実施形態のスイッチング素子２は、圧電シート５１と半導体基板５５が、絶縁膜５７または絶縁部５８を介して接続された積層体からなる。 As shown in FIG. 7, the switching element 2 according to the second embodiment is composed of a laminated body in which the piezoelectric sheet 51 and the semiconductor substrate 55 are connected via an insulating film 57 or an insulating part 58.
　圧電シート５１は、圧電膜５２を電極フィルム５３ａ、５３ｂで挟み込んだ構造をとる。圧電シート５１の材料および形成方法は、第１の実施形態と同様である。 The piezoelectric sheet 51 has a structure in which a piezoelectric film 52 is sandwiched between electrode films 53a and 53b. The material and forming method of the piezoelectric sheet 51 are the same as those in the first embodiment.
　圧電シート５１の端部（外側）の電極の一部には、圧電シート５１を被覆せずに、電極バンプ５６と、電極バンプ５６を囲む絶縁部５８が設置されている。 A part of the electrode on the end (outer side) of the piezoelectric sheet 51 is provided with an electrode bump 56 and an insulating part 58 surrounding the electrode bump 56 without covering the piezoelectric sheet 51.
　第２の実施形態の半導体基板５５には、ｐ型半導体基板を用いている。半導体基板５５は、半導体層５０の構成要素となる。半導体層５０は、内部にチャネル層５５ｂ（Ｐwell層の一部）と、Ｐwell層の内部のＮ+領域５５ａを有する。 A p-type semiconductor substrate is used as the semiconductor substrate 55 of the second embodiment. The semiconductor substrate 55 is a component of the semiconductor layer 50. The semiconductor layer 50 has a channel layer 55b (a part of the Pwell layer) and an N + region 55a inside the Pwell layer.
　第２の実施形態においては、Ｎ+領域５５ａの表面に、ソース電極５４ａまたはドレイン電極５４ｂを形成する。ソース電極５４ａとドレイン電極５４ｂとの位置関係および接続状態は、第１の実施形態と同様である。 In the second embodiment, the source electrode 54a or the drain electrode 54b is formed on the surface of the N + region 55a. The positional relationship and connection state between the source electrode 54a and the drain electrode 54b are the same as in the first embodiment.
　絶縁膜５７を挟んでチャネル層５５ｂと対面する位置には、ゲート電極５４ｃが位置する。ゲート電極５４ｃの一方の面は絶縁膜５７と接し、また、他方の面は電極フィルム５３ｂと接している。 The gate electrode 54c is located at a position facing the channel layer 55b with the insulating film 57 interposed therebetween. One surface of the gate electrode 54c is in contact with the insulating film 57, and the other surface is in contact with the electrode film 53b.
　なお、絶縁膜５７は、ゲート電極５４ｃとチャネル層５５ｂの間のみに形成されていてもよい。その場合は、ソース電極５４ａまたはドレイン電極５４ｂと、電極フィルム５３ｂとの間には、絶縁部５８があるものとする。 Note that the insulating film 57 may be formed only between the gate electrode 54c and the channel layer 55b. In that case, it is assumed that there is an insulating portion 58 between the source electrode 54a or the drain electrode 54b and the electrode film 53b.
　圧電シート５１の電極フィルム５３ｂは、半導体基板５５上のソース電極５４ａおよびドレイン電極５４ｂが配置された面と、絶縁膜５７を挟んで接合される。ソース電極５４ａと、ドレイン電極５４ｂと、ソース電極５４ａとドレイン電極５４ｂに挟まれた半導体基板５５に形成されるチャネル層５５ｂと、絶縁膜５７と、電極フィルム５３ｂのチャネル層５５ｂと電気的に接続されたゲート電極５４ｃによって、スイッチングトランジスタが形成される。なお、電極フィルム５３ｂとゲート電極５４ｃと電気的に接続されているため、電極フィルム５３ｂは、前述のスイッチングトランジスタのゲート電極５４ｃと、圧電シート５１の電極を兼ねることになる。 The electrode film 53b of the piezoelectric sheet 51 is bonded to the surface of the semiconductor substrate 55 on which the source electrode 54a and the drain electrode 54b are disposed with the insulating film 57 interposed therebetween. The source electrode 54a, the drain electrode 54b, the channel layer 55b formed on the semiconductor substrate 55 sandwiched between the source electrode 54a and the drain electrode 54b, the insulating film 57, and the channel layer 55b of the electrode film 53b are electrically connected. A switching transistor is formed by the gate electrode 54c thus formed. Since the electrode film 53b and the gate electrode 54c are electrically connected, the electrode film 53b also serves as the gate electrode 54c of the switching transistor described above and the electrode of the piezoelectric sheet 51.
　また、ソース電極５４ａの一部は、半導体基板５５表面に露出している。ソース電極５４ａの露出面は、圧電シート５１の外側の電極フィルム５３ａと電極バンプ５６を介して電気的に接続される。半導体基板５５の他方の面には、樹脂製の保護フィルム５９が貼付されている。 Further, a part of the source electrode 54 a is exposed on the surface of the semiconductor substrate 55. The exposed surface of the source electrode 54 a is electrically connected to the outer electrode film 53 a of the piezoelectric sheet 51 via the electrode bump 56. A resin protective film 59 is affixed to the other surface of the semiconductor substrate 55.
　以上のような構成の第２の実施形態のスイッチング素子においても、第１の実施形態と同様の作用・効果を得ることができる。 Also in the switching element of the second embodiment having the above-described configuration, the same operations and effects as those of the first embodiment can be obtained.
　さらに、第２の実施形態のスイッチング素子は、埋め込み配線を形成する必要がないため比較的簡便な工程でトランジスタを形成することができる。 Furthermore, since the switching element of the second embodiment does not need to form a buried wiring, a transistor can be formed by a relatively simple process.
　〔第３の実施形態〕図８に、本発明の第３の実施形態に係るスイッチング素子３の断面構造図を示す。 [Third Embodiment] FIG. 8 is a sectional structural view of a switching element 3 according to a third embodiment of the present invention.
　第１の実施形態との相違点は、半導体層６０において、圧電シート６１との対向面にソース電極（電極フィルム６３ｂ）を形成し、その反対面（裏面）にドレイン電極（電極フィルム６３ｃ）を形成する点である。 The difference from the first embodiment is that in the semiconductor layer 60, a source electrode (electrode film 63b) is formed on the surface facing the piezoelectric sheet 61, and a drain electrode (electrode film 63c) is formed on the opposite surface (back surface). It is a point to form.
　図８に示す通り、第３の実施形態のスイッチング素子３は、圧電シート６１と半導体基板６５が、絶縁部６８を介して接続された積層体からなる。 As shown in FIG. 8, the switching element 3 according to the third embodiment includes a stacked body in which a piezoelectric sheet 61 and a semiconductor substrate 65 are connected via an insulating portion 68.
　圧電シート６１は、圧電膜６２を電極フィルム６３ａ、６３ｂで挟み込んだ構造をとる。圧電シート６１の材料および形成方法は、第１の実施形態と同様である。 The piezoelectric sheet 61 has a structure in which a piezoelectric film 62 is sandwiched between electrode films 63a and 63b. The material and forming method of the piezoelectric sheet 61 are the same as those in the first embodiment.
　第３の実施形態の半導体基板６５には、ｎ型半導体基板を用いている。半導体基板６５は、半導体層６０の構成要素となる。半導体層６０の内部は、圧電シート６１との対向面から順に、Ｎ+領域６５ａ、Ｐbase領域（チャネル層６５ｂ）、Ｎwell領域（基板６５）が形成されている。また、Ｎ+領域６５ａおよびチャネル層６５ｂの一部をエッチングして形成した溝と、溝の壁面を覆う酸化膜（絶縁膜６７）と、その内部を充填した導電材料よりなる埋め込み配線（ゲート電極６４）が形成されている。 An n-type semiconductor substrate is used as the semiconductor substrate 65 of the third embodiment. The semiconductor substrate 65 is a constituent element of the semiconductor layer 60. Inside the semiconductor layer 60, an N + region 65a, a Pbase region (channel layer 65b), and an Nwell region (substrate 65) are formed in this order from the surface facing the piezoelectric sheet 61. Also, a groove formed by etching a part of the N + region 65a and the channel layer 65b, an oxide film (insulating film 67) covering the wall surface of the groove, and a buried wiring (gate electrode) made of a conductive material filling the inside thereof 64) is formed.
　この埋め込み配線がいわゆるゲート電極６４となる。ゲート電極６４は、半導体基板６５の表面の一部で露出している。半導体基板６５の表面の一部は、電極バンプ６６を介して圧電シート６１の外側の電極フィルム６３ａと電気的に接続される。 This buried wiring becomes a so-called gate electrode 64. The gate electrode 64 is exposed at a part of the surface of the semiconductor substrate 65. A part of the surface of the semiconductor substrate 65 is electrically connected to the electrode film 63 a outside the piezoelectric sheet 61 through the electrode bumps 66.
　以上のような構成の第３の実施形態のスイッチング素子においても、第１の実施形態と同様の作用・効果を得ることができる。 Also in the switching element of the third embodiment having the above-described configuration, it is possible to obtain the same operations and effects as those of the first embodiment.
　また、第１の実施形態のスイッチング素子１では、横型のトランジスタで構成されているため、電流は半導体基板の表面に対して平行な方向に流れる。それに対し、第３の実施形態のスイッチング素子３は、縦型のトランジスタで構成されるため、電流は半導体基板の表面に対して垂直な方向に流れる。すなわち、第３の実施形態では、縦型のトランジスタ構造とすることによって、単位面積当たりのキャリアパスを多くすることができるため、より低いオン抵抗を実現でき、トランジスタによる電力損失をより小さくすることができる。 In addition, since the switching element 1 of the first embodiment is composed of a horizontal transistor, the current flows in a direction parallel to the surface of the semiconductor substrate. On the other hand, since the switching element 3 of the third embodiment is composed of a vertical transistor, the current flows in a direction perpendicular to the surface of the semiconductor substrate. That is, in the third embodiment, since the vertical transistor structure can increase the number of carrier paths per unit area, lower on-resistance can be realized, and power loss due to the transistor can be further reduced. Can do.
　〔第４の実施形態〕図９に、本発明の第４の実施形態に係るスイッチング素子４の断面構造図を示す。 [Fourth Embodiment] FIG. 9 is a sectional structural view of a switching element 4 according to a fourth embodiment of the present invention.
　第１の実施形態との相違点は、第４の実施形態では半導体層としてシリコン系の半導体ではなく、有機系の半導体を用いることである。 The difference from the first embodiment is that in the fourth embodiment, an organic semiconductor is used as a semiconductor layer instead of a silicon semiconductor.
　圧電シート７１は、第１の実施形態と同様に、圧電膜７２と、電極シート７３ａ，７３ｂからなる。圧電シート７１の一端部には、電極フィルム７３ａと電気的に接続するように形成した導電性の電極バンプ７６と、電極バンプ７６を取り囲むように形成した絶縁部７８を設ける。 The piezoelectric sheet 71 includes a piezoelectric film 72 and electrode sheets 73a and 73b, as in the first embodiment. One end portion of the piezoelectric sheet 71 is provided with a conductive electrode bump 76 formed so as to be electrically connected to the electrode film 73 a and an insulating portion 78 formed so as to surround the electrode bump 76.
　圧電シート７１の電極フィルム７３ｂ側の面には、電極バンプ７６の一部が露出するように、絶縁膜７７を形成する。絶縁膜７７は、後述する印刷プロセスで形成することが好ましい。 An insulating film 77 is formed on the surface of the piezoelectric sheet 71 on the electrode film 73b side so that a part of the electrode bumps 76 is exposed. The insulating film 77 is preferably formed by a printing process described later.
　絶縁膜７７の表面には、例えば印刷工法などによって、ソース電極７４ａまたはドレイン電極７４ｂとなる金属配線を形成する。その後、金属配線の間に、スクリーン印刷やインクジェット、マイクロコンタクト等の印刷プロセスにより、有機系半導体を塗布して半導体領域７５を形成する。 On the surface of the insulating film 77, a metal wiring to be the source electrode 74a or the drain electrode 74b is formed by, for example, a printing method. Thereafter, an organic semiconductor is applied between the metal wirings by a printing process such as screen printing, ink jetting, or microcontact to form the semiconductor region 75.
　ソース電極７４ａとドレイン電極７４ｂとの間に位置し、圧電シート７１に近い側の半導体領域７５が、チャネル層７５ａとして機能する。ソース電極７４ａ、ドレイン電極７４ｂ、半導体領域７５およびチャネル層７５ａによって半導体層７０が形成される。また、電極フィルム７３ｂのチャネル層７５ａと対面する部位は、ゲート電極として機能する。このように、有機系半導体を用いたトランジスタ構造を形成することができる。 The semiconductor region 75 located between the source electrode 74a and the drain electrode 74b and close to the piezoelectric sheet 71 functions as the channel layer 75a. The semiconductor layer 70 is formed by the source electrode 74a, the drain electrode 74b, the semiconductor region 75, and the channel layer 75a. Further, the portion of the electrode film 73b that faces the channel layer 75a functions as a gate electrode. As described above, a transistor structure using an organic semiconductor can be formed.
　すなわち、有機系半導体を用いることにより、予め形成した圧電シートと半導体基板を貼り合わせるのではなく、印刷プロセスによって圧電シート７１上に直接トランジスタを形成することができる。 That is, by using an organic semiconductor, a transistor can be directly formed on the piezoelectric sheet 71 by a printing process, instead of pasting a previously formed piezoelectric sheet and a semiconductor substrate.
　以上のような構成の第４の実施形態のスイッチング素子においても、第１の実施形態と同様の作用・効果を得ることができる。 Also in the switching element of the fourth embodiment configured as described above, the same operations and effects as those of the first embodiment can be obtained.
　さらに、第４の実施形態では、印刷工程を使用することにより、スイッチング素子の製造コストを低く抑えられる。 Furthermore, in the fourth embodiment, the manufacturing cost of the switching element can be kept low by using the printing process.
　〔第５の実施形態〕図１０に、本発明の第５の実施形態に係るスイッチング素子８０を用いた回路図を示す。 [Fifth Embodiment] FIG. 10 is a circuit diagram using a switching element 80 according to a fifth embodiment of the present invention.
　第１の実施形態との相違点は、半導体内部または表面に抵抗８８、ツェナーダイオード８７、デプレッション型のｐ型ＭＯＳＦＥＴ８２が設けられている点である。ツェナーダイオード８７とデプレッション型のｐ型ＭＯＳＦＥＴ８２は、圧電素子８１とｎ型ＭＯＳＦＥＴ８３のゲート電極との間とＧＮＤ８５との間に接続されている。また、ｐ型ＭＯＳＦＥＴ８２のゲート電極とｎ型ＭＯＳＦＥＴ８３のドレイン電極９４ｂが抵抗８８を介して接続されている。なお、電源８４および抵抗８９は、第１の実施形態と同様であるため、説明は省略する。 The difference from the first embodiment is that a resistor 88, a Zener diode 87, and a depletion type p-type MOSFET 82 are provided inside or on the surface of the semiconductor. The zener diode 87 and the depletion type p-type MOSFET 82 are connected between the piezoelectric element 81 and the gate electrode of the n-type MOSFET 83 and between the GND 85. Further, the gate electrode of the p-type MOSFET 82 and the drain electrode 94 b of the n-type MOSFET 83 are connected via a resistor 88. Note that the power supply 84 and the resistor 89 are the same as those in the first embodiment, and thus description thereof is omitted.
　圧電素子８１の変形により生じた電荷がｎ型ＭＯＳＦＥＴ８３のゲート電極に蓄積され、マイコン８６に信号出力した後、マイコン８６の制御によりｐ型ＭＯＳＦＥＴ８２のゲート電極をＧＮＤ電位に保持すると、ｐ型ＭＯＳＦＥＴ８２が動作する。その結果、圧電素子８１及びｎ型ＭＯＳＦＥＴ８３のゲート電極に蓄積された電荷をＧＮＤ８５に放出することができる。これにより、ｎ型ＭＯＳＦＥＴ８３のゲート電極に電荷が蓄積され、動作が不安定になることを抑制することができる。 After the electric charge generated by the deformation of the piezoelectric element 81 is accumulated in the gate electrode of the n-type MOSFET 83 and a signal is output to the microcomputer 86, the p-type MOSFET 82 is controlled by the microcomputer 86 to hold the gate electrode of the p-type MOSFET 82 at the GND potential. Operate. As a result, charges accumulated in the gate electrodes of the piezoelectric element 81 and the n-type MOSFET 83 can be released to the GND 85. As a result, it is possible to suppress the accumulation of charge in the gate electrode of the n-type MOSFET 83 and the unstable operation.
　続いて、図１１に、本発明の第５の実施形態に係るスイッチング素子５の断面構造図を示す。 Subsequently, FIG. 11 shows a sectional structural view of the switching element 5 according to the fifth embodiment of the present invention.
　第５の実施形態の半導体基板９５には、ｐ型半導体基板を用いている。半導体基板９５は、半導体層９０の構成要素となる。 A p-type semiconductor substrate is used as the semiconductor substrate 95 of the fifth embodiment. The semiconductor substrate 95 is a component of the semiconductor layer 90.
　半導体層９０は、内部にチャネル層９５ｂ（Ｐwell層の一部）と、Ｐwell層の内部のＮ+領域９５ａを有するｎ型ＭＯＳＦＥＴ８３を備えている。また、Ｎ+領域９５ａの内部には、ソース電極９４ａまたはドレイン電極９４ｂが設けられている。さらに、半導体層９０は、Ｎbase領域９５ｃを有するｐ型ＭＯＳＦＥＴ８２を備えている。Ｎbase領域９５ｃは、その内部に、２つのＰ+領域９５ｄ、９５ｅと、Ｎ+領域９５ｆと、Ｐ-領域９５ｇとを有している。 The semiconductor layer 90 includes an n-type MOSFET 83 having a channel layer 95b (a part of the Pwell layer) and an N + region 95a inside the Pwell layer. A source electrode 94a or a drain electrode 94b is provided inside the N + region 95a. Further, the semiconductor layer 90 includes a p-type MOSFET 82 having an Nbase region 95c. The Nbase region 95c has two P + regions 95d and 95e, an N + region 95f, and a P− region 95g.
　ｐ型ＭＯＳＦＥＴ８２において、２つのＰ+領域９５ｄ、９５ｅは、チャネル層となるＰ-領域９５ｇによって接続されている。また、一方のＰ+領域９５ｅは、Ｎ+領域９５ｆと接しており、その間にはソース電極９４ｄが形成されている。また、他方のＰ+領域９５ｄにはドレイン電極９４ｃが形成されている。 In the p-type MOSFET 82, the two P + regions 95d and 95e are connected by a P− region 95g serving as a channel layer. One P + region 95e is in contact with the N + region 95f, and a source electrode 94d is formed therebetween. A drain electrode 94c is formed in the other P + region 95d.
　ｐ型ＭＯＳＦＥＴ８２を形成するためには、まず、Ｐwell層内部にＮbase領域９５ｃを形成する。次に、Ｎbase領域９５ｃ内部に、Ｐ+領域９５ｄ、９５ｅ、Ｎ+領域９５ｆ、Ｐ-領域９５ｇを形成する。さらに、Ｐ+領域９５ｄ、９５ｅおよびＮ+領域９５ｆに埋め込み配線を形成し、これをドレイン電極９４ｃ、ソース電極９４ｄとする。 In order to form the p-type MOSFET 82, first, the Nbase region 95c is formed inside the Pwell layer. Next, P + regions 95d and 95e, an N + region 95f, and a P− region 95g are formed in the Nbase region 95c. Further, buried wiring is formed in the P + regions 95d and 95e and the N + region 95f, and these are used as the drain electrode 94c and the source electrode 94d.
　さらに、半導体基板９５表面には絶縁層９７を介して、ポリシリコンで形成されたゲート電極９４ｅ、９４ｆが設けられている。なお、ツェナーダイオード８７及び抵抗８８は、ｐ型ＭＯＳＦＥＴ８２を形成する工程で半導体層９０に作り込むことができる。また、抵抗８８を設けることが好ましいが、必須の構成ではない。 Furthermore, gate electrodes 94e and 94f made of polysilicon are provided on the surface of the semiconductor substrate 95 via an insulating layer 97. Note that the Zener diode 87 and the resistor 88 can be formed in the semiconductor layer 90 in the process of forming the p-type MOSFET 82. Moreover, although it is preferable to provide the resistor 88, it is not an essential configuration.
　圧電シート９１は、圧電膜９２を電極フィルム９３とゲート電極９４ｅで挟み込んだ構造をとる。圧電シート９１の材料および形成方法は、電極フィルム９３を一つだけ設けるという点以外は、第１の実施形態と同様である。また、圧電シート９１の端部（外側）の電極の一部には、圧電膜９２およびゲート電極９４ｅを設けずに、電極バンプ９６と、電極バンプ９６を囲む絶縁部９８が設置されている。 The piezoelectric sheet 91 has a structure in which a piezoelectric film 92 is sandwiched between an electrode film 93 and a gate electrode 94e. The material and the forming method of the piezoelectric sheet 91 are the same as those in the first embodiment except that only one electrode film 93 is provided. In addition, an electrode bump 96 and an insulating portion 98 surrounding the electrode bump 96 are provided on a part of the electrode on the end (outside) of the piezoelectric sheet 91 without providing the piezoelectric film 92 and the gate electrode 94e.
　なお、ｐ型ＭＯＳＦＥＴ８２のソース電極９４ｄとｎ型ＭＯＳＦＥＴ８３のゲート電極９４ｅは、図示しないが電気的に接続されている。また、ゲート電極９４ｆは、抵抗８８に接続されている。 Note that the source electrode 94d of the p-type MOSFET 82 and the gate electrode 94e of the n-type MOSFET 83 are electrically connected (not shown). The gate electrode 94f is connected to the resistor 88.
　また、半導体基板９５において、圧電シート９１を形成した面と反対側の面には、保護シート９９を設ける。ただし、本実施形態のスイッチング素子５においては、保護シート９９は、必ずしも必須の構成ではない。 Further, a protective sheet 99 is provided on the surface of the semiconductor substrate 95 opposite to the surface on which the piezoelectric sheet 91 is formed. However, in the switching element 5 of the present embodiment, the protective sheet 99 is not necessarily an essential configuration.
　以上のような構成の第５の実施形態のスイッチング素子においても、第１の実施形態と同様の作用・効果を得ることができる。 Also in the switching element according to the fifth embodiment having the above-described configuration, the same operations and effects as those in the first embodiment can be obtained.
　また、第５の実施形態のスイッチング素子においては、スイッチング素子の中に２つのＭＯＳＦＥＴを形成しているが、同様に３つ以上のＭＯＳＦＥＴを形成することもできる。 In the switching element of the fifth embodiment, two MOSFETs are formed in the switching element, but three or more MOSFETs can be formed in the same manner.
　さらに、第５の実施形態では、ダイオード、抵抗、あるいは、コンデンサを半導体層に作り込むことができる。そのため、ダイオードブリッジ回路の様な整流回路や、半波倍整流回路の様な昇圧回路を組み込むことが可能である。 Furthermore, in the fifth embodiment, a diode, a resistor, or a capacitor can be formed in the semiconductor layer. Therefore, it is possible to incorporate a rectifier circuit such as a diode bridge circuit or a booster circuit such as a half wave double rectifier circuit.
　〔第６の実施形態〕図１２に、本発明の実施形態に係るスイッチング素子を用いた無線センサの回路図を示す。 [Sixth Embodiment] FIG. 12 shows a circuit diagram of a wireless sensor using a switching element according to an embodiment of the present invention.
　図１２に示した第６の実施形態の無線センサは、センサデバイス１０９と、無線モジュール１０８と、マイコン１０６と、電源１０４と、スイッチングトランジスタ１０７と、スイッチング素子１１０とを備えている。抵抗１０３とスイッチング素子１１０は、電源１０４とＧＮＤ１０５の間に直列に接続されている。なお、スイッチングトランジスタ１０７は、スイッチング素子１１０に含まれるスイッチングトランジスタとは異なるものである。 The wireless sensor according to the sixth embodiment shown in FIG. 12 includes a sensor device 109, a wireless module 108, a microcomputer 106, a power source 104, a switching transistor 107, and a switching element 110. The resistor 103 and the switching element 110 are connected in series between the power supply 104 and the GND 105. Note that the switching transistor 107 is different from the switching transistor included in the switching element 110.
　センサデバイス１０９は、環境情報を取得する。無線モジュール１０８は、センサデバイス１０９で取得した情報を無線で送信する。マイコン１０６は、無線モジュール１０８の制御を行う。電源１０４は、マイコン１０６や無線モジュール１０８を起動するための電力を供給する。 The sensor device 109 acquires environmental information. The wireless module 108 wirelessly transmits information acquired by the sensor device 109. The microcomputer 106 controls the wireless module 108. The power source 104 supplies power for starting the microcomputer 106 and the wireless module 108.
　スイッチング素子１１０の電源１０４側の電極とマイコン１０６が接続されている。電源１０４と、無線モジュール１０８およびセンサデバイス１０９の間に、電力供給を制御するスイッチングトランジスタ１０７が設けられている。スイッチング素子１１０からの出力により、マイコン１０６が起動される。 The microcomputer 106 is connected to the electrode on the power supply 104 side of the switching element 110. A switching transistor 107 that controls power supply is provided between the power source 104 and the wireless module 108 and the sensor device 109. The microcomputer 106 is activated by the output from the switching element 110.
　マイコン１０６が起動されると、マイコン１０６によりスイッチングトランジスタ１０７が導通され、無線モジュール１０８およびセンサデバイス１０９に電力が供給される。なお、マイコン１０６の動作は、第１の実施形態と同様である。 When the microcomputer 106 is activated, the switching transistor 107 is turned on by the microcomputer 106 and power is supplied to the wireless module 108 and the sensor device 109. The operation of the microcomputer 106 is the same as that in the first embodiment.
　その際、無線モジュール１０８は、センサデバイス１０９が取得した環境情報を、無線センサネットワークの管理装置などに送信する。 At that time, the wireless module 108 transmits the environment information acquired by the sensor device 109 to a management device of the wireless sensor network.
　以上のように、本実施形態の無線センサデバイスを用いれば、圧電素子とスイッチングトランジスタを一つのデバイスとして製造することができるため、誤動作のない信頼性の高いトリガ回路が得られる。 As described above, if the wireless sensor device of this embodiment is used, the piezoelectric element and the switching transistor can be manufactured as one device, so that a highly reliable trigger circuit without malfunction can be obtained.
　なお、第６の実施形態において、本発明のスイッチング素子を用いた無線センサについて記載したが、本発明のスイッチング素子の用途は無線センサに限定されるわけではなく、種々の環境センサなどに適応可能である。 In the sixth embodiment, the wireless sensor using the switching element of the present invention has been described. However, the application of the switching element of the present invention is not limited to the wireless sensor, and can be applied to various environmental sensors. It is.
　以上のように、本発明の実施形態にかかるスイッチング素子を用いれば、圧電素子と、その圧電素子の出力電圧により導通するスイッチングトランジスタを一つのデバイスで実現することができる。そのため、外来ノイズの影響を抑制でき、誤動作のない信頼性の高いトリガ回路を実現することができる。 As described above, if the switching element according to the embodiment of the present invention is used, the piezoelectric element and the switching transistor that is turned on by the output voltage of the piezoelectric element can be realized by one device. Therefore, the influence of external noise can be suppressed, and a highly reliable trigger circuit without malfunction can be realized.
　以上、実施形態及び実施例を参照して本願発明を説明してきたが、本願発明は上記実施形態及び実施例に限定されるものではない。本願発明の構成や詳細には、本願発明のスコープ内で当業者が理解し得る様々な変更をすることができる。 Although the present invention has been described above with reference to the embodiments and examples, the present invention is not limited to the above embodiments and examples. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
　この出願は、２０１２年３月２１日に出願された日本出願特願２０１２－６３５８３を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2012-63583 filed on March 21, 2012, the entire disclosure of which is incorporated herein.
　本発明は、スイッチングトランジスタのゲート電極と圧電素子の電極を一体化したスイッチング素子に関する。特に、圧電素子によって発生した起電力を利用して動作するスイッチング素子およびそれを適用したデバイスに関する。本発明のスイッチング素子は、例えば、無線機能を有する環境センサのトリガ回路などとして用いることができる。 The present invention relates to a switching element in which a gate electrode of a switching transistor and an electrode of a piezoelectric element are integrated. In particular, the present invention relates to a switching element that operates using an electromotive force generated by a piezoelectric element and a device to which the switching element is applied. The switching element of the present invention can be used, for example, as a trigger circuit for an environmental sensor having a wireless function.
　１　　スイッチング素子
　１０　　半導体層
　１１　　圧電シート
　１２　　圧電膜
　１３ａ、１３ｂ　　電極フィルム
　１４ａ　　ソース電極
　１４ｂ　　ドレイン電極
　１５　　半導体基板
　１５ａ　　Ｎ+領域
　１５ｂ　　チャネル層
　１６　　電極バンプ
　１７　　絶縁膜
　１８　　絶縁部
　１９　　保護フィルム
　２０　　スイッチングデバイス
　２１　　筐体
　２２　　固定部
　２３　　支持板
　２４　　錘
　２５　　配線
　３１　　圧電素子
　３２　　ｎ型ＭＯＳＦＥＴ
　３３　　抵抗
　３４　　電源
　３５　　ＧＮＤ
　３６　　マイコン
　８０　　スイッチング素子
　８１　　圧電素子
　８２　　ｐ型ＭＯＳＦＥＴ
　８３　　ｎ型ＭＯＳＦＥＴ
　８７　　ツェナーダイオード
　９４ｃ　　ドレイン電極
　９４ｄ　　ソース電極
　９４ｅ、９４ｆ　　ゲート電極
　９５ａ、９５ｆ　　Ｎ+領域
　９５ｂ　　チャネル層
　９５ｃ　　Ｎbase領域
　９５ｄ、９５ｅ　　Ｐ+領域
　９５ｇ　　Ｐ-領域
　１０７　　スイッチングトランジスタ
　１０８　　無線モジュール
　１０９　　センサデバイス
　１１０　　スイッチング素子 DESCRIPTION OF SYMBOLS 1 Switching element 10 Semiconductor layer 11 Piezoelectric sheet 12 Piezoelectric film 13a, 13b Electrode film 14a Source electrode 14b Drain electrode 15 Semiconductor substrate 15a N + area | region 15b Channel layer 16 Electrode bump 17 Insulating film 18 Insulating part 19 Protective film 20 Switching device 21 Housing Body 22 Fixed portion 23 Support plate 24 Weight 25 Wiring 31 Piezoelectric element 32 n-type MOSFET
33 Resistor 34 Power supply 35 GND
36 Microcomputer 80 Switching element 81 Piezoelectric element 82 p-type MOSFET
83 n-type MOSFET
87 Zener diode 94c Drain electrode 94d Source electrode 94e, 94f Gate electrode 95a, 95f N + region 95b Channel layer 95c Nbase region 95d, 95e P + region 95g P- region 107 Switching transistor 108 Wireless module 109 Sensor device 110 Switching element

Claims (10)

  1. 　圧電素子の電極がスイッチングトランジスタのいずれかの電極を兼ねることを特徴とするスイッチング素子。 A switching element characterized in that the electrode of the piezoelectric element also serves as any electrode of a switching transistor.
  2. 　基板と、
    　前記基板の一方の面に設けられたソース領域およびドレイン領域と、
    　前記基板上に配置された絶縁膜と、
    　前記絶縁膜上に配置された第１の電極層と、
    　前記第１の電極層上に配置された圧電膜と、
    　前記圧電膜上に配置された第２の電極層と、を備えることを特徴とする請求項１に記載のスイッチング素子。     A substrate,
    A source region and a drain region provided on one surface of the substrate;
    An insulating film disposed on the substrate;
    A first electrode layer disposed on the insulating film;
    A piezoelectric film disposed on the first electrode layer;
    The switching element according to claim 1, further comprising: a second electrode layer disposed on the piezoelectric film.
  3. 　前記第２の電極層と、前記ソース電極と、が電極端に接続されていることを特徴とする請求項２に記載のスイッチング素子。 The switching element according to claim 2, wherein the second electrode layer and the source electrode are connected to an electrode end.
  4. 　前記ソース領域と、前記ドレイン領域と、前記絶縁膜と、前記第１の電極層と、で形成されるトランジスタが複数配置されていることを特徴とする請求項３に記載のスイッチング素子。 4. The switching element according to claim 3, wherein a plurality of transistors formed of the source region, the drain region, the insulating film, and the first electrode layer are arranged.
  5. 　複数の前記トランジスタが並列に接続されていることを特徴とする請求項４に記載のスイッチング素子。 The switching element according to claim 4, wherein a plurality of the transistors are connected in parallel.
  6. 　前記圧電膜は、バリウム、チタン、鉛、亜鉛、ジルコニウムおよびニオブからなる群より選ばれた１種以上の金属元素を有する酸化物を含む圧電セラミックスであることを特徴とする請求項２乃至５のいずれか一項に記載のスイッチング素子。 6. The piezoelectric ceramic according to claim 2, wherein the piezoelectric film is a piezoelectric ceramic containing an oxide having one or more metal elements selected from the group consisting of barium, titanium, lead, zinc, zirconium and niobium. The switching element as described in any one.
  7. 　前記圧電膜は、少なくともポリフッ化ビニリデンを含む圧電高分子材料であることを特徴とする請求項２乃至５のいずれか一項に記載のスイッチング素子。 The switching element according to any one of claims 2 to 5, wherein the piezoelectric film is a piezoelectric polymer material containing at least polyvinylidene fluoride.
  8. 　請求項５に記載のスイッチング素子において、
    　前記基板には、ツェナーダイオードおよび電界効果トランジスタが設けられ、
    　前記ツェナーダイオードおよび前記電界効果トランジスタの一方の端子は前記第１の電極層と接続され、他方の端子は電源端に接続されることを特徴とするスイッチング素子。     The switching element according to claim 5, wherein
    The substrate is provided with a Zener diode and a field effect transistor,
    One terminal of the Zener diode and the field effect transistor is connected to the first electrode layer, and the other terminal is connected to a power supply terminal.
  9. 　請求項１乃至８のいずれか一項に記載のスイッチング素子と、
    　情報を取得するセンサデバイスと、
    　前記センサデバイスで取得した情報を無線で送信する無線モジュールと、
    　前記センサデバイスおよび前記無線モジュールを制御するマイコンと、
    　前記センサデバイス、前記無線モジュールおよび前記マイコンを起動するための電源と、
    　前記電源から前記無線モジュールおよび前記センサデバイスへの電力供給を制御するスイッチングトランジスタと、を備え、
    　前記スイッチング素子からの出力により起動されたマイコンにより前記スイッチングトランジスタが導通され、前記無線モジュールおよび前記センサデバイスに電力供給されることを特徴とする無線センサデバイス。     The switching element according to any one of claims 1 to 8,
    A sensor device for obtaining information;
    A wireless module that wirelessly transmits information acquired by the sensor device;
    A microcomputer for controlling the sensor device and the wireless module;
    A power source for activating the sensor device, the wireless module and the microcomputer;
    A switching transistor for controlling power supply from the power source to the wireless module and the sensor device,
    A wireless sensor device, wherein the switching transistor is turned on by a microcomputer activated by an output from the switching element, and power is supplied to the wireless module and the sensor device.
  10. 　基板と、
    　前記基板上に配置された拡散領域と、
    　前記拡散領域上に配置された絶縁膜と、
    　前記絶縁膜上に配置された圧電素子と、を備えることを特徴とするスイッチング素子。     A substrate,
    A diffusion region disposed on the substrate;
    An insulating film disposed on the diffusion region;
    And a piezoelectric element disposed on the insulating film.
PCT/JP2013/001692 2012-03-21 2013-03-14 Switching element and device using same WO2013140759A1 (en)

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CN104578362A (en) * 2015-01-21 2015-04-29 广东顺德中山大学卡内基梅隆大学国际联合研究院 Vibration energy collection device
EP3627704A1 (en) * 2018-09-20 2020-03-25 Boréas Technologies Inc. Zero-power wake-up sensing circuit in piezoelectric haptic feedback

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JPH09139472A (en) * 1995-11-10 1997-05-27 Nec Corp Ferroelectric memory
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JP2006140271A (en) * 2004-11-11 2006-06-01 Toshiba Corp Semiconductor apparatus
JP2007310177A (en) * 2006-05-18 2007-11-29 Fdk Corp Spatial light modulator

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104578362A (en) * 2015-01-21 2015-04-29 广东顺德中山大学卡内基梅隆大学国际联合研究院 Vibration energy collection device
EP3627704A1 (en) * 2018-09-20 2020-03-25 Boréas Technologies Inc. Zero-power wake-up sensing circuit in piezoelectric haptic feedback
CN110928405A (en) * 2018-09-20 2020-03-27 波瑞阿斯技术公司 Zero power wake-up sensing circuit in piezoelectric haptic feedback
KR20200033750A (en) * 2018-09-20 2020-03-30 보레어스 테크놀로지스 인크. Zero-Power Wake-up Sensing Circuit in Piezoelectric Haptic Feedback
US11302859B2 (en) 2018-09-20 2022-04-12 Boréas Technologies Inc. Zero-power wake-up sensing circuit in piezoelectric haptic feedback
KR102511129B1 (en) 2018-09-20 2023-03-15 보레어스 테크놀로지스 인크. Zero-Power Wake-up Sensing Circuit in Piezoelectric Haptic Feedback
JP7467053B2 (en) 2018-09-20 2024-04-15 ボレアス テクノロジーズ インコーポレイテッド A Zero-Power Wake-Up Detection Circuit for Piezoelectric Haptic Feedback

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