WO2013129471A1 - Substrate joining method and semiconductor device - Google Patents

Substrate joining method and semiconductor device Download PDF

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Publication number
WO2013129471A1
WO2013129471A1 PCT/JP2013/055119 JP2013055119W WO2013129471A1 WO 2013129471 A1 WO2013129471 A1 WO 2013129471A1 JP 2013055119 W JP2013055119 W JP 2013055119W WO 2013129471 A1 WO2013129471 A1 WO 2013129471A1
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WO
WIPO (PCT)
Prior art keywords
region
wafer
substrate
semiconductor device
bonded
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PCT/JP2013/055119
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French (fr)
Japanese (ja)
Inventor
春生 岩津
重徳 北原
松本　俊行
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東京エレクトロン株式会社
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Publication of WO2013129471A1 publication Critical patent/WO2013129471A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a substrate bonding method for bonding a first substrate on which a plurality of semiconductor devices are formed and a second substrate on which a plurality of semiconductor devices are formed, and a substrate on which a plurality of semiconductor devices are formed.
  • the present invention relates to a semiconductor device bonded to a plurality of layers.
  • Patent Document 1 proposes a joining method for deformed base material. Specifically, an arbitrary region of the first base material is selectively hydrophilized, and the bonding surface of the second base material is hydrophilized, and then the first base is passed through the liquid having a hydroxyl group. The arbitrary area
  • the present invention has been made in view of such a point, and an object thereof is to easily and appropriately join substrates on which a plurality of semiconductor devices are formed.
  • the present invention provides a method for bonding substrates, in which a first substrate on which a plurality of semiconductor devices are formed and a second substrate on which a plurality of semiconductor devices are formed are bonded.
  • the semiconductor device region of the first substrate is formed higher than the region serving as the scribe line, and in the second step, the bonded region of the second substrate is hydrophilized. ing.
  • the processing liquid flows out from between the semiconductor device region and the bonded region due to a so-called pinning effect. There is no.
  • a restoring force that moves at least the first substrate or the second substrate acts by the surface tension of the processing liquid. Then, the position adjustment of the first substrate and the second substrate is performed with high positional accuracy so that the semiconductor device region and the bonded region correspond exactly.
  • the first substrate and the second substrate can be appropriately bonded thereafter.
  • the first substrate and the second substrate can be appropriately joined only by forming the semiconductor device region higher than the region serving as the scribe line.
  • a semiconductor device in which a substrate on which a plurality of semiconductor devices are formed is bonded to a plurality of layers, and a scribe line between the semiconductor devices on a surface on which the plurality of semiconductor devices are formed.
  • the region corresponding to the semiconductor device region is hydrophilized on the first substrate having the semiconductor device region formed higher than the region to be formed, and the surface bonded to the first substrate.
  • a processing liquid is supplied between the semiconductor device region and the bonded region, and the first substrate and the second substrate are bonded to each other. .
  • substrates on which a plurality of semiconductor devices are formed can be easily and appropriately joined.
  • FIG. 1 shows a main processing flow of the wafer bonding method according to the present embodiment.
  • a first wafer as a first substrate and a second wafer as a second substrate are bonded. More specifically, the first wafer and the second wafer are bonded together in a state where the first wafer is disposed relatively downward and the second wafer is disposed relatively upward.
  • the dimensions of each component do not necessarily correspond to the actual dimensions in order to prioritize easy understanding of the technology.
  • a device layer 12 is formed on the bulk layer 11 of the first wafer 10.
  • the surface on the device layer 12 side is referred to as a front surface 11a
  • the surface on the opposite side to the device layer 12 is referred to as a back surface 11b.
  • a surface opposite to the bulk layer 11 is referred to as a front surface 12a
  • a surface on the bulk layer 11 side is referred to as a back surface 12b.
  • a device 13 (hereinafter, also referred to as “device region 13”) as a semiconductor device is formed on the device layer 12 of the first wafer 10 (step S1 in FIG. 1). As shown in FIG. 3, a plurality of devices 13 are uniformly formed on the first wafer 10 within the wafer surface.
  • the wafer stacking method in which the first wafer 10 and a later-described second wafer 20 are stacked at the wafer level before the first wafer 10 is cut into semiconductor chips including the individual devices 13. Is used.
  • a plurality of circuits 14 are formed in the device 13 as shown in FIG.
  • a plurality of transistors and memory cells (not shown) are arranged.
  • wiring for wiring the circuit 14 and a through electrode 40 described later various circuits, electrodes, and the like are also formed.
  • the plurality of circuits 14 and the like are formed at the same time in the series of device layer 12 forming steps.
  • a scribe line 15 (hereinafter sometimes referred to as “scribe line region 15”) is formed between the plurality of devices 13.
  • the device region 13 is formed higher than the scribe line region 15. Note that the scribe line is a line when the wafer is cut and divided into a plurality of semiconductor chips.
  • connection region 16 that connects the adjacent device regions 13 is formed (step S2 in FIG. 1).
  • the device region 13 has a quadrangular shape in plan view, and the plurality of device regions 13 are arranged in a lattice shape. Therefore, four connection regions 16 are connected to the inner device region 13 of the first wafer 10, and two connection regions 16 are connected to the outer device region 13.
  • the connection region 16 has the same height as the device region 13 as shown in FIG.
  • the scribe line region 15 where the connection region 16 is not formed nothing is formed as shown in FIG. 4, or an inspection element having a height lower than the height of the device region 13 as shown in FIG. The element 17 is formed.
  • the scribe line region 15 in which the connection region 16 is not formed is lower than the device region 13.
  • the formation of the device region 13 and the connection region 16 has been described in order, but the device region 13 and the connection region 16 are actually formed at the same time. Since the connection region 16 is formed in the scribe line region 15, the connection region 16 does not adversely affect the device 13. In addition, since the scribe line area 15 is an area where the device 13 is not originally formed, the connection area 16 does not adversely affect the yield of the device 13 from one wafer 10.
  • ammonia (ammonia water obtained by diluting ammonia to a predetermined concentration) is supplied onto the device region 13 and the connection region 16.
  • This ammonia activates the surfaces of the device region 13 and the connection region 16, in other words, the surface of the first wafer 10 (step S3 in FIG. 1).
  • the surface of the device region 13 and the connection region 16 is broken, and then the surfaces are activated so as to be easily hydrophilized. If organic residues remain on the bonding surface, it may cause later bubbles. Therefore, before activation with ammonia, SC1 (Standard Clean 1) is sprayed onto the surface of the first wafer 10 with a two-fluid nozzle. Therefore, it is better to perform pre-cleaning.
  • the surfaces of the device region 13 and the connection region 16 are washed with pure water, and then the pure water is dried.
  • the first wafer 10 may be dried by heating or the like.
  • the surfaces of the device region 13 and the connection region 16 are activated by ammonia, but the liquid for activating them is not limited to this, and various liquids such as pure water are used. Can do.
  • An aqueous alkali solution such as potassium hydroxide can also be used.
  • next process is performed on the second wafer 20 in parallel with or before and after the processes S1 to S3.
  • the device layer 22 is formed on the bulk layer 21 of the second wafer 20.
  • the surface on the device layer 22 side is referred to as a front surface 21a
  • the surface on the opposite side to the device layer 22 is referred to as a back surface 21b.
  • the surface opposite to the bulk layer 21 is referred to as a front surface 22a
  • the surface on the bulk layer 21 side is referred to as a back surface 22b.
  • a device 23 (hereinafter also referred to as “device region 23”) is formed on the device layer 22 of the second wafer 20 (step S4 in FIG. 1). Similar to the device 13 of the first wafer 10, a plurality of devices 23 are uniformly formed in the wafer surface on the second wafer 20.
  • a plurality of circuits 24 are formed in the device 13 as shown in FIG.
  • a plurality of transistors and memory cells (not shown) are arranged.
  • wiring for wiring the circuit 24 and a through electrode 29 described later, various circuits, electrodes, and the like are also formed.
  • the plurality of circuits 24 and the like are simultaneously formed in a series of device layer 22 formation steps.
  • a scribe line 25 (hereinafter sometimes referred to as “scribe line area 25”) is formed between the plurality of devices 23.
  • the connection region 16 is formed in the scribe line region 15 in the first wafer 10
  • a similar connection region may or may not be formed in the second wafer 20.
  • a connection region 26 is formed on the second wafer 20.
  • a support wafer 27 as a support substrate is disposed on the surface 22a of the device layer 22 (step S5 in FIG. 1).
  • the support wafer 27 is bonded to the device layer 22 by, for example, a peelable adhesive.
  • a silicon wafer or a glass substrate is used as the support substrate.
  • the back surface 21b of the bulk layer 21 is polished to thin the second wafer 20 (step S6 in FIG. 1).
  • the front and back surfaces of the second wafer 20 are reversed, the device layer 22 is disposed below the bulk layer 21, and then the through hole 28 that penetrates the device layer 22 and the bulk layer 21 in the thickness direction. Is formed (step S7 in FIG. 1).
  • the through hole 28 is formed so as to be connected to a wiring (not shown) that is actually connected to the circuit 24 so as to be connected to the circuit 24.
  • a plurality of through holes 28 are formed in the second wafer 20.
  • the plurality of through holes 28 are simultaneously formed by, for example, a photolithography process and an etching process.
  • the through hole 28 is formed by etching the bulk layer 21 and the device layer 22 using the resist pattern as a mask. After the through hole 28 is formed, the resist pattern is removed by ashing, for example.
  • each through-hole 28 is filled with a conductive material to form a through-electrode (TSV: Through Silicon Via) 29 as shown in FIG. 10 (step S8 in FIG. 1).
  • TSV Through Silicon Via
  • a barrier film, an insulating film, and the like are formed on the inner wall of each through-hole 28 before the conductive material is filled, but this is omitted for the sake of simplicity.
  • an insulating film 30 is formed on the back surface 21b of the bulk layer 21 (step S9 in FIG. 1).
  • the insulating film 30 is formed by a method such as CVD (Chemical Vapor Deposition) by appropriately selecting a material from, for example, a silicon oxide film.
  • the insulating film 30 is patterned into a predetermined pattern (step S10 in FIG. 1).
  • the insulating film 30 at positions corresponding to the device region 13 and the connection region 16 of the first wafer 10 is left, and the scribe line region 15 where the connection region 16 is not formed is left.
  • the insulating film 30 at the corresponding position is removed.
  • the insulating film 30 patterned in this way constitutes a bonded region 31 that is bonded to the device region 13 and the connection region 16.
  • the bonded region 31 is relatively hydrophilized and the region 32 other than the bonded region 31 is relatively hydrophobized on the back surface of the second wafer 20.
  • the hydrophilicity of the bonded region 31 is not limited to the patterning of the insulating film 30 as described above, and the surface of the bonded region 31 may be modified to perform the hydrophilic treatment.
  • ammonia (ammonia water in which ammonia is diluted to a predetermined concentration) is supplied onto the bonded region 31.
  • the surface of the bonded region 31, in other words, the back surface of the second wafer 20 is activated (step S11 in FIG. 1).
  • the surface of the bonded region 31 is broken so that the surface of the bonded region 31 is activated, and then the surface is activated so as to be easily hydrophilized. Note that if organic residue or the like remains on the bonding surface, it may cause later bubbles. Therefore, before activation with ammonia, SC1 (Standard Clean 1) is sprayed to the back surface of the second wafer 20 with a two-fluid nozzle.
  • the surface of the bonded region 31 is washed with pure water, and then the pure water is dried.
  • the second wafer 20 may be dried by heating or the like.
  • the surface of the bonded region 31 is activated by ammonia.
  • the liquid for activating this is not limited to this, and various liquids can be used.
  • An aqueous alkali solution such as potassium hydroxide can also be used.
  • pure water P as a processing liquid is supplied onto the device region 13 and the connection region 16 of the first wafer 10 (step S12 in FIG. 1).
  • the device region 13 and the connection region 16 are formed higher than the scribe line region 15 in which the connection region 16 is not formed.
  • the pure water P has a large predetermined contact angle due to the surface tension at the edges of the device region 13 and the connection region 16.
  • the pure water P remains on the device region 13 and the connection region 16.
  • the phenomenon of suppressing the spread of pure water P in this way is known as a so-called pinning effect.
  • the pure water P diffuses over the device region 13 and the connection region 16.
  • pure water P is used as the treatment liquid.
  • various liquids can be used as long as the liquid has a hydroxyl group.
  • the second wafer 20 is disposed on the device layer 12 side of the first wafer 10.
  • the second wafer 20 is arranged such that the bulk layer 21 faces the device layer 12 of the first wafer 10.
  • the bonded region 31 of the second wafer 20 is hydrophilized, the pure water P does not flow out of the bonded region 31, that is, the device region 13 and the connection region 16 of the first wafer 10. .
  • the positions of the bonded region 31 of the bulk layer 21 and the positions of the device region 13 and the connection region 16 of the device layer 12 do not need to correspond exactly. As shown in FIG. 16, even when these positions are slightly deviated, the position adjustment of the first wafer 10 and the second wafer 20 is performed in step S13 described later.
  • a restoring force moves the second wafer 20 as shown in FIG. An arrow
  • the second wafer 20 moves so that they are opposed to each other.
  • the position adjustment of the wafer 10 and the second wafer 20 is performed with high accuracy (submicron order) (step S13 in FIG. 1).
  • the arrangement of the second wafer 20 and the movement of the second wafer 20 have been described in order, but actually these phenomena proceed almost simultaneously.
  • the pure water P filled between the first wafer 10 and the second wafer 20 causes hydroxyl groups to adhere to the device region 13 and the connection region 16 of the first wafer 10 so that the device region 13 and the connection are connected. While the surface of the region 16 is hydrophilized, a hydroxyl group adheres to the bonded region 31 of the second wafer 20 and the surface of the bonded region 31 is hydrophilized. Since the surfaces of the device region 13 and the connection region 16 and the surface of the bonded region 31 are activated in steps S3 and S11, respectively, first, the surfaces of the device region 13 and the connection region 16 and the bonded region 31 are first activated. Van der Waals force is generated between the two surfaces and the surfaces are joined to each other.
  • the surfaces of the device region 13 and the connection region 16 and the surface of the bonded region 31 are made hydrophilic as described above, the hydroxyl group between the surface of the device region 13 and the connection region 16 and the surface of the bonded region 31 is obtained. Hydrogen bond, and the surfaces are bonded more firmly (step S14 in FIG. 1).
  • the pure water P between the first wafer 10 and the second wafer 20 is removed, and the first wafer 10 and the second wafer 20 are bonded.
  • the second wafer 20 is dried.
  • the back surface 11b of the bulk layer 11 in the first wafer 10 is polished to thin the first wafer 10 (step S15 in FIG. 1).
  • the front and back surfaces of the first wafer 10 are reversed, and the device layer 12 is disposed below the bulk layer 11.
  • a through hole (not shown) is formed in the first wafer 10, and then a through electrode 40 is formed (step S16 in FIG. 1).
  • the through electrode 40 is formed so as to penetrate the bulk layer 11 and device layer 12 of the first wafer 10 and the insulating film 30 of the second wafer 20 in the thickness direction.
  • the through electrode 40 is connected to the circuit 14 and to the through electrode 29 of the second wafer 20.
  • the method of forming these through-holes and the through-electrodes 40 is the same as the method in steps S8 and S9 described above, the description thereof is omitted. In practice, bumps and the like are formed between the through electrode 40 and the through electrode 29, but are omitted for the sake of simplicity.
  • the through electrode 40 of the first wafer 10 is formed before bonding to the second wafer 20
  • the through electrode 40 of the first wafer 10 and the through electrode 29 of the second wafer 20 are formed by the insulating film 30. Not electrically conductive. For this reason, the through electrode 40 of the first wafer 10 is formed after bonding to the second wafer 20 as in the present embodiment.
  • an insulating film 30 is formed on the back surface 11b of the bulk layer 11 (step S17 in FIG. 1), and the insulating film 30 is further patterned into a predetermined pattern to form a bonded region 31. (Step S18 in FIG. 1). Thereafter, the surface of the bonded region 31, in other words, the back surface of the first wafer 10 is activated with ammonia (ammonia water diluted with ammonia to a predetermined concentration) (step S19 in FIG. 1).
  • ammonia ammonia water diluted with ammonia to a predetermined concentration
  • the same processing as the back surface of the second wafer 20 (the back surface 21b of the bulk layer 21) is performed on the back surface of the first wafer 10 (the back surface 11b of the bulk layer 11).
  • the first wafer 10 is caused to function in the same manner as the second wafer 20, and the first wafer 10 (hereinafter sometimes referred to as the “old first wafer 10”) and the new first wafer 10.
  • the wafer 10 (hereinafter may be referred to as “the new first wafer 10”) is bonded.
  • the new first wafer 10 is processed in the same manner as the above-described steps S1 to S3.
  • Step S20 the same processing as in the above-described steps S12 to S14 is performed to join the old first wafer 10 and the new first wafer 10 together.
  • a plurality of first wafers 10 are stacked, and the support wafer 27 is further peeled off to manufacture a semiconductor device 100 in which the wafers 10 and 20 are stacked in a plurality of layers (FIG. 1).
  • Step S20 the case where the wafers 10 and 20 are stacked in four layers will be described.
  • the number of stacked wafers 10 and 20 is not limited to this and can be arbitrarily set.
  • the device region 13 and the connection region 16 of the first wafer 10 are formed higher than the scribe line region 15 where the connection region 16 is not formed, and the insulation of the second wafer 20 is performed.
  • the film 30 is patterned to make the bonded region 31 hydrophilic. Then, even if pure water P is supplied between the device region 13 and the connection region 16 and the bonded region 31 after that, the pure water P is converted into the device region 13 and the connection region 16 and the bonded region 31 by a so-called pinning effect. Will not flow out of between. And the restoring force which moves the 2nd wafer 20 acts with the surface tension of this pure water P.
  • the position adjustment of the first wafer 10 and the second wafer 20 is performed with high positional accuracy so that the device region 13 and the connection region 16 and the bonded region 31 correspond accurately. If it does so, the 1st wafer 10 and the 2nd wafer 20 can be joined appropriately after that. Moreover, in the first wafer 10, the first wafer 10 and the second wafer 20 can be appropriately bonded only by forming the device region 13 and the connection region 16 higher than the scribe line region 15. The bonding process between the first wafer 10 and the second wafer 20 can be simplified, and the processing cost of the bonding process can be reduced.
  • the device region 13 and the connection region 16 are formed in the device layer 12 of one wafer 10. For example, even when the connection region 16 is not formed, the device region 13 is more than the scribe line region. If it is formed high, the above-described effects can be enjoyed.
  • region 16 which connects the adjacent device area
  • the surfaces of the device region 13 and the connection region 16 of the first wafer 10 are activated and the surface of the bonded region 31 of the second wafer 20 is activated.
  • the wafer 20 can be bonded more firmly.
  • the through-hole electrode 40 is formed when the through-hole electrode 40 is formed on the first wafer 10 thereafter.
  • the electrode 40 can be formed at an appropriate position. Then, the semiconductor device 100 can be manufactured appropriately.
  • the devices 13 and 23 can be prevented from being damaged, and the reliability of the devices 13 and 23 can be improved.
  • a plurality of air holes 110 may be formed in a region other than the bonded region 31 of the second wafer 20 as shown in FIG.
  • the air holes 110 are formed in each space closed in the bonded region 31.
  • the support wafer 27 provided on the second wafer 20 has an air hole 111 that penetrates the support wafer 27 in the thickness direction and communicates with the space closed by the bonded region 31. Is formed.
  • the plurality of air holes 110 are formed so as to penetrate in the thickness direction of the second wafer 20 as shown in FIG.
  • the plurality of air holes 110 are formed at the same time as the through holes 28 in the above-described step S7, that is, formed simultaneously by the photolithography process and the etching process.
  • the other processes for the second wafer 20 are the same as the above-described processes S4 to S6 and S8 to S11, and thus description thereof is omitted.
  • step S12 after supplying pure water P to the first wafer 10 in step S12, when the second wafer 20 is disposed on the device layer 12 side of the first wafer 10, as shown in FIG. 13 and the space closed by the joined region 31 are exhausted to the outside through the air holes 110 and 111.
  • the atmospheric pressure in the space closed by the device region 13 and the bonded region 31 can be maintained appropriately in the same manner as the external atmospheric pressure, the position adjustment of the first wafer 10 and the second wafer 20 in the subsequent step S13 is performed.
  • the first wafer 10 and the second wafer 20 can be appropriately bonded in step S14.
  • the pure water P when pure water P is filled between the first wafer 10 and the second wafer 20, the pure water P may vaporize. In such a case, latent heat is generated as the pure water P is vaporized, and the air in the space closed by the device region 13 and the bonded region 31 is cooled. If it does so, condensation will generate
  • in the present embodiment since air is exhausted from the air holes 110 and 111, this condensation can be prevented. Furthermore, the periphery of the first wafer 10 and the second wafer 20 may be depressurized in order to promote exhaust from the air holes 110 and 111.
  • the first wafer 10 and the second wafer 20 are placed in a state where the first wafer 10 is disposed relatively downward and the second wafer 20 is disposed relatively upward.
  • the arrangement of the first wafer 10 and the second wafer 20 may be reversed. That is, even when the first wafer 10 and the second wafer 20 are bonded in a state where the first wafer 10 is disposed relatively upward and the second wafer 20 is disposed relatively to the other. Good.
  • step S13 pure water P is supplied onto the bonded region 31 of the second wafer 20 as shown in FIG.
  • step S14 the restoring force (FIG. 26) moves the first wafer 10 as shown in FIG. 26 by the surface tension of the pure water P filled between the first wafer 10 and the second wafer 20. ) Acts on the first wafer 10.
  • step S14 the first wafer 10 and the second wafer 20 are appropriately bonded.
  • the same effects as those of the above-described embodiment can be obtained, and the first wafer 10 and the second wafer 20 can be simply and appropriately bonded.
  • air holes 110 and 111 may be formed in the second wafer 20 and the support wafer 27, respectively, as shown in FIG.
  • the support wafer 27 of the above embodiment has an elevating mechanism 120 as a position adjustment mechanism for adjusting the vertical relative positions of the first wafer 10 and the second wafer 20 as shown in FIG. It may be.
  • a plurality of lifting mechanisms 120 are provided on the outer peripheral portions of the first wafer 10 and the second wafer 20.
  • the elevating mechanism 120 extends vertically downward from the surface of the support wafer 27, bends further, and extends in the horizontal direction so as to be positioned between the first wafer 10 and the second wafer 20.
  • a telescopic lifting pin is used for a portion extending in the vertical direction of the lifting mechanism 120.
  • the lifting mechanism 120 supports the space between the first wafer 10 and the second wafer 20. And the space
  • the elevating mechanism 120 starts to be reduced.
  • the second wafer 20 is supported only by the pure water P supplied onto the first wafer 10 in step S12, and the first wafer 10 in step S13. Then, the position adjustment of the second wafer 20 proceeds. Thereafter, in step S14, the first wafer 10 and the second wafer 20 are bonded.
  • the position adjustment of the first wafer 10 and the second wafer 20 can be performed.
  • a joining process can be performed appropriately.
  • the distance between the first wafer 10 and the second wafer 20 is very small and the weight of the second wafer 20 and the support wafer 27 is large, the distance may not be properly maintained with pure water P alone. .
  • the present embodiment in which the distance between the first wafer 10 and the second wafer 20 can be physically maintained by the elevating mechanism 120 is particularly useful.
  • the structure of the raising / lowering mechanism 120 is not limited to the said embodiment, A various structure can be taken.
  • the lifting mechanism 120 may be configured to extend in the vertical direction from the surface of the support wafer 27 at the outer peripheral portions of the first wafer 10 and the second wafer 20.
  • a telescopic elevating pin is used for the elevating mechanism 120.
  • the lifting mechanism 120 is supported at its end by a mounting table 121 on which the first wafer 10 is mounted.
  • the distance between the first wafer 10 and the second wafer 20 can be controlled to an appropriate distance by the elevating mechanism 120 as in the above embodiment, and the position of the first wafer 10 and the second wafer 20 can be controlled. Adjustment and joining processing can be performed appropriately.

Abstract

This substrate joining method, which joins a first substrate to which a plurality of semiconductor devices have been formed and a second substrate to which a plurality of semiconductor devices have been formed, has: a first step for, at the surface to which the plurality of semiconductor devices of the first substrate are formed, forming a semiconductor device region at which the plurality of semiconductor devices are formed and that is higher than the region that is to be scribe lines between each semiconductor device; a second step for, at the surface of the second semiconductor device to join to the first semiconductor device, hydrophilicizing the region corresponding to the semiconductor device region to form a region to join; and a third step for supplying processing liquid between the semiconductor device region and the region to join, and joining the first substrate and the second substrate.

Description

基板の接合方法及び半導体装置Substrate bonding method and semiconductor device
　本発明は、複数の半導体デバイスが形成された第１の基板と、複数の半導体デバイスが形成された第２の基板とを接合する基板の接合方法、及び複数の半導体デバイスが形成された基板が複数層に接合された半導体装置に関する。
　本願は、２０１２年３月１日に日本に出願された特願２０１２－０４５０１７号に基づき優先権を主張し、その内容をここに援用する。 The present invention relates to a substrate bonding method for bonding a first substrate on which a plurality of semiconductor devices are formed and a second substrate on which a plurality of semiconductor devices are formed, and a substrate on which a plurality of semiconductor devices are formed. The present invention relates to a semiconductor device bonded to a plurality of layers.
This application claims priority based on Japanese Patent Application No. 2012-045017 for which it applied to Japan on March 1, 2012, and uses the content here.
　近年、半導体デバイスの高集積化が進んでいる。高集積化した複数の半導体デバイスを水平面内で配置し、これら半導体デバイスを配線で接続して製品化する場合、配線長が増大し、それにより配線の抵抗が大きくなること、また配線遅延が大きくなることが懸念される。 In recent years, higher integration of semiconductor devices has progressed. When a plurality of highly integrated semiconductor devices are arranged in a horizontal plane and these semiconductor devices are connected by wiring to produce a product, the wiring length increases, thereby increasing the wiring resistance and wiring delay. There is concern about becoming.
　そこで、半導体デバイスを３次元に積層する３次元集積技術が提案されている。この３次元集積技術においては、半導体ウェハ（以下、「ウェハ」という。）の接合や半導体チップの接合などが行われる。そして、半導体デバイスを適切に積層するために、高い位置精度の接合が要求されている。 Therefore, a three-dimensional integration technique in which semiconductor devices are stacked three-dimensionally has been proposed. In this three-dimensional integration technology, bonding of semiconductor wafers (hereinafter referred to as “wafers”), bonding of semiconductor chips, and the like are performed. And in order to laminate | stack a semiconductor device appropriately, joining with a high positional accuracy is requested | required.
　このように位置精度よく接合するため、例えば特許文献１には、異形基材材料の接合方法が提案されている。具体的には、第１の基材の任意の領域を選択的に親水化処理すると共に、第２の基材の接合面を親水化処理した後、水酸基を有する液体を介して、第１の基材の任意の領域と第２の基材の接合面とを接合する。 In order to join with high positional accuracy in this way, for example, Patent Document 1 proposes a joining method for deformed base material. Specifically, an arbitrary region of the first base material is selectively hydrophilized, and the bonding surface of the second base material is hydrophilized, and then the first base is passed through the liquid having a hydroxyl group. The arbitrary area | region of a base material and the joint surface of a 2nd base material are joined.
日本国特開２０００－２５２５４３号公報Japanese Unexamined Patent Publication No. 2000-252543
　しかしながら、特許文献１に記載された接合方法では、第１の基材の任意の領域を親水化するために、複数の処理を行う必要がある。具体的に特許文献１に記載された方法によれば、先ず、第１の基材の表面に金属膜を形成した後、フォトリソグラフィー処理とエッチング処理を行い、任意の領域の金属膜を選択的に除去する。その後、第１の基材をアルカリ性の親水化処理液中に浸漬させ、金属膜に覆われていない任意の領域が親水化される。かかる場合、接合処理が煩雑化し、また当該接合処理の処理コストも高価になる。 However, in the joining method described in Patent Document 1, it is necessary to perform a plurality of treatments in order to hydrophilize an arbitrary region of the first base material. Specifically, according to the method described in Patent Document 1, first, after forming a metal film on the surface of the first base material, a photolithography process and an etching process are performed to selectively select a metal film in an arbitrary region. To remove. Then, the 1st base material is immersed in an alkaline hydrophilization treatment liquid, and the arbitrary field which is not covered with a metal film is hydrophilized. In such a case, the joining process becomes complicated, and the processing cost of the joining process becomes expensive.
　また、この特許文献１に記載された接合方法を用いて、複数の半導体デバイスが形成されたウェハ同士を接合する場合、各半導体デバイスに対して親水化処理が必要となる。そうすると、接合処理がさらに煩雑化し、また当該接合処理の処理コストもさらに高価になる。 Further, when the wafers on which a plurality of semiconductor devices are formed are bonded using the bonding method described in Patent Document 1, a hydrophilic treatment is required for each semiconductor device. As a result, the joining process is further complicated, and the processing cost of the joining process is further increased.
　本発明は、かかる点に鑑みてなされたものであり、複数の半導体デバイスが形成された基板を簡易且つ適切に接合することを目的とする。 The present invention has been made in view of such a point, and an object thereof is to easily and appropriately join substrates on which a plurality of semiconductor devices are formed.
　前記の目的を達成するため、本発明は、複数の半導体デバイスが形成された第１の基板と、複数の半導体デバイスが形成された第２の基板とを接合する基板の接合方法であって、前記第１の基板の前記複数の半導体デバイスが形成される面において、当該複数の半導体デバイスを形成し、各半導体デバイスの間のスクライブラインとなる領域よりも高くされた半導体デバイス領域を形成する第１の工程と、前記第２の基板の前記第１の基板と接合される面において、前記半導体デバイス領域に対応する領域を親水化し、被接合領域を形成する第２の工程と、前記半導体デバイス領域と前記被接合領域との間に処理液を供給し、前記第１の基板と前記第２の基板とを接合する第３の工程と、を有する。 In order to achieve the above object, the present invention provides a method for bonding substrates, in which a first substrate on which a plurality of semiconductor devices are formed and a second substrate on which a plurality of semiconductor devices are formed are bonded. Forming a plurality of semiconductor devices on a surface of the first substrate on which the plurality of semiconductor devices are formed, and forming a semiconductor device region higher than a region that becomes a scribe line between the semiconductor devices; 1 and a second step of hydrophilizing a region corresponding to the semiconductor device region on a surface of the second substrate to be bonded to the first substrate to form a bonded region, and the semiconductor device A third step of supplying a processing liquid between the region and the region to be bonded, and bonding the first substrate and the second substrate.
　本発明によれば、第１の工程において、第１の基板の半導体デバイス領域をスクライブラインとなる領域よりも高く形成すると共に、第２の工程において、第２の基板の被接合領域を親水化している。そうすると、第３の工程において、半導体デバイス領域と被接合領域との間に処理液を供給しても、いわゆるピン止め効果によって、処理液が半導体デバイス領域と被接合領域との間から流出することはない。また、この処理液の表面張力によって、少なくとも第１の基板又は第２の基板を移動させる復元力が作用する。そして、半導体デバイス領域と被接合領域が正確に対応するように、第１の基板と第２の基板の位置調整が高い位置精度で行われる。そうすると、その後第１の基板と第２の基板を適切に接合することができる。しかも、第１の基板においては半導体デバイス領域をスクライブラインとなる領域よりも高く形成するだけで、第１の基板と第２の基板を適切に接合することができるので、第１の基板に対して従来のように追加的な処理を行う必要がない。したがって、第１の基板と第２の基板の接合処理を簡易化することができ、さらに接合処理の処理コストを低廉化することができる。 According to the present invention, in the first step, the semiconductor device region of the first substrate is formed higher than the region serving as the scribe line, and in the second step, the bonded region of the second substrate is hydrophilized. ing. Then, in the third step, even if the processing liquid is supplied between the semiconductor device region and the bonded region, the processing liquid flows out from between the semiconductor device region and the bonded region due to a so-called pinning effect. There is no. In addition, a restoring force that moves at least the first substrate or the second substrate acts by the surface tension of the processing liquid. Then, the position adjustment of the first substrate and the second substrate is performed with high positional accuracy so that the semiconductor device region and the bonded region correspond exactly. Then, the first substrate and the second substrate can be appropriately bonded thereafter. Moreover, in the first substrate, the first substrate and the second substrate can be appropriately joined only by forming the semiconductor device region higher than the region serving as the scribe line. Thus, there is no need to perform additional processing as in the prior art. Therefore, the bonding process between the first substrate and the second substrate can be simplified, and the processing cost of the bonding process can be reduced.
　別な観点による本発明は、複数の半導体デバイスが形成された基板が複数層に接合された半導体装置であって、前記複数の半導体デバイスが形成される面において、各半導体デバイスの間のスクライブラインとなる領域よりも高くされた半導体デバイス領域が形成された第１の基板と、前記第１の基板と接合される面において、前記半導体デバイス領域に対応する領域が親水化され、被接合領域が形成された第２の基板と、を有し、前記半導体デバイス領域と前記被接合領域との間に処理液が供給されて、前記第１の基板と前記第２の基板とが接合されている。 According to another aspect of the present invention, there is provided a semiconductor device in which a substrate on which a plurality of semiconductor devices are formed is bonded to a plurality of layers, and a scribe line between the semiconductor devices on a surface on which the plurality of semiconductor devices are formed. The region corresponding to the semiconductor device region is hydrophilized on the first substrate having the semiconductor device region formed higher than the region to be formed, and the surface bonded to the first substrate. And a processing liquid is supplied between the semiconductor device region and the bonded region, and the first substrate and the second substrate are bonded to each other. .
　本発明によれば、複数の半導体デバイスが形成された基板を簡易且つ適切に接合することができる。 According to the present invention, substrates on which a plurality of semiconductor devices are formed can be easily and appropriately joined.
本実施の形態にかかるウェハの接合方法の各工程を示したフローチャートである。It is the flowchart which showed each process of the bonding method of the wafer concerning this Embodiment. 第１のウェハにデバイス層を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the device layer was formed in the 1st wafer. 第１のウェハのデバイス層の構成の概略を示す平面図である。It is a top view which shows the outline of a structure of the device layer of a 1st wafer. 第１のウェハのデバイス領域と接続領域の配置を示す平面の説明図である。It is explanatory drawing of the plane which shows arrangement | positioning of the device area | region and connection area | region of a 1st wafer. 第１のウェハに接続領域を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the connection area | region was formed in the 1st wafer. 第１のウェハにスクライブライン領域を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the scribe line area | region was formed in the 1st wafer. 第２のウェハにデバイス層を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the device layer was formed in the 2nd wafer. 第２のウェハに支持ウェハを配設した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the support wafer was arrange | positioned to the 2nd wafer. 第２のウェハに貫通孔を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the through-hole was formed in the 2nd wafer. 第２のウェハに貫通電極を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the penetration electrode was formed in the 2nd wafer. 第２のウェハに絶縁膜を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the insulating film was formed in the 2nd wafer. 第２のウェハに被接合領域を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the to-be-joined area | region was formed in the 2nd wafer. 第２のウェハの被接合領域の配置を示す平面の説明図である。It is explanatory drawing of the plane which shows arrangement | positioning of the to-be-joined area | region of a 2nd wafer. 第１のウェハのデバイス領域と接続領域上に純水を供給した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the pure water was supplied on the device area | region and connection area | region of a 1st wafer. 第１のウェハのデバイス領域上に純水を供給した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the pure water was supplied on the device area | region of a 1st wafer. 第２のウェハを第１のウェハの上方に配設した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the 2nd wafer was arrange | positioned above the 1st wafer. 第１のウェハと第２のウェハを位置調整して接合した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the 1st wafer and the 2nd wafer were position-adjusted and joined. 第１のウェハを薄化した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the 1st wafer was thinned. 第１のウェハに貫通電極を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the penetration electrode was formed in the 1st wafer. 半導体装置を製造した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the semiconductor device was manufactured. 他の実施の形態における第２のウェハの被接合領域の配置を示す平面の説明図である。It is explanatory drawing of the plane which shows arrangement | positioning of the to-be-joined area | region of the 2nd wafer in other embodiment. 他の実施の形態において空気孔が形成された支持ウェハを第２のウェハに配設した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the support wafer in which the air hole was formed in other embodiment was arrange | positioned in the 2nd wafer. 他の実施の形態において第２のウェハに空気孔を形成した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the air hole was formed in the 2nd wafer in other embodiment. 他の実施の形態において第１のウェハと第２のウェハを位置調整して接合した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the 1st wafer and the 2nd wafer were position-adjusted and joined in other embodiment. 他の実施の形態において第２のウェハを第１のウェハの上方に配設した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the 2nd wafer was arrange | positioned above the 1st wafer in other embodiment. 他の実施の形態において第１のウェハと第２のウェハを位置調整して接合した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the 1st wafer and the 2nd wafer were position-adjusted and joined in other embodiment. 他の実施の形態において第１のウェハと第２のウェハを位置調整して接合した様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the 1st wafer and the 2nd wafer were position-adjusted and joined in other embodiment. 他の実施の形態において支持ウェハに昇降機構を設けた様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the raising / lowering mechanism was provided in the support wafer in other embodiment. 他の実施の形態において支持ウェハに昇降機構を設けた様子を示す縦断面の説明図である。It is explanatory drawing of the longitudinal cross-section which shows a mode that the raising / lowering mechanism was provided in the support wafer in other embodiment.
　以下、本発明の実施の形態について説明する。本実施の形態では、本発明にかかる基板としてのウェハの接合方法と、当該接合方法によって接合されたウェハが複数層に積層された半導体装置について説明する。図１は、本実施の形態にかかるウェハの接合方法の主な処理フローを示している。本実施の形態では、第１の基板としての第１のウェハと第２の基板としての第２のウェハを接合する。より具体的には、第１のウェハを相対的に下方に配置し、第２のウェハを相対的に上方に配置した状態で、当該第１のウェハと第２のウェハを接合する。なお、以下の説明で用いる図面において、各構成要素の寸法は、技術の理解の容易さを優先させるため、必ずしも実際の寸法に対応していない。 Hereinafter, embodiments of the present invention will be described. In this embodiment mode, a method for bonding a wafer as a substrate according to the present invention and a semiconductor device in which wafers bonded by the bonding method are stacked in a plurality of layers will be described. FIG. 1 shows a main processing flow of the wafer bonding method according to the present embodiment. In this embodiment mode, a first wafer as a first substrate and a second wafer as a second substrate are bonded. More specifically, the first wafer and the second wafer are bonded together in a state where the first wafer is disposed relatively downward and the second wafer is disposed relatively upward. In the drawings used in the following description, the dimensions of each component do not necessarily correspond to the actual dimensions in order to prioritize easy understanding of the technology.
　先ず、図２に示すように第１のウェハ１０のバルク層１１上にデバイス層１２を形成する。以下、バルク層１１において、デバイス層１２側の面を表面１１ａといい、デバイス層１２と反対側の面を裏面１１ｂという。また、デバイス層１２において、バルク層１１と反対側の面を表面１２ａといい、バルク層１１側の面を裏面１２ｂという。 First, as shown in FIG. 2, a device layer 12 is formed on the bulk layer 11 of the first wafer 10. Hereinafter, in the bulk layer 11, the surface on the device layer 12 side is referred to as a front surface 11a, and the surface on the opposite side to the device layer 12 is referred to as a back surface 11b. Further, in the device layer 12, a surface opposite to the bulk layer 11 is referred to as a front surface 12a, and a surface on the bulk layer 11 side is referred to as a back surface 12b.
　第１のウェハ１０のデバイス層１２には、半導体デバイスとしてのデバイス１３（以下、「デバイス領域１３」という場合がある。）が形成されている（図１の工程Ｓ１）。デバイス１３は、図３に示すように第１のウェハ１０上において、ウェハ面内均一に複数形成されている。そして、本実施の形態では、第１のウェハ１０を個々のデバイス１３からなる半導体チップに切り出す前に、当該第１のウェハ１０と後述する第２のウェハ２０をウェハレベルで積層するウェハ積層方式が用いられる。 A device 13 (hereinafter, also referred to as “device region 13”) as a semiconductor device is formed on the device layer 12 of the first wafer 10 (step S1 in FIG. 1). As shown in FIG. 3, a plurality of devices 13 are uniformly formed on the first wafer 10 within the wafer surface. In this embodiment, the wafer stacking method in which the first wafer 10 and a later-described second wafer 20 are stacked at the wafer level before the first wafer 10 is cut into semiconductor chips including the individual devices 13. Is used.
　デバイス１３には、図２に示すように複数の回路１４が形成されている。回路１４内には、複数のトランジスタやメモリセル（図示せず）が配置されている。なお、図示はしないが、デバイス１３内には、回路１４と後述する貫通電極４０を配線する配線や、種々の回路、電極等も形成されている。また、複数の回路１４等は、一連のデバイス層１２の形成工程において同時に形成される。 A plurality of circuits 14 are formed in the device 13 as shown in FIG. In the circuit 14, a plurality of transistors and memory cells (not shown) are arranged. Although not shown, in the device 13, wiring for wiring the circuit 14 and a through electrode 40 described later, various circuits, electrodes, and the like are also formed. The plurality of circuits 14 and the like are formed at the same time in the series of device layer 12 forming steps.
　複数のデバイス１３間には、スクライブライン１５（以下、「スクライブライン領域１５」という場合がある。）が形成されている。デバイス領域１３はスクライブライン領域１５よりも高く形成されている。なお、スクライブラインとは、ウェハが切断され複数の半導体チップに分割される際のラインのことである。 A scribe line 15 (hereinafter sometimes referred to as “scribe line region 15”) is formed between the plurality of devices 13. The device region 13 is formed higher than the scribe line region 15. Note that the scribe line is a line when the wafer is cut and divided into a plurality of semiconductor chips.
　その後、図３及び図４に示すようにスクライブライン領域１５において、隣り合うデバイス領域１３を接続する接続領域１６を形成する（図１の工程Ｓ２）。本実施の形態では、デバイス領域１３は平面視において四角形状を有し、複数のデバイス領域１３は格子状に配置されている。そこで、第１のウェハ１０における内側のデバイス領域１３には４つの接続領域１６が接続され、外側のデバイス領域１３には２つの接続領域１６が接続されている。この接続領域１６は、図５に示すようにデバイス領域１３の高さと同じ高さを有している。一方、接続領域１６が形成されないスクライブライン領域１５には、図４に示すように何も形成されていないか、或いは図６に示すようにデバイス領域１３の高さより低い高さを有する検査素子等の素子１７が形成されている。いずれにしても、接続領域１６が形成されないスクライブライン領域１５は、デバイス領域１３よりも低くなっている。なお、説明の便宜上、デバイス領域１３と接続領域１６の形成を順に説明したが、実際にはデバイス領域１３と接続領域１６は同時に形成される。接続領域１６はスクライブライン領域１５に形成されているため、当該接続領域１６がデバイス１３に悪影響を及ぼすことはない。また、スクライブライン領域１５は本来的にデバイス１３の形成されない領域であるため、当該接続領域１６は、１枚のウェハ１０からのデバイス１３の取れ量に悪影響を与えない。 Thereafter, as shown in FIGS. 3 and 4, in the scribe line region 15, a connection region 16 that connects the adjacent device regions 13 is formed (step S2 in FIG. 1). In the present embodiment, the device region 13 has a quadrangular shape in plan view, and the plurality of device regions 13 are arranged in a lattice shape. Therefore, four connection regions 16 are connected to the inner device region 13 of the first wafer 10, and two connection regions 16 are connected to the outer device region 13. The connection region 16 has the same height as the device region 13 as shown in FIG. On the other hand, in the scribe line region 15 where the connection region 16 is not formed, nothing is formed as shown in FIG. 4, or an inspection element having a height lower than the height of the device region 13 as shown in FIG. The element 17 is formed. In any case, the scribe line region 15 in which the connection region 16 is not formed is lower than the device region 13. For convenience of explanation, the formation of the device region 13 and the connection region 16 has been described in order, but the device region 13 and the connection region 16 are actually formed at the same time. Since the connection region 16 is formed in the scribe line region 15, the connection region 16 does not adversely affect the device 13. In addition, since the scribe line area 15 is an area where the device 13 is not originally formed, the connection area 16 does not adversely affect the yield of the device 13 from one wafer 10.
　その後、デバイス領域１３及び接続領域１６上にアンモニア（アンモニアを所定の濃度に希釈したアンモニア水）を供給する。このアンモニアによって、デバイス領域１３及び接続領域１６の表面、換言すれば第１のウェハ１０の表面が活性化される（図１の工程Ｓ３）。具体的には、デバイス領域１３及び接続領域１６の表面における分子の結合を切断して、その後親水化されやすくするように当該表面を活性化する。なお、接合面に有機残渣などが残っていると後の気泡の原因となるので、アンモニアで活性化する前に、第１のウェハ１０の表面にＳＣ１（Ｓｔａｎｄａｒｄ　Ｃｌｅａｎ　１）を２流体ノズルで吹き付けることで、前洗浄を行っておくとよい。その後、例えば純水でデバイス領域１３及び接続領域１６の表面を洗浄した後、当該純水を乾燥させる。第１のウェハ１０を加熱することなどにより乾燥させてればよい。なお、本実施の形態ではアンモニアによってデバイス領域１３及び接続領域１６の表面を活性化したが、これらを活性化するための液はこれに限定されず、例えば純水等の種々の液を用いることができる。水酸化カリウムなどのアルカリ水溶液を用いることもできる。 Thereafter, ammonia (ammonia water obtained by diluting ammonia to a predetermined concentration) is supplied onto the device region 13 and the connection region 16. This ammonia activates the surfaces of the device region 13 and the connection region 16, in other words, the surface of the first wafer 10 (step S3 in FIG. 1). Specifically, the surface of the device region 13 and the connection region 16 is broken, and then the surfaces are activated so as to be easily hydrophilized. If organic residues remain on the bonding surface, it may cause later bubbles. Therefore, before activation with ammonia, SC1 (Standard Clean 1) is sprayed onto the surface of the first wafer 10 with a two-fluid nozzle. Therefore, it is better to perform pre-cleaning. Thereafter, for example, the surfaces of the device region 13 and the connection region 16 are washed with pure water, and then the pure water is dried. The first wafer 10 may be dried by heating or the like. In this embodiment, the surfaces of the device region 13 and the connection region 16 are activated by ammonia, but the liquid for activating them is not limited to this, and various liquids such as pure water are used. Can do. An aqueous alkali solution such as potassium hydroxide can also be used.
　このように第１のウェハ１０に工程Ｓ１～Ｓ３の処理を行うのに並行して、或いはその工程Ｓ１～Ｓ３の前後において、第２のウェハ２０に対して次の処理が行われる。 In this way, the next process is performed on the second wafer 20 in parallel with or before and after the processes S1 to S3.
　先ず、図７に示すように第２のウェハ２０のバルク層２１上にデバイス層２２を形成する。以下、バルク層２１において、デバイス層２２側の面を表面２１ａといい、デバイス層２２と反対側の面を裏面２１ｂという。また、デバイス層２２において、バルク層２１と反対側の面を表面２２ａといい、バルク層２１側の面を裏面２２ｂという。 First, as shown in FIG. 7, the device layer 22 is formed on the bulk layer 21 of the second wafer 20. Hereinafter, in the bulk layer 21, the surface on the device layer 22 side is referred to as a front surface 21a, and the surface on the opposite side to the device layer 22 is referred to as a back surface 21b. Further, in the device layer 22, the surface opposite to the bulk layer 21 is referred to as a front surface 22a, and the surface on the bulk layer 21 side is referred to as a back surface 22b.
　第２のウェハ２０のデバイス層２２には、デバイス２３（以下、「デバイス領域２３」という場合がある。）が形成されている（図１の工程Ｓ４）。デバイス２３は、第１のウェハ１０のデバイス１３と同様に、第２のウェハ２０上においてウェハ面内均一に複数形成されている。 A device 23 (hereinafter also referred to as “device region 23”) is formed on the device layer 22 of the second wafer 20 (step S4 in FIG. 1). Similar to the device 13 of the first wafer 10, a plurality of devices 23 are uniformly formed in the wafer surface on the second wafer 20.
　デバイス１３には、図７に示すように複数の回路２４が形成されている。回路２４内には、複数のトランジスタやメモリセル（図示せず）が配置されている。なお、図示はしないが、デバイス２３内には、回路２４と後述する貫通電極２９を配線する配線や、種々の回路、電極等も形成されている。また、複数の回路２４等は、一連のデバイス層２２の形成工程において同時に形成される。 A plurality of circuits 24 are formed in the device 13 as shown in FIG. In the circuit 24, a plurality of transistors and memory cells (not shown) are arranged. Although not shown, in the device 23, wiring for wiring the circuit 24 and a through electrode 29 described later, various circuits, electrodes, and the like are also formed. The plurality of circuits 24 and the like are simultaneously formed in a series of device layer 22 formation steps.
　複数のデバイス２３間には、スクライブライン２５（以下、「スクライブライン領域２５」という場合がある。）が形成されている。なお、第１のウェハ１０ではスクライブライン領域１５において接続領域１６が形成されていたが、第２のウェハ２０においては同様の接続領域が形成されていてもよいし、形成されていなくてもよい。本実施の形態では第２のウェハ２０に接続領域２６が形成されている。 A scribe line 25 (hereinafter sometimes referred to as “scribe line area 25”) is formed between the plurality of devices 23. Although the connection region 16 is formed in the scribe line region 15 in the first wafer 10, a similar connection region may or may not be formed in the second wafer 20. . In the present embodiment, a connection region 26 is formed on the second wafer 20.
　その後、図８に示すようにデバイス層２２の表面２２ａに支持基板としての支持ウェハ２７を配設する（図１の工程Ｓ５）。支持ウェハ２７は、例えば剥離可能な接着剤によってデバイス層２２と接着される。なお、支持基板にはシリコンウェハやガラス基板が用いられる。 Thereafter, as shown in FIG. 8, a support wafer 27 as a support substrate is disposed on the surface 22a of the device layer 22 (step S5 in FIG. 1). The support wafer 27 is bonded to the device layer 22 by, for example, a peelable adhesive. A silicon wafer or a glass substrate is used as the support substrate.
　その後、図８に示すようにバルク層２１の裏面２１ｂを研磨し、第２のウェハ２０を薄化する（図１の工程Ｓ６）。 Thereafter, as shown in FIG. 8, the back surface 21b of the bulk layer 21 is polished to thin the second wafer 20 (step S6 in FIG. 1).
　その後、図９に示すように第２のウェハ２０の表裏面を反転させ、バルク層２１の下方にデバイス層２２を配置した後、デバイス層２２とバルク層２１を厚み方向に貫通する貫通孔２８を形成する（図１の工程Ｓ７）。貫通孔２８は、回路２４と接続されるように、実際には回路２４に接続される配線（図示せず）に接続されるように形成される。また、貫通孔２８は、第２のウェハ２０において複数形成される。これら複数の貫通孔２８は、例えばフォトリソグラフィー処理及びエッチング処理によって同時に形成される。すなわち、フォトリソグラフィー処理によってバルク層２１上に所定のレジストパターンを形成した後、当該レジストパターンをマスクとしてバルク層２１とデバイス層２２をエッチングして、貫通孔２８が形成される。貫通孔２８の形成後、レジストパターンは、例えばアッシングされて除去される。 Thereafter, as shown in FIG. 9, the front and back surfaces of the second wafer 20 are reversed, the device layer 22 is disposed below the bulk layer 21, and then the through hole 28 that penetrates the device layer 22 and the bulk layer 21 in the thickness direction. Is formed (step S7 in FIG. 1). The through hole 28 is formed so as to be connected to a wiring (not shown) that is actually connected to the circuit 24 so as to be connected to the circuit 24. A plurality of through holes 28 are formed in the second wafer 20. The plurality of through holes 28 are simultaneously formed by, for example, a photolithography process and an etching process. That is, after a predetermined resist pattern is formed on the bulk layer 21 by photolithography, the through hole 28 is formed by etching the bulk layer 21 and the device layer 22 using the resist pattern as a mask. After the through hole 28 is formed, the resist pattern is removed by ashing, for example.
　その後、各貫通孔２８内に導電性材料を充填して、図１０に示すように貫通電極（ＴＳＶ：Ｔｈｒｏｕｇｈ　Ｓｉｌｉｃｏｎ　Ｖｉａ）２９を形成する（図１の工程Ｓ８）。なお実際には、導電性材料が充填される前に各貫通孔２８の内壁にバリア膜や絶縁膜等が形成されるが、説明を簡略化させるために省略する。 Thereafter, each through-hole 28 is filled with a conductive material to form a through-electrode (TSV: Through Silicon Via) 29 as shown in FIG. 10 (step S8 in FIG. 1). In practice, a barrier film, an insulating film, and the like are formed on the inner wall of each through-hole 28 before the conductive material is filled, but this is omitted for the sake of simplicity.
　その後、図１１に示すようにバルク層２１の裏面２１ｂ上に絶縁膜３０を形成する（図１の工程Ｓ９）。なお、絶縁膜３０は、例えばシリコン酸化膜などから材料を適宜選択し、ＣＶＤ（化学気相蒸着）などの方法で成膜される。 Thereafter, as shown in FIG. 11, an insulating film 30 is formed on the back surface 21b of the bulk layer 21 (step S9 in FIG. 1). The insulating film 30 is formed by a method such as CVD (Chemical Vapor Deposition) by appropriately selecting a material from, for example, a silicon oxide film.
　その後、図１２に示すように絶縁膜３０を所定のパターンにパターニングする（図１の工程Ｓ１０）。このパターニングでは、図１２及び図１３に示すように第１のウェハ１０のデバイス領域１３及び接続領域１６に対応する位置の絶縁膜３０を残し、接続領域１６が形成されていないスクライブライン領域１５に対応する位置の絶縁膜３０を除去する。そして、このようにパターニングされた絶縁膜３０が、デバイス領域１３及び接続領域１６と接合される被接合領域３１を構成する。そうすると、後述するピン止め効果により、第２のウェハ２０の裏面において、被接合領域３１は相対的に親水化され、被接合領域３１以外の領域３２は相対的に疎水化される。なお、被接合領域３１の親水化は、上述のように絶縁膜３０のパターニングに限定されず、被接合領域３１の表面を改質して親水化処理を行ってもよい。 Thereafter, as shown in FIG. 12, the insulating film 30 is patterned into a predetermined pattern (step S10 in FIG. 1). In this patterning, as shown in FIGS. 12 and 13, the insulating film 30 at positions corresponding to the device region 13 and the connection region 16 of the first wafer 10 is left, and the scribe line region 15 where the connection region 16 is not formed is left. The insulating film 30 at the corresponding position is removed. The insulating film 30 patterned in this way constitutes a bonded region 31 that is bonded to the device region 13 and the connection region 16. Then, due to the pinning effect described later, the bonded region 31 is relatively hydrophilized and the region 32 other than the bonded region 31 is relatively hydrophobized on the back surface of the second wafer 20. The hydrophilicity of the bonded region 31 is not limited to the patterning of the insulating film 30 as described above, and the surface of the bonded region 31 may be modified to perform the hydrophilic treatment.
　その後、被接合領域３１上にアンモニア（アンモニアを所定の濃度に希釈したアンモニア水）を供給する。このアンモニアによって、被接合領域３１の表面、換言すれば第２のウェハ２０の裏面が活性化される（図１の工程Ｓ１１）。具体的には、被接合領域３１の表面における分子の結合を切断して、その後親水化されやすくするように当該表面を活性化する。なお、接合面に有機残渣などが残っていると後の気泡の原因となるので、アンモニアで活性化する前に、第２のウェハ２０の裏面にＳＣ１（Ｓｔａｎｄａｒｄ　Ｃｌｅａｎ　１）を２流体ノズルで吹き付けることで、前洗浄を行っておくとよい。その後、例えば純水で被接合領域３１の表面を洗浄した後、当該純水を乾燥させる。第２のウェハ２０を加熱することなどにより乾燥させてればよい。なお、本実施の形態ではアンモニアによって被接合領域３１の表面を活性化したが、これを活性化するための液はこれに限定されず、種々の液を用いることができる。水酸化カリウムなどのアルカリ水溶液を用いることもできる。 Thereafter, ammonia (ammonia water in which ammonia is diluted to a predetermined concentration) is supplied onto the bonded region 31. By this ammonia, the surface of the bonded region 31, in other words, the back surface of the second wafer 20 is activated (step S11 in FIG. 1). Specifically, the surface of the bonded region 31 is broken so that the surface of the bonded region 31 is activated, and then the surface is activated so as to be easily hydrophilized. Note that if organic residue or the like remains on the bonding surface, it may cause later bubbles. Therefore, before activation with ammonia, SC1 (Standard Clean 1) is sprayed to the back surface of the second wafer 20 with a two-fluid nozzle. Therefore, it is better to perform pre-cleaning. Thereafter, for example, the surface of the bonded region 31 is washed with pure water, and then the pure water is dried. The second wafer 20 may be dried by heating or the like. In the present embodiment, the surface of the bonded region 31 is activated by ammonia. However, the liquid for activating this is not limited to this, and various liquids can be used. An aqueous alkali solution such as potassium hydroxide can also be used.
　このように第１のウェハ１０と第２のウェハ２０に工程Ｓ１～Ｓ１１の所定の処理が行われると、次に当該第１のウェハ１０と第２のウェハ２０の接合処理が行われる。 When the predetermined processing of steps S1 to S11 is performed on the first wafer 10 and the second wafer 20 in this way, the bonding processing of the first wafer 10 and the second wafer 20 is performed next.
　先ず、図１４と図１５に示すように第１のウェハ１０のデバイス領域１３及び接続領域１６上に、処理液としての純水Ｐを供給する（図１の工程Ｓ１２）。ここで、上述したようにデバイス領域１３及び接続領域１６は、接続領域１６が形成されていないスクライブライン領域１５よりも高く形成されている。このため純水Ｐは、デバイス領域１３及び接続領域１６の縁部において、その表面張力により大きな所定の接触角を持つ。そうすると、純水Ｐはデバイス領域１３及び接続領域１６上に留まる。このように純水Ｐの広がりを抑える現象は、いわゆるピン止め効果として知られている。そして、純水Ｐはデバイス領域１３及び接続領域１６上に拡散する。なお、本実施の形態では処理液として純水Ｐを用いたが、水酸基を有する液体であれば種々の液体を用いることができる。 First, as shown in FIGS. 14 and 15, pure water P as a processing liquid is supplied onto the device region 13 and the connection region 16 of the first wafer 10 (step S12 in FIG. 1). Here, as described above, the device region 13 and the connection region 16 are formed higher than the scribe line region 15 in which the connection region 16 is not formed. For this reason, the pure water P has a large predetermined contact angle due to the surface tension at the edges of the device region 13 and the connection region 16. As a result, the pure water P remains on the device region 13 and the connection region 16. The phenomenon of suppressing the spread of pure water P in this way is known as a so-called pinning effect. The pure water P diffuses over the device region 13 and the connection region 16. In this embodiment, pure water P is used as the treatment liquid. However, various liquids can be used as long as the liquid has a hydroxyl group.
　その後、図１６に示すように第１のウェハ１０のデバイス層１２側に第２のウェハ２０を配設する。第２のウェハ２０は、そのバルク層２１が第１のウェハ１０のデバイス層１２に対向するように配置される。このとき、第２のウェハ２０の被接合領域３１は親水化されているので、純水Ｐが被接合領域３１、すなわち第１のウェハ１０のデバイス領域１３及び接続領域１６から流出することはない。なお、バルク層２１の被接合領域３１の位置と、デバイス層１２のデバイス領域１３及び接続領域１６の位置とは、厳密に対応している必要はない。図１６に示すようにこれらの位置が多少ずれている場合でも、後述する工程Ｓ１３において第１のウェハ１０と第２のウェハ２０の位置調整が行われる。 Thereafter, as shown in FIG. 16, the second wafer 20 is disposed on the device layer 12 side of the first wafer 10. The second wafer 20 is arranged such that the bulk layer 21 faces the device layer 12 of the first wafer 10. At this time, since the bonded region 31 of the second wafer 20 is hydrophilized, the pure water P does not flow out of the bonded region 31, that is, the device region 13 and the connection region 16 of the first wafer 10. . Note that the positions of the bonded region 31 of the bulk layer 21 and the positions of the device region 13 and the connection region 16 of the device layer 12 do not need to correspond exactly. As shown in FIG. 16, even when these positions are slightly deviated, the position adjustment of the first wafer 10 and the second wafer 20 is performed in step S13 described later.
　その後、上述した第１のウェハ１０と第２のウェハ２０との間に充填された純水Ｐの表面張力によって、図１７に示すように第２のウェハ２０を移動させる復元力（図１７の矢印）が第２のウェハ２０に作用する。そうすると、バルク層２１の接続領域１６の位置とデバイス層１２のデバイス領域１３及び接続領域１６の位置とがずれている場合でも、これらが対向するように第２のウェハ２０が移動し、第１のウェハ１０と第２のウェハ２０の位置調整が高精度に（サブミクロンオーダー）行われる（図１の工程Ｓ１３）。なお、説明の便宜上、第２のウェハ２０の配設と第２のウェハ２０の移動を順に説明したが、実際にはこれらの現象はほぼ同時に進行する。 Thereafter, due to the surface tension of the pure water P filled between the first wafer 10 and the second wafer 20 described above, a restoring force (as shown in FIG. 17) moves the second wafer 20 as shown in FIG. An arrow) acts on the second wafer 20. Then, even when the position of the connection region 16 of the bulk layer 21 and the position of the device region 13 and the connection region 16 of the device layer 12 are shifted, the second wafer 20 moves so that they are opposed to each other. The position adjustment of the wafer 10 and the second wafer 20 is performed with high accuracy (submicron order) (step S13 in FIG. 1). For convenience of explanation, the arrangement of the second wafer 20 and the movement of the second wafer 20 have been described in order, but actually these phenomena proceed almost simultaneously.
　その後、第１のウェハ１０と第２のウェハ２０との間に充填された純水Ｐによって、第１のウェハ１０のデバイス領域１３及び接続領域１６に水酸基が付着して当該デバイス領域１３及び接続領域１６の表面が親水化される共に、第２のウェハ２０の被接合領域３１に水酸基が付着して当該被接合領域３１の表面が親水化される。そして、デバイス領域１３及び接続領域１６の表面と被接合領域３１の表面とは、それぞれ工程Ｓ３、Ｓ１１において活性化されているため、先ず、デバイス領域１３及び接続領域１６の表面と被接合領域３１の表面との間にファンデルワールス力が生じ、当該表面同士が接合される。その後、デバイス領域１３及び接続領域１６の表面と被接合領域３１の表面はそれぞれ上述したように親水化されているため、デバイス領域１３及び接続領域１６の表面と被接合領域３１の表面間の水酸基が水素結合し、当該表面同士がより強固に接合される（図１の工程Ｓ１４）。なお、第１のウェハ１０と第２のウェハ２０が接合されると、当該第１のウェハ１０と第２のウェハ２０との間の純水Ｐは除去されて、第１のウェハ１０と第２のウェハ２０が乾燥される。 Thereafter, the pure water P filled between the first wafer 10 and the second wafer 20 causes hydroxyl groups to adhere to the device region 13 and the connection region 16 of the first wafer 10 so that the device region 13 and the connection are connected. While the surface of the region 16 is hydrophilized, a hydroxyl group adheres to the bonded region 31 of the second wafer 20 and the surface of the bonded region 31 is hydrophilized. Since the surfaces of the device region 13 and the connection region 16 and the surface of the bonded region 31 are activated in steps S3 and S11, respectively, first, the surfaces of the device region 13 and the connection region 16 and the bonded region 31 are first activated. Van der Waals force is generated between the two surfaces and the surfaces are joined to each other. Thereafter, since the surfaces of the device region 13 and the connection region 16 and the surface of the bonded region 31 are made hydrophilic as described above, the hydroxyl group between the surface of the device region 13 and the connection region 16 and the surface of the bonded region 31 is obtained. Hydrogen bond, and the surfaces are bonded more firmly (step S14 in FIG. 1). When the first wafer 10 and the second wafer 20 are bonded, the pure water P between the first wafer 10 and the second wafer 20 is removed, and the first wafer 10 and the second wafer 20 are bonded. The second wafer 20 is dried.
　その後、図１８に示すように第１のウェハ１０におけるバルク層１１の裏面１１ｂを研磨し、第１のウェハ１０を薄化する（図１の工程Ｓ１５）。このとき、第１のウェハ１０の表裏面を反転させ、バルク層１１の下方にデバイス層１２を配置する。 Then, as shown in FIG. 18, the back surface 11b of the bulk layer 11 in the first wafer 10 is polished to thin the first wafer 10 (step S15 in FIG. 1). At this time, the front and back surfaces of the first wafer 10 are reversed, and the device layer 12 is disposed below the bulk layer 11.
　その後、図１９に示すように第１のウェハ１０に貫通孔（図示せず）を形成した後、貫通電極４０を形成する（図１の工程Ｓ１６）。貫通電極４０は、第１のウェハ１０のバルク層１１及びデバイス層１２と第２のウェハ２０の絶縁膜３０を厚み方向に貫通するように形成される。また、貫通電極４０は、回路１４と接続され、且つ第２のウェハ２０の貫通電極２９に接続される。なお、これら貫通孔と貫通電極４０を形成する方法は、上述した工程Ｓ８、Ｓ９における方法と同様であるので説明を省略する。また実際には、貫通電極４０と貫通電極２９の間にバンプ等が形成されるが、説明を簡略化させるために省略する。 Thereafter, as shown in FIG. 19, a through hole (not shown) is formed in the first wafer 10, and then a through electrode 40 is formed (step S16 in FIG. 1). The through electrode 40 is formed so as to penetrate the bulk layer 11 and device layer 12 of the first wafer 10 and the insulating film 30 of the second wafer 20 in the thickness direction. The through electrode 40 is connected to the circuit 14 and to the through electrode 29 of the second wafer 20. In addition, since the method of forming these through-holes and the through-electrodes 40 is the same as the method in steps S8 and S9 described above, the description thereof is omitted. In practice, bumps and the like are formed between the through electrode 40 and the through electrode 29, but are omitted for the sake of simplicity.
　ここで、第１のウェハ１０の貫通電極４０を第２のウェハ２０との接合前に形成すると、絶縁膜３０によって第１のウェハ１０の貫通電極４０と第２のウェハ２０の貫通電極２９が電気的に導通しない。このため、本実施の形態のように第１のウェハ１０の貫通電極４０は第２のウェハ２０との接合後に形成される。 Here, when the through electrode 40 of the first wafer 10 is formed before bonding to the second wafer 20, the through electrode 40 of the first wafer 10 and the through electrode 29 of the second wafer 20 are formed by the insulating film 30. Not electrically conductive. For this reason, the through electrode 40 of the first wafer 10 is formed after bonding to the second wafer 20 as in the present embodiment.
　その後、第１のウェハ１０において、バルク層１１の裏面１１ｂ上に絶縁膜３０を形成し（図１の工程Ｓ１７）、さらに絶縁膜３０を所定のパターンにパターニングして被接合領域３１を形成する（図１の工程Ｓ１８）。その後、被接合領域３１の表面、換言すれば第１のウェハ１０の裏面をアンモニア（アンモニアを所定の濃度に希釈したアンモニア水）によって活性化する（図１の工程Ｓ１９）。なお、これら絶縁膜３０の形成、被接合領域３１の形成、被接合領域３１の表面の活性化は、上述した工程Ｓ９～Ｓ１１と同様であるので説明を省略する。 Thereafter, in the first wafer 10, an insulating film 30 is formed on the back surface 11b of the bulk layer 11 (step S17 in FIG. 1), and the insulating film 30 is further patterned into a predetermined pattern to form a bonded region 31. (Step S18 in FIG. 1). Thereafter, the surface of the bonded region 31, in other words, the back surface of the first wafer 10 is activated with ammonia (ammonia water diluted with ammonia to a predetermined concentration) (step S19 in FIG. 1). The formation of the insulating film 30, the formation of the bonded region 31, and the activation of the surface of the bonded region 31 are the same as the above-described steps S9 to S11, and thus description thereof is omitted.
　以上のように第１のウェハ１０の裏面（バルク層１１の裏面１１ｂ）に対して、第２のウェハ２０の裏面（バルク層２１の裏面２１ｂ）と同様の処理を行う。そして、この第１のウェハ１０を第２のウェハ２０と同様に機能させて、当該第１のウェハ１０（以下、「旧第１のウェハ１０」という場合がある。）と新たな第１のウェハ１０（以下、「新第１のウェハ１０」という場合がある。）を接合する。なお、新第１のウェハ１０には、上述した工程Ｓ１～Ｓ３と同様の処理が行われている。そして、上述した工程Ｓ１２～Ｓ１４と同様の処理を行って、旧第１のウェハ１０と新第１のウェハ１０を接合する。こうして、図２０に示すように複数の第１のウェハ１０を積層し、さらに支持ウェハ２７を剥離して、ウェハ１０、２０が複数層に積層された半導体装置１００が製造される（図１の工程Ｓ２０）。なお、図示の例においては、ウェハ１０、２０を４層に積層する場合について説明するが、ウェハ１０、２０の積層数はこれに限定されず任意に設定することができる。 As described above, the same processing as the back surface of the second wafer 20 (the back surface 21b of the bulk layer 21) is performed on the back surface of the first wafer 10 (the back surface 11b of the bulk layer 11). Then, the first wafer 10 is caused to function in the same manner as the second wafer 20, and the first wafer 10 (hereinafter sometimes referred to as the “old first wafer 10”) and the new first wafer 10. The wafer 10 (hereinafter may be referred to as “the new first wafer 10”) is bonded. The new first wafer 10 is processed in the same manner as the above-described steps S1 to S3. Then, the same processing as in the above-described steps S12 to S14 is performed to join the old first wafer 10 and the new first wafer 10 together. In this way, as shown in FIG. 20, a plurality of first wafers 10 are stacked, and the support wafer 27 is further peeled off to manufacture a semiconductor device 100 in which the wafers 10 and 20 are stacked in a plurality of layers (FIG. 1). Step S20). In the illustrated example, the case where the wafers 10 and 20 are stacked in four layers will be described. However, the number of stacked wafers 10 and 20 is not limited to this and can be arbitrarily set.
　以上の実施の形態によれば、第１のウェハ１０のデバイス領域１３及び接続領域１６を、接続領域１６が形成されていないスクライブライン領域１５よりも高く形成すると共に、第２のウェハ２０の絶縁膜３０をパターニングして被接合領域３１を親水化している。そうすると、その後デバイス領域１３及び接続領域１６と被接合領域３１との間に純水Ｐを供給しても、いわゆるピン止め効果によって、純水Ｐがデバイス領域１３及び接続領域１６と被接合領域３１との間から流出することはない。そして、この純水Ｐの表面張力によって、第２のウェハ２０を移動させる復元力が作用する。そして、デバイス領域１３及び接続領域１６と被接合領域３１が正確に対応するように、第１のウェハ１０と第２のウェハ２０の位置調整が高い位置精度で行われる。そうすると、その後第１のウェハ１０と第２のウェハ２０を適切に接合することができる。しかも、第１のウェハ１０においてはデバイス領域１３及び接続領域１６をスクライブライン領域１５よりも高く形成するだけで、第１のウェハ１０と第２のウェハ２０を適切に接合することができるので、第１のウェハ１０と第２のウェハ２０の接合処理を簡易化することができ、さらに接合処理の処理コストを低廉化することができる。 According to the above embodiment, the device region 13 and the connection region 16 of the first wafer 10 are formed higher than the scribe line region 15 where the connection region 16 is not formed, and the insulation of the second wafer 20 is performed. The film 30 is patterned to make the bonded region 31 hydrophilic. Then, even if pure water P is supplied between the device region 13 and the connection region 16 and the bonded region 31 after that, the pure water P is converted into the device region 13 and the connection region 16 and the bonded region 31 by a so-called pinning effect. Will not flow out of between. And the restoring force which moves the 2nd wafer 20 acts with the surface tension of this pure water P. Then, the position adjustment of the first wafer 10 and the second wafer 20 is performed with high positional accuracy so that the device region 13 and the connection region 16 and the bonded region 31 correspond accurately. If it does so, the 1st wafer 10 and the 2nd wafer 20 can be joined appropriately after that. Moreover, in the first wafer 10, the first wafer 10 and the second wafer 20 can be appropriately bonded only by forming the device region 13 and the connection region 16 higher than the scribe line region 15. The bonding process between the first wafer 10 and the second wafer 20 can be simplified, and the processing cost of the bonding process can be reduced.
　なお、本実施の形態では１のウェハ１０のデバイス層１２にデバイス領域１３と接続領域１６が形成されているが、例えば接続領域１６が形成されていない場合でも、デバイス領域１３がスクライブライン領域より高く形成されていれば、上述した効果を享受することができる。 In the present embodiment, the device region 13 and the connection region 16 are formed in the device layer 12 of one wafer 10. For example, even when the connection region 16 is not formed, the device region 13 is more than the scribe line region. If it is formed high, the above-described effects can be enjoyed.
　また、第１のウェハ１０には隣り合うデバイス領域１３を接続する接続領域１６が形成されているので、純水Ｐを１回供給するだけで、複数のデバイス領域１３と複数の接続領域１６に純水Ｐを拡散させることができる。したがって、第１のウェハ１０と第２のウェハ２０の接合処理をより簡易化することができる。 Moreover, since the connection area | region 16 which connects the adjacent device area | region 13 is formed in the 1st wafer 10, only by supplying pure water P once, it is to the several device area | region 13 and the several connection area | region 16. Pure water P can be diffused. Therefore, the bonding process between the first wafer 10 and the second wafer 20 can be further simplified.
　また、第１のウェハ１０のデバイス領域１３及び接続領域１６の表面を活性化すると共に、第２のウェハ２０の被接合領域３１の表面を活性化しているので、第１のウェハ１０と第２のウェハ２０をより強固に接合することができる。 In addition, the surfaces of the device region 13 and the connection region 16 of the first wafer 10 are activated and the surface of the bonded region 31 of the second wafer 20 is activated. The wafer 20 can be bonded more firmly.
　さらに、このように第１のウェハ１０と第２のウェハ２０はその位置調整が正確に行われて接合されるので、その後第１のウェハ１０に貫通電極４０を形成する際にも、当該貫通電極４０を適切な位置に形成することができる。そうすると、半導体装置１００を適切に製造することができる。 Further, since the first wafer 10 and the second wafer 20 are thus accurately adjusted and bonded, the through-hole electrode 40 is formed when the through-hole electrode 40 is formed on the first wafer 10 thereafter. The electrode 40 can be formed at an appropriate position. Then, the semiconductor device 100 can be manufactured appropriately.
　また、本実施の形態では、第１のウェハ１０と第２のウェハ２０を接合するに際し、これら第１のウェハ１０と第２のウェハ２０を加熱する必要がない。このため、デバイス１３、２３が損傷を被るのを抑制することができ、デバイス１３、２３の信頼性を向上させることができる。 In the present embodiment, when the first wafer 10 and the second wafer 20 are bonded, it is not necessary to heat the first wafer 10 and the second wafer 20. Therefore, the devices 13 and 23 can be prevented from being damaged, and the reliability of the devices 13 and 23 can be improved.
　以上の実施の形態の第２のウェハ２０には、図２１に示すように当該第２のウェハ２０の被接合領域３１以外の領域に複数の空気孔１１０が形成されていてもよい。この空気孔１１０は、例えば被接合領域３１で閉じられた空間毎に形成される。なお、図２２に示すように第２のウェハ２０に設けられる支持ウェハ２７には、当該支持ウェハ２７を厚み方向に貫通し、且つ上記被接合領域３１で閉じられた空間に連通する空気孔１１１が形成されている。 In the second wafer 20 of the above embodiment, a plurality of air holes 110 may be formed in a region other than the bonded region 31 of the second wafer 20 as shown in FIG. For example, the air holes 110 are formed in each space closed in the bonded region 31. As shown in FIG. 22, the support wafer 27 provided on the second wafer 20 has an air hole 111 that penetrates the support wafer 27 in the thickness direction and communicates with the space closed by the bonded region 31. Is formed.
　これら複数の空気孔１１０は、図２３に示すように第２のウェハ２０の厚み方向に貫通して形成される。また、複数の空気孔１１０は、上述した工程Ｓ７における貫通孔２８と同時に形成され、すなわちフォトリソグラフィー処理及びエッチング処理によって同時に形成される。なお、第２のウェハ２０に対するその他の工程は、上述した工程Ｓ４～Ｓ６、Ｓ８～Ｓ１１と同様であるので説明を省略する。 The plurality of air holes 110 are formed so as to penetrate in the thickness direction of the second wafer 20 as shown in FIG. The plurality of air holes 110 are formed at the same time as the through holes 28 in the above-described step S7, that is, formed simultaneously by the photolithography process and the etching process. The other processes for the second wafer 20 are the same as the above-described processes S4 to S6 and S8 to S11, and thus description thereof is omitted.
　かかる場合、工程Ｓ１２において第１のウェハ１０に純水Ｐを供給した後、第２のウェハ２０を第１のウェハ１０のデバイス層１２側に配設する際、図２４に示すようにデバイス領域１３と被接合領域３１で閉じられた空間に存在する空気は、空気孔１１０、１１１を通って外部に排気される。このようにデバイス領域１３と被接合領域３１で閉じられた空間内の気圧を外気圧と同じく適切に維持できるので、その後の工程Ｓ１３における第１のウェハ１０と第２のウェハ２０の位置調整と、工程Ｓ１４における第１のウェハ１０と第２のウェハ２０の接合を適切に行うことができる。 In such a case, after supplying pure water P to the first wafer 10 in step S12, when the second wafer 20 is disposed on the device layer 12 side of the first wafer 10, as shown in FIG. 13 and the space closed by the joined region 31 are exhausted to the outside through the air holes 110 and 111. As described above, since the atmospheric pressure in the space closed by the device region 13 and the bonded region 31 can be maintained appropriately in the same manner as the external atmospheric pressure, the position adjustment of the first wafer 10 and the second wafer 20 in the subsequent step S13 is performed. The first wafer 10 and the second wafer 20 can be appropriately bonded in step S14.
　また、第１のウェハ１０と第２のウェハ２０の間に純水Ｐを充填すると、当該純水Ｐが気化する場合がある。かかる場合、純水Ｐの気化に伴い潜熱が発生し、デバイス領域１３と被接合領域３１で閉じられた空間内の空気が冷却される。そうすると、デバイス領域１３の側面に結露が発生してしまい、純水Ｐの表面張力による位置調整に悪影響を及ぼす恐れがある。この点、本実施の形態では空気孔１１０、１１１から空気が排気されるので、この結露を防止することができる。さらには、空気孔１１０、１１１からの排気を促進するために、第１のウェハ１０と第２のウェハ２０の周囲を減圧してもよい。 In addition, when pure water P is filled between the first wafer 10 and the second wafer 20, the pure water P may vaporize. In such a case, latent heat is generated as the pure water P is vaporized, and the air in the space closed by the device region 13 and the bonded region 31 is cooled. If it does so, condensation will generate | occur | produce on the side surface of the device area | region 13, and there exists a possibility of having a bad influence on the position adjustment by the surface tension of the pure water P. FIG. In this regard, in the present embodiment, since air is exhausted from the air holes 110 and 111, this condensation can be prevented. Furthermore, the periphery of the first wafer 10 and the second wafer 20 may be depressurized in order to promote exhaust from the air holes 110 and 111.
　以上の実施の形態では、第１のウェハ１０を相対的に下方に配置し、第２のウェハ２０を相対的に上方に配置した状態で、当該第１のウェハ１０と第２のウェハ２０を接合していたが、第１のウェハ１０と第２のウェハ２０の配置を反対にしてもよい。すなわち、第１のウェハ１０を相対的に上方に配置し、第２のウェハ２０を相対的にした方に配置した状態で、当該第１のウェハ１０と第２のウェハ２０を接合してもよい。 In the above embodiment, the first wafer 10 and the second wafer 20 are placed in a state where the first wafer 10 is disposed relatively downward and the second wafer 20 is disposed relatively upward. Although bonded, the arrangement of the first wafer 10 and the second wafer 20 may be reversed. That is, even when the first wafer 10 and the second wafer 20 are bonded in a state where the first wafer 10 is disposed relatively upward and the second wafer 20 is disposed relatively to the other. Good.
　かかる場合、工程Ｓ１３において、図２５に示すように純水Ｐは第２のウェハ２０の被接合領域３１上に供給される。その後工程Ｓ１４において、第１のウェハ１０と第２のウェハ２０との間に充填された純水Ｐの表面張力によって、図２６に示すように第１のウェハ１０を移動させる復元力（図２６の矢印）が第１のウェハ１０に作用する。こうして第１のウェハ１０と第２のウェハ２０の位置調整が行われる。その後工程Ｓ１４において、第１のウェハ１０と第２のウェハ２０が適切に接合される。 In such a case, in step S13, pure water P is supplied onto the bonded region 31 of the second wafer 20 as shown in FIG. Thereafter, in step S14, the restoring force (FIG. 26) moves the first wafer 10 as shown in FIG. 26 by the surface tension of the pure water P filled between the first wafer 10 and the second wafer 20. ) Acts on the first wafer 10. Thus, the position adjustment of the first wafer 10 and the second wafer 20 is performed. Thereafter, in step S14, the first wafer 10 and the second wafer 20 are appropriately bonded.
　本実施の形態においても、上記実施の形態と同様の効果を享受することができ、第１のウェハ１０と第２のウェハ２０を簡易且つ適切に接合することができる。 Also in the present embodiment, the same effects as those of the above-described embodiment can be obtained, and the first wafer 10 and the second wafer 20 can be simply and appropriately bonded.
　なお、本実施の形態においても、図２７に示すように第２のウェハ２０と支持ウェハ２７にそれぞれ空気孔１１０、１１１が形成されていてもよい。 In the present embodiment, air holes 110 and 111 may be formed in the second wafer 20 and the support wafer 27, respectively, as shown in FIG.
　以上の実施の形態の支持ウェハ２７は、図２８に示すように第１のウェハ１０と第２のウェハ２０の鉛直方向の相対位置を調整するための位置調整機構としての昇降機構１２０を有していてもよい。昇降機構１２０は、第１のウェハ１０と第２のウェハ２０の外周部に複数設けられている。昇降機構１２０は、支持ウェハ２７の表面から鉛直下方に延伸し、さらに屈曲して、第１のウェハ１０と第２のウェハ２０の間に位置するように水平方向に延伸している。また、昇降機構１２０の鉛直方向に延伸する部分には、例えば伸縮自在の昇降ピンが用いられる。 The support wafer 27 of the above embodiment has an elevating mechanism 120 as a position adjustment mechanism for adjusting the vertical relative positions of the first wafer 10 and the second wafer 20 as shown in FIG. It may be. A plurality of lifting mechanisms 120 are provided on the outer peripheral portions of the first wafer 10 and the second wafer 20. The elevating mechanism 120 extends vertically downward from the surface of the support wafer 27, bends further, and extends in the horizontal direction so as to be positioned between the first wafer 10 and the second wafer 20. In addition, for example, a telescopic lifting pin is used for a portion extending in the vertical direction of the lifting mechanism 120.
　かかる場合、工程Ｓ１３において第１のウェハ１０のデバイス層１２側に第２のウェハ２０を配設する際、第１のウェハ１０と第２のウェハ２０との間を昇降機構１２０によって支持する。そして、昇降機構１２０によって、第１のウェハ１０と第２のウェハ２０間の間隔を適切な間隔に維持する。この段階では第２のウェハ２０は昇降機構１２０に支えられているので、昇降機構１２０がない場合に比べて、より精密に水平な状態を維持することができる。次に昇降機構１２０の縮小を開始する。昇降機構１２０の縮小が開始されると、第２のウェハ２０は、工程Ｓ１２で第１のウェハ１０上に供給された純水Ｐのみで支えられる状態になり、工程Ｓ１３における第１のウェハ１０と第２のウェハ２０の位置調整が進行する。その後、工程Ｓ１４において第１のウェハ１０と第２のウェハ２０が接合される。 In such a case, when the second wafer 20 is disposed on the device layer 12 side of the first wafer 10 in step S13, the lifting mechanism 120 supports the space between the first wafer 10 and the second wafer 20. And the space | interval between the 1st wafer 10 and the 2nd wafer 20 is maintained by the raising / lowering mechanism 120 at a suitable space | interval. At this stage, since the second wafer 20 is supported by the elevating mechanism 120, the level state can be maintained more precisely than when the elevating mechanism 120 is not provided. Next, the elevating mechanism 120 starts to be reduced. When the elevating mechanism 120 starts to be reduced, the second wafer 20 is supported only by the pure water P supplied onto the first wafer 10 in step S12, and the first wafer 10 in step S13. Then, the position adjustment of the second wafer 20 proceeds. Thereafter, in step S14, the first wafer 10 and the second wafer 20 are bonded.
　本実施の形態によれば、昇降機構１２０によって第１のウェハ１０と第２のウェハ２０間の間隔を適切な間隔に制御できるので、第１のウェハ１０と第２のウェハ２０の位置調整と接合処理を適切に行うことができる。また、第１のウェハ１０と第２のウェハ２０間の間隔が微小で、且つ第２のウェハ２０と支持ウェハ２７の自重が大きいと、純水Ｐだけでは間隔を適切に維持できない場合がある。かかる場合において、昇降機構１２０によって第１のウェハ１０と第２のウェハ２０間の間隔を物理的に維持することができる本実施の形態は特に有用である。 According to the present embodiment, since the interval between the first wafer 10 and the second wafer 20 can be controlled to an appropriate interval by the lifting mechanism 120, the position adjustment of the first wafer 10 and the second wafer 20 can be performed. A joining process can be performed appropriately. Further, if the distance between the first wafer 10 and the second wafer 20 is very small and the weight of the second wafer 20 and the support wafer 27 is large, the distance may not be properly maintained with pure water P alone. . In this case, the present embodiment in which the distance between the first wafer 10 and the second wafer 20 can be physically maintained by the elevating mechanism 120 is particularly useful.
　なお昇降機構１２０の構成は、上記実施の形態に限定されず、種々の構成を取り得る。例えば図２９に示すように昇降機構１２０は、第１のウェハ１０と第２のウェハ２０の外周部において、支持ウェハ２７の表面から鉛直方向に延伸する構成であってもよい。この昇降機構１２０にも、例えば伸縮自在の昇降ピンが用いられる。そして昇降機構１２０は、その端部が第１のウェハ１０を載置する載置台１２１に支持されるようになっている。 In addition, the structure of the raising / lowering mechanism 120 is not limited to the said embodiment, A various structure can be taken. For example, as shown in FIG. 29, the lifting mechanism 120 may be configured to extend in the vertical direction from the surface of the support wafer 27 at the outer peripheral portions of the first wafer 10 and the second wafer 20. For the elevating mechanism 120, for example, a telescopic elevating pin is used. The lifting mechanism 120 is supported at its end by a mounting table 121 on which the first wafer 10 is mounted.
　かかる場合でも、上記実施の形態と同様に昇降機構１２０によって第１のウェハ１０と第２のウェハ２０間の間隔を適切な間隔に制御でき、第１のウェハ１０と第２のウェハ２０の位置調整と接合処理を適切に行うことができる。 Even in such a case, the distance between the first wafer 10 and the second wafer 20 can be controlled to an appropriate distance by the elevating mechanism 120 as in the above embodiment, and the position of the first wafer 10 and the second wafer 20 can be controlled. Adjustment and joining processing can be performed appropriately.
　以上、添付図面を参照しながら本発明の好適な実施の形態について説明したが、本発明はかかる例に限定されない。当業者であれば、特許請求の範囲に記載された思想の範疇内において、各種の変更例または修正例に想到し得ることは明らかであり、それらについても当然に本発明の技術的範囲に属するものと了解される。本発明はこの例に限らず種々の態様を採りうるものである。 The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious for those skilled in the art that various modifications or modifications can be conceived within the scope of the idea described in the claims, and these naturally belong to the technical scope of the present invention. It is understood. The present invention is not limited to this example and can take various forms.
　　１０　第１のウェハ
　　１１　バルク層
　　１２　デバイス層
　　１３　デバイス（デバイス領域）
　　１５　スクライブライン（スクライブライン領域）
　　１６　接続領域
　　２０　第２のウェハ
　　２１　バルク層
　　２２　デバイス層
　　２３　デバイス（デバイス領域）
　　２５　スクライブライン（スクライブライン領域）
　　２７　支持ウェハ
　　２８　貫通孔
　　２９　貫通電極
　　３０　絶縁膜
　　３１　被接合領域
　　４０　貫通電極
　　１００　半導体装置
　　１１０　空気孔
　　１１１　空気孔
　　１２０　昇降機構
　　Ｐ　　純水 DESCRIPTION OF SYMBOLS 10 1st wafer 11 Bulk layer 12 Device layer 13 Device (device area)
15 Scribe line (scribe line area)
16 Connection region 20 Second wafer 21 Bulk layer 22 Device layer 23 Device (device region)
25 Scribe line (scribe line area)
27 Support wafer 28 Through hole 29 Through electrode 30 Insulating film 31 Bonded region 40 Through electrode 100 Semiconductor device 110 Air hole 111 Air hole 120 Lifting mechanism P Pure water

Claims (15)

  1. 複数の半導体デバイスが形成された第１の基板と、複数の半導体デバイスが形成された第２の基板とを接合する基板の接合方法であって、
    前記第１の基板の前記複数の半導体デバイスが形成される面において、当該複数の半導体デバイスを形成し、各半導体デバイスの間のスクライブラインとなる領域よりも高くされた半導体デバイス領域を形成する第１の工程と、
    前記第２の基板の前記第１の基板と接合される面において、前記半導体デバイス領域に対応する領域を親水化し、被接合領域を形成する第２の工程と、
    前記半導体デバイス領域と前記被接合領域との間に処理液を供給し、前記第１の基板と前記第２の基板とを接合する第３の工程と、を有する。     A substrate bonding method for bonding a first substrate on which a plurality of semiconductor devices are formed and a second substrate on which a plurality of semiconductor devices are formed,
    Forming a plurality of semiconductor devices on a surface of the first substrate on which the plurality of semiconductor devices are formed, and forming a semiconductor device region higher than a region that becomes a scribe line between the semiconductor devices; 1 process,
    A second step of hydrophilizing a region corresponding to the semiconductor device region on a surface of the second substrate to be bonded to the first substrate to form a bonded region;
    And a third step of supplying a processing liquid between the semiconductor device region and the bonded region to bond the first substrate and the second substrate.
  2. 請求項１に記載の基板の接合方法であって、
    前記第２の基板の前記第１の基板と接合される面は、前記複数の半導体デバイスが形成されていない面であって、
    前記第３の工程の後に、前記第１の基板の前記半導体デバイスに貫通電極を形成する第４の工程を有する。     A method for bonding substrates according to claim 1, comprising:
    The surface bonded to the first substrate of the second substrate is a surface on which the plurality of semiconductor devices are not formed,
    After the third step, there is a fourth step of forming a through electrode in the semiconductor device of the first substrate.
  3. 請求項１に記載の基板の接合方法であって、
    前記第１の工程において、前記スクライブラインとなる領域には、隣り合う前記半導体デバイス領域と同じ高さを有し、且つ当該隣り合う半導体デバイス領域を接続する接続領域を形成する。     A method for bonding substrates according to claim 1, comprising:
    In the first step, a connection region that has the same height as the adjacent semiconductor device region and connects the adjacent semiconductor device regions is formed in the region to be the scribe line.
  4. 請求項１に記載の基板の接合方法であって、
    前記第２の工程の前に、前記第２の基板の被接合領域以外の領域において、当該第２の基板の厚み方向に貫通する空気孔を形成する。     A method for bonding substrates according to claim 1, comprising:
    Prior to the second step, an air hole penetrating in the thickness direction of the second substrate is formed in a region other than the bonded region of the second substrate.
  5. 請求項１に記載の基板の接合方法であって、
    前記処理液は純水である。     A method for bonding substrates according to claim 1, comprising:
    The treatment liquid is pure water.
  6. 請求項１に記載の基板の接合方法であって、
    前記第１の工程の後であって前記第３の工程の前に、前記半導体デバイス領域の表面を活性化し、
    前記第２の工程の後であって前記第３の工程の前に、前記被接合領域の表面を活性化する。     A method for bonding substrates according to claim 1, comprising:
    Activating the surface of the semiconductor device region after the first step and before the third step;
    After the second step and before the third step, the surface of the bonded region is activated.
  7. 請求項６に記載の基板の接合方法であって、
    前記半導体デバイスの表面の活性化と前記被接合領域の表面の活性化は、それぞれアンモニアによって行われる。     A method for bonding substrates according to claim 6, comprising:
    The activation of the surface of the semiconductor device and the activation of the surface of the bonded region are each performed by ammonia.
  8. 請求項１に記載の基板の接合方法であって、
    前記第３の工程において、第１の基板と第２の基板の相対位置を調整するための位置調整機構を用いて、第１の基板と第２の基板との間を所定の間隔に維持する。     A method for bonding substrates according to claim 1, comprising:
    In the third step, a position adjustment mechanism for adjusting a relative position between the first substrate and the second substrate is used to maintain a predetermined distance between the first substrate and the second substrate. .
  9. 複数の半導体デバイスが形成された基板が複数層に接合された半導体装置であって、
    前記複数の半導体デバイスが形成される面において、各半導体デバイスの間のスクライブラインとなる領域よりも高くされた半導体デバイス領域が形成された第１の基板と、
    前記第１の基板と接合される面において、前記半導体デバイス領域に対応する領域が親水化され、被接合領域が形成された第２の基板と、を有し、
    前記半導体デバイス領域と前記被接合領域との間に処理液が供給されて、前記第１の基板と前記第２の基板とが接合されている。     A semiconductor device in which a substrate on which a plurality of semiconductor devices are formed is bonded to a plurality of layers,
    A first substrate having a semiconductor device region formed higher than a region to be a scribe line between the semiconductor devices on a surface on which the plurality of semiconductor devices are formed;
    A surface bonded to the first substrate, a region corresponding to the semiconductor device region is hydrophilized, and a second substrate on which a bonded region is formed;
    A processing liquid is supplied between the semiconductor device region and the bonded region, and the first substrate and the second substrate are bonded.
  10. 請求項９に記載の半導体装置であって、
    前記第１の基板において、前記スクライブラインとなる領域には、隣り合う前記半導体デバイス領域と同じ高さを有し、且つ当該隣り合う半導体デバイス領域を接続する接続領域が形成されている。     The semiconductor device according to claim 9,
    In the first substrate, a connection region that has the same height as the adjacent semiconductor device region and connects the adjacent semiconductor device regions is formed in the region to be the scribe line.
  11. 請求項９に記載の半導体装置であって、
    前記第２の基板の被接合領域以外の領域において、当該第２の基板の厚み方向に貫通する空気孔が形成されている。     The semiconductor device according to claim 9,
    An air hole penetrating in the thickness direction of the second substrate is formed in a region other than the bonded region of the second substrate.
  12. 請求項９に記載の半導体装置であって、
    前記処理液は純水である。     The semiconductor device according to claim 9,
    The treatment liquid is pure water.
  13. 請求項９に記載の半導体装置であって、
    前記半導体デバイス領域の表面と前記被接合領域の表面は、それぞれ活性化されている。     The semiconductor device according to claim 9,
    The surface of the semiconductor device region and the surface of the bonded region are each activated.
  14. 請求項１３に記載の半導体装置であって、
    前記半導体デバイスの表面の活性化と前記被接合領域の表面の活性化は、それぞれアンモニアによって行われる。     The semiconductor device according to claim 13,
    The activation of the surface of the semiconductor device and the activation of the surface of the bonded region are each performed by ammonia.
  15. 請求項９に記載の半導体装置であって、
    前記半導体デバイス領域と前記被接合領域との間に処理液が供給されて、前記第１の基板と前記第２の基板とが接合される際、第１の基板と第２の基板の間を所定の間隔に維持する位置調整機構が用いられる。     The semiconductor device according to claim 9,
    When a processing liquid is supplied between the semiconductor device region and the bonded region, and the first substrate and the second substrate are bonded, a gap between the first substrate and the second substrate is obtained. A position adjustment mechanism that maintains a predetermined interval is used.
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KR102178872B1 (en) * 2018-10-31 2020-11-13 세메스 주식회사 Apparatus and method of bonding die or substrate, apparatus and method for driving jetting head

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