WO2013128831A1

WO2013128831A1 - Solid-state image pickup device

Info

Publication number: WO2013128831A1
Application number: PCT/JP2013/000854
Authority: WO
Inventors: 楠田　将之
Original assignee: コニカミノルタ株式会社
Priority date: 2012-02-29
Filing date: 2013-02-15
Publication date: 2013-09-06
Also published as: JP5454741B1; JPWO2013128831A1

Abstract

At a time (t5) after an ordinary exposure output, a charge is injected to a PD. At a time (t6), a φTX is kept at an intermediate potential, and the charge of the PD gradually leaks to an FD side. At a time (t7), the potential of the FD is read, as a noise component signal, by a column ADC. At a time (t8), the signal charge stored in the PD is transferred to the FD. At a time (t9), the potential of the FD is read, as a noise signal component signal, by the column ADC. M white resets having the same PD leakage time (where M is an integer equal to or greater than two) are implemented, and the column ADC averages the signal.

Description

Solid-state imaging device

The present invention relates to a solid-state imaging device having a linear log characteristic in which a linear characteristic and a log characteristic are switched at an inflection point.

In recent years, in order to expand the dynamic range, a solid-state imaging device having a linear characteristic on the low luminance side and a log characteristic on the high luminance side at the inflection point is known. Such photoelectric conversion characteristics are called linear log characteristics, and for example, Patent Document 1 is known. Hereinafter, in the linear log characteristics, an area having linear characteristics is described as a linear area, and an area having log characteristics is described as a log area.

Such a solid-state imaging device includes a photoelectric conversion element exhibiting linear log characteristics, a transfer transistor connected to the photoelectric conversion element, a floating diffusion layer connected to the transfer transistor, and a reset transistor having a source connected to the floating diffusion layer. And a pixel section having amplifying transistors that amplify the voltage of the floating diffusion layer and output the pixel signal as a pixel signal. Japanese Patent Application Laid-Open No. 2004-26883 discloses an image pickup apparatus drive that can observe an inflection point position of a linear log characteristic and an inclination of the log characteristic in real time by injecting a charge from the drain of the reset transistor to the photoelectric conversion element (white reset). A method is described.

In Patent Document 3, N-bit analog / digital conversion processing is repeatedly performed W times for each of a reset signal indicating a noise component of a pixel signal and a signal signal indicating a noise component and a signal component, and these are added. A technique for reducing random noise by performing digital addition processing is described.

However, in the technique described in Patent Document 2, it is necessary to remove random noise included in the pixel signal output at the time of white reset in order to increase the effect of correcting the variation of the pixel signal. In particular, since the inclination detection of the log characteristic is performed using the output difference between the two white resets, the noise component included in the pixel signal output at the time of the white reset has a large influence.

Also, Patent Document 3 describes a method for reducing random noise during AD conversion of a pixel signal, but does not describe white reset.

JP 2006-50544 A JP 2006-140666 A JP 2009-296423 A

An object of the present invention is to provide a solid-state imaging device in which random noise included in a white reset output is reduced without increasing the circuit scale.

A solid-state imaging device according to one aspect of the present invention includes a photoelectric conversion element in which a low luminance side exhibits linear characteristics and a high luminance side exhibits log characteristics at an inflection point, a transfer transistor connected to the photoelectric conversion element, A pixel having a floating diffusion layer connected to a transfer transistor, a control transistor and a reset transistor connected between the floating diffusion layer, and an amplification transistor that amplifies the voltage of the floating diffusion layer and outputs it as a pixel signal The pixel array unit in which circuits are arranged in a matrix and the control voltage are set, and the voltages of the control terminals of the reset transistor and the transfer transistor are set to control on / off of the reset transistor and the transfer transistor. The control unit, and a reading unit that is provided for each column of the pixel unit and reads out the pixel signal, the control unit Then, after the pixel signal obtained by exposing the subject with the control terminal of the transfer transistor set to an intermediate potential is read as a normal pixel signal to the reading unit, (1) the control voltage is set to the photoelectric By setting the voltage at which charge can be injected into the conversion element, charge is injected into the photoelectric conversion element via the reset transistor. (2) Next, the control terminal of the transfer transistor is turned on for a predetermined time. By setting the intermediate potential, the charge injected into the photoelectric conversion element is leaked. (3) Next, the reading unit is controlled to read out the pixel signal as a white reset signal. (4) Next In addition, the steps (1) to (3) are repeated M times (M is an integer of 2 or more), and the reading unit calculates the average value of the read M white reset signals.

The block diagram which shows the structure of a solid-state imaging device and an external device. The block diagram which shows the structure of a solid-state image sensor. The circuit diagram of a pixel. Pixel timing chart. Photoelectric conversion characteristics during normal exposure output of pixels. Photoelectric conversion characteristics during pixel white reset. 6 is a timing chart illustrating pixel driving and column ADC operations according to the first embodiment. 9 is a timing chart illustrating pixel driving and column ADC operations according to the second embodiment.

[First Embodiment]
FIG. 1 is a block diagram showing an overall configuration of a solid-state imaging device 1 according to an embodiment of the present invention. A solid-state imaging device 1 illustrated in FIG. 1 is a solid-state imaging device having a photoelectric conversion characteristic of a linear log characteristic in which a linear characteristic and a log characteristic are switched at an inflection point. Specifically, the solid-state imaging device 1 according to the present embodiment is a solid-state imaging device having a linear log characteristic photoelectric conversion characteristic having a linear characteristic on the low luminance side and a log characteristic on the high luminance side from the inflection point.

The solid-state imaging device 1 includes an imaging element 110 and an image processing unit 120. The image sensor 110 and the image processing unit 120 may be configured in one IC chip or may be configured as separate IC chips.

The image processing unit 120 includes an image signal processing unit 121 and an image sensor control unit 122. The image sensor control unit 122 outputs SYSCLK and the register control signal to the image sensor 110 to control the image sensor 110. SYSCLK is a clock signal having a predetermined frequency (for example, 54 MHz) generated by an oscillation circuit (not shown), for example. The register control signal is a signal for writing data to various registers included in the timing control unit 22 shown in FIG.

The image sensor 110 outputs an image signal to the image signal processing unit 121. The image signal processing unit 121 performs various image processing on the image signal and outputs the image signal as an image output signal to an external device. Here, the external device corresponds to a display device such as a liquid crystal panel or an organic EL panel, a memory for holding an image output signal, or the like.

FIG. 2 is a block diagram showing a detailed configuration of the image sensor 110 shown in FIG. The image sensor 110 includes a pixel array unit 21, a timing control unit 22, a row decoder 23, a column ADC array unit 24 (reading unit), a column decoder 25, a sense amplifier 26, an LVDS serializer 27, an output terminal 28, and a ramp wave generation circuit 29. (Reference signal generator) and

input terminals

210 and 211 are provided.

The pixel array unit 21 includes a plurality of pixels GC arranged in a matrix with M (an integer of 2 or more) rows × N (an integer of 2 or more) columns.

The timing control unit 22 includes a PLL, a timing generator (TG), and a register, and controls the row decoder 23, the column ADC array unit 24, the column decoder 25, the sense amplifier 26, the LVDS serializer 27, and the ramp wave generation circuit 29. The PLL multiplies (for example, doubles) SYSCLK as necessary and supplies it to the TG. The TG generates timing signals such as a horizontal synchronization signal and a vertical synchronization signal according to the signal supplied from the PLL, and generates a row decoder 23, a column ADC array unit 24, a column decoder 25, a sense amplifier 26, an LVDS serializer 27, and a ramp wave. The circuit 29 is supplied to synchronize these operations.

The register holds data for defining waveforms of various pixel control signals output to each pixel by the row decoder 23, for example. Here, data held by the register is written by a register control signal output from the image sensor control unit 122.

The row decoder 23 includes, for example, a vertical scanning circuit and a driver circuit. The vertical scanning circuit is configured by, for example, a shift register, and cyclically selects each row of the pixel array unit 21 using a vertical synchronization signal output from the TG of the timing control unit 22 as a trigger, and vertically scans the pixel array unit 21. To do. The driver circuit generates a pixel control signal according to the data written in the register of the timing control unit 22, and drives each pixel GC by supplying the pixel control signal to each pixel GC. Here, the timing control unit 22 and the row decoder 23 correspond to the control unit in the present invention.

The column ADC array unit 24 includes N column ADCs 212 corresponding to the respective columns of the pixel array unit 21. The column ADC 212 is connected to the pixel GC of each column via the vertical signal line L_1 corresponding to each column of the pixel array unit 21, and reads the pixel signal from the pixel GC of the row selected by the vertical scanning circuit.

Each pixel of the pixel array unit 21 outputs a pixel signal composed of only a noise component and a pixel signal obtained by adding a signal component to the noise component in one horizontal period. Here, a pixel signal including only a noise component is described as a noise component signal, and a pixel signal obtained by adding a signal component to the noise component is described as a noise / signal component signal.

When an analog pixel signal is input from the pixel GC, the column ADC 212 performs AD conversion by counting time until the level of the ramp signal output from the ramp wave generation circuit 29 exceeds the level of the pixel signal. This is a single slope AD converter.

The column decoder 25 is constituted by, for example, a shift register, and cyclically selects the column ADC 212 of each column in one horizontal scanning period by outputting a column selection signal synchronized with the horizontal synchronization signal. As a result, the column ADC array unit 24 is horizontally scanned, and digital image signals held by the column ADC 212 of each column are sequentially output to the sense amplifier 26.

The sense amplifier 26 amplifies a digital image signal output from the column ADC array unit 24 via the horizontal signal line L_2 and outputs the amplified signal to the LVDS serializer 27.

The LVDS serializer 27 is a serializer compliant with the LVDS (Low Voltage differential signaling) standard, and differentially amplifies a signal output in parallel via the horizontal signal line L_2 from the sense amplifier 26 to obtain a predetermined bit signal. And output to the output terminal 28.

The output terminal 28 outputs the image signal from the LVDS serializer 27 to the image signal processing unit 121.

The ramp wave generation circuit 29 generates a ramp signal that changes linearly with a certain inclination and outputs the ramp signal to the column ADC 212.

The input terminal 210 receives SYSCLK supplied from the image sensor control unit 122 and outputs it to the timing control unit 22. The input terminal 211 receives a register control signal supplied from the image sensor control unit 122 and outputs the register control signal to the timing control unit 22.

FIG. 3 is a circuit diagram showing an example of the pixel GC constituting the pixel array unit 21. The pixel circuit shown in FIG. 3 includes a light receiving element (hereinafter referred to as “PD”), a transfer transistor TX (hereinafter referred to as “TX”), a reset transistor RST (hereinafter referred to as “RST”), and amplification. A transistor SF (hereinafter referred to as “SF”), a row selection transistor SEL (hereinafter referred to as “SEL”), and a floating diffusion layer FD (hereinafter referred to as “FD”; FD: Floating Diffusion) are provided. Yes.

PD is composed of a buried (complete transfer type) photodiode, a drive voltage PVSS is applied to the anode, and TX is connected to the cathode. The electric charge accumulated in the PD is transferred to the FD via TX.

TX is composed of, for example, an nMOS (negative channel, metal, oxide, semiconductor), and transfers signal charges accumulated in the PD to the FD. A transfer control signal φTX (an example of a pixel control signal, hereinafter referred to as “φTX”) for turning on / off TX is input to the gate of TX. The drain of TX is connected to RST via FD. When φTX becomes a low level (hereinafter referred to as “Lo”), TX is turned off, and when φTX becomes a high level (hereinafter referred to as “Hi”), TX is turned on. Note that φTX is output from the row decoder 23.

FD accumulates signal charges transferred from PD. As a result, a voltage corresponding to the signal charge appears in the FD.

RST is composed of, for example, an nMOS, resets the FD, and discharges signal charges accumulated in the FD to the outside of the FD. A reset signal φRST (an example of a pixel control signal, hereinafter referred to as “φRST”) for turning on / off RST is input to the gate of RST, and φRD (control voltage, hereinafter referred to as “φRD”) is described as a drain. And the source is connected to the gate of the SF through the FD. RST is turned on when φRST = Hi, and FD is set to the potential of φRD. The RST is turned off when φRST = Lo.

Note that PVDD and PVSS are output from a voltage source (not shown), and φRST and φRD are output from the row decoder 23.

SF is composed of, for example, an nMOS, the gate is connected to TX and RST via FD, PVDD is input to the drain, and the source is connected to SEL. The SF amplifies the voltage appearing on the FD and outputs it to the SEL.

The SEL is composed of, for example, an nMOS, and a row selection signal φVSEN (an example of a pixel control signal, hereinafter referred to as “φVSEN”) is input to a gate, a drain is connected to SF, and a source is connected via a vertical signal line L_1. Are connected to the column ADC 212 of the corresponding row. The SEL outputs the voltage amplified by the SF as an image signal to the column ADC 212 in the corresponding column via the vertical signal line L_1. Here, φVSEN is output from the row decoder 23.

FIG. 4 is a timing chart of the pixel GC in the present embodiment. At time t0, φTX is an intermediate potential and the exposure time is linear log characteristics. Since φRD = Hi and φRST = Hi, FD is always reset to PVDD.

And when φRST becomes Lo, the voltage of the FD decreases from the reset level V_PVDD to the noise level. This is because signal charges are generated in the FD due to the influence of the parasitic capacitance between the FD and RST, the ktc noise of the FD, and the like due to the change of φRST from Hi to Lo. Since such parasitic capacitance between FD and RST and ktc noise vary from pixel to pixel, the noise level varies from pixel to pixel. The reset level V_PVDD indicates the level of PVDD.

At time t1, φVSEN = Hi is set, and the potential (noise level) of FD is read to the column ADC 212 as a noise component signal. The column ADC 212 performs AD conversion on the analog noise component signal by counting the time until the level of the signal RAMP exceeds the level of the noise component signal.

At time t2, φTX = Hi, and the signal charge stored in the PD is transferred to the FD. Therefore, at time t2, the potential of FD decreases from the noise level to the signal level according to the signal charge amount transferred from the PD.

At time t3, φTX = Lo, and the potential (signal level) of FD is read to the column ADC 212 as a noise signal component signal. The column ADC 212 performs AD conversion on the analog noise signal component signal by counting the time until the level of the signal RAMP output from the ramp wave generation circuit 29 exceeds the level of the noise signal component signal.

The column ADC 212 removes the digital noise component signal from the digital noise signal component signal and outputs the digital signal component signal as an image signal. At time t4, φRST = Hi, and the FD is reset. The drive sequence shown at times t0 to t4 is for normal exposure.

After the time t5, it is a white reset period. First, at time t5, φRD = Lo, φRST = Hi, φTX = Hi, and charges are injected from φRD into FD and PD. Normally, speaking of resetting, the charge of the PD is emptied (that is, black reset), but at time t5, the operation of filling the PD with the charge is performed, and this operation is called “white reset”. .

At time t6, φRD = Hi, and φTX is set to an intermediate potential. As a result, the PD charge gradually leaks to the FD side. When the PD leak time during which φTX is an intermediate potential is made infinitely long, the PD has a charge up to the potential barrier of the transfer transistor, that is, a charge amount indicating the inflection point output of the pixel GC. However, even if the PD leakage time is not infinitely long, the charge remaining in the PD after securing a certain amount of PD leakage time indicates the potential barrier of the transfer transistor of each pixel GC.

At time t7, φVSEN = Hi, and the potential (noise level) of FD is read to the column ADC 212 as a noise component signal. The column ADC 212 AD converts the analog noise component signal.

At time t8, φTX = Hi, and the signal charge accumulated in the PD is transferred to the FD. Therefore, at time t8, the potential of the FD decreases from the noise level to the signal level according to the signal charge amount transferred from the PD.

At time t9, φTX = Lo, and the potential (signal level) of FD is read to the column ADC 212 as a noise signal component signal. The column ADC 212 AD converts the analog noise signal component signal.

Here, the reason why the signal RAMP used when the column ADC 212 AD converts the noise signal component signal between the normal exposure output and the white reset output will be described. The signal RAMP shown at time t3, which is the normal exposure output time, has a waveform in which the voltage decreases with a predetermined gradient from the voltage V1 to the voltage V3. On the other hand, the signal RAMP shown at time t9 at the time of white reset output has a waveform in which the voltage decreases with a predetermined gradient from the voltage V2 to the voltage V3. Here, V1> V2> V3, and the voltage V2 is an offset value.

FIG. 5 shows the photoelectric conversion characteristics at the time of normal exposure output of the pixel GC. In addition to the sensor output changing depending on the amount of incident light, there is an inflection point variation for each pixel GC. For this reason, the output of the log area varies for each pixel GC. Therefore, when AD converting the noise / signal component signal of the normal exposure output, it is necessary to set the voltage range of the signal RAMP so as to include the entire output range of the pixel GC.

FIG. 6 is a photoelectric conversion characteristic at the time of white reset output of the pixel GC. Ideally, the white reset output does not depend on the amount of incident light, and an output corresponding to the inflection point position of each pixel GC is always obtained. The output width that the white reset output can take corresponds to the inflection point variation of each pixel GC. Therefore, it is not necessary to prepare a signal RAMP that includes the entire output range of the pixel GC as in normal exposure output, and it is sufficient to prepare a signal RAMP that can include inflection point variations. By doing so, the column ADC 212 has a narrow scan range of the signal RAMP, and therefore, the AD conversion time at the time of white reset output can be shortened. The white reset can be performed a plurality of times using the shortened time.

Returning to FIG. 4, after the white reset sequence WR1a shown at times t4 to t10, a white reset sequence WR1b (times t10 to t16) having the same PD leak time is performed. Thereafter, a white reset sequence WR2a (time t16 to t22) and a white reset sequence WR2b (time t22 to t28) having different PD leak times from the first white reset are performed. The white reset sequences WR2a and WR2b have the same PD leak time. The reason why white reset with different PD leak times is performed is to correct variation in log inclination in addition to variation in inflection points.

Note that one sequence constituted by the white reset sequences WR1a and WR1b corresponds to a unit sequence. Further, one sequence composed of the white reset sequences WR2a and WR2b corresponds to a unit sequence. Here, two types of unit sequences with different leak times are illustrated as unit sequences, but the present invention is not limited to this, and three or more types of unit sequences with different leak times may be executed.

FIG. 7 is a timing chart showing the pixel driving and the operation of the column ADC 212 in the present embodiment. First, the column ADC 212 reads out the noise component signal (Ref) at the time of normal exposure (S1), performs AD conversion (S2), and holds the converted digital data in the memory in the column ADC 212 (S3). Subsequently, the noise signal component signal (Signal) is read out (S4) and AD converted (S5), and the converted digital data is held in the memory (S6). Then, the column ADC 212 performs CDS by taking the difference between the digital Ref and Signal (S7). The data after the CDS is accumulated in the memory in the column ADC 212 (S8).

Next, after white reset and PD leak are performed, the column ADC 212 reads the noise component signal (WR1a_R) (S9), performs AD conversion (S10), and holds the converted digital data in the memory in the column ADC 212 (S11). Subsequently, the noise signal component signal (WR1a_S) is read out (S12) and AD converted (S13), and the converted digital data is held in the memory (S14). The column ADC 212 performs CDS by taking the difference between the digital WR1a_R and WR1a_S (S15). The post-CDS data (WR1a) is held in the memory in the column ADC 212 (S16).

Subsequently, after white reset and PD leak are similarly performed, the column ADC 212 reads the noise component signal (WR1b_R) (S17) and performs AD conversion (S18), and the converted digital data is stored in the memory in the column ADC 212. (S19). Subsequently, the noise signal component signal (WR1b_S) is read out (S20) and AD converted (S21), and the converted digital data is held in the memory (S22). The column ADC 212 performs CDS by taking the difference between the digital WR1b_R and WR1b_S (S23). The post-CDS data (WR1b) is held in the memory in the column ADC 212 (S24). Thereafter, the column ADC 212 calculates an average value (WR1) of WR1a and WR1b, which is data after CDS (S25), and holds it in the memory in the column ADC 212 (S26).

Next, after a white leak and a PD leak with different PD leak times from the first and second PD leaks, the column ADC 212 reads the noise component signal (WR2a_R) (S27) and performs AD conversion (S28). The converted digital data is held in the memory in the column ADC 212 (S29). Subsequently, the noise signal component signal (WR2a_S) is read out (S30) and AD converted (S31), and the converted digital data is held in the memory (S32). Then, the column ADC 212 performs CDS by taking the difference between the digital WR2a_R and WR2a_S (S33). The post-CDS data (WR2a) is held in the memory in the column ADC 212 (S34).

Subsequently, after white reset and PD leak are similarly performed, the column ADC 212 reads out the noise component signal (WR2b_R) (S35) and performs AD conversion (S36), and the converted digital data is stored in the memory in the column ADC 212. (S37). Subsequently, the noise signal component signal (WR2b_S) is read out (S38) and subjected to AD conversion (S39), and the converted digital data is held in the memory (S40). Then, the column ADC 212 performs CDS by taking the difference between the digital WR2b_R and WR2b_S (S41). The post-CDS data (WR2b) is held in the memory in the column ADC 212 (S42). Thereafter, the column ADC 212 obtains an average value (WR2) of WR1a and WR2b, which is data after CDS (S43), and holds it in the memory in the column ADC 212 (S44).

By using the white reset output obtained in this way, the image signal processing unit 121 corrects the pixel signal obtained during the normal exposure, so that noise such as inflection point variation and log inclination variation in the pixel signal is corrected. It can be corrected.

As described above, random noise included in the white reset output can be reduced by continuously performing the white reset with the same PD leak time twice and averaging each white reset output. Furthermore, by performing white reset with different PD leak times a plurality of times, it is possible to correct variations in inflection points and log inclinations of pixel signals obtained by normal exposure.

Furthermore, by setting the signal RAMP at the time of white reset output to a waveform having an offset, the time required for AD conversion at the time of white reset output can be shortened. Therefore, a plurality of white resets can be performed in one horizontal scan.

In the present embodiment, the white reset with the same PD leak time is performed twice, but is not limited to twice. The effect of reducing random noise increases as the number of white resets increases. In a simple calculation, if the white reset is performed M times (M is an integer of 2 or more) and averaging is performed, the random noise becomes 1 / √M.

In addition, although the pixel GC has been described as using an embedded PD, it may be configured by a surface PD.

Furthermore, although the present embodiment has been described using a single slope type as the method of the column ADC 212, an ADC method other than the single slope type may be used.

[Second Embodiment]
In the first embodiment, the digital data after AD conversion is averaged at all white reset outputs. In the second embodiment, the CDS of white reset output and the averaging process are performed using analog values, and AD conversion is performed only on the averaged values. Note that the structure of the solid-state imaging device 1 and the imaging element 110, the circuit diagram of the pixel GC, and the timing chart of the pixel GC in the second embodiment are the same as those in FIGS.

FIG. 8 is a timing chart showing the pixel driving and the operation of the column ADC 212 in the present embodiment. First, the column ADC 212 reads the noise component signal (Ref) at the time of normal exposure (S51), further reads the noise signal component signal (Signal) (S52), and performs CDS by taking the difference between the two (S53). ). The column ADC 212 AD-converts the analog data after CDS (S54) and stores it in the memory in the column ADC 212 (S55).

Next, after white reset and PD leak are performed, the column ADC 212 reads the noise component signal (WR1a_R) (S56), further reads the noise signal component signal (WR1a_S) (S57), and obtains the difference between the two. Thus, CDS is performed (S58). The column ADC 212 holds the analog data (WR1a) after CDS in the memory in the column ADC 212.

Subsequently, after white reset and PD leak are similarly performed, the column ADC 212 reads out the noise component signal (WR1b_R) at the time of white reset (S59), and further reads out the noise signal component signal (WR1b_S) ( S60) CDS is performed by taking the difference between the two (S61). Then, the column ADC 212 obtains an average value (WR1) of WR1a and WR1b, which is analog data after CDS (S62), performs AD conversion on the average value (WR1) (S63), and after conversion Data is held in the memory (S64).

Next, after a white leak and a PD leak with different PD leak times from the first and second PD leaks, the column ADC 212 reads the noise component signal (WR2a_R) (S65), and further the noise signal component The signal (WR2a_S) is read (S66), and CDS is performed by taking the difference between the two (S67). The column ADC 212 holds the analog data (WR2a) after CDS in the memory in the column ADC 212.

Subsequently, after white reset and PD leak are similarly performed, the column ADC 212 reads the noise component signal (WR2b_R) (S68), and further reads the noise signal component signal (WR2b_S) (S69). The CDS is performed by taking (S70). Then, the column ADC 212 obtains an average value (WR2) of WR2a and WR2b, which is analog data after CDS (S71), performs AD conversion on the average value (WR2) (S72), and after conversion Data is held in the memory (S73).

In the second embodiment, compared to the first embodiment, the number of AD conversions is reduced in this embodiment, so that the time required for one scan can be shortened. In addition, the power consumption of the entire image sensor 110 is reduced.

(Summary of the above solid-state imaging device)
The solid-state imaging device includes a photoelectric conversion element having a linear characteristic on a low luminance side and a log characteristic on a high luminance side at an inflection point, a transfer transistor connected to the photoelectric conversion element, and a transfer transistor connected to the transfer transistor. A pixel circuit having a floating diffusion layer, a reset transistor connected between the control voltage and the floating diffusion layer, and an amplification transistor that amplifies the voltage of the floating diffusion layer and outputs the amplified pixel signal as a pixel signal. An arrayed pixel array unit, a control unit for setting the control voltage, and setting a voltage at a control terminal of the reset transistor and the transfer transistor to control on / off of the reset transistor and the transfer transistor; A reading unit that is provided for each column of the pixel units and reads out the pixel signals, and the control unit includes the transfer traffic. After the pixel signal obtained by exposing the subject with the control terminal of the register set to an intermediate potential is read as a normal pixel signal to the reading unit, (1) the control voltage is supplied to the photoelectric conversion element. By setting the voltage to allow charge injection, charge is injected into the photoelectric conversion element via the reset transistor. (2) Next, the control terminal of the transfer transistor is set to an intermediate potential for a predetermined time. By setting, the charge injected into the photoelectric conversion element is leaked. (3) Next, the reading unit is controlled to read the pixel signal as a white reset signal. (4) Next, Steps (1) to (3) are repeated M times (M is an integer of 2 or more), and the reading unit calculates an average value of the read white reset signals for the M times.

According to this configuration, the white reset shown in steps (1) to (3) is repeated M times, and each white reset signal is averaged, thereby reducing random noise included in the white reset signal. it can. Therefore, it is possible to improve the effect of correcting the variation of the normal pixel signal.

In the above configuration, it is preferable that the reading unit performs analog / digital conversion on the M white reset signals and averages the digital white reset signals to calculate the average value.

According to this configuration, since the averaging process is performed after analog / digital conversion of each white reset signal, random noise of the white reset signal can be reduced without increasing the circuit scale.

The reading unit preferably averages the M analog white reset signals and calculates the average value, and then performs analog / digital conversion on the average value.

According to this configuration, since the number of analog / digital conversions can be reduced, one horizontal scanning time can be shortened and the power consumption of the apparatus can be reduced.

Further, in the above configuration, a reference signal generation unit that generates a ramp signal is further provided, and the readout unit is a single slope type, and performs analog / digital conversion of the pixel signal using the ramp signal. The reference signal generator has a first change that changes with a predetermined slope from time to time when the reading unit performs analog / digital conversion of the normal pixel signal from a predetermined voltage V1 to a predetermined voltage V3. When the reading unit outputs the ramp signal and the reading unit performs analog / digital conversion of the white reset signal, the predetermined voltage with time elapses from the voltage V2 which is a voltage between the voltage V1 and the voltage V3 to the voltage V3. It is preferable to output a second ramp signal that changes with an inclination.

According to this configuration, the first lamp signal used during the normal exposure has a waveform from the voltage V1 to the voltage V3, whereas the second lamp signal used during the white reset has a waveform from the voltage V2 to the voltage V3, and the voltage V2 Is a value between the voltage V1 and the voltage V3, the second ramp signal has a shorter scan width at the time of analog / digital conversion than the first ramp signal. That is, the time required for the analog / digital conversion can be shortened, and the white reset can be performed a plurality of times for the shortened time.

Further, in the above configuration, it is preferable that a range from the voltage V2 to the voltage V3 of the second ramp signal is a range including variations in the white reset signal.

At the time of white reset, a pixel signal corresponding to the inflection point position is obtained. That is, by making the second ramp signal a waveform including at least inflection point variation, the scan range of the ramp signal at the time of analog / digital conversion is narrowed, and the analog / digital conversion time of the white reset signal can be shortened. it can.

Further, in the above configuration, in the step (4), if the leak time in the step (2) is constant and the sequence in which the steps (1) to (3) are repeated M times is a unit sequence, the leak time differs. The unit sequence may be executed a plurality of times.

According to this configuration, a plurality of white reset outputs having different leak periods can be obtained.

Claims

The low luminance side shows linear characteristics at the inflection point and the high luminance side shows log characteristics, a transfer transistor connected to the photoelectric conversion element, a floating diffusion layer connected to the transfer transistor, A pixel array unit in which pixel circuits having a reset transistor connected between a control voltage and the floating diffusion layer, and an amplification transistor that amplifies the voltage of the floating diffusion layer and outputs it as a pixel signal are arranged in a matrix When,
A control unit for setting the control voltage, and setting a voltage at a control terminal of the reset transistor and the transfer transistor to control on / off of the reset transistor and the transfer transistor;
A readout unit that is provided for each column of the pixel unit and reads out the pixel signal;
With
The control unit causes the reading unit to read the pixel signal obtained by setting the control terminal of the transfer transistor to an intermediate potential and exposing the subject as a normal pixel signal;
(1) By setting the control voltage to a voltage that allows charge injection into the photoelectric conversion element, charge is injected into the photoelectric conversion element via the reset transistor,
(2) Next, by setting the control terminal of the transfer transistor to an intermediate potential for a predetermined time, the charge injected into the photoelectric conversion element is leaked,
(3) Next, control is performed to cause the readout unit to read out the pixel signal as a white reset signal,
(4) Next, the steps (1) to (3) are repeated M times (M is an integer of 2 or more),
The readout unit calculates a mean value of the read M white reset signals.
The solid-state imaging device according to claim 1, wherein the reading unit performs analog / digital conversion on each of the M white reset signals and averages the digital white reset signals to calculate the average value.
The solid-state imaging device according to claim 1, wherein the reading unit averages the M analog white reset signals to calculate the average value, and then performs analog / digital conversion on the average value.
A reference signal generator for generating a ramp signal;
The readout unit is a single slope type, and performs analog / digital conversion of the pixel signal using the ramp signal.
The reference signal generator has a first change that changes with a predetermined slope from time to time when the reading unit performs analog / digital conversion of the normal pixel signal from a predetermined voltage V1 to a predetermined voltage V3. When the reading unit outputs the ramp signal and the reading unit performs analog / digital conversion of the white reset signal, the predetermined voltage with time elapses from the voltage V2 which is a voltage between the voltage V1 and the voltage V3 to the voltage V3. The solid-state imaging device according to any one of claims 1 to 3, wherein a second ramp signal that changes with an inclination is output.
The solid-state imaging device according to claim 4, wherein a range from the voltage V2 to the voltage V3 of the second ramp signal includes a variation of the white reset signal.
In the step (4), assuming that the sequence in which the leak time in the step (2) is constant and the steps (1) to (3) are repeated M times is a unit sequence, the unit sequences having different leak times are executed a plurality of times. The solid-state imaging device according to any one of claims 1 to 5, wherein