WO2013127211A1

WO2013127211A1 - Display panel and display device comprising the display panel

Info

Publication number: WO2013127211A1
Application number: PCT/CN2012/085275
Authority: WO
Inventors: 廖燕平
Original assignee: 京东方科技集团股份有限公司; 北京京东方显示技术有限公司
Priority date: 2012-03-02
Filing date: 2012-11-26
Publication date: 2013-09-06
Also published as: CN102650785A

Abstract

Provided are a display panel and a display device comprising the display panel. The display panel comprises an array substrate, a data signal chip on film (1-1), and a gate signal chip on film (2-1). A data signal pad region, a gate signal pad region, and a display region are formed on the array substrate. A common electrode line (3) is distributed around the display region and in the display region. The display panel is provided with at least one filter capacitor (4) for filtering an alternating current signal on the common electrode line (3). The display panel and the display device are provided with at least one filter capacitor (4), and a crosstalk volatile voltage signal induced by parasitic capacitance on the common electrode line (3) is filtered out, so as to stabilize the common voltage on the common electrode line (3), thereby alleviating or avoiding the greenish phenomenon and image sticking. Further, through an external capacitor, the option of the filter capacitor (4) is not limited, and the filter capacitor (4) of the suitable size may be selected according to needs.

Description

Display panel and display device including the same

Embodiments of the present invention relate to a display panel and a display device including the same. Background technique

The connection and distribution of common electrodes in a conventional liquid crystal display panel are shown in Figure 1: Common voltage

(Vcom) is input into the panel by the data signal pad (hereinafter referred to as D-Pad) and distributed by the thin film metal line (common electrode line) 3 in the panel. The width of the common electrode line 3 may vary depending on the design of the panel. In a region where a chip on film (Chip On Flex or Chip On Film, hereinafter referred to as COF) is provided (that is, a plurality of data signal flip-chip films (D-COF) 1-1 and a plurality of gate electrodes in FIG. In the vicinity of the signal-on-film (G-COF) 2-1, the common electrode line 3 is relatively narrow, and in other areas (the side opposite to D-COF 1-1 shown in Fig. 1 and with G- The opposite side of the COF 2-1) common electrode line 3 can be designed to be wider. The width of the common electrode line 3 and the distance from the input point affect the resistance of the common electrode line 3. The common electrode line 3 overlaps with the gate signal electrode line (not shown) and the data signal electrode line (not shown), and a parasitic capacitance is formed at the overlapping and adjacent areas. The self-resistance of the common electrode line 3 and the parasitic capacitance formed cause the voltage on the common electrode line to vary with changes in the gate signal voltage and the data signal voltage, that is, the voltage on the otherwise stable common electrode line is affected and fluctuates. This is equivalent to superimposing an alternating crosstalk ripple signal on a DC voltage, and the crosstalk fluctuation signal induced on the common electrode line farther from the input end is larger. Unstable voltage on the common electrode line can cause deterioration in panel display performance, such as the appearance of Greenish and Image Sticking. Summary of the invention

Embodiments of the present invention provide a display panel capable of filtering out an AC signal generated on a common electrode line and a display device including the display panel.

Embodiments of the present invention provide a display panel including an array substrate, a data signal flip chip, and a gate signal flip chip, wherein the array substrate is formed with a data signal, a panel, and a gate signal. And a common electrode line is disposed around the display area and the display area, wherein the display panel is provided with at least one filter capacitor for filtering an alternating current signal on the common electrode line.

Embodiments of the present invention also provide a display device including the above display panel. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1 is a schematic structural view of a conventional display panel;

2 is a schematic structural view of a display panel according to a first embodiment of the present invention;

3 is a schematic structural view of a display panel according to a second embodiment of the present invention;

4 is a cross-sectional view of a display panel in accordance with a second embodiment of the present invention. detailed description

The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

A display panel and a display device according to an embodiment of the present invention will hereinafter be described in detail with reference to the accompanying drawings and embodiments.

The display panel of the embodiment of the present invention is connected to at least one of the distal end points of the common electrode (the common electrode line farther from the input end) (the following embodiments are all taken as an example, but the invention is not limited thereto) The AC crosstalk fluctuating voltage signal induced by the parasitic capacitance on the common electrode line is filtered out, thereby realizing the voltage stabilization on the common electrode line, thereby achieving the purpose of improving or avoiding greening and afterimage. One electrode of the filter capacitor can be connected to a reference potential which is lower than the common voltage input from the D-Pad region, and the other electrode of the filter capacitor can be connected to the common electrode line.

2 is a schematic structural view of a display panel according to a first embodiment of the present invention. The display of this embodiment The display panel may include an array substrate and a color filter substrate (the first rectangular frame region and the second rectangular frame region from the outside to the inside shown in FIG. 2, respectively). In the display panel of the embodiment, the array substrate may be a thin film transistor LCD (TFT-LCD) array substrate of any mode, such as a twisted nematic (TN) mode, an in-plane switch (In -Plane Switching, IPS) mode and Fringe Field Switching (FSS) mode.

The array substrate of the present embodiment may be formed with a display area (the smallest rectangular frame area shown in the drawing;), a D-Pad area, and a Gate Signal Pad (hereinafter referred to as G-Pad).

The display panel of this embodiment may further include a D-COF and a G-COF connected to the D-Pad and the G-Pad, respectively. In the display panel of the embodiment, the D-COF and D-Pad regions may be disposed on one side of the array substrate (the top side in FIG. 2;), and the G-COF and G-Pad regions may be disposed in the D-Pad The adjacent side of the zone (left side in Figure 2). A plurality of D-COF 1-1 may be disposed on the display panel, and each D-COF 1-1 may correspond to one D-Pad 1-2 in the D-Pad area on the array substrate, and each D-COF 1 A data signal driving integrated circuit (IC) 1-1-1 can be provided on the -1, and each D-Pad 1-2 can be connected to the corresponding data driving IC 1-1-1. A plurality of G-COFs 2-1 may also be disposed on the display panel, and each G-COF 2-1 may correspond to one G-Pad 2-2 in the G-Pad area on the array substrate, and each G-COF A gate signal driving IC 2-1-1 may be disposed on 2-1, and each G-Pad 2-2 may be connected to a corresponding gate signal driving IC 2-1-1. Since the drive signal on the array substrate is through D-Pad and D-COF? The setting is made, so the way the filter capacitor is connected to the low potential can be implemented, for example, by connecting to the D-Pad and D-COF, or by other means, such as by connecting to the ground pin of the drive signal IC, or by wire. Connect to the outside of the array substrate, etc.

The common electrode line 3 may include a common electrode lead 3-1 and a common electrode trace 3-2. The common electrode traces 3-2 can be distributed over the entire display area, and the common electrode lead 3-1 can be disposed outside the display area. As shown in Fig. 2, four common electrode leads 3-1 may be disposed outside the four sides of the display area, and the common electrode traces 3-2 may be distributed in parallel with each other in the display area. Each of the common electrode traces 3-2 may be respectively connected to the common electrode lead 3-1, the common electrode lead 3-1 may be connected to the D-Pad area, and the Vcom signal may be introduced from the D-COF via the D-Pad, and then through the common The electrode lead 3-1 is introduced to the common electrode trace 3-2 to be introduced to the entire display area.

An external filter capacitor 4 may be disposed in the display panel of the embodiment, and the filter capacitor 4 may be disposed in a G-Pad region or a D-Pad region. In Figure 2, the filter capacitor 4 can be placed in the G-Pad The lower left corner of the area, but the embodiment of the present invention is not limited thereto, for example, the filter capacitor 4 can be set in the G-COF

2-1 on or D-COF 1-1. One electrode of the filter capacitor 4 can be grounded, and the other electrode of the filter capacitor 4 can be connected to the common electrode line 3 farthest from the G-Pad region. Specifically, as shown in FIG. 2, in the display panel of the present embodiment, a reference electrode line 4-1 (indicated by a broken line in FIG. 2) may be formed on the array substrate. The reference electrode line 4-1 may form a first terminal in the G-Pad region, and then lead a line from the common electrode lead 3-1 on the bottom side of the array substrate to the G-Pad region and form a second terminal, the first terminal And the second terminal is respectively connected to the two electrodes of the external filter capacitor 4. The distance between the two terminals can be reasonably designed according to the size of the required filter capacitor. The reference electrode line 4-1 can connect one electrode of the filter capacitor 4 to the nearest D-Pad 1-2, so that the electrode of the filter capacitor 4 is connected through D-Pad 1-2 and D-COF 1-1 Zero potential. Due to the need of wiring, it is necessary to pass the G-Pad area when connecting the reference electrode line 4-1 to the D-Pad 1-2.

3 is a schematic structural view of a display panel according to a second embodiment of the present invention. Compared with the display panel of the first embodiment, the external filter capacitor 4 of the display panel of the embodiment can be disposed on the G-COF 2-1 or the D-COF 1-1 (in FIG. 3, the filter capacitor 4 is disposed at The G-COF 2-1 in the lower left corner is not limited thereto, and may be set, for example, in the G-Pad area or the D-Pad area. One electrode of the filter capacitor 4 can be led out to the first terminal 4-1-1 formed on the surface of the array substrate by a metal wire 4-1-2 (indicated by a chain line in the figure). Since the G-Pad area has no grounded terminal, it is necessary to take the electrode of the filter capacitor 4 out of the array substrate by the first terminal 4-1-1 and connect it to zero potential. The other electrode of the filter capacitor 4 can be connected to the common electrode lead 3-1 at the bottom end of the array substrate.

As shown in Fig. 4, when the liquid crystal module is formed, the outer casing of the liquid crystal module can be usually made of a metal material (for example, aluminum), and the metal case 5 can be grounded (zero potential). Therefore, a conductive cotton 6 can be disposed at the first terminal 4-1-1 (here, the conductive cotton 6 is only an example, and the embodiment of the present invention is obviously not limited thereto), wherein one end of the conductive cotton 6 and the array substrate The first terminal 4-1-1 is connected, and the other end can be in contact with the metal shell 5 of the liquid crystal module, thereby achieving the effect of grounding one electrode of the filter capacitor 4 disposed on the G-COF.

Compared with the display panel of the first embodiment, the filter capacitor used in the display panel of the third embodiment of the present invention may not be an external capacitor, and the filter capacitor in the third embodiment may be integrated into the gate signal on the G-COF. The data signal on the driver IC or D-COF is driven on the IC (not shown), that is, the filter capacitor can be formed directly on the IC. By connecting one electrode of the filter capacitor to the gate signal drive The ground pin of the IC or data signal driver IC can realize the grounding of one electrode of the filter capacitor, and the other electrode of the filter capacitor can be connected to the common electrode line farthest from the D-Pad region.

The display panel according to the fourth embodiment of the present invention may further include a Printed Circuit Board (PCB) (not shown). The printed circuit board can be disposed outside the array substrate and can be connected to the data signal driving IC on the D-COF and to the gate signal driving IC on the G-COF. Although the printed circuit board is not shown here, the arrangement and connection of the printed circuit board are well-established technologies in the field, and are not mentioned here. Compared with the display panel according to the first embodiment, the filter capacitor of the display panel of the embodiment may be disposed on the PCB, and one electrode of the filter capacitor may be connected to the ground terminal on the PCB, and the other electrode of the filter capacitor may be It is connected to the common electrode line farthest from the D-Pad area. The filter capacitor of the embodiment of the present invention may also be disposed or integrated at any suitable position other than the above position, as long as one electrode of the filter capacitor is connected to a potential lower than the common voltage and the wiring does not affect the original function of the display panel. Therefore, the specific location of the filter capacitor described above does not limit the invention.

The display panel and the display device of the embodiment of the present invention filter the crosstalk wave voltage signal induced by the parasitic capacitance on the common electrode line by setting at least one filter capacitor, thereby realizing the stabilization of the common voltage on the common electrode line, thereby improving or Avoid greening and afterimages on the display panel. In addition, the selection range of the filter capacitor can be unrestricted by means of an external capacitor, and a filter capacitor of a suitable size can be selected as needed.

At least the following structure can be provided according to an embodiment of the present invention:

(1) A display panel comprising an array substrate, a data signal flip chip, and a gate signal flip chip, wherein the array substrate is formed with a data signal pad region, a gate signal pad region, and a display region. A common electrode line is disposed around the display area and the display area, wherein the display panel is provided with at least one filter capacitor for filtering an alternating current signal on the common electrode line.

(2) The display panel of (1), wherein the common electrode line includes a common electrode lead and a common electrode trace, the common electrode lead being formed around the display area and connected to the data signal In the pad region, the common electrode traces are distributed in the display area of the array substrate and are respectively connected to the common electrode leads.

The display panel according to any one of (1), wherein one electrode of the filter capacitor is connected to a potential lower than a common voltage on the common electrode line. The display panel according to any one of (1), wherein the filter capacitor is disposed in the gate signal pad region, the gate signal flip chip, and the data A signal pad region, or the data signal is overlying the crystalline film.

The display panel according to any one of (2), wherein the array substrate is formed with a reference electrode line, and one electrode of the filter capacitor passes through the reference electrode line The data signal pads are connected, and the other electrode of the filter capacitor is connected to a common electrode lead that is furthest from the data signal pad region.

(6) The display panel according to any one of (2), wherein one electrode of the filter capacitor is led out to the outside of the display panel by a wire and forms a ground terminal, and the filter capacitor is further An electrode is connected to a common electrode lead that is furthest from the data signal pad region.

The display panel according to any one of (1), wherein the data signal flip chip is provided with a data signal driving IC connected to a corresponding data signal pad, the gate A gate signal driving IC connected to the corresponding gate signal pad is disposed on the polar signal flip chip, and the filter capacitor is integrated on the data signal driving IC or the gate signal driving IC.

(8) The display panel of (7), wherein one electrode of the filter capacitor is connected to a ground pin of the data signal driving IC, and the other electrode of the filter capacitor is soldered to the data signal The farthest common electrode leads of the panel are connected.

(9) The display panel of (7), wherein one electrode of the filter capacitor is connected to a ground pin of the gate signal driving IC, and the other electrode of the filter capacitor is separated from the data signal The farthest common electrode leads in the pad area are connected.

The display panel according to any one of (2), wherein the display panel further includes a printed circuit board, the printed circuit board being connected to the data signal flip chip, a filter capacitor is disposed on the printed circuit board, and one electrode of the filter capacitor is connected to a ground terminal on the printed circuit board, and another electrode of the filter capacitor is farthest from the data signal pad region The common electrode leads are connected.

(11) A display device comprising the display panel according to any one of (1) to (10). The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

Claim

A display panel comprising an array substrate, a data signal flip chip, and a gate signal flip chip, wherein the array substrate is formed with a data signal pad region, a gate signal pad region, and a display region, wherein the display A common electrode line is disposed around the area and the display area, wherein the display panel is provided with at least one filter capacitor for filtering an alternating current signal on the common electrode line.

2. The display panel of claim 1, wherein the common electrode line comprises a common electrode lead and a common electrode trace, the common electrode lead being formed around the display area and connected to the data signal pad The common electrode traces are distributed on the display area of the array substrate and are respectively connected to the common electrode lead.

The display panel according to any one of claims 1 to 2, wherein one electrode of the filter capacitor is connected to a potential lower than a common voltage on the common electrode line.

The display panel according to any one of claims 1 to 3, wherein the filter capacitor is disposed in the gate signal pad region, the gate signal flip chip, and the data signal pad region. Or the data signal is on the flip chip.

The display panel according to any one of claims 2 to 4, wherein a reference electrode line is formed on the array substrate, and one electrode of the filter capacitor is soldered to the data signal through the reference electrode line. The pads are connected, and the other electrode of the filter capacitor is connected to a common electrode lead that is furthest from the data signal pad region.

The display panel according to any one of claims 2 to 4, wherein one electrode of the filter capacitor is led out to the outside of the display panel by a wire and forms a ground terminal, and the other electrode of the filter capacitor and the distance The common electrode leads farthest from the data signal pad region are connected.

The display panel according to any one of claims 1 to 4, wherein the data signal flip chip is provided with a data signal driving IC connected to a corresponding data signal pad, and the gate signal is flipped. A gate signal driving IC connected to the corresponding gate signal pad is disposed on the film, and the filter capacitor is integrated on the data signal driving IC or the gate signal driving IC.

8. The display panel of claim 7, wherein one electrode of the filter capacitor is connected to a ground pin of the data signal driving IC, and the other electrode of the filter capacitor is spaced apart from the data signal pad region. The farthest common electrode leads are connected.

9. The display panel of claim 7, wherein one electrode of the filter capacitor is The ground pin of the gate signal driving IC is connected, and the other electrode of the filter capacitor is connected to the common electrode lead farthest from the data signal;): the early panel.

The display panel according to any one of claims 2-3, wherein the display panel further comprises a printed circuit board, the printed circuit board is connected to the data signal flip chip, and the filter capacitor is disposed at On the printed circuit board, and one electrode of the filter capacitor is connected to a ground terminal on the printed circuit board, and the other electrode of the filter capacitor and a common electrode lead farthest from the data signal pad region Connected.

A display device comprising the display panel according to any one of claims 1-10.