WO2013120516A1

WO2013120516A1 - Field-programmable logic gate arrangement

Info

Publication number: WO2013120516A1
Application number: PCT/EP2012/052549
Authority: WO
Inventors: Holger Heine; Stephan Jorra; Harald Kapp
Original assignee: Siemens Aktiengesellschaft
Priority date: 2012-02-15
Filing date: 2012-02-15
Publication date: 2013-08-22
Also published as: CN104115402B; EP2801154A1; CN104115402A; RU2014137144A; BR112014020003A2; BR112014020003A8

Abstract

The invention relates inter alia to a field-programmable logic gate arrangement (10). According to the invention, a dual-port or multi-port memory chip (20) having a predetermined number of ports that permit a parallel interrogation of the memory chip (20) and a read-out device (30) are provided. Said read-out device is suitable for reading out in parallel memory cells of the dual-port or multi-port memory chip (20) at at least two ports of the memory chip (20), for comparing in parallel the memory contents (I(A1), I(A2)) emitted at the at least two ports with a predetermined memory content (I-1, I-n) and, when the memory contents match, for emitting a result signal (S1-S4) signalling the match and/or the corresponding memory cell address of the memory cell having the predetermined memory content (I-1, I-n).

Description

description

Field Programmable logic gate arrangement The invention relates to a field programmable Lo ^¬ gik gate arrangement.

Field programmable logic gate arrays are often referred to in technical language as FPGAs (FPGA: Field Programmable Gate Array). A FPGA programming is usually carried out by means of a defined in a hardware description language ^¬ program that defines the to reali by the FPGA ^¬ sierende circuit structure. The program with the desired circuit pattern is transferred to the FPGA, which are activated in the FPGA existing switch on or off and hardware in the FPGA circuit a digi ^¬ tale results corresponding to the software-predetermined circuit pattern. The invention has for its object to provide a field-programmable logic program ^¬ gate arrangement, including a comparison with conventional field programmable logic gate arrays extended memory readout functionality. This object is achieved by a feldprogram ^¬ mable logic gate arrangement with the features of claim 1. Advantageous embodiments of the field-programmable logic gate arrangement are specified in subclaims.

According to the invention, a field-programmable logic gate arrangement is provided with a dual-port or multiport memory module with a predetermined number of ports, which enable a parallel query of the memory module, and a read-out device which is suitable, Speicherzel ^¬ len of the dual port or multiport read -Speicherbausteins parallel to at ^¬ least two ports of the memory device, the memory contents outputted to the at least two ports to compare in parallel with a predetermined memory content and to output a coincidence-signal indicative result signal and / or the korres ^¬ ponding memory cell address of the storage unit having the predetermined memory contents in accordance with the memory contents.

A significant advantage of the logic gate arrangement according to the invention is the fact that it enables operation of a dual-port or multiport memory module as associative memory within the logic gate arrangement. Thus, it is possible according to the invention, using two or more ports of the dual-port or multi-port memory module simultaneously read several memory cells and ermit ^¬ teln, whether in a memory cell - and if so in which - a predetermined memory content is stored. The OF INVENTION ^¬ dung contemporary logic gate arrangement can thus advantageously in the range of network switches (fachsprachlich "Network Switch") to use, where to be checked very quickly, as a rule, if a MAC contained in an incoming the message (Media Access Control or Me ^¬ serving Access Control) address is contained in a predetermined amount of stored MAC addresses.

The readout device is preferably formed in the logic gate arrangement by programming.

The dual port or multiport memory device is preferably monolithically integrated in the logic gate array. Alternatively, it may be formed by programming.

The parallel or synchronous reading of the memory device is particularly easy and therefore advantageous imple ^¬ reindeer, if the reading device is configured such that it permanently preset to a port of the memory device one address of the memory cell addresses to a logical "one" and at another port of the memory module, the same address bit of the memory cell addresses with a logical "zero" fixed. In the case of a multi-port memory module, it is considered to be ^advantageous if the read-out device is designed to charge the at least two ports of the memory module with memory cell addresses during parallel readout of the memory contents, in which case a predetermined subset of address bits are port-individually a fixed predetermined address bit information is pre-assigned and in which the remaining address bits are changed during the read-out process.

In order to enable an automatic searching the memory cells, it is considered advantageous when the readout ^¬ means comprises an address counter which can pass through a predefined NEN address space of the memory device and having at least two address outputs, to each of which a memory cell address is output, the Address counter outputs to the at least two address outputs memory cell addresses, in which a predetermined subset of address bits each port individually with a fixed address ^¬ bit information is fixed pre-assigned and in which the other address bits during the counting process changed ^{identi ¬} the. With a view to the input of a predetermined memory content, it is considered advantageous if the read-out device has at least one evaluation device, on the input side the memory contents output by the memory module, the predetermined memory contents and the respectively selected memory cell addresses are applied and on the output side that memory cell address for which the memory contents are identical to the predetermined memory contents. The evaluation device preferably comprises a multiplexer and a comparator unit per port of the memory module. Each comparator has per information of the SpeI ^¬ contents from another preferably in each case a comparator whose output is linked to an AND gate. Especially advantageous is considered if it can be done in looking through ^¬ of the memory device in a predetermined memory contents a parallel investigation regarding various memory contents. In this regard, it is considered advantageous when the read-out means having a plurality of inputs, each represents a individu ^¬ eller memory contents can be entered into and each associated with an input individual evaluation device, wherein at each evaluation on the input side, the memory contents outputted from the memory device, the individu - Express predetermined memory contents and the respectively selected

Memory cell addresses are present and wherein each evaluation device on the output side that memory cell address from ^¬ , for which the memory contents with the individually eingege ^¬ benen memory contents is identical.

If only predetermined memory areas of the memory module are to be interrogated, then it is considered advantageous if the start address and the end address of the memory cell area to be searched are stored in the memory module.

If the memory module is a dual-port memory module having two ports, which enable a parallel polling of the memory module, then it is considered advantageous if the read-out device is configured such that it assigns a predetermined address bit to one of the two ports of the memory module Memory cell addresses with a logical "one" pre-assigned and at the other of the two ports of the memory module, the same address bit of the memory cell addresses with a logical "zero" pre-assigned. The address bit permanently pre-assigned with a logic "one" or a logical "zero" is preferably the least ^significant address bit. The field programmable logic gate array forms before ^¬ preferably a part of a network switch or ei ^¬ nes Network Switch to check MAC addresses. The invention thus also relates to a network switch or a network switch with a field-programmable logic gate arrangement, as described above.

The invention also relates to a method of operating a field programmable logic gate array. According to the invention of such a comparison is with respect to driving provided that all memory cells or a subset of memory cells of an integrated logic gate arrangement dual port or multi-port memory block is read from ^¬, the contents of the memory cells to a predetermined memory contents are compared and conformity of the memory contents of one being carried out at a predetermined number of ports of the memory device a paralle ^¬ le query accordance signalisie ^¬ rendes result signal and / or the memory cell address of the respective memory cell is output, by reading out at least two ports of the memory device in parallel and the are compared to the at least two ports ^¬ output memory contents in parallel with the given memory content.

Regarding the advantages of the process according to the invention, reference is made to the above statements in connection with the inventive field programmable logic gate array, as the advantages of the process according to the invention de ^¬ nen of field programmable logic gang invention correspond arrangement essentially.

The invention also relates to a memory module with a program code stored therein for programming. a field programmable logic gate arrangement as described above.

According to the invention in this respect is provided in that the program code is adapted to program the field programmable logic gang arrangement such that in the field-programmable logic gate array read-out means is formed, which is suitable for memory cells of the dual port ^¬ or multiport memory module on at least read out two ports of the memory module in parallel, to compare the memory contents outputted at least two ports in parallel with a predetermined memory content and output a coincidence signal indicative result signal and / or the corresponding Spei ^¬ cherzellenadresse of the predetermined memory contents aufwei ^¬ send memory cell in accordance with the memory contents.

With regard to the advantages of the memory module according to the invention, reference is made to the above statements in connection with the field programmable logic gate arrangement according to the invention, since the advantages of the memory module according to the invention essentially correspond to those of the field programmable logic gate arrangement according to the invention.

The invention will be explained in more detail with reference to a Ausführungsbei ^¬ game; thereby show exemplarily:

Figure 1 shows an embodiment of an arrangement with egg ^¬ ner field programmable logic gate arrangement according to which the method of the invention is exemplified, and a memory module with a stored therein program code for programming the field programmable logic gate array, and

FIG. 2 shows an exemplary embodiment of a comparator unit, as can be used in the field programmable logic gate arrangement according to FIG. FIG. 1 shows a field-programmable logic gate arrangement 10 which comprises a dual-port memory module 20 integrated in the logic gate arrangement as well as a read-out device 30 programmed in the logic gate arrangement 10.

The dual-port memory device 20 has a first port and a second port. The first port is formed by a first input port 21 and an associated or corresponding first output port 22. The second port of the memory module 20 is formed by a second A ^¬ through port 23 and a second output port 24th If a memory cell address is input at the first input port 21, the memory module 20 outputs at its first output port 22 the memory contents of the memory cell with the corresponding memory cell address which is applied to the first input port 21.

In a corresponding manner, the second port of the SpeI ^¬ cherbausteins works 20. If a memory cell address input to the second input port 23, the storage construction ^¬ stone 20 is at its second output port 24 the memory contents of those memory cell, the memory cell address input with the second input port 23 Speicherzellenad ^¬ ress is identical.

Thus, the memory device 20 makes it possible to compensate for the Speicherin- holding two memory cells simultaneously or parallel ^¬ read by 23 different memory cell addresses are fed to the first input port 21 and into the second input port. The readout device 30 has an address counter 40, which is connected to a first address output 40a to the first input port 21 of the memory module 20. A second address output 40b of the address counter 40 is connected to the second input port 23 of the memory module 20 in connec ^¬ tion.

The address counter 40 has a binary counter 41, a multiplexer 42 and a comparator 43.

The address counter 40 is capable of outputting at its first address output 40a a first memory cell address AI and at its second address output 40b a second memory cell address A2, wherein the first memory cell address AI differs from the second memory cell address A2 only with respect to a single address bit.

In order to achieve the described memory cell address formation, the address counter 40 sets the first memory cell address AI, which is output at the first address output 40a, from the respective count Z of the counter 41 and a fixed vorbe ^¬ laid address bit together. The fixed pre-assigned address bit may be any address bit of the first memory cell address AI; In the following, it is assumed by way of example that the fixed pre-assigned address bit is the least significant address bit. The low ^¬ wertigste address bit is also referred to as the LSB in the technical language (English for Least Significant Bit).

In the embodiment according to Figure 1 of the Adresszäh ^¬ ler 40 is thus a storage ^¬ cell address output as first memory cell address AI, in which the least significant address bit LSB is preset to a logic "0" and all the other high-order address bits of the memory cell address by the respective counter reading Z of Counter 41 are given.

In a corresponding manner, the address counter 40 operates with respect to the second memory cell address A2, which is output at the second address output 40b of the address counter 40. The address counter 40 sets the second memory cell address A2 from the respective counter reading Z of the counter 41, and an occupied before ^¬ address bit preset to a logic "1" is, together. The fixed pre-assigned address bit is - as with the first memory address AI - the least significant address bit LSB. The mode of operation of the address counter 40 will be explained in greater detail on the basis of a numerical example, it being assumed by way of example that the counter reading Z of the counter 41 is "8" in binary notation "1000". In this case, the address counter 40 will output at its first address output 40a a first memory cell address AI which is as follows:

AI = "10000" At its second address output 40b, the address counter 40 will combine the counter reading Z of the counter 41 with the permanently pre-assigned LSB address bit "1" in such a way that the following second memory cell address A2 is produced: A2 = "10001"

The two memory cell addresses AI and A2 thus differ only in terms of the fixed least significant address bit LSB, the remaining address bits of the two memory cell addresses AI and A2 are identical.

In order to ensure that the address counter 40 can count from a predetermined start address to a predetermined end address, the address counter 40 has a first input 40c and a second input 40d.

At the first input 40c, a minimum count Zmin can be fed to the address counter 40, which indicates the start address for the address counter 40. At the second input 40d, a maximum count Zmax, which predefines the end address for the address counter 40, can be fed into the address counter 40. The address counter 40 can be operated, for example, as follows:

If the address counter is started 40, the multiplexer 42 is initially the minimum count are derived Zmin as a counter reading Z to the first address output 40a and the second address output 40b of the address counter 40 so that 40a at the two Ad ^¬ ressausgängen and 40b, the two memory cell addresses Al and A2 be formed, as has already been described above.

The counter reading Z reaches the counter 41, which increments or increments the counter reading within the scope of the next counting step. From there, the increased counter reading reaches the multiplexer 42, which in turn forwards the new or now increased counter reading Z to the two address outputs 40a and 40b.

If the count reaches the maximum count Z Zmax, which is fixed at the second input 40d of the address counter 40, this is detected by the comparator 43, which switches over ei ^¬ ne control line 44 to multiplexer 42nd By switching the multiplexer 42 is again the minimum count Zmin, which is present at the first input 40c, durchgeschal- tet and 40a of the two address outputs and 40b weitergelei ^¬ tet, so that the counting operation from the minimum count Zmin to the maximum count Zmax and from the by the Minimum count Zmin predetermined start address can restart to the predetermined by the maximum count Zmax end address.

The readout device 30 also has n-Auswerteinrich- tions, of which two are shown in Figure 1 and designated by the reference numerals 50-1 and 50-n. The n-type evaluation devices 50-1 to 50-n each have a first input 50a and a second input 50b. The first input 50a of the evaluation devices is in each case connected to the first output port 22 of the memory module 20. sen. The second input 50b of the evaluation devices is in each case connected to the second output port 24 of the memory module 20. In other words, the inputs 50a and 50b of the n-evaluation devices 50-1 to 50-n turns on parallel and respectively connected to two output ports of the memory block ^¬ 20th

The n-type evaluation devices 50-1 to 50-n may, for example, have the same design, so that only the evaluation device 50-1 is to be described in more detail below for all of the n-type evaluation devices.

As can be seen in FIG. 1, the evaluation device 50-1 is equipped with two comparator units, of which a first comparator unit is designated by the reference numeral 51 and a second comparator unit 52.

The two comparator units 51 and 52 are the output side with control inputs of a multiplexer 53 in connection, on the input side with four signals Sl, S2, S3 and S4 beauf ^¬ beat. Depending on the output signals of the two comparator units 51 and 52, one of the four signals S1 to S4 is switched through to the output A53 of the multiplexer 53 or to the output A50 of the evaluation device 50-1.

The evaluation device 50-1 is also equipped with an on-circuit 150-1, to which a storage content 1-1 ei ^¬ ner desired memory cell of the memory device can be fed in the evaluation device 50-1 20th

The evaluation device 50-1, for example, as follows ^¬ be exaggerated:

Is at the terminal 150-1, a memory contents 1-1 for which the memory cell or the memory cell address in the memory ^¬ building block 20 is searched for, fed into the evaluation device 50-1. The memory contents 1-1 reach both the first comparator unit 51 and the second comparator unit. standardized 52. The first comparator 51 compares the SpeI ^¬ cheri stop 1-1 with the memory content I (A1), which is output from the memory device 20 to the first output port 22nd Represents the first comparator unit 51 determines that the two memory contents 1-1 and I (A1) are identical, it ^¬ it demonstrates its output a control signal ST1 with a logi ^¬ rule "1". If the memory content 1-1 does not match the memory ^content I (A1), the first comparator unit 51 generates a control signal ST1 with a logic "0".

In a corresponding manner, the second comparator unit 52 operates the second comparator 52 compares the memory contents ^¬ 1-1, which abuts the terminal 150-1 of the evaluation device 50 1, the memory content I (A2), the cell in the memory with the second memory cell address A2 is stored in the SpeI ^¬ cherbaustein 20th The memory content I (A2) is output from the memory device 20 at the second output port 24. , The second comparator unit 52 determines that the SpeI ^¬ cheri stop 1-1 with the memory content I (A2) of the memory cell to the second memory cell address A2 agrees, it generates a second control signal ST2 with a logic "1" and transmits this to the multiplexer 53. Otherwise, if the memory content of 1-1 and the memory content I (A2) are un ^¬ differently, generates the second comparator 52, a second control signal ST2 with a logic "0".

Thus, on the input side, two control signals ST1 and ST2 are present at the multiplexer 53, which indicate whether the two comparator units 51 and 52 have ascertained an identity of the memory contents or not. As a function of the two control signals ST1 and ST2, the multiplexer 53 switches one of four input side signals Sl, S2, S3 or S4, as indicated ^¬ the truth table W in Figure 1 to, say for example in accordance with the following assignment:

ST1 = "0" and ST2 = "0"=> Sl ST1 = "0" and ST2 = "1"=> S2

ST1 = "1" and ST2 = "0" => S3

ST1 = "1" and ST2 = "1"=> S4 The signal S1 indicates, for example, by the symbol "%" that no identity of the memory contents has been detected. The signal Sl can be generated, for example, by a signal image Bsl. The signal S2 is, for example, by giving the counter ^¬ article Z and a "0" indicates that the memory cell with the first memory cell address AI has the input side pre give ^¬ NEN memory content 1-1. The signal S2 can be generated in ^¬ example by a signal images Bs2, which combines the count Z with the logical "0" binary.

The signal S3 is, for example, by giving the counter ^¬ article Z and a "1" indicates that the memory cell with the second memory cell address A2 to the input side vorgege- surrounded memory content comprises 1-1. The signal S3 can be generated at ^¬ example by a signal images Bs3, which combines the count Z with the logical "1" binary.

The signal S4 is a result signal indicating, for example, by specifying the count Z and an "X", that both in the memory cell with the first Speicherzellenad ^¬ ress AI as well as in the memory cell with the second SpeI ^¬ cherzellenadresse A2 the predetermined memory contents 1- 1 abge ^¬ stores. The signal S4 can be generated, for example, by a signal image Bs4, which supplements the counter reading Z by the indication "X".

The respectively through multiplexer 53 through-connected signal S1-S4 reaches the output A53 of the multiplexer 53 and the output A50 of the evaluation device 50-1, so that it can be determined at the output of the evaluation device 50-1, whether a memory cell with the desired memory contents 1-1 was found and possibly which memory cell address the memory cell having the desired memory contents 1-1. At the output A50 of the evaluation device 50-1 it can thus be determined whether the predetermined memory content 1-1 is stored in the first memory cell address AI and / or the second memory cell address A2.

The field-programmable logic gate arrangement 10 according to FIG. 1 thus makes it possible to operate the memory module 20 as an associative memory, wherein a reading speed that is twice as high as a simple one-port memory is achieved. This will be explained in detail with reference to a numerical example: If a predetermined area of memory is defined by a start address and an end address are examined availability of a predetermined memory contents to the pre ^¬, half of the memory cells via the first

Input port 21 and the first output port 22 and at the same time the other half of the memory cells via the second input port 23 and the second output port 24 queried. In this case, starting from a start address P, which is defined by the minimum count Zmin, the even addresses P, P + 2, P + 4, P + 6, etc. are queried via the first input port 21 and the second output port 22. The odd addresses P + 1, P + 3, P + 5, P + 7, etc. are processed via the second input port 23 and the second output port 24.

The counting up of the memory cell addresses of the memory cells to be read out is accomplished by the address counter 40 whose counter 41 increments the counter reading Z after each successful read-out process.

As already mentioned, the evaluation devices 50-1 to 50-n can be made identical. This makes it possible zusätz ^¬ Lich simultaneously to the memory content of 1-1 or parallel wei ^¬ tere memory contents in the read-out means 30 sen einzuspei- so that the memory module 20 not only in terms of the memory content 1-1, but also at the same time to other Memory contents can be examined out. So it is possible, for example, the memory contents In the terminal I50-n fed into the evaluation device 50-n and with the help of the evaluation device 50-n to check whether the memory contents are stored in the memory module 20 and if so, the corresponding memory cell or the respective memory cell address determine .

FIG. 1 also shows a memory module 100 with a program code 110 stored therein for the field-programmable logic gate arrangement 10. The program code 110 is suitable for programming the field-programmable logic gate arrangement 10 such that it can be programmed in the field-programmable logic Logic gate arrangement 10, the read-out device 30 is formed, which is adapted to read memory cells of the dual-port or multiport memory module 20 parallel to at least two ports of the memory module, the output at the at least two ports memory contents paral ^¬ lel with a predetermined memory content comparing and outputting a result signal signaling the agreement and / or the correspondent ^¬ chief of memory cell address of the predetermined storage ^¬ having content storage cell in accordance of the memory contents.

In the embodiment according to FIG. 1, the memory cell addresses are determined and output which indicate in which memory cells a predetermined memory content is stored. Alternatively, only a binary result signal, for example, may be generated which merely indicates whether or not a memory cell having the predetermined memory content is present.

FIG. 2 shows an exemplary embodiment for the comparator unit 51 according to FIG. 1. A number q of comparators 511 is identified, which in each case are connected to an information input IB-1 to IB-q of the memory content I (A1) (FIG. see Fig. 1) of the memory module are acted upon. An information bit IV-1 to IV-q of the predetermined memory content 1-1 (see FIG. At the outputs of the comparators 511, a respective comparison signal Vl to Vq is generated, which has a logic "1" on ^¬ if the input side applied information bits are identical, and otherwise has a logic "0".

The outputs of comparators 511 are connected to an AND gate 512, which generates the control signal ST1 with a logic "1" if all the input side comparison signals Vl to Vq have a logic "1", and other ^¬ if the control signal ST1 generated with a logical "0".

The comparator unit 52 according to FIG. 1 can be identical or identical to the comparator unit 51 according to FIG.

Although the invention has been further illustrated and described in detail by the preferred embodiment, the invention is not limited by the disclosed example, and other variations can be derived therefrom by those skilled in the art without departing from the scope of the invention.

Reference sign list

10 logic gate arrangement

20 dual-port memory module 21 first input port

22 first output port

23 second input port

24 second output port

30 read-out device

40 address counters

40a first address output

40b second address output

40c first entrance

40d second input

41 counters

42 multiplexers

43 comparator

44 control line

50-1 evaluation device

50-n evaluation device

50a first entrance

50b second entrance

51 first comparator unit

52 second comparator unit

53 multiplexers

100 memory module

110 program code

511 comparator

512 AND gate

AI first memory cell address

A2 second memory cell address

A50 output of the evaluation device

A53 Output of the multiplexer Bsl Signal pictures

Bs2 signal images

Bs3 signal images

Bs4 signal images 150-1 connection

I50-n connection

1-1 Speieherinhalt

I-n Speieherinhalt

I (AI) Speieherinhalt

I (A2) Species content

IB-1 to IB information bit

IV- 1 to IV information bit

LSB least significant address bit

Sl signal

S2 signal

S3 signal

S4 signal

ST1 control signal

ST2 control signal

V-1 to V-q comparison signal

W truth pieces

Z counter reading

Zmin minimum count

Zmax Maximum count

Claims

claims

1. Field programmable logic gate arrangement (10),

marked by

- A dual-port or multiport memory device (20) with a predetermined number of ports that allow a parallel Ab ^¬ question the memory module (20), and

- A read-out device (30) which is adapted to read memory cells of the dual-port or multiport memory module (20) paral ^¬ lel to at least two ports of the memory module (20), the output at the at least two ports ^NEN memory contents (I (AI , I (A2)), In) to compare) in parallel with a (pre ^¬ given memory content 1-1 and in accordance of the memory contents a compliance signaling result signal (S1-S4) and / or the corresponding memory cell address of the pre give ^¬ NEN memory content To output (1-1, In) having memory cell.

2. Arrangement according to claim 1,

d a d u r c h e c e n c i n e s that

readout means (30) is designed such that it at one port of the memory device (20) one address bit (LSB) of the memory cell addresses (A2) with a logical "one" permanently preset, and (to a different port of the storage construction ^¬ steins the same address bit LSB ) of the memory cell addresses (AI) with a logical "zero" fixed.

3. Arrangement according to one of the preceding claims, characterized in that a

, the read-out means (30) is designed such that it acts on the at least two ports of the memory device (20) having Speicherzellenad ^¬ ests (Al, A2) in parallel reading out of the memory contents, wherein a predetermined subset of address bits each port individually with a fixed Adressbitinformation is fixed and in which the remaining address bits are changed during the read-out process.

4. Arrangement according to one of the preceding claims,

d a d u r c h e c e n c i n e s that

the read-out device (30) comprises an address counter (40) which can pass through a predetermined address space of the memory module (20) and has at least two address outputs (40a, 40b), at each of which a memory cell address (AI, A2) is output, the address counter (40) to the at least two address outputs (40a, 40b) Speicherzellenadres- sen (Al, A2) outputs, in which a predetermined subset of address bits each port individually preassigned fixed with a fixed pre give ^¬ NEN Adressbitinformation and in which the other address bits during the Counting be changed identically ^¬ changed.

5. Arrangement according to one of the preceding claims,

d a d u r c h e c e n c i n e s that

the read-out device (30) has at least one evaluation device (50-1, 50-n), on the input side of which the memory contents (I (A1) output by the memory module (20),

I (A2)), the predetermined memory content (1-1, bear In) and each ^¬ weils selected memory cell addresses and the output side that memory cell address outputs for which the memory content with the given memory content is identical.

6. Arrangement according to one of the preceding claims,

d a d u r c h e c e n c i n e s that

- The read-out device (30) has a plurality of inputs

(150-1, I50-n), in each case an individual

Memory content (1-1, I-n) can be input and to each of which a connection-specific evaluation device (50-1, 50-n) is assigned,

- Wherein at each evaluation device (50-1, 50-n) on the input side of the memory module (20) output

Memory contents (I (A1), I (A2)), the individually ^{vorgebe ¬} ne memory contents (1-1, In) and the respective selected memory cell addresses are present and - Each evaluation device (50-1, 50-n) outputs on the output side that memory cell address for which the Spei ^¬ cherinhalt is identical to the individually entered memory content.

7. Arrangement according to one of the preceding claims,

d a d u r c h e c e n c i n e s that

the start address and the end address of the memory cell area to be searched are stored in the memory module (20).

8. Arrangement according to one of the preceding claims,

d a d u r c h e c e n c i n e s that

- The memory module (20) is a dual port memory module with two ports, which allow a parallel query of Spei ^¬ cherbausteins, and

- The read-out device (30) is designed such that it pre- ^¬ given address bit of the memory cell addresses with one logical "one" fixed at one of the two ports of the memory module and at the other of the two ports of the memory chip the same address bit of the memory cell addresses with a logical "Zero" fixed.

9. Arrangement according to claim 8,

d a d u r c h e c e n c i n e s that

the address bit having a logical "one" or a logical "zero" is the least significant address bit (LSB).

10. A method of operating a field programmable logic gate array,

d a d u r c h e c e n c i n e s that

- All memory cells or a subset of memory cells of an integrated in the logic gate array (10) dual port or multiport memory device (20) are read, the contents of the memory cells (I (A1), I (A2)) with a predetermined Memory contents (1-1), In) compared and, if the memory contents match, a result signal indicating the coincidence and / or the memory cell address of the respective memory cell is output,

- wherein a parallel inquiry is carried out on a predetermined number of ports of the memory device by being ^¬ read at least two ports of the memory device in parallel and the memory contents outputted to the at least two ports are compared in parallel with the predetermined Speicherin- halt.

11. Memory module (100) with a program code (110) stored therein for a field-programmable logic gate arrangement (10) according to one of the preceding claims 1-9, characterized in that

the program code (110) is adapted to program the field programmable logic gate array (10) to form in the field programmable logic gate array (10) a readout means (30) suitable for storing dual port memory cells or multiport memory module (20) at at least two ports of Spei ^¬ cherbausteins (20) read out in parallel,

- to compare the output at the at least two ports memory contents (I (A1), I (A2)) in parallel with a predetermined memory contents (1-1, I-n) and

- a signaling the correspondence result signal (S1-S4) and / or the corresponding memory cell address of the pre ^¬ given memory content having the memory cell pass exclusively in correspondence of the memory contents.

12. Arrangement with a memory module according to claim 11 and a field programmable logic gate arrangement according to one of the preceding claims 1-9.