BR112014020003A2 - - Google Patents

Info

Publication number
BR112014020003A2
BR112014020003A2 BR112014020003A BR112014020003A BR112014020003A2 BR 112014020003 A2 BR112014020003 A2 BR 112014020003A2 BR 112014020003 A BR112014020003 A BR 112014020003A BR 112014020003 A BR112014020003 A BR 112014020003A BR 112014020003 A2 BR112014020003 A2 BR 112014020003A2
Authority
BR
Brazil
Application number
BR112014020003A
Other languages
Portuguese (pt)
Other versions
BR112014020003A8 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of BR112014020003A2 publication Critical patent/BR112014020003A2/pt
Publication of BR112014020003A8 publication Critical patent/BR112014020003A8/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
BR112014020003A 2012-02-15 2012-02-15 LOGICAL ACCESS ARRANGEMENT, METHOD FOR OPERATING A LOGICAL ACCESS ARRANGEMENT, AND, MEMORY CHIP BR112014020003A8 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2012/052549 WO2013120516A1 (en) 2012-02-15 2012-02-15 Field-programmable logic gate arrangement

Publications (2)

Publication Number Publication Date
BR112014020003A2 true BR112014020003A2 (en) 2017-06-20
BR112014020003A8 BR112014020003A8 (en) 2017-07-11

Family

ID=45688477

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112014020003A BR112014020003A8 (en) 2012-02-15 2012-02-15 LOGICAL ACCESS ARRANGEMENT, METHOD FOR OPERATING A LOGICAL ACCESS ARRANGEMENT, AND, MEMORY CHIP

Country Status (5)

Country Link
EP (1) EP2801154A1 (en)
CN (1) CN104115402B (en)
BR (1) BR112014020003A8 (en)
RU (1) RU2014137144A (en)
WO (1) WO2013120516A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6211695B1 (en) * 1999-01-21 2001-04-03 Vantis Corporation FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections
US6353332B1 (en) * 2000-02-07 2002-03-05 Xilinx, Inc. Methods for implementing CAM functions using dual-port RAM
US7380053B2 (en) * 2005-03-17 2008-05-27 International Business Machines Corporation Method and system for emulating content-addressable memory primitives
US7589555B1 (en) * 2007-01-08 2009-09-15 Altera Corporation Variable sized soft memory macros in structured cell arrays, and related methods
US7483283B2 (en) * 2007-03-30 2009-01-27 Motorola, Inc. Apparatus for efficient streaming data access on reconfigurable hardware and method for automatic generation thereof

Also Published As

Publication number Publication date
EP2801154A1 (en) 2014-11-12
WO2013120516A1 (en) 2013-08-22
BR112014020003A8 (en) 2017-07-11
RU2014137144A (en) 2016-04-10
CN104115402A (en) 2014-10-22
CN104115402B (en) 2017-03-15

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]
B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]