WO2013095010A1 - Procédé de fabrication d'une cellule solaire à contact arrière - Google Patents

Procédé de fabrication d'une cellule solaire à contact arrière Download PDF

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Publication number
WO2013095010A1
WO2013095010A1 PCT/KR2012/011179 KR2012011179W WO2013095010A1 WO 2013095010 A1 WO2013095010 A1 WO 2013095010A1 KR 2012011179 W KR2012011179 W KR 2012011179W WO 2013095010 A1 WO2013095010 A1 WO 2013095010A1
Authority
WO
WIPO (PCT)
Prior art keywords
etching
semiconductor substrate
conductive type
layer
electrode
Prior art date
Application number
PCT/KR2012/011179
Other languages
English (en)
Inventor
Woo Won Jung
Jae Eock Cho
Hong Gu Lee
Se-Young Seo
Deoc Hwan Hyun
Yong Hwa Lee
Gang II KIM
Original Assignee
Hanwha Chemical Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020120084073A external-priority patent/KR101341831B1/ko
Application filed by Hanwha Chemical Corporation filed Critical Hanwha Chemical Corporation
Publication of WO2013095010A1 publication Critical patent/WO2013095010A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the following disclosure relates to a manufacturing method of a back contact solar cell, and in particular, to a manufacturing method of a back contact solar cell allowing a light receiving surface and a back surface, which is an opposite surface to the light receiving surface, to have different sheet resistances, by a simple doping process, and having high short current, open voltage, and fidelity to thereby exhibit excellent photovoltaic conversion efficiency.
  • Patent Document 1 Korean Patent Laid-Open Publication No. 2007-0004671
  • An embodiment of the present invention is directed to providing a manufacturing method of a back contact solar cell having high short current, open voltage, and fidelity, through a single doping process to thereby exhibit excellent photovoltaic conversion efficiency; a manufacturing method of a back contact solar cell capable of preventing generation of leakage current at the time of forming electrodes; and a manufacturing method of a back contact solar cell capable of decreasing the number of process stages and reducing the manufacturing time to thereby achieve cost reduction and high productivity.
  • the method may further include: f) forming dielectric layers by forming a passivation film on one surface of the semiconductor substrate and an anti-reflection film on the other surface of the semiconductor substrate; g) partially removing the passivation film by partially coating an etching paste for etching the passivation film on one surface, to thereby expose a region of the semiconductor substrate, from which the layer of a second conductive type is removed by the selective etching; and h) forming electrodes by forming, on one surface, a first electrode connected with the exposed region of the semiconductor substrate and a second electrode connected with layer of a second conductive type through punch-through.
  • the partial etching may be carried out by dry etching.
  • the thickness of the layer of a second conductive type formed on an inner surface of the via hole may be reduced from one surface of the semiconductor substrate toward the other surface of the semiconductor substrate by the partial etching.
  • the etching-resist pattern may be formed by a printing process, and the printing
  • a back contact solar cell is manufactured by the foregoing method.
  • FIG, 1 is a process view showing a manufacturing method of a back contact solar cell according to an embodiment of the present invention.
  • the manufacturing method may include: forming a via hole 1 to pass through two opposing surfaces of a semiconductor substrate 100 of a first conductive type; allowing an impurity of a second conductive type to be diffused into surfaces of the semiconductor substrate 100 including the two opposing surfaces of the semiconductor substrate and an inner surface of the via hole, to thereby form layers of a second conductive type 210, 220, and 230 on the two opposing surfaces of the semiconductor substrate and the inner surface of the via hole 1 ; coating an etching-resist on at least one of the two opposing surfaces to cover an opening portion of the via hole 1 to form an etching-resist pattern 300; selectively etching one surface of the semiconductor substrate using the etching-resist pattern 300 as an etching mask, to thereby remove a portion of the layer of a second conductive type present
  • the first conductive type may mean p-type conductivity due to a p-type impurity
  • the second conductive type may mean n-type conductivity due to an n-type impurity which is an impurity complementary to the p-type impurity
  • the p-type impurity may include an impurity that is doped in a semiconductor substrate to provide holes
  • the n-type impurity may include an impurity that is doped in a semiconductor substrate to provide electrons.
  • the p-type impurity may be one or two or more selected from aluminum, boron, and indium
  • the n-type impurity may be one or two or more selected from arsenic and phosphorous.
  • the forming of the via hole may include forming the via hole 1 to pass through the two opposing surfaces of the semiconductor substrate 100, for example, a light receiving surface receiving a solar light and a back surface which is an opposite surface to the light receiving surface.
  • a plurality of via holes may be regularly spaced apart from each other such that an MxN matrix is composed of M opening portions of via holes 1 in a first direction and N opening portions of via holes 1 in a second direction.
  • the first direction and the second direction belong in the same plane (a surface of the semiconductor substrate), and the first direction and the second direction may have a predetermined angle including 90°.
  • the etching-resist pattern 300 may be formed on one of the opposing surfaces of the semiconductor substrate 100 through which the via hole 1 passes, to cover the opening portion of the via hole 1.
  • the etching-resist pattern 300 may include a plurality of bands spaced apart in parallel with each other in the first direction and the bands (etching-resist bands) may cover all the opening portions of the plurality of via holes 1 positioned on the same line in the second direction.
  • the back emitter layer 210 may be patterned to have a shape corresponding to the etching-resist pattern 300.
  • the back emitter layer 210 is patterned to have a shape and a place corresponding to a shape and a place of the n-type finger electrodes (and the n-type bus bar electrode) by carrying out the selective etching (step (d)), and a surface step height is formed in the back surface of the semiconductor substrate 100, so that leakage current can be prevented from being generated and fidelity can be improved.
  • the selective etching may be earned out by using wet etching or dry
  • the emitter layer 220 is formed, is etched by a predetermined depth, using dry etching having directivity, so that the thickness of the via hole emitter layer 230 formed on the inner surface of the via hole can be also regulated. That is, through the partial etching (step (e)), the thickness of the via hole emitter layer 230 formed on the inner surface of the via hole 1 may be decreased from the back surface of the semiconductor substrate 100 toward the light receiving surface of the semiconductor substrate 100, and the thickness of the via hole emitter layer 230 may be continuously decreased from the back surface of the semiconductor substrate 100 toward the light receiving surface of the semiconductor substrate 100.
  • FIG. 2 is a scanning electron microscope (SEM) image obtained by observing a cross section of the via hole when the partial etching is performed using plasma etching.
  • the term "front surface” means the light receiving surface and the term “rear surface” means the back surface.
  • P1-P5 represent regions analyzed by using an energy dispersive spectroscopy (EDS) equipped at the scanning electron microscope (SEM). Each of numerals (mm) positioned below P1 ⁇ P5 shows p-n junction depth, that is, thickness of the via hole emitter layer for each region.
  • EDS energy dispersive spectroscopy
  • the p-n junction depth between the via hole emitter layer and the substrate is thinner from the back surface toward the light receiving surface. This results from straight directivity of etching at the time of dry etching, and it can be seen that the depth of the via hole emitter layer is gradually thinner from the back surface toward the light receiving surface due to dry etching.
  • step (e) a washing process using a radio corporation of
  • step f forming of dielectric films (step f) may be further carried out by forming a passivation film 500 on one surface of the semiconductor substrate and an antireflection film 400 on the other surface of the semiconductor substrate.
  • the antireflection film 400 formed on one surface of the semiconductor substrate 100 on which the front emitter layer 220 is formed means a film that does both of roles of preventing the light received into the solar cell from again escaping out of the solar cell and passivating a surface defect acting as an electron trap site in the surface of the semiconductor substrate 100.
  • the antireflection film 400 may be a multilayer thin film where different material layers are stacked, in order to maximize the reflection preventing action and effectively passivate the defect.
  • a single film type antireflection film 400 may be a silicon nitride film, a silicon nitride film or containing hydrogen, or a silicon oxynitride film, and a multilayer thin film type antireflection film 400 may include a stacked thin film where films of at least two selected from silicon oxide, silicon nitride, A1 2 0 3 , MgF 2 , ZnS, MgF 2 , Ti0 2 , and Ce0 2 are stacked.
  • the passivation film 500 formed on the other surface of the semiconductor substrate, on which the patterned back emitter layer 211 is formed, means a film that does a role of passivating a surface defect acting as an electron trap site in the surface of the semiconductor substrate 100.
  • the passivation film 500 may include a film of semiconductor oxide, semiconductor nitride, semiconductor oxide containing nitrogen, semiconductor nitride containing hydrogen, semiconductor carbide, or titania, or a stacked thin film thereof.
  • the partial removing of the passivation film 500 may be carried out by coating an etching paste for etching a passivation film.
  • any paste that can etch the passivation film 500 may be used.
  • any paste that can etch the passivation film 500 may be used.
  • use products including SolarEtch series (MERCK Company) may be used as the etching paste.
  • a p-type electrode 600 is formed on the p-type semiconductor region surface- exposed due to the removal of the passivation film.
  • the p-type electrode 600 may include a plurality of band shaped finger electrodes spaced apart from each other and a bus bar electrode electrically connecting the plurality of finger electrodes.
  • the constitution described above of forming the layers of a second conductive type through one stage of doping process, forming the high-concentration back emitter layer through selective etching, forming a low-concentration front emitter layer through partial etching, forming the dielectric film, and removing the passivation film for forming the p-type electrode, can have high short current, open voltage, and fidelity, through a simple process such as partial etching using one stage of doping and printing; prevent leakage current from being generated at the time of forming •electrodes; and allowing the manufacture of a high-efficiency solar cell in a short time through the simple process, thereby realizing reduction of cost and superior productivity.
  • step (h) After the removing of the passivation film (step (g)), forming of electrodes (step (h)) is carried out to form the n-type electrode and the p-type electrode.
  • the n- type electrode and the p-type electrode are formed by coating an n-type electrode material and coating a p-type electrode material and then carrying out heat treatment.
  • the p-type electrode material is coated on the p-type region
  • a back surface field (BSF) 610 is formed by the heat treatment at the time of forming the p-type electrode, and the p-type electrode material preferably contains aluminum so as to be bound to the semiconductor substrate.
  • the n-type electrode (second electrode) 700 includes a 2-1 electrode after punch through 71 1 and a 2-2 electrode 720.
  • the 2-1 electrode 71 1 is connected with the patterned back emitter layer 211 through a punch through phenomenon penetrating the passivation film.
  • the 2-2 electrode 720 is formed on the 2-1 electrode 711 such that the 2-2 electrode 720 does not pass through the passivation film and covers the 2-1 electrode 711.
  • a 2-1 electrode before heat treatment 710 is a connection electrode for passing
  • electrode may be one or two or more selected from silver (Ag), copper (Cu), titanium (Ti), gold (Au), aluminum (Al), tungsten (W), nickel (Ni), chrome (Cr), molybdenum (Mo), platinum (Pt), lead (Pb), palladium (Pd), and an alloy thereof, and silver, copper, nickel, aluminum, or an alloy thereof is preferable in view of a low melting point and excellent electric conductivity.
  • the glass frit that is contained in the 2-1 electrode and etches the passivation film lead glass containing lead oxide or lead-free glass containing bismuth oxide or boron oxide, which is generally used to form an electrode of a solar cell, may be used.
  • the glass frit contained in the 2-2 electrode does not interface-react with the passivation film to improve physical binding strength of the 2-2 electrode, and thus serves to increase interface binding strength between the patterned back emitter layer and the 2-1 electrode.
  • the conductive material contained in the 2-2 electrode is preferably a conductive material enables smooth densification and grain growth by the heat that is applied for punch through of the first electrode.
  • the glass frit contained in the 2-2 electrode is preferably a silica based or phosphate based glass not containing B, Bi, and Pb, of which the glass temperature (Tg) 1.2 - 2 times that of the glass frit contained in the 2-1 electrode.
  • the n-type electrode that collects electrons or holes generated by irradiation of light may include the 2-1 electrode and the 2-2 electrode.

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  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une cellule solaire à contact arrière, le procédé consistant : a) à former un trou d'interconnexion pour traverser deux surfaces opposées d'un substrat semi-conducteur d'un premier type conducteur ; b) à doper une impureté d'un second type conducteur dans des surfaces du substrat semi-conducteur pour former des couches d'un second type conducteur ; c) à former un motif résistant à la gravure sur une des deux surfaces opposées pour couvrir une partie d'ouverture du trou d'interconnexion ; d) à graver sélectivement une surface du substrat semi-conducteur en utilisant le motif résistant à la gravure comme masque de gravure, pour retirer ainsi une partie de la couche d'un second type conducteur présente sur une surface du substrat semi-conducteur sur laquelle le motif résistant à la gravure n'est pas formé ; et e) à graver partiellement la couche d'un second type conducteur présente sur l'autre surface du substrat semi-conducteur, laquelle est opposée à une surface du substrat semi-conducteur, pour contrôler ainsi une concentration de l'impureté dans la couche d'un second type conducteur présente sur l'autre surface du substrat semi-conducteur.
PCT/KR2012/011179 2011-12-23 2012-12-20 Procédé de fabrication d'une cellule solaire à contact arrière WO2013095010A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2011-0140698 2011-12-23
KR20110140698 2011-12-23
KR1020120084073A KR101341831B1 (ko) 2011-12-23 2012-07-31 후면 전극 태양전지의 제조방법
KR10-2012-0084073 2012-07-31

Publications (1)

Publication Number Publication Date
WO2013095010A1 true WO2013095010A1 (fr) 2013-06-27

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PCT/KR2012/011179 WO2013095010A1 (fr) 2011-12-23 2012-12-20 Procédé de fabrication d'une cellule solaire à contact arrière

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WO (1) WO2013095010A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050176164A1 (en) * 2004-02-05 2005-08-11 Advent Solar, Inc. Back-contact solar cells and methods for fabrication
US20110005582A1 (en) * 2007-12-03 2011-01-13 Imec Photovoltaic cells having metal wrap through and improved passivation
WO2011081336A2 (fr) * 2009-12-28 2011-07-07 현대중공업 주식회사 Procédé de fabrication d'une cellule solaire à contact arrière
WO2011105907A1 (fr) * 2010-02-26 2011-09-01 Stichting Energieonderzoek Centrum Nederland Procédé de fabrication d'une cellule photovoltaïque à contact à l'arrière, ainsi que cellule photovoltaïque à contact à l'arrière fabriquée par ce procédé
US20110290323A1 (en) * 2010-12-17 2011-12-01 Youngsik Lee Solar cell and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050176164A1 (en) * 2004-02-05 2005-08-11 Advent Solar, Inc. Back-contact solar cells and methods for fabrication
US20110005582A1 (en) * 2007-12-03 2011-01-13 Imec Photovoltaic cells having metal wrap through and improved passivation
WO2011081336A2 (fr) * 2009-12-28 2011-07-07 현대중공업 주식회사 Procédé de fabrication d'une cellule solaire à contact arrière
WO2011105907A1 (fr) * 2010-02-26 2011-09-01 Stichting Energieonderzoek Centrum Nederland Procédé de fabrication d'une cellule photovoltaïque à contact à l'arrière, ainsi que cellule photovoltaïque à contact à l'arrière fabriquée par ce procédé
US20110290323A1 (en) * 2010-12-17 2011-12-01 Youngsik Lee Solar cell and method for manufacturing the same

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