WO2013094416A1 - 高周波モジュール及びそれを用いた携帯端末 - Google Patents
高周波モジュール及びそれを用いた携帯端末 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
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- H03—ELECTRONIC CIRCUITRY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/50—Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
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- H—ELECTRICITY
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- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/38—Impedance-matching networks
- H03H7/40—Automatic matching of load impedance to source impedance
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- H—ELECTRICITY
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
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- H03F2203/45454—Indexing scheme relating to differential amplifiers the CSC comprising biasing means controlled by the input signal
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- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45476—Indexing scheme relating to differential amplifiers the CSC comprising a mirror circuit
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Definitions
- the present invention relates to a high-frequency module, and more particularly to a technique that is used in a mobile terminal and is effective when applied to a high-frequency module that transmits a high-frequency signal.
- Patent Document 1 describes that a low-pass filter is formed by a passive element in a bias portion of an amplifying transistor and a high-frequency component is reduced by adjusting impedance to ensure linearity.
- An amplifier circuit is disclosed.
- the low-pass filter is formed of a passive element, and there is no awareness of the reduction of high-frequency components of a plurality of frequencies that are generated when the frequency band width changes.
- the high-frequency module includes an amplifier circuit having an amplification transistor and a variable impedance circuit, and a matching circuit connected to the amplifier circuit.
- the output impedance of the amplifier circuit changes according to a control signal corresponding to the width of the frequency band supplied to the variable impedance circuit.
- the high frequency component can be reduced, and the linearity can be ensured.
- FIG. 1 is a circuit diagram showing a high-frequency module according to Embodiment 1.
- FIG. 3 is an explanatory diagram for explaining the first embodiment.
- FIG. 3 is a circuit diagram illustrating a voltage follower circuit used in the high-frequency module according to Embodiment 1.
- FIG. 3 is an explanatory diagram for explaining the first embodiment.
- FIG. 3 is a circuit diagram illustrating an example of a buffer current control circuit used in the high-frequency module according to Embodiment 1.
- FIG. FIG. 6 is a circuit diagram illustrating another example of a buffer current control circuit used in the high frequency module according to the first embodiment.
- 3 is an explanatory diagram for explaining the first embodiment.
- FIG. 3 is a block diagram illustrating an example of a mobile terminal that uses the high-frequency module according to Embodiment 1.
- FIG. 3 is a block diagram illustrating an example of a mobile terminal that uses the high-frequency module according to Embodiment 1.
- FIG. 6 is a block diagram illustrating another example of a mobile terminal using the high-frequency module according to Embodiment 1.
- FIG. 3 is an explanatory diagram for explaining the first embodiment.
- FIG. 5 is a circuit diagram showing a high-frequency module according to Embodiment 2.
- FIG. 6 is a circuit diagram showing a voltage follower circuit of a high-frequency module according to Embodiment 2.
- FIG. 3 is a circuit diagram showing an example of a matching circuit according to the first and second embodiments.
- a high-frequency module compatible with LTE Long Term Evolution
- LTE Long Term Evolution
- a plurality of frequency bands adjacent to each other are used as carrier waves, and a communication signal (hereinafter also referred to as a high frequency signal) is a combination of signals in the respective frequency bands.
- a communication signal hereinafter also referred to as a high frequency signal
- the plurality of units fall within the frequency band width defined by the LTE communication standard. Examples of the frequency band width defined by the LTE communication standard include 5 MHz, 10 MHz, 15 MHz, and 20 MHz.
- the second-order distortion component means a distortion component of the output signal caused by the square component of the nonlinear characteristic of the amplifier
- the third-order distortion component is caused by the cube component of the nonlinear characteristic of the amplifier. This means the distortion component of the output signal.
- the input signal is a composite of two signals with angular frequencies ⁇ 1 and ⁇ 2 (Equation 2).
- equation (4) is obtained as the third-order distortion component.
- FIG. 2 shows the second term of Equation (3) in the second-order distortion component and the second and fourth terms of Equation (4) in the third-order distortion component on the frequency axis.
- main signals 401 and 402 are components of the input signal to be originally amplified (the level of the output signal having the same frequency as the frequency of the input signal), and exist in the frequency band of the input signal.
- signals 403 and 404 are third-order distortion components
- signal 405 is a second-order distortion component.
- the signal 403 is the third-order distortion component of the second term of equation (4)
- the signal 404 is the third-order distortion component of the fourth term of equation (4).
- Signal 405 corresponds to the second-order distortion component of the second term of equation (3).
- the signals 403 and 404 which are third-order distortion components, are generated in the adjacent frequencies of the main signals 401 and 402, and thus cause the above-described adjacent channel interference. For this reason, the amplifier is required to have a low third-order distortion component of the output signal.
- the input signal is an example of the synthesis of two signals having different frequencies.
- an input signal which is a communication signal is actually a synthesis of signals existing in a plurality of frequency bands.
- it can be considered as a synthesis of signals in a frequency band width (for example, 5 MHz) defined by a communication standard.
- FIG. 10 shows frequency characteristics of an output signal when a communication signal formed by combining a plurality of signals existing in a frequency band width that is closer to an actual communication signal than two waves is input to an amplifier. Show.
- an output signal indicated by the solid line is obtained if the amplifier does not have any nonlinear characteristics. That is, when the amplifier has no nonlinear characteristic, the above-described third-order distortion component does not occur, and only a signal in a frequency band corresponding to the frequency band of the communication signal is output.
- a characteristic indicated by a broken line is an output characteristic of a signal in which the amplifier has a nonlinear characteristic and is affected by the third-order distortion component.
- ⁇ 1 is a fundamental frequency (input signal frequency) coefficient
- ⁇ 2 is a second-order nonlinear term coefficient
- ⁇ 3 is a third-order nonlinear term coefficient.
- ⁇ 2 and ⁇ 3 indicate how much distortion components are added to the output signal due to the nonlinear characteristics of the amplifier.
- A1 represents the amplitude of one of the two input signals
- A2 represents the amplitude of the other of the two input signals.
- the signal is two sine waves having different frequencies.
- the amplifying transistor is, for example, a field effect transistor (hereinafter also referred to as a MOS transistor), and the input signal and a part of the second-order distortion component are superimposed on the gate and supplied for amplification as described above.
- the input signal is A1 cos ⁇ 1t, which is one of the main signals, and A3 cos ( ⁇ 2- ⁇ 1) t, which is the second order distortion component, and substituting these terms into equation (1),
- A3 means ⁇ 2 ⁇ A1 ⁇ A2.
- A4 means ⁇ 2 ⁇ A1 ⁇ A2 for simplification of the equation.
- Equations (5) and (6) are equal to the frequencies of the second and fourth terms of Equation (4), which are the aforementioned third-order distortion components, these third-order distortion components are superimposed on each other. Will be. In other words, the presence of the second-order distortion component increases the third-order distortion component that causes the adjacent channel interference.
- the frequency at which the second-order distortion component appears changes according to the width of the band.
- the bandwidth of the frequency band of the input signal is ⁇ 4 to ⁇ 3 ( ⁇ 4 > ⁇ 3 )
- the 2nd order distortion component appears at a frequency of 0 to ⁇ 4 ⁇ 3 .
- the bandwidth (width) of the frequency band means 5 MHz, 10 MHz, 15 MHz, 20 MHz or the like in the case of LTE. Therefore, when 5 MHz is taken as an example, the secondary distortion component appears at 0 to 5 MHz, and at 10 MHz, the secondary distortion component appears at 0 to 10 MHz.
- the high frequency module 10 includes an amplifier circuit 20 and an output matching circuit 109.
- the amplifier circuit 20 includes an output terminal 112, a high frequency amplification transistor 106, and a variable impedance circuit 103.
- the variable impedance circuit 40 receives a control signal according to the frequency band width of the communication signal, and its output impedance changes according to the value of the control signal.
- the output impedance of the amplifier circuit 20 viewed from the output terminal 112 is at least a combined impedance of the variable impedance circuit 40 and the amplifying transistor 106, and changes when the output impedance of the variable impedance circuit 40 is changed.
- the output impedance of the amplifier circuit 20 can be changed by the control signal for each frequency band width of the communication signal.
- the second-order distortion component is matched with the matching circuit 109 without matching the impedance of the output matching circuit 109 viewed from the output terminal 112 and the output impedance of the amplifier circuit 20 in the frequency band of the second-order distortion component. Reflect to.
- the amount of transmission of the second-order distortion component signal to the amplifier circuit 20 is reduced, the generation of unnecessary signals of the third-order distortion component is reduced, and the linearity of the amplifier circuit can be ensured. It is possible to provide a high-frequency module with reduced interference with adjacent channels.
- the variable impedance circuit has a buffer circuit, and the buffer circuit is connected so as to constitute a voltage follower circuit.
- the voltage follower circuit receives a bias voltage for biasing the amplifying transistor 106 from the bias circuit, and supplies a bias voltage corresponding to the received bias voltage to the amplifying transistor.
- the high frequency signal is also transmitted to the output of the voltage follower circuit.
- the input and output of the voltage follower circuit are electrically separated, it is possible to prevent the high frequency signal from being transmitted to the bias circuit.
- the voltage follower circuit also functions as the variable impedance circuit described above, so that it is possible to reduce interference with adjacent channels.
- FIG. 1 shows a circuit diagram of a high-frequency module according to the embodiment 1.
- the high frequency module 10 includes an amplifier circuit 20, a bias circuit 30, and an output matching circuit 109.
- the amplification circuit 20 includes a high frequency amplification transistor 106 and a variable impedance circuit 40.
- the variable impedance circuit 40 includes a voltage follower circuit 103 configured by a buffer circuit.
- the bias circuit 30 includes a bias current source 101 and a bias MOS transistor 102.
- the bias MOS transistor 102 has its drain and source connected, and a bias current is supplied to the drain from the bias power source 101.
- the bias circuit 30 generates a constant voltage according to the bias current from the bias current source 101 and supplies it to the positive input (+) of the voltage follower circuit 103.
- the output of the voltage follower circuit 103 is connected to its negative input.
- the output of the voltage follower circuit 103 is connected to the gate of the high-frequency amplification transistor 106 via a resistor 104 for reducing a high-frequency signal.
- the gate of the amplifying transistor 106 is biased by a bias voltage output from the voltage follower circuit 103.
- a high-frequency communication signal (high-frequency signal) is supplied from the input matching circuit 108 to the gate of the amplifying transistor 106 through a DC cut capacitor 105 for cutting a DC component.
- the resistor 104 functions to attenuate transmission of a high-frequency signal to the voltage follower circuit 103.
- the high-frequency signal transmitted to the output of the voltage follower circuit 103 without being attenuated by the resistor 104 electrically separates the bias circuit 30 and the resistor 104 (or the gate of the amplifying transistor 106) by the voltage follower circuit 103.
- the resistor 104 can be omitted for the purpose of attenuating the high-frequency signal.
- the amplification circuit 20 (including the voltage follower circuit 103, the resistor 40, the amplification transistor 106, and the capacitor 105) and the bias circuit 30 (including the transistor 102 and the bias current source 101) are not particularly limited. Are formed on one semiconductor chip.
- the amplifier circuit 20 When the amplifier circuit 20 is formed on a semiconductor chip, if a coil is used to reduce high-frequency signals, the area occupied by the semiconductor chip increases. By using the voltage follower circuit as in this embodiment, it is possible to suppress an increase in the area of the semiconductor chip.
- the input matching circuit 108 is a matching circuit for impedance matching between the amplifier or signal source (not shown) connected to the terminal 111 and the amplifier circuit 20.
- the load inductor 107 is connected between the output terminal 112 and the power supply voltage point Vdd, and operates as a load of the high frequency amplification transistor 106.
- the output matching circuit 109 is connected between a subsequent circuit (not shown) connected to the terminal 113 of the module and the output terminal 112 of the amplifier circuit 20 to achieve impedance matching.
- a buffer current control circuit 110 controls the current of the voltage follower circuit 103.
- a frequency band selection circuit 201 is provided outside the high frequency module 10. As will be described in detail later, the frequency band selection unit 201 is used to specify the frequency band width of the communication signal amplified by the amplifier circuit 20.
- the high frequency amplifying transistor 106 is biased by the bias voltage supplied from the voltage follower circuit 103 via the resistor 104 and amplifies the high frequency signal supplied via the direct current cut capacitor 105, and outputs the output matching circuit 109. To output.
- FIG. 3 is a circuit diagram showing an example of the voltage follower circuit 103.
- the operational amplifier circuit constituting the voltage follower circuit includes a bias current source 10308, input terminals 10301 and 10302, a differential amplification stage 10310, a second amplification stage 10320, and an output terminal 10307.
- the differential amplification stage 10310 has a pair of differential amplification MOS transistors 10303 and 10304, and the gate (input terminal 10302) of one differential amplification MOS transistor 10304 is connected to the positive input terminal of the voltage follower circuit 103.
- the gate (input terminal 10301) of the other differential amplification MOS transistor 10303 is the negative input terminal of the voltage follower circuit 103.
- a pair of load MOSFETs 10340 and 10341 connected in a current mirror connection is connected to the pair of differential amplification MOS transistors.
- the second amplification stage includes an amplification MOS transistor 10305 and a phase compensation capacitor 10306.
- MOSFETs 10330, 10331, and 10332 for current sources are current mirror connected, and supply currents according to the current from the bias current source 10308 to the differential amplification MOS transistor and the amplification MOS transistor 10305.
- the output of the operational amplifier circuit is connected to the input terminal 10301.
- the voltage follower circuit 103 functions as the variable impedance circuit 40 (buffer circuit).
- the output frequency characteristic for the AC input signal that determines the output impedance characteristic when the voltage follower circuit of FIG. 3 is viewed as a buffer circuit is determined by the transconductance gm of the amplification MOS transistors 10303 and 10304 and the value C of the phase compensation capacitor 10306. .
- the unity gain frequency that is the cutoff frequency of the output frequency characteristic with respect to the AC input signal of the buffer circuit is ⁇ u .
- the transconductance gm of the MOS transistor is obtained by using the mobility ⁇ of the MOS transistor, the gate oxide film capacitance C OX per unit area, the gate width W, the gate length L, and the drain current ID. 8).
- the transconductance gm is changed by changing the drain current ID, and the cutoff frequency of the buffer frequency characteristic is changed. That is, the cutoff frequency of the buffer circuit can be changed by changing the drain currents of the amplification MOSFETs 103030 and 10304.
- the output impedance of the buffer circuit 40 can be changed by changing the drain current. That is, the output impedance of the buffer circuit (voltage follower circuit 103) can be changed by changing the drain current.
- FIG. 4 shows an example of frequency characteristics of the buffer circuit.
- the cutoff frequency decreases. Conversely, when the drain current ID increases, the cutoff frequency increases.
- the vertical axis represents the input / output signal level ratio, but it can be regarded as representing the output impedance of the buffer circuit 40 (voltage follower circuit 103).
- the output impedance of the amplifier circuit 20 When the output impedance of the amplifier circuit 20 is viewed from the output terminal 112 of the amplifier circuit 20, the output impedance is that of the high-frequency amplifier transistor 106, the resistor 104, the DC cut capacitor 105, and the buffer circuit 40 (voltage follower circuit 103). It becomes the synthetic impedance. Among these elements, it is difficult to adjust the impedance of the high frequency amplification transistor 106, the resistor 104, and the direct current cut capacitor 105 after the high frequency module is manufactured. On the other hand, as described above, the buffer circuit 40 (voltage follower circuit 103) can change the value of its output impedance, for example, by changing the drain current of the differential amplification MOSFET.
- the drain current of the differential amplification MOS transistor in the buffer circuit 40 is set to I1 when the frequency band of the secondary distortion component is 0 to f1 (for example, 0 to 5 MHz), the frequency band of the secondary distortion component is Matching occurs between the output impedance of the amplifier circuit 20 and the impedance viewed from the output terminal 112 to the output matching circuit 109 side.
- the secondary distortion component is transmitted from the output terminal 112 to the gate side of the high frequency amplification transistor 106.
- the drain current of the differential amplification MOS transistor in the buffer circuit 40 is set to I2 or I3, and the frequency band of the secondary distortion component is 0 to f2.
- the drain current is set to I3
- the frequency band of the secondary distortion component is 0 to f3 (0 to 15 MHz)
- the drain current is set to be larger than I3. This prevents matching from occurring within the frequency band of the secondary distortion component.
- the frequency band width of the communication signal is wide, the frequency band range of the secondary distortion component is wide, so the drain current of the differential amplification transistor is set large (for example, I3).
- the second order distortion component having a frequency higher than the frequency range of the second order distortion component matching is achieved between the output impedance of the amplifier circuit 20 and the impedance viewed from the output terminal 112 to the output matching circuit 109 side.
- reflection due to impedance mismatch can be performed in the frequency band of the secondary distortion component, and the secondary distortion component can be prevented from being transmitted to the gate side.
- the frequency band width of the communication signal is narrow, the frequency range of the secondary distortion component is also narrow.
- the drain current of the differential amplification MOS transistor is small, impedance is matched at a frequency higher than the frequency range of the secondary distortion component, and reflection due to impedance mismatch can be performed in the frequency band of the secondary distortion component. It is possible to prevent the component from being transmitted to the gate side. In this case, since the drain current of the differential amplification MOS transistor can be reduced, the power consumption can be reduced.
- the buffer circuit 40 is arranged so that the total combined impedance composed of the amplification transistor 106, the resistor 104, the DC cut capacitor 105, and the buffer circuit 40 does not match the impedance of the output matching circuit 109 viewed from the output terminal 112. Is set to a fixed value. By doing so, it is possible to prevent impedance matching between the combined impedance and the impedance on the output side of the amplification MOS transistor, and to prevent the secondary distortion component from being transmitted into the amplifier circuit 20. In this case, by configuring the voltage follower circuit with the buffer circuit, the coil for reducing the high-frequency signal as described above becomes unnecessary, and the semiconductor chip can be miniaturized.
- the width of the frequency band of the communication signal changes as in LTE, for example, if the output impedance of the buffer circuit 40 is fixed, the width of the frequency band of the communication signal changes.
- the width of the frequency band of the next distortion component also changes, and impedance matching occurs. Therefore, when the width of the frequency band of the communication signal changes, the output impedance of the buffer circuit 40, the combined impedance of the amplification MOS transistor 106, and the output matching circuit 109 from the output terminal 112 in the frequency band of the secondary distortion component at that time. Impedance matching is performed with the impedance viewed from the side, and transmission of the second-order distortion component occurs, resulting in an increase in the third-order distortion component.
- the output impedance of the buffer circuit 40 is controlled so that transmission of the secondary distortion component due to impedance matching does not occur.
- the frequency band selection circuit 201 transmits digital data indicating the width of the frequency band of the signal to be transmitted to the buffer current control circuit 110.
- the buffer current control circuit 110 forms a control signal corresponding to the width of the frequency band of the signal, and controls the current source 10308 of the buffer circuit 40 of FIG.
- FIG. 5 shows a circuit diagram of the current source 10308 of the buffer circuit 40.
- the current source 10308 includes resistors 505 to 508 and resistance changeover switches 509 to 512.
- a reference voltage source 501 provides a reference voltage Vref which is a voltage applied to one end of each of the resistors 505 to 508.
- the operational amplifier (comparator) 502 controls the voltages applied to the resistors 505 to 508 to be equal to the reference voltage by feedback control.
- a MOS transistor 503 serves as a current source for supplying a current to each of the resistors by the feedback control.
- the MOS transistor 504 is controlled by the operational amplifier 502 and becomes an output current source.
- the drain of the MOS transistor 503 is connected to the drain of the MOS transistor 10330 in FIG.
- the operational amplifier 502 the voltage applied to one end of the resistors 505, 506, 507, and 508 is fixed to the voltage of the reference voltage source 501.
- the current flowing from the drain of the MOS transistor 503 is determined by the resistance values of the resistors 505, 506, 507 and 508.
- the resistance to be used is switched by switches 509, 510, 511 and 512.
- the MOS transistors 503 and 504 are current mirror connected, when the gate lengths of these MOS transistors are equal, the ratio of the channel width of the MOS transistors 503 and 504 and the ratio of the current flowing through the MOS transistors 503 and 504 are the same. To do. That is, the current output from the MOS transistor 504 is (drain current of the MOS transistor 503) ⁇ ((channel width of the MOS transistor 504) / (channel width of the MOS transistor 503)). From the above, the desired current is supplied to the MOS transistor 10330 (FIG. 3) by adjusting the voltage of the reference voltage source 501, the resistance values of the resistors 505, 506, 507, and 508, and the channel width ratio of the MOS transistors 503 and 504. ).
- the adjustment of the resistance value of each resistor will be described.
- the value of the current source 10308 when the output impedance of the amplifier circuit 20 in FIG. Obtained for each frequency band width of communication signals by IC trial manufacture.
- the values of the resistors in FIG. 5 are adjusted so that the obtained current value is obtained.
- the switch 509 is turned on, and the value of the resistor 505 is adjusted so that the current value obtained with the frequency bandwidth of 5 MHz is obtained.
- the switch 510 is turned on and the value of the resistor 506 is adjusted so that the current obtained at 10 MHz is obtained.
- the resistor 507 (switch 511 is turned on) when the signal frequency bandwidth is 15 MHz
- the resistor 508 switch 512 is turned on
- the buffer current control circuit 110 turns on the switch 509 of the current source 10308 (FIG. 5), The other switches 510, 511 and 512 are turned off, and a control signal is generated so that only the resistor 506 is used. Even in the case of widths in other frequency bands, control is performed so that each resistor is used according to the bandwidth as shown in FIG. Thereby, the switch is controlled so that a predetermined current flows in the buffer circuit 40 in accordance with the frequency band width of each communication signal. That is, as the operating current of the pair of differential amplification transistors 10303 and 10304 shown in FIG. 3, a current that is predetermined according to the frequency band width of each communication signal flows.
- By performing the control in this way it is possible to reduce the transmission of the second-order distortion component signal corresponding to the frequency band width of each communication signal to the amplifier circuit 20, and to ensure the linearity of the amplifier circuit. It becomes possible.
- control signal formed by the buffer current control circuit 110 selects a current value corresponding to the width of each frequency band, it can also be regarded as a selection signal.
- FIG. 6 shows another circuit diagram of the current source 10308.
- MOS transistors 513 to 516 are used as the switches 509, 510, 511 and 512.
- a MEMS switch (not shown) may be used in place of the MOS transistor.
- the number of switches, MOS transistors, and resistors need not be four, and may be the number corresponding to the width of the frequency band of the signal to be switched or the number according to the control.
- FIG. 13 is a circuit diagram showing an example of the output matching circuit 109.
- 10353 is an input terminal connected to the output terminal 112 of the amplifier circuit 20
- 10354 is an output terminal connected to the terminal 113 of FIG.
- a coil (inductance) 10350 is connected between the input terminal 10353 and the output terminal 10354, and capacitors 10352 and 10351 are connected between the ground potential point and both ends of the coil 10350.
- the output matching circuit is configured by a so-called ⁇ -type filter.
- the output matching circuit 109 matches the input impedance of the input terminal 10353 and the output impedance of the amplifier circuit in the frequency band of the signal to be communicated, and is connected to the output impedance of the output terminal 10354 and the terminal 113 of FIG.
- the value of each element is set so that the impedance with a circuit (for example, an amplifier) matches.
- the impedance when the output matching circuit 109 side is viewed from the output terminal 112 used in the above description means the input impedance of the output matching circuit 109 and the load connected to the output terminal 112 in the frequency band of the second order distortion component.
- the combined impedance with the inductance 107 is meant.
- FIG. 8 is a block diagram showing an example of a mobile terminal.
- reference numeral 820 denotes a baseband semiconductor integrated circuit device (hereinafter also referred to as an IC) that forms and outputs a baseband signal (transmission baseband signal) to be transmitted.
- the transmission baseband signal is amplified by an RF signal processing IC (RFIC) 830, converted into a high-frequency communication signal, and supplied to the amplifier module 810.
- RFIC RF signal processing IC
- the transmission signal amplified by the amplifier module 810 is supplied to the antenna 850 that performs transmission / reception via the duplexer 840 and transmitted.
- the duplexer 840 utilizes the fact that the frequency band of the transmission signal and that of the reception signal are different, uses bandpass filter characteristics, transmits the transmission signal from the amplifier module 810 to the antenna 850, and the reception signal from the antenna 850 is transmitted to the amplifier module 810.
- the signal is transmitted to the RF signal processing IC 830 without flowing into.
- the baseband IC 820 includes the frequency bandwidth selection unit 201 described above, and the amplifier module 810 includes the high frequency module.
- the width of the frequency band of the communication signal used for transmission and reception is set.
- the frequency bandwidth selection circuit 201 generates the bandwidth selection data and transmits it as a digital signal to the buffer current control circuit 110 in the amplifier module 810 via a digital interface (not shown). .
- FIG. 9 is a block diagram showing another embodiment of the portable terminal. Also in this figure, the same parts as those in FIG. In the example of FIG. 9, the RF signal processing IC 930 collectively receives the control signals (including the above-described bandwidth selection data) from the baseband IC 820, and the control signal (bandwidth selection) required by the amplifier module 810 is received.
- the RF signal processing IC 930 is the same as the RF signal processing IC 830 except that the inter-chip data communication circuit 301 is included.
- the configuration suitable for the FDD system has been described with reference to FIGS. 8 and 9, but the present invention is not limited to this, and the mobile terminal is a TDD system (time division duplex). It may be applied.
- FIG. 11 shows a circuit of the high frequency module according to the second embodiment. Also in this figure, the same parts as those in FIG. The difference from the first embodiment is that a buffer follower circuit 153 having a buffer capacitor control circuit 150 and a variable phase compensation capacitor is provided instead of the buffer current control circuit 110 (FIG. 1).
- FIG. 12 shows a circuit of the voltage follower circuit 153. Also in FIG. 12, the same parts as those in FIG. 12 is different from the phase compensation capacitor 10306 (FIG. 3) in that a plurality of phase compensation capacitors 15301, 15302, 15303 and 15304 and capacitor switching switches 15305, 15306, 15307 and 15308 are different. It is to provide.
- the frequency characteristic of the buffer circuit can be changed by changing the value of the capacitor for phase compensation, as can be understood from the above equation (7).
- the values of the phase compensation capacitors 15301, 15302, 15303, and 15304 are determined in advance by circuit simulation and trial manufacture so that the impedance matching as described above cannot be obtained in the frequency band width of each communication signal.
- the buffer capacitor control circuit 150 receives the bandwidth data from the frequency band selection circuit 201, switches the capacitor switching switches 15305, 15306, 15307, and 15308 according to the selected bandwidth, and uses the phase compensation capacitor 15301 to be used. , 15302, 15303, and 15304 are switched.
- the impedance of the variable impedance circuit is changed by switching the phase compensation capacitor, it is possible to prevent an increase in power consumption.
- the high-frequency module shown in this embodiment can be applied to the portable terminal shown in FIGS.
- the MOS transistor is used for the description.
- a bipolar transistor may be used.
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Abstract
Description
その他の課題と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。
増幅回路(以下、アンプ又はアンプ回路と称することもある)で信号を増幅した場合、増幅後の信号は、アンプの非線形性により歪を有する。この歪により、入力した信号(入力信号)の周波数帯以外にも信号が漏れ出し、隣接した周波数帯に存在する信号への妨害となる隣接チャネル妨害が生じる。アンプへの入力信号をx(t)とし、2次歪成分と3次歪成分を考慮するとアンプの出力信号y(t)は、
上述したように増幅後に生じたところの2次歪成分の一部が、増幅回路に漏れ込んだ場合、例えば後で説明する図1の増幅用トランジスタ106に戻り、入力信号(増幅用トランジスタによって増幅されるべき周波数帯の信号)に加わった場合を、次に説明する。増幅用トランジスタは、例えば電界効果型トランジスタ(以下、MOSトランジスタとも称する)であり、そのゲートに上述の様に入力信号と2次歪成分の一部が重畳されて供給され、増幅される。
図1を用いて一実施の形態の概要を説明する。高周波モジュール10は、増幅回路20及び出力整合回路109を有する。増幅回路20は、出力端子112、高周波増幅用トランジスタ106及び可変インピーダンス回路103を有している。可変インピーダンス回路40は、通信信号の周波数帯域の幅に従った制御信号を受け、制御信号の値に従ってその出力インピーダンスが変わる。出力端子112から見た増幅回路20の出力インピーダンスは、少なくとも可変インピーダンス回路40と増幅用トランジスタ106との合成インピーダンスであり、可変インピーダンス回路40の出力インピーダンスを変えることにより、変化する。従って、制御信号により、通信信号の周波数帯域の幅毎に、増幅回路20の出力インピーダンスを変えることが出来る。通信信号を増幅するとき、2次歪成分の周波数帯において、出力端子112から見た出力整合回路109のインピーダンスと増幅回路20の出力インピーダンスとを整合させずに、2次歪成分を整合回路109へ反射させる。これにより、2次歪成分の信号が増幅回路20へ透過する量を低減し、3次歪成分の不要な信号が発生するのを低減し、増幅回路の線形性を確保することが可能となり、隣接チャネルへの妨害を低減した高周波モジュールを提供することが可能となる。
図1には、実施の携帯1に係わる高周波モジュールの回路図が示されている。同図において、高周波モジュール10は、増幅回路20と、バイアス回路30と、出力整合回路109を含んでいる。
図11には、第2の実施の形態に係わる高周波モジュールの回路が示されている。この図においても、図1と同じ部分には同じ記号を付してあり、その説明を省略する。実施の形態1との相違点は、バッファ電流制御回路110(図1)の替わりに、バッファコンデンサ制御回路150を備え、位相補償用コンデンサを可変としたボルテージフォロア回路153を備える点である。
20 増幅回路
30 バイアス回路
40 可変インピーダンス回路
103 ボルテージフォロア回路
106 増幅用トランジスタ
109 出力整合回路
110 バッファ電流制御回路
201 周波数帯域選択回路
Claims (17)
- 出力端子と、上記出力端子に接続され、高周波信号を増幅して、上記出力端子へ出力する増幅用トランジスタと、上記増幅用トランジスタに接続され、上記高周波信号の周波数帯域の幅に応じた制御信号に従って上記出力端子における出力インピーダンスを設定する可変インピーダンス回路とを有する増幅回路と、
上記増幅回路の出力端子に接続された整合回路と
を具備する高周波モジュール。 - 上記増幅用トランジスタに供給されるべきバイアス電圧を形成するバイアス回路を有し、
上記可変インピーダンス回路は、上記バイアス電圧を上記増幅用トランジスタに供給し、上記制御信号に従って、その周波数特性が変わるボルテージフォロア回路を有する請求項1の高周波モジュール。 - 上記ボルテージフォロア回路は、上記バイアス電圧を一方に受け、ボルテージフォロア回路の出力を他方に受ける1対の差動増幅トランジスタと、上記制御信号に従った電流を上記差動増幅トランジスタの動作電流として供給する電流回路とを有する請求項2の高周波モジュール。
- 上記増幅回路は、上記高周波信号を受け、上記増幅用トランジスタに高周波信号を供給するコンデンサを有する請求項3の高周波モジュール。
- 上記高周波信号は、LTE規格に従って送信される信号である請求項4の高周波モジュール。
- 上記ボルテージフォロア回路は、上記バイアス電圧を一方に受け、ボルテージフォロア回路の出力を他方に受ける1対の差動増幅トランジスタと、上記差動増幅トランジスタの出力を受ける出力トランジスタと、上記出力トランジスタの出力と入力との間に設けられた複数の帰還用コンデンサとを有し、
上記複数の帰還用コンデンサは、上記制御信号に従って選択的に上記出力トランジスタの入力と出力との間に接続される請求項2の高周波モジュール。 - 上記増幅回路は、上記高周波信号を受け、上記増幅用トランジスタに高周波信号を供給するコンデンサを有する請求項6の高周波モジュール。
- 上記高周波信号は、LTE規格に従って送信される信号である請求項7の高周波モジュール。
- アンテナと、
上記アンテナを介して送信されるべき信号を形成する回路と、
送信に使われる周波数帯域の幅を表す選択信号を出力する選択回路と、
上記送信されるべき信号に対応した高周波信号を増幅して、出力端子へ出力する増幅用トランジスタと、上記増幅用トランジスタとに接続され、上記選択回路からの選択信号に従って上記出力端子における出力インピーダンスを設定する可変インピーダンス回路とを有する増幅回路と、上記増幅回路の出力端子と上記アンテナとの間に接続された整合回路とを有する高周波モジュールと
を具備する携帯端末。 - 上記増幅用トランジスタに供給されるべきバイアス電圧を形成するバイアス回路を具備し、
上記可変インピーダンス回路は、上記バイアス電圧を上記増幅用トランジスタに供給し、上記選択信号に従って、その周波数特性が変わるボルテージフォロア回路を有する請求項9の携帯端末。 - 上記高周波信号は、LTE規格で送信される請求項10の携帯端末。
- 上記バイアス回路と上記増幅用トランジスタと上記可変インピーダンス回路は、1つの半導体チップに形成されている請求項10の携帯端末。
- バイアス電圧を形成するバイアス回路と、
高周波信号を増幅する増幅用トランジスタと、
上記バイアス回路に、その入力が接続され、上記増幅用トランジスタに、その出力が接続されたボルテージフォロア回路と、
上記増幅用トランジスタに接続され、上記高周波信号を上記増幅用トランジスタに供給するコンデンサと
を具備する高周波モジュール。 - 上記ボルテージフォロア回路の出力と上記増幅用トランジスタとの間に接続された抵抗を含む請求項13の高周波モジュール。
- 上記バイアス回路、上記ボルテージフォロア回路、上記増幅用トランジスタは、1つの半導体チップに形成されている請求項13又は14の高周波モジュール。
- 上記バイアス回路は、トランジスタと定電流源を有する請求項15の高周波モジュール。
- 上記増幅用トランジスタは、電界効果型トランジスタである請求項16の高周波モジュール。
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US14/366,744 US9166542B2 (en) | 2011-12-22 | 2012-12-05 | High frequency module and portable terminal using same |
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