WO2013093590A1 - Procédés de fabrication de structures semi-conductrices au moyen de processus de pulvérisation thermique, et structures semi-conductrices fabriquées au moyen de tels procédés - Google Patents

Procédés de fabrication de structures semi-conductrices au moyen de processus de pulvérisation thermique, et structures semi-conductrices fabriquées au moyen de tels procédés Download PDF

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Publication number
WO2013093590A1
WO2013093590A1 PCT/IB2012/002690 IB2012002690W WO2013093590A1 WO 2013093590 A1 WO2013093590 A1 WO 2013093590A1 IB 2012002690 W IB2012002690 W IB 2012002690W WO 2013093590 A1 WO2013093590 A1 WO 2013093590A1
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layer
substrate layer
semiconductor
semiconductor layer
substrate
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PCT/IB2012/002690
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English (en)
Inventor
Christiaan Werkhoven
Chantal Arena
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Soitec
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Priority claimed from US13/336,853 external-priority patent/US9082948B2/en
Priority claimed from FR1250388A external-priority patent/FR2985853B1/fr
Application filed by Soitec filed Critical Soitec
Publication of WO2013093590A1 publication Critical patent/WO2013093590A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02389—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02425—Conductive materials, e.g. metallic silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Definitions

  • the present disclosure generally relates to the fabrication of engineered substrates for use in the fabrication of semiconductor structures or devices, intermediate structures formed during the fabrication of semiconductor structures or devices, and to semiconductor structures or devices using engineered substrates.
  • Substrates that include one or more layers of semiconductor material are used to form a wide variety of semiconductor structures and devices including, for example, integrated circuit (IC) devices (e.g., logic processors and memory devices) and discrete devices such as, radiation emitting devices (e.g. , light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity surface emitting lasers (VCSELs)), and radiation sensing devices (e.g., optical sensors).
  • IC integrated circuit
  • LEDs light emitting diodes
  • RCLEDs resonant cavity light emitting diodes
  • VCSELs vertical cavity surface emitting lasers
  • Such semiconductor devices are conventionally formed in a layer-by-layer manner (i.e. , lithographically) on and/or in a surface of a semiconductor substrate.
  • Such wafers of silicon material are fabricated by first fonning a large generally cylindrical silicon single crystal ingot and subsequently slicing the single crystal ingot perpendicularly to its longitudinal axis to form a plurality of silicon wafers.
  • Such silicon wafers may have diameters as large as about thirty centimeters (30 cm) or more (about twelve inches ( 12 in) or more).
  • silicon wafers generally have thicknesses of several hundred microns (e.g., about 700 microns) or more, only a very thin layer (e.g., less than about three hundred nanometers (300 nm)) of the semiconductor material on a major surface of the silicon wafer is generally used to form active devices on the silicon wafer.
  • a very thin layer e.g., less than about three hundred nanometers (300 nm)
  • the majority of the silicon wafer thickness may be included in the electrical path-way of one or more device structures formed from the sil icon wafer, such device structures being commonly referred to as "vertical" device structures.
  • So-called "engineered substrates” have been developed that include a relatively thin layer of semiconductor material (e.g., a layer having a thickness of less than about three hundred nanometers (300 nm)) disposed on a layer of dielectric material (e.g., silicon dioxide (S1O2), silicon nitride (S13N4), or aluminum oxide (AI2O3)).
  • the layer of dielectric material may be relatively thin (e.g., too thin to enable handling by conventional semiconductor device manufacturing equipment), and the semiconductor material and the layer of dielectric material may be disposed on a relatively thicker host or base substrate to facilitate handl ing of the overall engineered substrate by manufacturing equipment.
  • the base substrate is often referred to in the art as a "handle” or "handling” substrate.
  • the base substrate may also comprise a semiconductor material other than silicon.
  • a wide variety of engineered substrates are known in the art and may include semiconductor materials such as, for example, silicon (Si), germanium (Ge), II1-V semiconductor materials, and 1I-VI semiconductor materials.
  • an engineered substrate may include an epitaxial layer of I1I-V semiconductor material formed on a surface of a base substrate, such as, for example, aluminum oxide (AI2O3) (which may be referred to as "sapphire").
  • the epitaxial layer may be formed on the surface of the base substrate by a transfer process from a donor structure, for example a donor substrate or donor ingot. The transfer from a donor structure may be desirable when the donor material is highly valuable or in scarce supply.
  • additional layers of material may be formed and processed (e.g., patterned) over the epitaxial layer of II1-V semiconductor material to form one or more devices on the engineered substrate.
  • the Coefficient of Thermal Expansion (CTE) mismatch (or difference) between the epitaxial layer and the base substrate comprising the engineered substrate may influence the formation and processing of the additional layers of material.
  • CTE mismatch between the epitaxial layer and the base substrate is substantial, then the engineered substrate may be negatively impacted during the formation of additional layers of materials.
  • FIG. I illustrates a conventional LED.
  • An active region 130 which may include multiple layers, such as, for example, quantum wells, barrier layers, electron blocking layer(s) (EBL) etc., is disposed between the n-type layer 120 and a p-type layer 140. The result is an LED formed by the n-type layer 120, the active region 130, and the p-type layer 140.
  • EBL electron blocking layer
  • a first contact 160 provides an electrical connection to the n-type layer 120 and a second contact 150 provides another electrical connection to the to the p-type layer 140.
  • These contacts may be opaque to the wavelength of light emitted by the LED and, as a result, may diminish the overal l amount of light available from the LED. Thus, only the area between the first contact 160 and the second contact 1 50 may produce significant amounts of light.
  • the physical layout of the second contact 150 relative to the n-type layer 120 may cause current crowding in the current flowing between the p-type layer 140 and the n-type layer 120.
  • the physical layout may require that both p-type and n-type contacts are disposed on an upper surface of the LED structure, wherein such a physical layout may require removal of a portion of the device layers to expose regions for contacting.
  • the removal of a portion of the device layers may increase the complexity of device fabrication, may reduce the area available for light generation and may also decrease device yield.
  • the various embodiments of the present disclosure generally relate to engineered substrates and methods of producing the engineered substrates that provide a suitable base substrate with a CTE that closely matches a CTE of the engineered substrate.
  • This summary is provided to introduce a selection of concepts in a simplified form that are further described in the detailed description below of some example embodiments of the disclosure. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
  • the present disclosure includes methods of fabricating a semiconductor substrate.
  • the methods include forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface.
  • a substrate layer is formed on the attachment surface.
  • the substrate layer exhibits a CTE closely matching a CTE of the transfer layer, and has sufficient stiffness to provide structural support to the transfer layer.
  • the transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer and the substrate layer.
  • the present disclosure includes methods of fabricating a semiconductor substrate.
  • the methods include forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface.
  • An ohmic contact is formed between the transfer layer and a contact layer disposed thereon.
  • a low impedance coupling is formed between a substrate layer and the contact layer, wherein the substrate layer provides a structural support for the semiconductor substrate.
  • the methods also include separating the transfer layer from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer, the contact layer, and the substrate layer.
  • the present disclosure comprises a semiconductor substrate including a substrate layer configured to provide a sufficient stiffness to the semiconductor substrate.
  • the semiconductor substrate also includes a transfer layer comprising a semiconductor material in contact with an attachment surface of the substrate layer.
  • the transfer layer may be detached from a donor structure comprising the semiconductor material and including a weakened zone in the donor structure at a predetermined depth from the attachment surface to define the transfer layer between the attachment surface and the weakened zone.
  • the substrate layer exhibits a CTE that closely matches a CTE exhibited by the transfer layer.
  • the disclosure includes methods of fabricating a semiconductor substrate.
  • a substrate layer is formed over a surface of a first semiconductor layer.
  • At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the substrate layer, and the substrate layer is formulated to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • the present disclosure includes semiconductor structures comprising a substrate layer, a first semiconductor layer disposed over a surface of the substrate layer, and at least one additional semiconductor layer epitaxially deposited over the first semiconductor layer on a side thereof opposite the substrate layer.
  • the substrate layer exhibits a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • the present disclosure includes methods that may be used to fabricate a semiconductor structure.
  • a first substrate layer is formed over a surface of a first semiconductor layer.
  • a second substrate layer is thermally sprayed on a side of the first substrate layer opposite the first semiconductor layer.
  • At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer, and at least one of the first substrate layer and the second substrate layer is formulated to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • the present disclosure includes semiconductor structures that comprise a substrate including a first substrate layer and at least a second substrate layer, a first semiconductor layer disposed over a surface of the first substrate layer, and at least one additional semiconductor layer epitaxially deposited over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer exhibits a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • FIG. 1 is a simplified cross-section drawing of a conventional LED structure
  • FIG. 2 is a simplified cross-section drawing of a donor structure with a weakened zone to create a transfer layer
  • FIGS. 3A-3B are simplified cross-section drawings illustrating development of a composite substrate with a substrate layer and a transfer layer according to additional embodiments of the disclosure
  • FIGS. 4A-4C are simplified cross-section drawings illustrating development of a composite substrate with a substrate layer, a transfer layer, and a contact layer therebetween according to additional embodiments of the disclosure;
  • FIG. 5 is a simplified cross-section drawing illustrating additional semiconductor material deposited over a semiconductor material of the structure of FIG. 3B;
  • F'G- 6 is a simplified cross-section drawing illustrating additional semiconductor material deposited over the semiconductor material of the structure of FIG. 4C;
  • FIGS. 7A-7C illustrate a composite substrate with a silicon carbide (SiC) transfer layer and a high power electronic device formed on the composite substrate according to additional embodiments of the disclosure
  • FIGS. 8A-8D illustrate a composite substrate with an n-doped gallium nitride (GaN) transfer layer and a photonic device formed on the composite substrate, which is flipped to form an n-layer-up photonic device according to additional embodiments of the disclosure; and
  • GaN gallium nitride
  • FIG. 9 is a simplified schematic illustration showing a thermal spray device spraying a substrate layer onto a donor structure that includes a semiconductor material.
  • the materials described herein may be formed (e.g. , deposited or grown) by any suitable technique including, but not limited to, spin-coating, blanket coating, Bridgeman and Czochralski processes, chemical vapor deposition ("CVD"), plasma enhanced chemical vapor deposition (“PECVD”), atomic layer deposition (“ALD”), plasma enhanced ALD, or physical vapor deposition (“PVD”). While the materials described and illustrated herein may be formed as layers, the materials are not limited to layers and may be formed in other three-dimensional configurations.
  • Terms such as “horizontal” and “vertical,” as used herein, define relative positions of elements or structures with respect to a major plane or surface of a semiconductor structure (e.g., wafer, die, substrate, etc. ), regardless of the orientation of the semiconductor structure, and are orthogonal dimensions interpreted with respect to the orientation of the structure being described.
  • the tenn “vertical” means and includes a dimension substantially perpendicular to the major surface of a semiconductor structure
  • the term “horizontal” means a dimension substantially parallel to the major surface of the semiconductor structure.
  • semiconductor structure means and includes any structure that is used in the formation of a semiconductor device.
  • Semiconductor structures include, for example, dies and wafers (e.g. , carrier substrates and device substrates), as well as assemblies or composite structures that include two or more dies and/or wafers three-dimensionally integrated with one another.
  • Semiconductor structures also include fully fabricated semiconductor devices, as well as intermediate structures formed during fabrication of semiconductor devices.
  • Semiconductor structures may comprise conductive materials, semiconductor materials, non-conductive materials (e.g., electrical insulators), and combinations thereof.
  • processed semiconductor structure means and includes any semiconductor structure that includes one or more at least partially formed device structures. Processed semiconductor structures are a subset of semiconductor structures, and all processed semiconductor structures are semiconductor structures.
  • I II-V semiconductor material means and includes any semiconductor material that is at least predominantly comprised of one or more elements from group I11A of the periodic table (e.g. , B, Al, Ga, In, and Ti) and one or more elements from group VA of the periodic table (e.g., N, P, As, Sb, and Bi).
  • coefficient of thermal expansion and “CTE,” when used with respect to a material or structure, are synonymous and mean the average linear coefficient of thermal expansion of the material or structure at room temperature.
  • engineered substrate in its broadest sense, means and includes any substrate comprising two or more layers of material and that is intended to be used as a substrate for the fabrication of one or more semiconductor devices thereon.
  • Engineered substrates include, as non-limiting examples, semiconductor-on-insulator type substrates.
  • the term "sufficient stiffness" means a stiffness for a
  • such structural damage may include
  • composite substrate layer means a layer of a substrate comprising an alloy or mixture of two or more elemental constituents.
  • the microstructure of some composite substrate layers may be at least substantially comprised of a single, generally
  • composite substrate layers may comprise two or more distinct phases, each of which may be homogeneous or inhomogeneous.
  • Such composite substrate layers may comprise one or more metal phases, one or more ceramic phases, one or more semiconductor phases, or a mixture of one or more of metal phases, ceramic phases, and semiconductor phases.
  • composite substrate layers may include, but are not limited to, metal-metal composite materials, ceramic-ceramic composite materials, and metal-ceramic composite materials.
  • the various embodiments of the present disclosure are concerned with engineered substrates and methods of producing the engineered substrates that provide a suitable base substrate layer with a CTE that closely matches a CTE of a semiconductor material carried on the base substrate layer.
  • Embodiments of the disclosure may have applications to engineered substrates comprising a wide range of semiconductor materials, such as silicon, germanium, silicon carbide, and Ill-V semiconductor materials.
  • semiconductor materials such as silicon, germanium, silicon carbide, and Ill-V semiconductor materials.
  • the methods and structures of the embodiments of the disclosure may be applied to Il l-nitrides, Ill-arsenides, Ill-phosphides and lll-antimonides, in binary, ternary, quaternary, and quinary form.
  • FIG. 2 is a simplified cross-section drawing of a donor structure 210 with a weakened zone 220 to create a first semiconductor layer 230.
  • a detachment process described- herein may use SMART -CUTTM technology. Such processes are described in detail in, for example, U.S. Patent No. RE39,484, issued February 6, 2007, to Bruel; U.S. Patent No. 6,303,468, issued October 16, 2001 , to Aspar et al.; U.S. Patent No. 6,335,258, issued January 1 , 2002, to Aspar et al.; U.S. Patent No. 6,756,286, issued June 29, 2004, to
  • a predetermined weakened zone 220 may be formed in the donor structure 210.
  • FIG. 2 shows use of the SMART -CUTTM technology wherein atomic species 250, such as one or more of hydrogen ions, helium ions or other inert gas ions, are implanted through an attachment surface 240 with a dose and energy to create the weakened zone 220 in the donor structure 130.
  • the weakened zone 220 is substantially parallel to the main attachment surface 240 and at a predetermined depth based on parameters of the atomic species implant process.
  • the first semiconductor layer 230 is thus formed between the attachment surface 240 and the weakened zone 220.
  • a residual donor structure is formed between the weakened zone 220 and an opposite surface from the attachment surface 240.
  • the donor structure 210 includes a semiconductor material such as silicon, germanium, a l l l-V semiconductor material such as a Ill-nitride (e.g., GaN, InGaN, AIGaN), a ll-VI semiconductor material, or SiC.
  • the semiconductor material may be un-doped or, for some applications, doped n-type or p-type (e.g. , highly doped (n+ or p+), moderately doped (n or p), or lightly doped (n- or p-)).
  • the semiconductor may be a freestanding wafer as shown in FIG. 2 or a multilayer wafer (e.g., GaN on a sapphire base).
  • the donor structure 210 may also comprise at least a portion of an ingot (or boule) of semiconductor material, and, in some embodiments, the at least a portion of the ingot (or boule) may include any of the semiconductor materials mentioned above.
  • the ingot (or boule) may comprise a structure such as those described in U.S. Patent No. 6,858, 107 issued February 22, 2005 to Ghyselen et al., and U.S. Patent No. 6,867,067 issued March 15, 2005 to Ghyselen et al.
  • the donor structure 210 is a Ill-nitride material
  • the polarity of the surface being implanted should be considered in determining the polarity of the final composite substrate.
  • a GaN donor structure may be used to develop a Gallium-polar face or a Nitrogen-polar face for subsequent processing.
  • an InGaN donor structure may be used to develop a metal-polar face or a Nitrogen-polar face for subsequent processing.
  • a bonding process is used followed by splitting off of the implanted wafer by means of some heat treatment.
  • the bonding process requires a high quality of the surfaces to be bonded to avoid large area defects
  • conductive bonding of a semiconductor material to a conductive substrate is desirable to construct vertical device structures, i.e., devices that have the active area near the surface of the semiconductor layer and a contact area near the interface of the semiconductor with the substrate or carrier wafer.
  • vertical device structures i.e., devices that have the active area near the surface of the semiconductor layer and a contact area near the interface of the semiconductor with the substrate or carrier wafer.
  • Si0 2 is an insulator and will make electrical conduction difficult, if not impossible, and, in addition, impede efficient heat dissipation of the device to the substrate.
  • embodiments of the present disclosure provide structures and processes for providing a support structure that may provide heat dissipation and with a CTE that closely matches a CTE of the first semiconductor layer 230 or device structure formed thereon.
  • electrical contact may be provided (for example, an ohmic or Schottky contact) between the first semiconductor layer 230 and a first substrate layer, which may serve as an electrically conductive contact layer.
  • a first substrate layer may comprise a metal or metal alloy in some embodiments.
  • An ohmic contact i.e. , a contact with a voltage-independent resistance
  • an ohmic contact will have current-versus-voltage characteristics that are substantially linear and symmetric. In such cases, the carriers are free to flow in or out of the semiconductor so that there is a minimal resistance across the ohmic contact.
  • FIGS. 3A-3B are simplified cross-section drawings i llustrating development of an engineered substrate that includes a base substrate layer 3 10 and a first semiconductor layer 230 according to some embodiments of the disclosure.
  • the first semiconductor layer 230 may be transferred to the base substrate layer 3 10, as described herein, and thus may comprise a
  • the base substrate layer 310 may be formed to a thickness sufficient to form a metall ic support substrate with sufficient stiffness to provide structural support to the first semiconductor layer 230.
  • the base substrate layer 310 may have an average thickness (measured perpendicular to the major planar surfaces of the substrate layer) that is sufficient to provide sufficient stiffness for structurally supporting the first semiconductor layer 230.
  • the base substrate layer 310 may have an average thickness of at least about five (5) microns, or at least about ten ( 10) microns.
  • the base substrate layer 3 10 may have an average thickness between about ten ( 10) microns and about one hundred ( 100) microns, and, more likely, between about ten ( 10) microns and about twenty (20) microns.
  • the base substrate layer 310 may be formed on the attachment surface 240 with a process suitable for providing an electrical contact, for example ohmic contact, between the base substrate layer 310 and the first semiconductor layer 230.
  • the surface of the semiconductor Prior to depositing the base substrate layer 3 10, the surface of the semiconductor may need treatment to remove any surface oxide or other surface layers that may impact the quality of the base substrate layer 310.
  • a thin gallium oxide layer may need to be removed from the first semiconductor layer 230 when the first semiconductor layer 230 comprises gallium nitride, prior to depositing the base substrate layer 310 and for the formation of an electrical contact, e.g., an ohmic contact.
  • the base substrate layer 310 may be deposited using one or more of a physical deposition process (e.g., physical vapor deposition (PVD), sputtering, etc.), a thermal spray coating process (e.g., a plasma spraying process, a flame spraying process, etc.), a plating process (e.g., an electroless plating process and/or an electroplating process), and a chemical vapor deposition process (CVD).
  • PVD physical vapor deposition
  • sputtering etc.
  • a thermal spray coating process e.g., a plasma spraying process, a flame spraying process, etc.
  • a plating process e.g., an electroless plating process and/or an electroplating process
  • CVD chemical vapor deposition process
  • the base substrate layer 3 10 may be deposited using a plasma spraying process.
  • FIG. 9 is a schematic illustration of a plasma spray nozzle depositing a base substrate layer 310 on a donor structure 210 that includes the first semiconductor layer 230 (FIG. 2).
  • a plasma spray device 900 may be used to spray at least partially melted particles 910 onto the donor structure 210.
  • the partially melted particles 910 may consolidate with one another and solidify over the donor structure 210 to form the base substrate layer 310 on the donor structure 210.
  • the plasma spray device 900 includes an outer body 920, which may be generally tubular in shape.
  • a first electrode 930 e.g.; an anode
  • the first electrode 930 may be generally annular in structure, such that a passageway is defined through the center of the first electrode 930.
  • a second electrode 940 e.g., a cathode
  • a passageway 950 is defined in the annular space between the exterior surface of the second electrode 940 and the interior surface of the outer body 920.
  • the passageway 950 communicates with the passageway extending through the center of the first electrode 930.
  • plasma-generating gas may be caused to flow through the passageway 950 and the passageway extending through the center of the first electrode 930, and out from the plasma spray device 900.
  • a voltage may be applied between the first electrode 930 and the second electrode 940 to generate an electrical current (i.e., an electrical discharge, or spark) therebetween, which, in the presence of the plasma-generating gas flowing through the plasma spray device 900, results in the formation of a plasma 960.
  • the plasma 960 is sprayed out from the plasma spray device 900 due to the flow of the plasma gas through the plasma spray device 900.
  • a conduit 970 may be used to convey powdered material from a powder source 980 to the plasma 960, as shown in FIG. 9.
  • the powdered material may comprise particles of the material or materials that will ultimately form the base substrate layer 310.
  • the powdered material may be carried through the conduit 970 by a carrier gas flowing through the conduit 970.
  • the powdered material may be at least partially melted and carried toward the donor structure 210 by the plasma jet emanating from the plasma spray device 900.
  • the particles impinge on the donor structure 210 or on material previously deposited on the donor structure 210), where they cool and solidify to form the material of the base substrate layer 310.
  • Methods other than thermal spray methods may be used to form the base substrate layer 310 on or over the donor structure 210 in additional embodiments of the disclosure.
  • the base substrate layer 310 may have (i.e., exhibit) a CTE that closely matches a CTE of the first semiconductor layer 230 and/or additional semiconductor material deposited on the first semiconductor layer 230 during subsequent growth processes, which may reduce or prevent strain and cracking in the first semiconductor layer 230 and/or the additional semiconductor material deposited on the first semiconductor layer 230 during subsequent growth processes.
  • Table 1 below lists CTE values for some non-limiting materials for the first semiconductor layer 230 and the base substrate layer 310 in some example embodiments of the disclosure.
  • the CTE of the base substrate layer 310 may be within about 20%, within about 10%, within about 5%, within about 2%, or even within about 1 % of the CTE of the first semiconductor layer 230 and/or any additional semiconductor material or materials ultimately deposited over the first semiconductor layer 230, as described herein.
  • the base substrate layer 310 may comprise a refractory metal or a refractory metal alloy.
  • tungsten, molybdenum, and zirconium (and particularly tungsten) used as the base substrate layer 310 would have a CTE closely matching a CTE of a SiC first semiconductor layer 230.
  • zirconium, hafnium, rhenium, and tantalum used as the base substrate layer 310 would closely match a GaN first semiconductor layer 230 and in some embodiments particularly molybdenum.
  • the base substrate layer 310 may comprise a composite substrate layer, which includes two or more elements so as to provide the base substrate layer 3 10 with a CTE between those of the two or more elements of which the base substrate layer 310 is composed.
  • the base substrate layer 310 may comprise an alloy or mixture of two or more elements.
  • the microstructure of the base substrate layer 310 may be at least substantially comprised of a single, generally homogeneous phase
  • the base substrate layer 3 10 may be at least substantially comprised of a single, inhomogeneous phase
  • the base substrate layer 310 may comprise two or more distinct phases, each of which may be homogeneous or inhomogeneous.
  • the base substrate layer 3 10 may comprise one or more metal phases, one or more ceramic phases, one or more semiconductor phases, or a mixture of one or more of metal phases, ceramic phases, and semiconductor phases.
  • the substrate layer may be formulated to comprise one of a metal-metal composite material, a ceramic-ceramic composite material, and a metal-ceramic composite material.
  • the entire structure including the donor structure 210 and the base substrate layer 310 shown in FIG. 3A may be placed into a furnace (not shown) and heated so that the weakened zone 220 may be further weakened. With the weakening, the first semiconductor layer 230 and accompanying base substrate layer 3 10 may be separated from the donor structure at the weakened zone 220. In addition to, or in place of thermal energy, other forms of energy, such as mechanical energy or chemical energy, may be used to weaken the structure along the weakened zone 220 and ultimately separate the first semiconductor layer 230 from the remainder of the donor structure 210.
  • other forms of energy such as mechanical energy or chemical energy
  • the structures thus formed after the separation are a residual donor structure (not shown) capable of donating further thin transfer layers, and an engineered substrate 450 shown in FIG. 3B, which includes the base substrate layer 310 and the first semiconductor layer 230.
  • the first semiconductor layer 230 may have an average layer thickness measured perpendicular to the major planar surfaces of the engineered substrate 450 of about one thousand ( 1 ,000) nanometers or less, about five hundred (500) nanometers or less, or even about one hundred ( 100) nanometers or less.
  • the engineered substrate 450 may be flipped over for additional processing on the exposed surface of the first semiconductor layer 230.
  • the engineered substrate 450 may receive a surface treatment, such as, for example, polishing, cleaning, or combinations thereof.
  • Additional processing may include, as a non-limiting example, adding device structures on the engineered substrate 450.
  • the device structures may include multiple layers of doped semiconductor material, un-doped semiconductor material, and active areas as are known in the art to produce electronic elements, photonic elements, and combinations thereof.
  • FIGS. 4A-4C are simplified cross-section drawings illustrating development of an engineered substrate 450 with an intermediate substrate layer 410 disposed between the base substrate layer 3 10 and the first semiconductor layer 230.
  • the intermediate substrate layer 410 may serve as an electrical contact layer and/or as a protective layer for protecting the first semiconductor layer 230 when the base substrate layer 310 is formed over the first semiconductor layer 230 using, for example, a thermal spray process like those previously described herein.
  • an intermediate substrate layer 410 comprising a metal or metal alloy is deposited on the attachment surface 240 of the donor structure 210 (FIG. 2) to form the structure shown in FIG. 4A.
  • the intermediate substrate layer 410 may be electrically conductive and configured to provide an ohmic contact that is of high quality (e.g. , low resistance) between the first semiconductor layer 230 and the intermediate substrate layer 410.
  • the intermediate substrate layer 410 may be, e.g., a Ti/Al/ i/Au stack, or a Ti/AI stack when the use of gold may be detrimental to the device performance.
  • the intermediate substrate layer 410 may be, e.g. , a Ni/Au stack or Ni (the first metal in the list being closest to the semiconductor).
  • the intermediate substrate layer 410 may be used to protect the first semiconductor layer 230 from damage that might otherwise result from formation of the base substrate layer 310 over the first semiconductor layer 230.
  • the base substrate layer 310 is formed using a thermal spray process as previously described herein, the impingement of the hot, thermally sprayed particles onto the first
  • semiconductor layer 230 might result in thermal damage to the first semiconductor layer 230, or defects created by the mechanical forces imparted on the first semiconductor layer 230 by the impinging particles.
  • the intermediate substrate layer 410 may be formed over the first semiconductor layer 230 using low temperature processes and processes that will not impart such mechanical forces on the first semiconductor layer 230.
  • the intermediate substrate layer 410 may be formed over the first semiconductor layer 230 using low temperature processes and processes that will not impart such mechanical forces on the first semiconductor layer 230.
  • intermediate substrate layer 410 may be deposited over the surface of the first semiconductor layer 230 at a temperature of about 900°C or less. After first forming the intermediate substrate layer 410, the base substrate layer may be thermally sprayed on a side of the intermediate substrate layer 410 opposite the first semiconductor layer 230. For example, the intermediate substrate layer 410 may be deposited on the first semiconductor layer 230 using at least one of a physical vapor deposition process, a sputtering process, a spin-on process, an electroless plating process, and an electrical plating process.
  • the intermediate substrate layer 410 may comprise a material that will conduct and dissipate the thermal energy brought to the structure by the impinging thermally sprayed particulate matter.
  • the intermediate substrate layer 410 may comprise a material exhibiting a thermal conductivity of at least about twenty watts per meter Kelvin (20 Wm 'K " 1 ).
  • the intermediate substrate layer 410 may comprise a material exhibiting a thermal conductivity of at least about one hundred watts per meter Kelvin ( 100 Wm ' K “ 1 ), at least about two hundred watts per meter Kelvin (200 Wm ' K “ 1 ), at least about three hundred watts per meter Kelvin (300 Wm “ ' K “ '), or even.at least about four hundred watts per meter Kelvin (400 Wm " ' K “ ' ).
  • the intermediate substrate layer 410 may comprise a material that is soft enough to absorb (by, for example, plastic deformation of the material of the intermediate substrate layer 410) the kinetic energy of the impinging thermally sprayed particulate matter so as to prevent damage to the first semiconductor layer 230.
  • the intermediate substrate layer 410 may comprise a material exhibiting a Vickers ' hardness of about 3500 MPa or less.
  • the intermediate substrate layer 410 may comprise a material exhibiting a Vickers hardness of about 2500 MPa or less, about 1800 MPa or less, or even about 1600 MPa or less.
  • the intermediate substrate layer 410 may comprise a refractory metal (i.e. , a commercially pure refractory metal or a metal alloy based on one or more refractory metals).
  • the intermediate substrate layer 410 may comprise at least one of titanium, molybdenum, zirconium, and hafnium. Zirconium, molybdenum and hafnium may be particularly suitable in some applications, as they exhibit relatively low hardness values.
  • the intermediate substrate layer 410 may have an average thickness of about one micron ( 1 .0 ⁇ ) or less, about five hundred nanometers (500 nm) or less, or about one hundred nanometers ( 100 nm) or less. In some embodiments, such as those in which the intermediate substrate layer 410 is used as an electrical contact layer but not as a protective layer, the
  • intermediate substrate layer 410 may be as thin as a few monolayers of atoms.
  • the intermediate substrate layer 410 may have an average thickness of between about one ( 1 ) nanometer and about fifty (50) nanometers.
  • the surface 240 of the semiconductor layer 230 may need treatment to remove any surface oxide or other surface layers which may impact the quality of the intermediate substrate layer 410, e.g. , a thin gallium oxide layer may need to be removed prior to depositing the intermediate substrate layer 410.
  • a base substrate layer 310 is formed on the intermediate substrate layer 410.
  • the base substrate layer 310 may be thermally sprayed on a side of the intermediate substrate layer 410 opposite the first semiconductor layer 230.
  • the process used to form the base substrate layer 310 on the intermediate substrate layer 410 may be suitable for providing a low-impedance coupling between the base substrate layer 310 and the intermediate substrate layer 410.
  • the combination of the intermediate substrate layer 410 and the base substrate layer 310 may be referred to herein as a multi-layer substrate 310A.
  • FIG. 4B which includes the donor structure 210 and the multi-layer substrate 31 OA, may be placed into a furnace (not shown) and heated so that the weakened zone 220 may be further weakened. With the weakening, the first semiconductor layer 230 and accompanying multi-layer substrate 31 OA may be separated from the donor structure 210 at the weakened zone 220, as previously described with reference to FIG. 3A.
  • the structures thus formed after the separation are a residual donor structure (not shown) capable of donating further thin transfer layers and an engineered substrate 450 including the base substrate layer 310, the intermediate substrate layer 410, and the first semiconductor layer 230.
  • the engineered substrate 450 may be flipped over for additional processing on the exposed surface of the first semiconductor layer 230, as previously described with reference to FIG. 3B.
  • the base substrate layer 310 (and, optionally, the intermediate substrate layer 410) should be able to remain chemically and physically stable at temperatures high enough for subsequent processing, such as, for example, the heating for the separation and growth/deposition/processing of additional layers of material.
  • the base substrate layer 310 (and the optional intermediate substrate layer 410) should be able to withstand temperatures in the range of about 900 °C to about 1 100 °C.
  • the base substrate layer 310 (and the optional intermediate substrate layer 410) should be able to withstand the chemical environment within the additional growth/deposition/processing equipment.
  • the base substrate layer 310 and/or the intermediate substrate layer 410 may have (i.e. , exhibit) a CTE that closely matches a CTE of the first semiconductor layer 230 and/or additional semiconductor material deposited on the first semiconductor layer 230 during subsequent growth processes, which may reduce or prevent strain and cracking in the first semiconductor layer 230 and/or the additional semiconductor material deposited on the first semiconductor layer 230 during subsequent growth processes.
  • at least one of the first substrate layer and the second substrate layer may be formulated to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer 230 and at least one additional semiconductor layer deposited over the first semiconductor layer 230.
  • FIG. 5 illustrates a relatively thick volume of additional semiconductor material 470 epitaxially deposited over the first layer of semiconductor material 230 of FIG. 3B.
  • FIG. 6 illustrates a relatively thick volume of additional semiconductor material 470 epitaxially deposited over the first layer of semiconductor material 230 of FIG. 4C.
  • the thick volume of additional semiconductor material 470 of FIGS. 5 and 6 may comprise a single additional layer of semiconductor material, or it may comprise a plurality of additional layers of semiconductor material epitaxially deposited over the first layer of semiconductor material 230, as described below with reference to FIGS. 7A-7C and 8A-8D.
  • the volume of additional semiconductor material 470 may be grown to relatively high thickness without cracking in order to complete the fabrication of a device structure.
  • the volume of additional semiconductor material 470 may have an average total thickness of at least about one hundred ( 100) nanometers or at least about five hundred (500) nanometers. In some embodiments, the volume of additional semiconductor material 470 may have an average total thickness of between about one ( 1 ) micron and about one hundred ( 100) microns.
  • compositions for the base substrate layer 3 10, the first semiconductor layer 230, and the volume of additional semiconductor material 470 are set forth in Table 2 below.
  • the percentages of the different elements or phases in the materials of the base substrate layers 310 may be tailored to render the CTE of the base substrate layer 310 closer to the CTE of the first semiconductor layer 230 and/or the volume of additional semiconductor material 470.
  • the Rule of Mixtures may be used to predict the CTE of the base substrate layer 310 when the base substrate layer 310 comprises a mixture of two or more phases using the relative volumetric percentages of the two or more phases in the composite material of such a base substrate layer 310. According to the rule of mixtures (for isotropic properties), the CTE of a two-phase composite material is given by the equation:
  • ac is the CTE of the composite material
  • is the CTE of the first phase in the composite material
  • a 2 is the CTE of the second phase in the composite material
  • is the volume fraction of the first phase in the composite material
  • V 2 is the volume fraction of the second phase in the composite material.
  • Example Numbers 1 through 13 optionally may further comprise an intermediate substrate layer 410 comprising a material as previously described herein.
  • an intermediate substrate layer 410 may be included comprising at least one of titanium, zirconium, molybdenum, and hafnium.
  • ' gallium nitride (GaN) has a CTE of about 5.6 x 10 "6 /°K.
  • Zirconium has a coefficient of thermal expansion of 5.7 x 10 "6 /° , which is within about 1.8% of the CTE of gallium nitride.
  • Molybdenum has a coefficient of thermal expansion of 5.5 x 10 "6 /° , which is within about 1 .8% of the CTE of gallium nitride.
  • FIGS. 7A-7C illustrate an engineered substrate 450S with a silicon carbide (SiC) first semiconductor layer 230S and a high power electronic device formed on the engineered substrate 450S according to additional embodiments of the disclosure.
  • the engineered substrate 450S includes the SiC first semiconductor layer 230S on the base substrate layer 310.
  • the substrate layer may comprise a tungsten layer 310T in some embodiments.
  • the SiC first semiconductor layer 230 and the tungsten layer 310T have closely matching in CTEs, such that the SiC first semiconductor layer 230 and high power electronic device formed thereon will experience little or no strain effects due to a CTE mismatch during device formation.
  • the base substrate layer 310 may comprise an S1O2/AI2O3 composite layer, as previously described.
  • a power device may be formed with one or more power device layers 710 on the SiC first semiconductor layer 230S.
  • a contact layer 730 provides an electrical connection to the power device layer 710.
  • FIG. 7C illustrates an optional thick substrate 750 bonded to the engineered substrate 450S.
  • FIGS. 8A-8D illustrate a composite substrate with an n-doped gallium nitride (GaN) first semiconductor layer 230 and a photonic device formed on the engineered substrate 450, which is flipped to form an n-layer-up photonic device according to additional embodiments of the disclosure.
  • GaN gallium nitride
  • a photonic device such as, for example, an LED may be formed on the semiconductor material 230, which is formed as an n-doped gallium nitride (GaN) first semiconductor layer 230N in this embodiment.
  • GaN gallium nitride
  • the photonic device may includes an active region 810, which may include multiple layers of semiconductor material, such as quantum wells, disposed on the n-type gallium nitride (GaN) first semiconductor layer 230N.
  • One or more p-type GaN layers 820 may be disposed on the active layer 810. The result is an LED formed by the n-type gallium nitride (GaN) first semiconductor layer 230N, the active layer 810, and the p-type layer 820.
  • a contact layer 840 such as those described above, may be formed on the p-type GaN layer 820 providing an electrical connection to the p-type layer 820.
  • a heat sink such as a thick substrate 850 comprising a metal may be formed on the contact layer 840.
  • the resulting structure may be characterized as being flipped relative to previously described embodiments.
  • the flipped configuration is illustrated in FIG. 8C.
  • the base substrate layer 3 10 may then be removed to expose the n-type gallium nitride (GaN) first semiconductor layer 230N.
  • GaN gallium nitride
  • the resulting LED structure provides a vertical diode structure, which, in contrast to the diode structure in FIG. 1 , does not need an additional electrical connection exposed on the top layers for connection to the p-side of the diode. Rather, the p-side of the diode may be contacted through the contact layer 840 and the thick substrate 850.
  • a contact layer 830 may be formed to provide an electrical connection to an n-doped gallium nitride (GaN) first semiconductor layer 230N.
  • GaN gallium nitride
  • Embodiment I A method of fabricating a semiconductor structure, comprising: forming a first substrate layer over a surface of a first semiconductor layer; thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer; epitaxially growing at least one additional semiconductor layer over the first semiconductor layer on a side thereof opposite the first substrate layer; and formulating at least one of the first substrate layer and the second substrate layer to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • CTE Coefficient of Thermal Expansion
  • Embodiment 2 The method of Embodiment 1 , further comprising formulating the first substrate layer to comprise a material exhibiting a thermal conductivity of at least about twenty watts per meter Kelvin (20 Wm ' K " 1 ) and a Vickers hardness of about 3500 MPa or less.
  • Embodiment 3 The method of Embodiment 1 or Embodiment 2, further comprising selecting the first semiconductor layer to comprise a portion of a donor structure for donating the first semiconductor layer to another structure comprising the second substrate layer.
  • Embodiment 4 The method of Embodiment 3, further comprising forming a weakened zone in the donor structure at a predetermined depth to define the first semiconductor layer between the surface of the first semiconductor layer and the weakened zone and a residual donor structure between the weakened zone and a surface of the donor structure opposite the surface of the first semiconductor layer.
  • Embodiment 5 The method of Embodiment 4, further comprising separating the first semiconductor layer from the donor structure at the weakened zone to form a substrate structure comprising the first semiconductor layer, the first substrate layer, and the second substrate layer.
  • Embodiment 6 The method of any one of Embodiments 1 through 5, wherein forming the second substrate layer on the first substrate layer comprises plasma spraying the second substrate layer onto the first substrate layer.
  • Embodiment 7 The method of any one of Embodiments 1 through 6, wherein formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE within about 5% of a CTE of the at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • Embodiment 8 The method of Embodiment 7, wherein formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE within about 2% of a CTE of the at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • Embodiment 9 The method of Embodiment 8, wherein formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE within about I % of a CTE of the at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • Embodiment 10 The method of any one of Embodiments 1 through 9, further comprising forming the first substrate layer to have an average thickness of about one micron ( 1.0 ⁇ ) or less.
  • Embodiment 1 1 The method of any one of Embodiments 1 through 10, further comprising forming the second substrate layer to have an average thickness of at least about ten microns ( 1 0.0 ⁇ ).
  • Embodiment 12 The method of Embodiment 1 1 , further comprising forming the second substrate layer to have an average thickness of between about ten microns ( 10.0 ⁇ ) and about one hundred microns ( 100.0 ⁇ ).
  • Embodiment 13 The method of any one of Embodiments 1 through 12, further comprising selecting the first semiconductor layer to have an average thickness of about five hundred nanometers (500 nm) or less.
  • Embodiment 14 The method of any one of Embodiments 1 through 13, further comprising forming the at least one additional semiconductor layer to have an average total thickness of at least one hundred nanometers ( 1 00 nm).
  • Embodiment 1 5 The method of Embodiment 14, further comprising formi ng the at least one additional semiconductor layer to have an average total th ickness of between about one m icron ( 1 .0 ⁇ ) and about one hundred microns ( 1 00.0 ⁇ ).
  • Embodiment 16 The method of any one of Embod iments 1 through 1 5, further comprising selecting the first semiconductor layer to comprise a sem iconductor material selected from the group consisting of si licon, germanium, 11 I-V semiconductor material, and I I- VI semiconductor material.
  • Embodiment 1 7 The method of any one of Embodiments 1 through 1 6, wherein formulating the first substrate layer further comprises formulating the first substrate layer to comprise a refractory metal .
  • Embodiment 1 8 The method of Embodiment 1 7, wherein formulating the first substrate layer further comprises formulating the first substrate layer to comprise at least one of titanium, molybdenum, zirconium, and hafnium.
  • Embodiment 19 The method of Embodiment 1 8, wherein formulating the first substrate layer to comprise at least one of titanium, molybdenum, zirconium, and hafnium comprises formulating the first substrate layer to comprise at least one of zirconium and molybdenum.
  • Embodiment 20 The method of Embodiment 19, further comprising selecting at least one of the first semiconductor layer and the at least one additional
  • GaN gallium nitride
  • Embodiment 21 The method of any one of Embodiments 1 through 20, wherein forming the first substrate layer over the surface of the first semiconductor layer comprises depositing the first substrate layer over the surface of the first semiconductor layer at a temperature of about 900°C or less.
  • Embodiment 22 The method of any one of Embodiments 1 through 21 , wherein forming the first substrate layer over the surface of the first semiconductor layer comprises depositing the first substrate layer over the surface of the first semiconductor layer using at least one of a physical vapor deposition process, a sputtering process, a spin-on deposition process, an electroless plating process, and an electrical plating process.
  • Embodiment 23 A semiconductor structure, comprising: a substrate comprising a first substrate layer and at least a second substrate layer; a first semiconductor layer disposed over a surface of the first substrate layer; and at least one additional semiconductor layer epitaxially deposited over the first semiconductor layer on a side thereof opposite the first substrate layer; wherein at least one of the first substrate layer and the second substrate layer exhibits a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • Embodiment 24 The semiconductor structure of Embodiment 23, wherein the first substrate layer comprises a material exhibiting a thermal conductivity of at least about twenty watts per meter Kelvin (20 Wm ' K " 1 ) and a Vickers hardness of about 3500 MPa or less.
  • Embodiment 25 The semiconductor structure of Embodiment 23 or Embodiment 24, wherein at least one of the first substrate layer and the second substrate layer exhibits a CTE within about 5% of a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • Embodiment 26 The semiconductor structure of Embodiment 25, wherein at least one of the first substrate layer and the second substrate layer exhibits a CTE within about 2% of a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • Embodiment 27 The semiconductor structure of Embodiment 26, wherein at least one of the first substrate layer and the second substrate layer exhibits a CTE within about 1 % of a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.
  • Embodiment 28 The semiconductor structure of any one of Embodiments 23 through 27, wherein the first substrate layer has an average thickness of about one micron ( 1 .0 ⁇ ) or less
  • Embodiment 29 The semiconductor structure of any one of Embodiments 23 through 28, wherein the second substrate layer has an average thickness of at least about ten microns ( 10.0 ⁇ ).
  • Embodiment 30 The semiconductor structure of Embodiment 29, wherein the second substrate layer has an average thickness of between about ten microns ( 10.0 ⁇ ) and about one hundred microns ( 100.0 ⁇ ).
  • Embodiment 31 The semiconductor structure of any one of Embodiments 23 through 30, wherein the first semiconductor layer has an average thickness of about five hundred nanometers (500 nm) or less.
  • Embodiment 32 The semiconductor structure of Embodiment 31 , wherein the first semiconductor layer has an average thickness of about one hundred nanometers ( 100 nm) or less.
  • Embodiment 33 The semiconductor structure of any one of Embodiments 23 through 32, wherein the at least one additional semiconductor layer has an average total thickness of at least one hundred nanometers ( 100 nm).
  • Embodiment 34 The semiconductor structure of Embodiment 33, wherein the at least one additional semiconductor layer has an average total thickness of between about one micron ( 1 .0 ⁇ ) and about one hundred microns ( 100.0 ⁇ ).
  • Embodiment 35 The semiconductor structure of any one of Embodiments 23 through 34, wherein the first semiconductor layer comprises a semiconductor material selected from the group consisting of silicon, germanium, III- V semiconductor material, and II- VI semiconductor material.
  • Embodiment 36 The semiconductor structure of any one of Embodiments 23 through 35, wherein the first substrate layer comprises a refractory metal.
  • Embodiment 37 The semiconductor structure of Embodiment 36, wherein the first substrate layer comprises at least one of titanium, molybdenum, zirconium, and hafnium.
  • Embodiment 38 The semiconductor structure of Embodiment 37, wherein the first substrate layer comprises at least one of zirconium and molybdenum.
  • Embodiment 39 The semiconductor structure of Embodiment 38, wherein at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises gallium nitride (GaN).
  • GaN gallium nitride

Abstract

Les procédés de fabrication selon l'invention d'un substrat semi-conducteur consistent à former une première couche de substrat sur une surface d'une première couche semi-conductrice, et à pulvériser thermiquement une seconde couche de substrat sur un côté de la première couche de substrat opposé à la première couche semi-conductrice. Au moins une couche semi-conductrice additionnelle est déposée par croissance épitaxique sur la première couche semi-conductrice sur un de ses côtés opposé à la première couche de substrat. La première couche de substrat et/ou la seconde couche de substrat peuvent être formulées pour présenter un coefficient d'expansion thermique (CET) associé étroitement au CET de la première couche semi-conductrice et/ou de la ou des couches semi-conductrices additionnelles. Des structures semi-conductrices sont fabriquées au moyen d'un tel procédé.
PCT/IB2012/002690 2011-12-23 2012-12-10 Procédés de fabrication de structures semi-conductrices au moyen de processus de pulvérisation thermique, et structures semi-conductrices fabriquées au moyen de tels procédés WO2013093590A1 (fr)

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US13/336,853 US9082948B2 (en) 2011-02-03 2011-12-23 Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods
FR1250388A FR2985853B1 (fr) 2012-01-16 2012-01-16 Procedes de fabrication de structures a semi-conducteurs a l'aide de processus de pulverisation thermique, et structures a semi-conducteurs fabriquees a l'aide desdits procedes
FR1250388 2012-01-16

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US6946365B2 (en) 2000-12-08 2005-09-20 Commissariat A L'energie Atomique Method for producing a thin film comprising introduction of gaseous species
US20030064535A1 (en) * 2001-09-28 2003-04-03 Kub Francis J. Method of manufacturing a semiconductor device having a thin GaN material directly bonded to an optimized substrate
US6858107B2 (en) 2002-07-17 2005-02-22 S.O.I. Tec Silicon On Insulator Technologies S.A. Method of fabricating substrates, in particular for optics, electronics or optoelectronics
US7531428B2 (en) 2004-11-09 2009-05-12 S.O.I.Tec Silicon On Insulator Technologies Recycling the reconditioned substrates for fabricating compound material wafers
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
FR2953328A1 (fr) * 2009-12-01 2011-06-03 Soitec Silicon On Insulator Heterostructure pour composants electroniques de puissance, composants optoelectroniques ou photovoltaiques

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