WO2013084280A1 - Système de communication - Google Patents

Système de communication Download PDF

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Publication number
WO2013084280A1
WO2013084280A1 PCT/JP2011/078093 JP2011078093W WO2013084280A1 WO 2013084280 A1 WO2013084280 A1 WO 2013084280A1 JP 2011078093 W JP2011078093 W JP 2011078093W WO 2013084280 A1 WO2013084280 A1 WO 2013084280A1
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WIPO (PCT)
Prior art keywords
communication
cycle
bus
fixed
message
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PCT/JP2011/078093
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English (en)
Japanese (ja)
Inventor
智久 山口
信夫 菊地
藤島　光城
真充 服部
民樹 小林
橋本　茂
Original Assignee
三菱電機株式会社
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Priority to PCT/JP2011/078093 priority Critical patent/WO2013084280A1/fr
Publication of WO2013084280A1 publication Critical patent/WO2013084280A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40169—Flexible bus arrangements
    • H04L12/40176—Flexible bus arrangements involving redundancy
    • H04L12/40189—Flexible bus arrangements involving redundancy by using a plurality of bus systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40143—Bus networks involving priority mechanisms
    • H04L12/40156—Bus networks involving priority mechanisms by using dedicated slots associated with a priority level

Definitions

  • the present invention relates to a communication system including a plurality of data processing devices.
  • each data processing device is an isochronous communication.
  • PLC Programmable logic controller
  • MC Motion Controller
  • NC Genetic Control
  • robot controller each data processing device is an isochronous communication.
  • bus IEEE 1394 or the like
  • phase regular communication phase
  • asynchronous communication phase asynchronous communication phase
  • the transmission timing of the cyclic trigger packet is determined by the time based on the planned total data amount, or the timing of the next asynchronous communication phase in which the transmission data in the asynchronous communication phase is interrupted. If the periodic data and the asynchronous data are mixed together, the interval at which the cyclic trigger packet is transmitted is not constant due to the nature of the asynchronous data, and there is a problem that the punctuality cannot be guaranteed.
  • the present invention has been made in view of the above, and an object of the present invention is to obtain a communication system in which the number of data processing devices capable of performing periodic communication is expanded.
  • the present invention connects a plurality of data processing devices, a first bus to which a part or all of the data processing devices are connected, and all the data processing devices.
  • the data processing device connected to the first bus is connected to the first bus by performing periodic communication in the first cycle via the first bus.
  • the data communicated on the first bus held by the storage area included in each of the data processing devices is updated to the same content every first cycle, and the data processing devices connected to the second bus communicate with each other via the second bus.
  • the data communicated on the second bus held in the storage area provided in each of the data processing devices connected to the second bus is updated to the same content every second cycle, and the second bus
  • the fixed-cycle communication is transmitted with priority over the non-fixed-cycle communication between the data processing devices connected to the second bus, and an upper limit is set for the data amount of the fixed-cycle communication during the second cycle in the second bus. It is characterized by.
  • the communication system according to the present invention is advantageous in that the number of data processing devices capable of performing periodic communication can be extended to controllers that are not compatible with the periodic communication bus.
  • FIG. 1 is a diagram showing a time chart showing the transmission timing of each communication node in a conventional cyclic communication cycle.
  • FIG. 2 is a diagram of a configuration example of the communication system according to the first embodiment of the present invention.
  • FIG. 3 is a diagram illustrating a configuration of an internal block of the controller according to the first embodiment of the present invention.
  • FIG. 4A is a diagram illustrating an example of the timing of data flowing on the bus when message periodic communication and message communication are mixed on the message communication bus in the first embodiment.
  • FIG. 4-2 is a diagram illustrating another timing example of data flowing on the bus when the message fixed period communication and the message communication are mixed on the message communication bus in the first embodiment.
  • FIG. 5 is a diagram illustrating an example of the data transmission timing of the fixed-cycle communication and the message fixed-cycle communication in the second embodiment.
  • FIG. 6 is a diagram illustrating an example of the data transmission timing of the fixed-cycle communication and the message fixed-cycle communication in the second embodiment.
  • FIG. 7 is a diagram illustrating an example of the data transmission timing of the fixed-cycle communication and the message fixed-cycle communication in the second embodiment.
  • FIG. 8 is a diagram illustrating an example of the data transmission timing of the fixed-cycle communication and the message fixed-cycle communication in the second embodiment.
  • FIG. 9 is a diagram showing a schematic configuration of a communication system by paying attention to the state of a fixed-cycle communication memory (shared memory) via a fixed-cycle communication bus.
  • FIG. 10 is a diagram showing a schematic configuration of a communication system by paying attention to the state of a fixed-cycle communication memory (shared memory) via a message communication bus.
  • FIG. 1 shows a time chart showing the transmission timing of each communication node in the cyclic communication cycle.
  • N1 to N6 are controllers (data processing devices) connected to one bus, N1 does not transmit data, and N2 to N6 perform data transmission.
  • a cyclic communication cycle is initially constituted by two isochronous cycles. That is, the cyclic communication cycle configured by the first and second cycles (actually included up to the third cycle) shows a case where the operation is performed without any problem.
  • the asynchronous data is transmitted in the third and fourth cycles, so the timing of the periodic data transmitted by N3, N4, and N5 is delayed, and the cyclic data is cyclic.
  • the communication cycle has been extended from the original two to three isochronous cycles.
  • the cyclic communication cycle started from the sixth cycle since asynchronous data is transmitted at the end of the sixth cycle, the start of the isochronous cycle itself is delayed, and accordingly, the next cyclic communication cycle is finally started.
  • the time has increased by t. In this way, when there is asynchronous data transmission, even if the timing for sending the cyclic communication cycle is devised, the period cannot be made constant due to the nature of asynchronous data.
  • FIG. 2 shows a configuration example of the communication system 100 according to the first embodiment of the present invention.
  • the communication system 100 includes a controller 1 to 8 as a plurality of controllers (data processing devices) and a fixed-cycle communication bus 10 and a message communication bus which are two buses connecting them.
  • 20 is a multi-controller system including an inter-controller synchronization signal line 30 for synchronizing the controllers 1-8.
  • the controllers 1 to 8, each of which is a data processing device, are, for example, a programmable logic controller (PLC), a motion controller (MC), an NC (Numerical Control) device, a robot controller, and the like.
  • PLC programmable logic controller
  • MC motion controller
  • NC Numerical Control
  • the fixed-cycle communication bus 10 is dedicated to fixed-cycle communication and is connected to the controllers 1 to 4 that are controllers compatible with the fixed-cycle communication bus, but the controllers 5 to 8 that are controllers not compatible with the fixed-cycle communication bus are connected. Absent. In order to guarantee punctuality, the communication cycle is time-divided, and a time slot that can be used by each of the controllers 1 to 4 is assigned for transmission / reception.
  • the fixed-cycle communication executed by the fixed-cycle communication bus is used to realize a fixed-cycle communication memory (shared memory) between the fixed-cycle communication bus-compatible controllers 1 to 4.
  • the fixed-cycle communication memory is a storage area secured in, for example, a DRAM provided in each of the controllers 1 to 4 as will be described later.
  • the contents of the fixed-cycle communication memory included in each of the controllers 1 to 4 are updated to a fixed period by fixed-cycle communication so that the contents are the same.
  • the message communication bus 20 is a bus for performing message communication (asynchronous communication), and all of the controllers 1 to 8 are connected, and each controller 1 to 8 can flow data of an arbitrary data size at an arbitrary timing. .
  • Message communication is non-periodic communication that is not fixed-period communication.
  • message fixed-cycle communication is also performed on the same message communication bus 20.
  • the priority control of the data flowing on the message communication bus 20 is made multicast> unicast, that is, priority is given to multicast data transmission over unicast data transmission.
  • a specific method of priority control is not particularly limited as long as it is a method capable of giving priority to multicast data transmission over unicast data transmission.
  • the data size that can be transmitted by one controller within the communication cycle is limited to the data size calculated from the bandwidth allocated for message fixed-cycle communication within the bandwidth of the message communication bus 20, and the restricted data size is multicast. By sending in.
  • FIG. 3 is a diagram showing the configuration of the internal blocks of the controllers 1 to 4 that are the fixed-cycle communication bus-compatible controllers according to the present embodiment, and shows the configuration of the internal blocks of the controller 1 as an example.
  • the controller 1 includes a CPU 3, a DRAM 4, a fixed-cycle communication bus I / F 50, and a message communication bus I / F 60 connected to the internal bus 2.
  • the fixed-cycle communication bus I / F 50 includes a fixed-cycle communication bus transmission memory 51 and a fixed-cycle communication bus reception memory 52
  • the message communication bus I / F 60 includes a message communication bus transmission memory 61 and a message communication bus.
  • Receiving memory 62 receives of the controllers 2 to 4 are the same.
  • controllers 5 to 8 which are controllers not corresponding to the fixed-cycle communication bus are the configurations excluding the fixed-cycle communication bus I / F 50 from FIG.
  • the controller 1 will be described as an example, but the same applies to the controllers 2 to 4.
  • the controller 1 refers to the data sent from the other controllers 2 to 4, performs calculation by the CPU 3, and transmits the result to the other controllers 2 to 4 to perform processing in cooperation between the controllers. be able to. Data exchange between controllers is performed using fixed-cycle communication and message fixed-cycle communication for fixed-cycle data, and message communication for asynchronous data.
  • the DRAM 4 stores the calculation result of the CPU 3 and data sent from another controller. That is, a fixed-cycle communication memory (shared memory) area between the fixed-cycle communication bus-compatible controllers 1 to 4 is secured in the DRAM 4. Specifically, as shown in FIG. 9, the area for each of the controllers 1 to 4 is divided into, for example, four in the fixed-cycle communication memory of the DRAM 4 of each of the controllers 1 to 4, and D1 ( Controller 1 area), D2 (Controller 2 area), D3 (Controller 3 area), and D4 (Controller 4 area) are secured from each controller 1 to 4 via the fixed-cycle communication bus 10. The data transmitted in the cycle (first cycle) is held.
  • FIG. 9 the area for each of the controllers 1 to 4 is divided into, for example, four in the fixed-cycle communication memory of the DRAM 4 of each of the controllers 1 to 4, and D1 ( Controller 1 area), D2 (Controller 2 area), D3 (Controller 3 area), and D4 (Controller 4 area) are secured from each controller 1 to 4 via
  • FIG. 9 is a diagram showing a schematic configuration of the communication system 100 by paying attention to the state of the fixed-cycle communication memory (shared memory) via the fixed-cycle communication bus 10.
  • the fixed-cycle communication memories (D1 to D4) provided in the respective DRAMs 4 of the respective controllers 1 to 4 are updated at a fixed cycle so as to have the same contents by the fixed-cycle communication. Therefore, the size of the fixed-cycle communication memory included in each of the controllers 1 to 4 is limited by the bus bandwidth that can be used for fixed-cycle communication.
  • the fixed-cycle communication bus I / F 50 is an I / F that connects the fixed-cycle communication bus 10 and the controller 1 and performs a fixed-cycle communication process.
  • the fixed-cycle communication bus transmission memory 51 is a buffer memory used when transmitting the calculation result of the CPU 3 stored in the DRAM 4 to another controller through the fixed-cycle communication bus 10.
  • the fixed-cycle communication bus reception memory 52 is a buffer memory used when receiving data sent from another controller through the fixed-cycle communication bus 10.
  • the message communication bus I / F 60 is an I / F that connects the message communication bus 20 and the controller 1, and performs message periodic communication and message communication processing.
  • the message communication bus transmission memory 61 is a buffer memory used when transmitting the calculation result of the CPU 3 stored in the DRAM 4 to another controller through the message communication bus 20.
  • the message communication bus reception memory 62 is a buffer memory used when receiving data sent from another controller through the message communication bus 20.
  • message periodic communication using the message communication bus I / F 60 in the present embodiment will be described.
  • message periodic communication the following 1. To 4. Is executed.
  • the CPU 3 copies data to be communicated with the message at regular intervals from the DRAM 4 to the message communication bus transmission memory 61, and transmits this data to the controllers (for example, the controllers 1 to 8 in FIG. 2) by multicast.
  • the message communication bus I / F 60 is notified.
  • the size of the data transmitted by the message fixed period communication is set to be equal to or smaller than the size that one controller can communicate within the communication period in the band of the message communication bus 20 allocated to the message fixed period communication. . This size is obtained by the following calculation formula.
  • the bandwidth of the message communication bus 20 is 1 Gbps (bit / second), of which 500 Mbps is a bandwidth allocated for message periodic communication, and the remaining 500 Mbps is allocated for message communication.
  • the communication cycle is 1 ms (second), for example, 500 Mbps ⁇ 1 ms is the upper limit value of the data amount of message fixed-cycle communication during one communication cycle in the message communication bus 20. Therefore, a value obtained by dividing 500 Mbps ⁇ 1 ms by the number of controllers that perform message periodic communication is the upper limit value of the size at which one controller can communicate within the communication period.
  • the value of (the size that one controller can communicate within the communication cycle) according to the above calculation formula is calculated by equalizing the size that each controller can transmit, but the total size of the data transmitted by each controller is ( It suffices to avoid exceeding (bandwidth allocated to message fixed-cycle communication) ⁇ (communication cycle), and it is possible to increase the size that can be transmitted by a certain controller and decrease the size that can be transmitted by another controller.
  • the message communication bus I / F 60 uses the multicast destination as the controller for performing the message fixed-cycle communication for each communication cycle synchronized with the synchronization signal of the inter-controller synchronization signal line 30, and transmits the data in the message communication bus transmission memory 61 to the message communication. Transmit to the bus 20. That is, data transmission in the message periodic communication is multicast transmission.
  • the message communication bus 20 controls priority control of multicast and unicast by multicast> unicast, that is, priority is given to multicast over unicast. Therefore, for example, since general message communication between the controller and the controller is unicast, the message communication bus 20 gives the message fixed-cycle communication data sent as multicast to the controller that performs the message fixed-cycle communication with the highest priority. To send.
  • FIG. 10 is a diagram showing a schematic configuration of the communication system 100 while paying attention to the state of the fixed-cycle communication memory (shared memory) via the message communication bus 20. Specifically, as shown in FIG.
  • the fixed-cycle message communication enables the fixed-cycle communication to be performed by the controllers 5 to 8 in FIG. 2 which are controllers not compatible with the fixed-cycle communication bus.
  • FIGS. 4A and 4B show examples of the timing of data flowing on the message communication bus 20 when message periodic communication and message communication are mixed on the message communication bus 20.
  • FIG. 4A and 4B show examples of the timing of data flowing on the message communication bus 20 when message periodic communication and message communication are mixed on the message communication bus 20.
  • cycle 1 in FIG. 4A shows the case of message fixed cycle communication only.
  • FIG. 4A shows a case where the controllers 1 to 4 transmit data simultaneously at the start of the communication cycle. Since the order of data flowing on the message communication bus 20 has the same priority during the message fixed period communication, it is possible to determine the order in random order, ID order, or the like. Here, in order to simplify the explanation, it is assumed that the transmission data of the message fixed-cycle communication is flowed on the message communication bus 20 in the order of the controller 1, the controller 2, the controller 3, and the controller 4.
  • cycle 2 in FIG. 4A shows a case where a request for message fixed cycle communication and message communication are issued within the same cycle.
  • Controllers 1 to 4 request message periodic communication, and controllers 5 and 6 request message communication.
  • the priority of transmission on the message communication bus 20 is controlled so that multicast is higher than unicast, and the message periodic communication is multicast and the message communication is unicast. Sent to. Then, message communication is transmitted after all message periodic communication is completed. In addition, since the transmission data of the message communication of the controller 6 is not completed in the period 2, the remaining transmission is shifted to the period 3.
  • the transmission of the remaining transmission data of the message communication of the controller 6 is shifted after all the message fixed-cycle communication is completed in the cycle 3 as well. Transmission of message communication data of the controller 5 in the cycle 3 is further thereafter.
  • Fig. 4-2 shows an example when there is a gap between the fixed-cycle message communications.
  • the message communication is performed during the time when the message fixed period communication is not performed.
  • the message communication data of the controller 5 is partially transmitted after transmission of the transmission data of the message fixed cycle communication of the controller 3 and before transmission of the transmission data of the message fixed cycle communication of the controller 4. Is transmitted after the transmission data of the message fixed period communication of the controller 4 is transmitted.
  • the message communication data is divided and transmitted using the gap between the message fixed cycle communications.
  • controllers 1 to 4 and the controllers 5 and 6 in FIGS. 4A and 4B are described as different controllers. However, the controllers 1 to 4 and the controllers 5 and 6 are duplicated. It doesn't matter. That is, for example, the controller 5 is the controller 1 and the controller 6 is the controller 2, and data transmission is executed at the same timing as described above even when message communication data is transmitted in addition to message periodic communication data. .
  • priority control on the message communication bus 20 is performed with priority given to multicast data transmission over unicast data transmission, and then message periodic communication is multicast and message communication. Is transmitted by unicast.
  • the data size that can be transmitted by one controller within a certain period is limited to, for example, the upper limit data size calculated from the band allocated to the message fixed period communication in the band of the message communication bus 20, Send data less than the size by multicast.
  • the number of data processing devices capable of fixed-cycle communication can be extended to controllers that do not support fixed-cycle communication buses.
  • the size of the fixed-cycle communication memory in the fixed-cycle communication bus compatible controller can be increased.
  • Embodiment 2 The system configuration and the operation of each bus in the second embodiment of the present invention are the same as those in the first embodiment. That is, the configuration example of the communication system according to the present embodiment is the same as that of the communication system 100 of FIG. In addition, the basic operation of the message fixed-cycle communication according to the present embodiment is the same as the basic operation of the message fixed-cycle communication described in the first embodiment. To 4. It is the same.
  • FIG. 5 shows data transmission timings of the fixed-cycle communication on the fixed-cycle communication bus 10 and the message fixed-cycle communication on the message communication bus 20 in the fixed-cycle communication bus compatible controller (controllers 1 to 4 in FIG. 2). .
  • FIG. 5 shows a case where the communication cycle (first cycle) of fixed cycle communication on the fixed cycle communication bus 10 and the communication cycle (second cycle) of message fixed cycle communication on the message communication bus 20 are the same.
  • the inter-controller synchronization signal line 30 is connected between the controllers 1 to 4 as shown in FIG. 2, and the timing of the communication cycle between the controllers 1 to 4 is synchronized by the synchronization signal that flows on the controller. Further, as shown in FIG. 5, each controller 1 to 4 performs fixed-cycle communication and message fixed-cycle communication for each communication cycle, so that data by fixed-cycle communication and data by message fixed-cycle communication are transmitted during the same communication cycle. Can be transmitted. As a result, each of the controllers 1 to 4 corresponding to the fixed-cycle communication bus can increase the data size that can be transmitted for each communication cycle compared to the case where fixed-cycle communication is performed only on the fixed-cycle communication bus 10. Thus, the size of the fixed-cycle communication memory (shared memory) can be increased.
  • fixed-cycle communication memory shared when fixed-cycle communication is performed only on the fixed-cycle communication bus 10.
  • the size of the memory is 100 kbytes
  • the reason why the increase of 100 kbytes does not occur is that the entire bandwidth of the message communication bus 20 is not used for the message periodic communication, and the portion of the message communication bus 20 excluding the bandwidth used for asynchronous message communication is the message. This is because the fixed-cycle communication can be used.
  • the message fixed cycle communication on the message communication bus 20 is performed between the controllers 1 to 4, but the message fixed cycle communication is performed between the controllers 1 to 8 as shown in FIG.
  • the number of controllers that perform message periodic communication may be increased. Also in this case, the communication cycle of the fixed-cycle communication and the communication cycle of the message fixed-cycle communication are the same. Assuming that the bandwidths of the fixed-cycle communication bus 10 and the message communication bus 20 are the same, and assuming that the bandwidth used for message fixed-cycle communication among the bandwidth of the message communication bus 20 is the same as in the case of FIG. The number of controllers that perform message periodic communication has doubled.
  • the fixed-cycle communication memory when performing fixed-cycle communication only on the fixed-cycle communication bus 10 is 100 kbytes as in the case of FIG. 5, the fixed-cycle communication memory increases. The amount of (shared memory) remains at 25 kbytes.
  • the communication cycle (second cycle) of the message fixed cycle communication on the message communication bus 20 is an integral multiple of the communication cycle (first cycle) of the fixed cycle communication on the fixed cycle communication bus 10, for example, as shown in FIG.
  • the message fixed period communication on the message communication bus 20 may be performed between the controllers 1 to 4.
  • the communication cycle (second cycle) of message fixed cycle communication on the message communication bus 20 is an integer fraction of the communication cycle (first cycle) of fixed cycle communication on the fixed cycle communication bus 10, for example, FIG.
  • the message fixed period communication on the message communication bus 20 may be performed between the controllers 1 to 4 by 1/2.
  • the number of controllers that perform message periodic communication may be increased so that message periodic communication is performed between controllers 1-8.
  • This also increases the amount of fixed-cycle communication memory (shared memory) by executing message fixed-cycle communication on the message communication bus 20 in addition to fixed-cycle communication on the fixed-cycle communication bus 10. Needless to say, this can be done.
  • the bandwidth of the message communication bus 20 is increased when the fixed-cycle communication bus 10 and the message communication bus 20 are speeded up, particularly when the message communication bus 20 is speeded up. It is the communication system which can utilize effectively. That is, by performing message fixed-cycle communication on the message communication bus 20, the data size that can be transmitted and received by message fixed-cycle communication is added to the fixed-cycle communication memory (shared memory) capacity that can be originally used by the controller corresponding to the fixed-cycle communication bus. It becomes possible to add.
  • fixed-cycle communication is performed per base (substrate having a bus) by performing fixed-cycle communication on the message communication bus 20 that can be used in common between the fixed-cycle communication bus compatible controller and the non-fixed-cycle communication bus compatible controller. It is possible to increase the number of controllers that can be used.
  • the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage.
  • the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent requirements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When an effect is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.
  • the constituent elements over different embodiments may be appropriately combined.
  • the communication system according to the present invention is useful as a communication system in which a plurality of data processing devices such as a programmable logic controller are connected, and is particularly suitable for a multi-controller system.

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Abstract

L'invention concerne un système de communication comprenant une pluralité de dispositifs de traitement de données, un premier bus auquel certains ou la totalité des dispositifs de traitement de données se connectent, et un second bus auquel la totalité des dispositifs de traitement de données se connectent. Du fait que les dispositifs de traitement de données qui sont connectés au premier bus communiquent de façon périodique par l'intermédiaire du premier bus à une première période, des données, qui sont conservées dans des régions de stockage que chacun des dispositifs de traitement de données qui sont communiqués par l'intermédiaire du premier bus comprend, sont mises à jour avec le même contenu pour chaque première période. Du fait que les dispositifs de traitement de données qui sont connectés au second bus communiquent de façon périodique par l'intermédiaire du second bus à une seconde période, des données, qui sont conservées dans des régions de stockage que chacun des dispositifs de traitement de données qui sont communiqués par l'intermédiaire du second bus comprend, sont mises à jour avec le même contenu pour chaque seconde période. La communication périodique par l'intermédiaire du second bus est transmise avec une priorité supérieure par rapport à une communication apériodique des dispositifs de traitement de données qui sont connectés au second bus, et une valeur limite supérieure est disposée pour la quantité de données de communication périodique entre les secondes périodes dans le second bus.
PCT/JP2011/078093 2011-12-05 2011-12-05 Système de communication WO2013084280A1 (fr)

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Publication number Priority date Publication date Assignee Title
JP2018129613A (ja) * 2017-02-07 2018-08-16 オムロン株式会社 制御装置および通信装置
JP2019054418A (ja) * 2017-09-15 2019-04-04 トヨタ自動車株式会社 車載装置、情報処理装置、情報処理方法、及びプログラム

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JP2000124927A (ja) * 1998-10-15 2000-04-28 Harness Syst Tech Res Ltd 車載データ通信装置及び車載データ通信方法
JP2003500960A (ja) * 1999-05-20 2003-01-07 ハネウェル・インコーポレーテッド クリティカルなアビオニクス・データバスを介して周期データおよび非周期データを伝送する方法およびシステム
WO2008041271A1 (fr) * 2006-09-29 2008-04-10 Fujitsu Microelectronics Limited Système d'émission/reception, noeud et procédé de communication

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124927A (ja) * 1998-10-15 2000-04-28 Harness Syst Tech Res Ltd 車載データ通信装置及び車載データ通信方法
JP2003500960A (ja) * 1999-05-20 2003-01-07 ハネウェル・インコーポレーテッド クリティカルなアビオニクス・データバスを介して周期データおよび非周期データを伝送する方法およびシステム
WO2008041271A1 (fr) * 2006-09-29 2008-04-10 Fujitsu Microelectronics Limited Système d'émission/reception, noeud et procédé de communication

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018129613A (ja) * 2017-02-07 2018-08-16 オムロン株式会社 制御装置および通信装置
CN110169017A (zh) * 2017-02-07 2019-08-23 欧姆龙株式会社 控制装置以及通信装置
EP3582445A4 (fr) * 2017-02-07 2021-03-03 Omron Corporation Dispositif de commande et dispositif de communication
US11036205B2 (en) 2017-02-07 2021-06-15 Omron Corporation Control device and communication device
CN110169017B (zh) * 2017-02-07 2021-06-25 欧姆龙株式会社 控制装置以及通信装置
JP2019054418A (ja) * 2017-09-15 2019-04-04 トヨタ自動車株式会社 車載装置、情報処理装置、情報処理方法、及びプログラム

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