WO2013082823A1 - 压电纳米线的叠层结构及其制造方法 - Google Patents

压电纳米线的叠层结构及其制造方法 Download PDF

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WO2013082823A1
WO2013082823A1 PCT/CN2011/083804 CN2011083804W WO2013082823A1 WO 2013082823 A1 WO2013082823 A1 WO 2013082823A1 CN 2011083804 W CN2011083804 W CN 2011083804W WO 2013082823 A1 WO2013082823 A1 WO 2013082823A1
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piezoelectric
nanowires
layer
liner sheet
laminated structure
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万里兮
周静
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/702—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive fibres

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  • the present invention relates to piezoelectric devices and manufacturing techniques, and more particularly to a laminated structure of piezoelectric nanowires and a method of fabricating the same. Background technique
  • Piezoelectric materials are crystalline materials that exhibit a potential difference between the two end faces when subjected to pressure. They are widely used in MEMS (Micro Electromechanical System) fields such as pressure, vibration sensors, and even micro-generators.
  • MEMS Micro Electromechanical System
  • the cross-section is always a positive potential, the lower part is a negative potential, the middle surface is connected to the growth substrate to a zero potential, and the positive potential at the upper part of the cross-section is proportional to the degree of bending of the nanorod, bending The larger, the higher the potential.
  • the voltage of zinc oxide nanorods with a length of about 1 micron and a diameter of 40 to 80 nanometers is deducted from the forward voltage drop on the Schottky diode generated by the contact, and the output voltage is between 5 and 50 microvolts.
  • the internal resistance is in the range of tens to hundreds.
  • a single nanorod produces a voltage of typically a few tens of millivolts, a current of a few picoamperes, and a voltage and current that are too small to drive a typical electronic system.
  • the area of the nanorod array is connected in parallel to increase the area and increase the number of participating nanorods, thereby increasing the current. It is very difficult to increase the voltage. It is necessary to connect the nanorods in series, but the scale of the nanorods is too small, and the process is difficult to obtain now. Therefore, it is necessary to propose a nano-rod structure having a large piezoelectric voltage and a method of manufacturing the same. Summary of the invention
  • Embodiments of the present invention provide a laminated structure of piezoelectric nanowires, which has a large piezoelectric voltage and is easy to implement.
  • a laminated structure of a piezoelectric nanowire comprising: a first conductive layer; a piezoelectric layer on the first conductive layer, wherein the piezoelectric layer includes a stack of piezoelectric nanowires formed; a second conductive layer on the piezoelectric layer.
  • the material of the piezoelectric nanowire is zinc oxide, silicon dioxide or gallium arsenide.
  • the piezoelectric nanowire has a diameter of 1 Onm - 1 OOum.
  • the piezoelectric nanowires have a length of 300 nm to 10 mm.
  • the piezoelectric layer has a thickness of 500 nm to 10000 um.
  • the piezoelectric nanowires in the stack are substantially ordered or disorderly aligned parallel to the first conductive surface.
  • the first conductive layer and the second conductive layer have a thickness of 100 nm to 10 mm.
  • the present invention also provides a method for fabricating a stacked structure of piezoelectric nanowires, comprising: providing a substrate; growing piezoelectric nanowires on the substrate; and stripping the piezoelectric nanowires from the substrate; The plurality of piezoelectric nanowires are stacked and then pressed to form a piezoelectric layer; and the first conductive layer and the second conductive layer are respectively formed on the opposite surfaces of the piezoelectric layer.
  • the step of laminating the plurality of piezoelectric nanowires after pressing comprises: immersing the stripped piezoelectric nanowires in a volatile liquid; and depositing the volatile liquid containing the plurality of piezoelectric nanowires On a liner sheet, after the volatile liquid is volatilized, the second liner sheet is placed on the piezoelectric nanowire; pressure is applied from the first liner sheet and the second liner sheet to form a plurality of strips a piezoelectric layer in which piezoelectric nanowires are stacked; the first liner sheet and the second liner sheet are removed.
  • the step of laminating the plurality of piezoelectric nanowires after lamination comprises: immersing the stripped piezoelectric nanowires in the filtering liquid; removing the filtering liquid through the filtering membrane; and disposing the piezoelectric nanometers from the filtering membrane Wire stripping and stacking the piezoelectric nanowires on the first liner sheet, and placing the second liner sheet over the piezoelectric nanowires; applying pressure from the first liner sheet and the second liner sheet for pressing, Forming a piezoelectric layer formed by stacking a plurality of piezoelectric nanowires; removing the first liner sheet and the second liner sheet.
  • the material of the piezoelectric nanowire is zinc oxide, silicon dioxide or gallium arsenide.
  • the laminated structure of the piezoelectric nanowire according to the embodiment of the present invention forms a piezoelectric layer by stacking a plurality of piezoelectric nanowires, thereby forming a structure in which the piezoelectric nanowires are self-connected, and when subjected to pressure bending, the piezoelectric The voltage generated by the effect is connected in series, thus outputting a higher voltage.
  • the first conductive layer and the second conductive layer facilitate the extraction of the piezoelectric signal and protect the piezoelectric layer, thereby facilitating the application of the laminated structure of the piezoelectric nanowire. In the manufacture of various devices.
  • FIG. 1 is a schematic structural view of a laminated structure of a piezoelectric nanowire of the present invention
  • FIG. 2 is a schematic diagram of a boosting scheme of a stack of piezoelectric nanowires
  • FIG. 3 is a schematic diagram of a self-boosting of a cross-section of a laminated structure of a piezoelectric nanowire of the present invention
  • FIG. 4 is a schematic view showing a state of deformation of a laminated structure of piezoelectric nanowires having a directional output voltage according to an embodiment of the present invention
  • FIG. 5 is a schematic view showing a state of deformation of a laminated structure of piezoelectric nanowires having no output voltage according to an embodiment of the present invention
  • Fig. 6 is a view showing the structure of a laminated structure of piezoelectric nanowires of omnidirectional output voltage according to an embodiment of the present invention. detailed description
  • a single zinc oxide nanowire produces a small voltage that is insufficient to drive the operation of the electronic device, and it is difficult to achieve a process in which the nanowires are connected in series to increase the output voltage.
  • a piezoelectric layer is formed by stacking piezoelectric nanowires, thereby forming a self-series in cross section.
  • the stacked structure, thereby increasing the output voltage, as shown in FIG. 1, is a boosting schematic diagram of the piezoelectric nanowire stack in the present invention, and the illustrated example is an ideal case in which the piezoelectric nanowires 101 are sequentially stacked together.
  • each of the piezoelectric nanowires 101 is stretched to generate a positive potential in the upper portion of the axial direction, and is subjected to a negative potential in the lower portion of the axial direction, since the piezoelectric nanowires 101 are stacked. Together, the axial surfaces of the piezoelectric nanowires are brought into contact with each other such that the output voltages are connected in series. If the output voltage 102 of each piezoelectric nanowire 101 is V, the output voltage 103 in the cross section of the stack is a series voltage nV. Thus, the increase in the overall output voltage is achieved by this self-tandem manner.
  • the present invention proposes a laminated structure of piezoelectric nanowires, which is formed by stacking a plurality of piezoelectric nanowires to form a piezoelectric layer, thereby forming a self-series structure of piezoelectric nanowires, and in piezoelectric Conductive layers are respectively formed on the upper and lower surfaces of the layer, and the output voltage signal can be extracted through the conductive layer, and the piezoelectric layer is protected, so that the laminated structure of the piezoelectric nanowires can be applied to the manufacture of various devices.
  • the laminated structure of the piezoelectric nanowire includes:
  • the first conductive layer 201 has an upper piezoelectric layer 202, and the piezoelectric layer includes a stack formed of a plurality of piezoelectric nanowires 202i;
  • a second conductive layer 203 on the piezoelectric layer 202 is formed on the piezoelectric layer 202.
  • the piezoelectric nanowire may also be referred to as a piezoelectric nanorod, which is a nanowire having a piezoelectric property material, and the piezoelectric material may be zinc oxide, silicon dioxide, gallium oxysulfide or other pressure. Electrical properties of the material.
  • nanowires or nanorods have a one-dimensional structure that is limited in the radial direction to the nanometer scale (the length is not limited).
  • typical nanowires have diameters ranging from a few ten nanometers to hundreds of nanometers and lengths of several micrometers.
  • the piezoelectric nanowire may have a diameter of lOnm-lOOum, and the piezoelectric nanowire may be lum-10 mm, or other suitable size.
  • an anisotropic conductive paste which may also have an anisotropic conductive paste. That is, there is a bonding effect, and there is a property of exhibiting conductivity only under pressure, which makes the contact between the piezoelectric nanowires more compact.
  • piezoelectric nanowires have substantially uniform lengths, the length of which is generally as long as possible, long nanowires are easy to interweave and stack, and too short will result in non-horizontal stacking and reduce the output efficiency of piezoelectric effect.
  • the piezoelectric nanowires may have a length of from 300 nm to 10 mm, or other suitable length.
  • the first conductive layer and the second conductive layer may be the same or different conductive materials, such as a single metal material, a multi-metal composite material, an alloy material or a conductive organic material, etc., the first conductive layer and The second conductive layers may have the same or different thicknesses and may range in thickness from 100 nm to 10 mm.
  • the first conductive layer and the second conductive layer are respectively formed on opposite surfaces of the piezoelectric layer, and the voltage signals of the piezoelectric layer are extracted by the first and second conductive layers, and the piezoelectric layer is provided with physical support, so that The entire piezoelectric layer is molded for subsequent application in the manufacture of various devices, and also provides protection for the piezoelectric layer from external contamination and damage.
  • the piezoelectric layer may be a stack formed by the substantially ordered arrangement of the piezoelectric nanowires. That is, in the piezoelectric layer, the radial orientation of the piezoelectric nanowires 402 is substantially uniform, and at least most of the piezoelectric nanowires in the stack are sequentially arranged in parallel with the first conductive surface, and the nanowires are ordered.
  • the aligned laminated structure has an output voltage that is a directional output, that is, the output voltage is related to the deformation direction of the structure, and the magnitude of the output voltage is related to the magnitude of the deformation, and the normal of the deformation surface of the structure is at the diameter of the nanowire 402.
  • the output of the structure is maximum; when the normal direction of the deformation surface of the structure is in the radial direction of the nanowire 502 and when the structure is not deformed
  • the normal phase is perpendicular to the plane, as shown in Fig. 5, the structure has no output, and the deformation at any other position produces an output boundary between the two, which is related to the direction of the specific deformation.
  • the piezoelectric layer formed by stacking the piezoelectric nanowires has a thickness of 500 nm to 10000 um, or other suitable thickness, and the thickness of the piezoelectric layer to be formed can be determined according to specific design requirements and manufacturing processes.
  • the piezoelectric layer may be a stack formed by the substantially disordered arrangement of the piezoelectric nanowires, that is, in the piezoelectric layer, the radial orientation of the piezoelectric nanowires 602 is disordered. At least a majority of the piezoelectric nanowires in the stack are disorderly aligned parallel to the first conductive layer.
  • the output voltage is an undirected output, although the nanowires are formed by a disorderly stack.
  • the piezoelectric layer, but the nanowires are still in contact, and the output voltage of the overall structure can be increased by self-series.
  • the output voltage is independent of the deformation direction, as shown in FIG.
  • the ideal state is all the piezoelectric nano
  • the rice noodles are arranged parallel to the first conductive layer and are sequentially stacked to form a piezoelectric layer.
  • the ideal state is not easy to realize, but most of the piezoelectric nanowires are arranged parallel to the first conductive layer and have The piezoelectric layers formed by stacking them sequentially or disorderly can also achieve the object of the present invention.
  • the present invention also provides a manufacturing method of the above structure, the method comprising:
  • a first conductive layer and a second conductive layer are formed on opposite surfaces of the piezoelectric layer, respectively.
  • a substrate is provided.
  • a silicon substrate is provided, which is a substrate for forming piezoelectric nanowires, which has been subjected to a preliminary operation such as a cleaning process.
  • step S102 piezoelectric nanowires are grown on the substrate.
  • piezoelectric nanowires can be formed by any suitable method.
  • a nanowire of zinc oxide is formed on a silicon substrate by an evaporation method, and the length of the nanowire of zinc oxide is substantially uniform, and in this embodiment, the length may be 10 um to 100 um.
  • step S103 the piezoelectric nanowires are peeled off from the substrate.
  • the zinc oxide nanowires are scraped from the silicon substrate.
  • step S104 a plurality of piezoelectric nanowires are stacked and then pressed to form a piezoelectric layer.
  • the piezoelectric layer is formed by a volatilization method, specifically:
  • the stripped piezoelectric nanowires are immersed in a volatile liquid.
  • the scraped zinc oxide nanowires are immersed in a liquid which is volatile liquid but does not dissolve zinc oxide, such as alcohol.
  • the volatile liquid containing the plurality of piezoelectric nanowires is poured on the first liner sheet, the piezoelectric nanowires are stacked together, and after the volatile liquid is volatilized, the second liner sheet is placed on the piezoelectric nanowire.
  • the first and second liner sheets are used to support a stacked substrate of a plurality of piezoelectric nanowires and are used for a liner of a subsequent compression process.
  • the first and second liner sheets are silicon wafers, and the zinc oxide nanowires are disorderly stacked on the first liner sheet, and the second liner sheet is overlaid on the zinc oxide nanowires.
  • the piezoelectric layer may also be formed by a filtering method, specifically: first, the peeled piezoelectric nanowire is immersed in a filtering liquid, and a liquid such as water is filtered, for example, a piezoelectric nanowire. Zinc oxide nanowires.
  • the filtered liquid is removed through the filter membrane, so that the piezoelectric nanowires are stacked on the filter membrane.
  • the piezoelectric nanowires are peeled off from the filter film and the piezoelectric nanowires are stacked on the first liner sheet, and the second liner sheet is placed on the piezoelectric nanowires, the first and second liner sheets For example, silicon wafers.
  • the above structure can be placed in a high voltage apparatus for a press synthesis film process, and the stacked piezoelectric nanowires are tightly integrated to form a piezoelectric layer in which piezoelectric nanowires are stacked. If necessary, in the press-fitting process, vacuuming or heating may be performed to better perform the pressing.
  • a first conductive layer and a second conductive layer are respectively formed on the opposite surfaces of the piezoelectric layer.
  • the piezoelectric layer may be subjected to double-sided metal sputtering, and the opposite surfaces of the piezoelectric layer may be plated with metal to form first and second conductive layers.

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

一种压电纳米线的叠层结构，包括：第一导电层（201）；第一导电层（201）上压电层（202），所述压电层（202）包括由多条压电纳米线（202i）形成的堆叠；压电层（202）上的第二导电层（203）。通过将多条压电纳米线堆叠后形成压电层，从而形成了压电纳米线自串联的结构，在受到压力弯曲时，其压电效应产生的电压串联，因此输出了更高的电压，此外，第一导电层和第二导电层便于将压电信号引出，并保护了压电层，便于将压电纳米线叠层结构应用于各种器件的制造。

Description

压电纳米线的叠层结构及其制造方法
本申请要求于 2011 年 12 月 07 日提交中国专利局、 申请号为 201110404235.3、 发明名称为"压电纳米线的叠层结构及其制造方法"的中国专 利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及压电器件及制造技术， 更具体地说， 涉及一种压电纳米线的叠 层结构及其制造方法。 背景技术
压电材料是受到压力作用时会在两端面间出现电势差的晶体材料，广泛应 用于 MEMS ( Micro Electromechanical System, 敖电子机械系统）领域， 例如 压力、 震动传感器， 甚至微型发电机等。
近年来的研究发现， 垂直生长的压电材料氧化锌纳米棒（或称氧化锌纳米 线）在受到侧向外力作用弯曲时具有压电特性。 氧化锌纳米棒的横截面为正六 边形， 当纳米棒受力被压弯时， 向外部分受到拉伸， 向内部分受到挤压。 由压 电原理知道，拉伸和挤压将产生方向相反的电场，也就是沿轴向方向在中分面 两侧将产生方向相反的两个电场。 因此， 无论向何方向弯曲， 横截面上部始终 为正电位， 下部为负电位， 中分面与生长衬底相连接为零电位， 截面上部的正 电位大小与纳米棒弯曲的程度成正比例， 弯曲越大， 电位越高。 根据研究， 长 度在 1微米左右，直径在 40至 80纳米的氧化锌纳米棒的电压在扣除由于接触 生成的肖特基二极管上的正向压降外， 输出电压在 5至 50微伏之间， 内阻在 几十到几百 左右。
然而， 单根纳米棒产生的电压一般为几十毫伏， 电流在几皮安左右， 电压 和电流都太小， 远不足以驱动通常的电子系统。 一般地， 通过纳米棒阵列并联 的方法来扩大面积， 增加参与的纳米棒数量， 从而增加电流。 而增加电压是十 分困难的， 需要将纳米棒串连起来， 但纳米棒的尺度太小， 现在工艺很难做得 到。 因此， 有必要提出一种具有大的压电电压纳米棒结构和其制造方法。 发明内容
本发明实施例提供了一种压电纳米线的叠层结构， 具有大的压电电压，且 易于实现。
为实现上述目的， 本发明实施例提供了如下技术方案： 一种压电纳米线的叠层结构， 包括： 第一导电层； 第一导电层上压电层， 所述压电层包括由多条压电纳米线形成的堆叠； 压电层上的第二导电层。 可选地， 所述压电纳米线的材料为氧化锌、 二氧化硅或四氧石充化镓。 可选地， 所述压电纳米线的直径为 1 Onm- 1 OOum。 可选地， 所述压电纳米线的长度为 300nm-10mm。 可选地， 所述压电层的厚度为 500nm-10000um。 可选地，所述堆叠中的压电纳米线基本上有序或无序地平行于与第一导电 面排列。 可选地， 所述第一导电层和第二导电层的厚度为 100nm-10mm。 此外， 本发明还提供了一种压电纳米线的叠层结构的制造方法， 包括： 提供衬底； 在所述衬底上生长压电纳米线； 将压电纳米线从衬底上剥离； 将多条压电纳米线堆叠后进行压合， 以形成压电层； 在压电层相对的表面上分别形成第一导电层和第二导电层。 可选地， 将多条压电纳米线堆叠后进行压合的步骤包括： 将剥离后的压电纳米线浸泡在挥发性液体中； 将包含多条压电纳米线的挥发性液体倒于第一衬垫片上 ,在挥发性液体挥 发后， 将第二衬垫片放置于压电纳米线之上； 从第一衬垫片及第二衬垫片施加压力进行压合，以形成由多条压电纳米线 堆叠而成的压电层； 去除第一衬垫片及第二衬垫片。 可选地， 将多条压电纳米线堆叠后进行压合的步骤包括： 将剥离后的压电纳米线浸泡在过滤液体中； 通过过滤膜将过滤液体去除； 从过滤膜上将压电纳米线剥离并将压电纳米线堆叠在第一衬垫片上，并将 第二衬垫片放置于压电纳米线之上； 从第一衬垫片及第二衬垫片施加压力进行压合，以形成由多条压电纳米线 堆叠而成的压电层； 去除第一衬垫片及第二衬垫片。 可选地， 所述压电纳米线的材料为氧化锌、 二氧化硅或四氧石充化镓。
与现有技术相比， 上述技术方案具有以下优点：
本发明实施例的压电纳米线的叠层结构，通过将多条压电纳米线堆叠后形 成压电层， 从而形成了压电纳米线自串联的结构， 在受到压力弯曲时， 其压电 效应产生的电压串联， 因此输出了更高的电压， 此外， 第一导电层和第二导电 层便于将压电信号引出， 并保护了压电层，便于将压电纳米线的叠层结构应用 于各种器件的制造。 附图说明 通过附图所示， 本发明的上述及其它目的、 特征和优势将更加清晰。 在全 部附图中相同的附图标记指示相同的部分。并未刻意按实际尺寸等比例缩放绘 制附图， 重点在于示出本发明的主旨。
图 1为本发明的压电纳米线的叠层结构的结构示意图；
图 2为压电纳米线的堆叠的升压原理图；
图 3为本发明的压电纳米线的叠层结构的横截面的自升压原理图； 图 4 为根据本发明实施例定向输出电压的压电纳米线的叠层结构的形变 状态示意图；
图 5 为根据本发明实施例无输出电压的压电纳米线的叠层结构的形变状 态示意图；
图 6 为根据本发明实施例的全向输出电压的压电纳米线的叠层结构的结 构示意图。 具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明 还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不 违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例 的限制。
其次， 本发明结合示意图进行详细描述， 在详述本发明实施例时， 为便于 说明，表示器件结构的剖面图会不依一般比例作局部放大， 而且所述示意图只 是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、 宽度及深度的三维空间尺寸。
正如背景技术中的描述，单条的氧化锌纳米线产生的电压很小， 不足以驱 动电子器件工作， 而将纳米线串联起来增大输出电压在工艺上 4艮难实现。在本 发明中，通过将压电纳米线的堆叠起来形成压电层，从而在截面上形成自串联 的层叠结构， 从而提高输出电压， 如图 1所示， 为本发明中的压电纳米线堆叠 的升压原理图， 图例中为压电纳米线 101有序地堆叠在一起的理想情况，在压 电纳米线 101弯曲时，每一才艮压电纳米线 101在轴向的上部都受到拉伸产生正 电位，在轴向的下部都受到挤压产生负电位， 由于压电纳米线 101堆叠在一起 而使压电纳米线的轴向的表面相互接触，从而使输出电压串联， 若每条压电纳 米线 101的输出电压 102为 V, 在堆叠的横截面上的输出电压 103 串联电压 nV, 从而通过这种自串联的方式实现了整体输出电压的升高。
基于上述原理， 本发明提出了一种压电纳米线的叠层结构，通过将多条压 电纳米线堆叠后形成压电层，从而形成了压电纳米线自串联的结构， 并且在压 电层的上下表面上分别形成导电层，通过导电层可以将输出电压信号引出， 并 保护了压电层，便于将压电纳米线的叠层结构应用于各种器件的制造。参考图
2-5所示， 该压电纳米线的叠层结构包括：
第一导电层 201 ;
第一导电层 201 上压电层 202, 所述压电层包括由多条压电纳米线 202i 形成的堆叠；
压电层 202上的第二导电层 203。
在本发明中， 所述压电纳米线也可称作压电纳米棒， 为具有压电特性材料 的纳米线， 压电材料可以为氧化锌、 二氧化硅、 四氧硫化镓或其他具有压电特 性的材料。 通常地， 纳米线或纳米棒为具有在径向上被限制在纳米尺度（长度 没有限制） 的一维结构， 目前， 典型的纳米线为直径在十几纳米到数百纳米、 长度在数微米到几十微米或更长的一维材料。在本发明的实施例中， 所述压电 纳米线的直径可以为 lOnm-lOOum, 压电纳米线可以为 lum-10mm, 或者其他 合适的尺寸。
可选地，在压电纳米线之间还具有其他有机或无机材料， 以提高该结构的 性能或工艺过程中的可制造性， 例如还可以具有各向异性导电胶， 该各向异性 导电胶即有粘接的作用， 又有只在受压才表现出导电性的特性，使压电纳米线 间接触更为紧密。
其中， 压电纳米线具有基本一致的长度， 其长度通常是越长越好， 长的纳 米线便于交织和堆叠， 过短会造成非水平的堆叠而减少压电效应的输出效率， 在本发明的实施例中， 压电纳米线的长度可以为 300nm-10mm, 或其他合适的 长度。
其中， 所述第一导电层和第二导电层可以为相同或不同的导电材料，导电 材料例如单金属材料、 多金属复合材料、 合金材料或导电有机材料等等， 所述 第一导电层和第二导电层可以具有相同或不同的厚度， 其厚度范围可以为 100nm-10mm。 所述第一导电层和第二导电层分别形成在压电层相对的表面 上，通过该第一和第二导电层将压电层的电压信号引出， 并对压电层提供物理 支撑， 使整个压电层成型， 便于后续应用于各种器件的制造， 也为压电层提供 了保护， 使其不受外界的污染和损坏等。
其中， 参考图 4所示， 所述压电层可以为由所述压电纳米线基本上有序排 列形成的堆叠。 也就是说， 在压电层中， 压电纳米线 402的径向取向基本一 致，堆叠中至少大多数的压电纳米线有序地与第一导电面平行地排列，对于该 纳米线有序排列的叠层结构， 其输出电压为定向输出，也就是说输出电压与该 结构的形变方向相关，输出电压的大小与形变大小有关，在该结构的形变面的 法向在纳米线 402的径向与该结构未形变时的法向面内时，如图 4所示， 该结 构的输出为最大；在该结构的形变面的法向在纳米线 502的径向与该结构未形 变时的法向相垂直的面内时， 如图 5所示， 该结构无输出， 其他任何位置的形 变产生的输出界于这两者之间， 与具体形变的方向有关。
其中， 由压电纳米线堆叠形成的压电层的厚度为 500nm-10000um, 或者 其他合适的厚度，可以根据具体的设计需要和制造工艺来确定所要形成的压电 层的厚度。
参考图 6所示，所述压电层可以为由所述压电纳米线基本无序排列形成的 堆叠， 也就是说， 在压电层中， 压电纳米线 602的径向取向是杂乱的， 堆叠中 的至少大多数的压电纳米线无序地平行于第一导电层排列，对于该纳米线无序 排列的叠层结构，其输出电压为不定向输出， 虽然纳米线为杂乱堆叠形成压电 层的，但纳米线间仍然是接触的，仍可以通过自串联的方式实现整体结构输出 电压的升高。对于该纳米线无序排列的叠层结构，其输出电压与形变方向无关， 如图 6所示。
需要说明的是，对于压电层中的压电纳米线， 理想的状态为全部的压电纳 米线都平行于第一导电层排列并有序地堆叠形成压电层，而由于制造工艺的限 制， 该理想状态并不易实现，但大多数的压电纳米线平行于第一导电层排列并 有序或无序地堆叠形成的压电层， 同样可以达到本发明的目的。
以上对本发明的压电纳米线的叠层结构的技术方案和效果进行了详细的 描述， 此外， 本发明还提供了上述结构的制造方法， 该方法包括：
提供衬底；
在所述衬底上生长压电纳米线；
将压电纳米线从衬底上剥离；
将多条压电纳米线堆叠后进行压合， 以形成压电层；
在压电层相对的表面上分别形成第一导电层和第二导电层。
为了更好地理解本发明，以下将根据该制造方法的流程对具体实施例的制 造过程进行详细的描述。
在步骤 S01 , 提供衬底。
在此实施例中， 提供硅衬底， 所述硅衬底为用于形成压电纳米线的基底， 所述硅衬底已进行过清洗处理等前期操作。
在步骤 S102, 在所述衬底上生长压电纳米线。
可以通过任何合适的方法形成其他所需的压电纳米线。
在此实施例中， 采用蒸发法在硅衬底上形成氧化锌的纳米线， 氧化锌的纳 米线的长度基本一致， 在此实施例中， 长度可以为 10um-100um。
在步骤 S103, 将压电纳米线从衬底上剥离。
在此实施例中， 将氧化锌的纳米线从硅衬底上刮下。
在步骤 S104, 将多条压电纳米线堆叠后进行压合， 以形成压电层。
具体地， 在一个实施例中通过挥发法来制作压电层， 具体地：
首先， 将剥离后的压电纳米线浸泡在挥发性液体中。
在此实施例中，将刮下的氧化锌的纳米线浸泡在挥发性液体但不溶解氧化 锌的液体中， 例如酒精。
而后，将包含多条压电纳米线的挥发性液体倒于第一衬垫片上，使压电纳 米线堆叠在一起，在挥发性液体挥发后，将第二衬垫片放置于压电纳米线的堆 叠之上。 所述第一和第二衬垫片用于支撑多条压电纳米线的堆叠的基片，并用于后 续压合工艺的衬垫。 在此实施例中， 所述第一和第二衬垫片为硅片， 氧化锌纳 米线杂乱地堆置在第一衬垫片上， 第二衬垫片覆盖在氧化锌纳米线之上。
而后，从第一衬垫片及第二衬垫片施加压力进行压合， 以形成由多条压电 纳米线堆叠而成的压电层。
可选地， 在此步骤中， 还可以采用过滤法来制作该压电层， 具体地： 首先， 将剥离后的压电纳米线浸泡在过滤液体中， 过滤液体例如水， 压电 纳米线例如氧化锌纳米线。
而后，通过过滤膜将过滤液体去除，这样，压电纳米线堆置在了过滤膜上。 而后， 从过滤膜上将压电纳米线剥离并将压电纳米线堆叠在第一衬垫片 上， 并将第二衬垫片放置于压电纳米线之上， 第一和第二衬垫片例如硅片。
而后， 同挥发法的制作步骤，从第一衬垫片及第二衬垫片施加压力进行压 合， 以形成由多条压电纳米线堆叠而成的压电层， 以及去除第一衬垫片及第二 衬垫片。
在此实施例中， 可以将上述结构放置于高压设备中进行压合成膜工艺，压 合后的压电纳米线的堆叠紧密集成在一起， 形成压电纳米线堆叠而成的压电 层。 根据需要， 在压合工艺中， 还可以进行抽真空或加热的操作， 以更好地进 行压合。
而后， 除去第一衬垫片和第二衬垫片。
在步骤 S105 , 在压电层相对的表面上分别形成第一导电层和第二导电层。 在此实施例中， 可以对上述压电层进行两面金属溅射，在压电层相对的两 个表面上镀上金属， 从而形成第一和第二导电层。
至此， 形成了本发明实施例的压电纳米线的叠层结构。
以上为本发明的较佳实施例， 本发明并不限于此。 虽然本发明已以较佳实施例披露如上， 然而并非用以限定本发明。任何熟 悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭 示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为 等同变化的等效实施例。 因此， 凡是未脱离本发明技术方案的内容， 依据本发 、等同变化及修饰， 均仍属于 本发明技术方案保护的范围内

Claims

权 利 要 求
1、 一种压电纳米线的叠层结构， 其特征在于， 包括： 第一导电层； 第一导电层上压电层， 所述压电层包括由多条压电纳米线形成的堆叠； 压电层上的第二导电层。
2、 根据权利要求 1所述的叠层结构， 其特征在于， 所述压电纳米线的材 料为氧化锌、 二氧化硅或四氧石充化镓。
3、 根据权利要求 1所述的叠层结构， 其特征在于， 所述压电纳米线的直 径为 10匪-100謹。
4、 根据权利要求 1所述的叠层结构， 其特征在于， 所述压电纳米线的长 度为 300nm-10mm。
5、 根据权利要求 1所述的叠层结构， 其特征在于， 所述压电层的厚度为 500nm-10000um。
6、 根据权利要求 1-5 中任一项所述的叠层结构， 其特征在于， 所述堆叠 中的压电纳米线基本上有序或无序地平行于第一导电面排列。
7、 根据权利要求 1所述的叠层结构， 其特征在于， 所述第一导电层和第 二导电层的厚度为 100nm-10mm。
8、 一种压电纳米线的叠层结构的制造方法， 其特征在于， 包括： 提供衬底； 在所述衬底上生长压电纳米线； 将多条压电纳米线从衬底上剥离； 将多条压电纳米线堆叠后进行压合， 以形成压电层； 在压电层相对的表面上分别形成第一导电层和第二导电层。
9、 根据权利要求 8所述的方法， 其特征在于， 将多条压电纳米线堆叠后 进行压合的步骤包括： 将剥离后的压电纳米线浸泡在挥发性液体中； 将包含多条压电纳米线的挥发性液体倒于第一衬垫片上 ,在挥发性液体挥 发后， 将第二衬垫片放置于压电纳米线之上； 从第一衬垫片及第二衬垫片施加压力进行压合，以形成由多条压电纳米线 堆叠而成的压电层； 去除第一衬垫片及第二衬垫片。
10、 根据权利要求 8所述的方法， 其特征在于， 将多条压电纳米线堆叠后 进行压合的步骤包括： 将剥离后的压电纳米线浸泡在过滤液体中； 通过过滤膜将过滤液体去除； 从过滤膜上将压电纳米线剥离并将压电纳米线堆叠在第一衬垫片上，并将 第二衬垫片放置于压电纳米线之上； 从第一衬垫片及第二衬垫片施加压力进行压合，以形成由多条压电纳米线 堆叠而成的压电层； 去除第一衬垫片及第二衬垫片。
11、 根据权利要求 8所述的方法， 其特征在于， 所述压电纳米线的材料为 氧化锌、 二氧化硅或四氧石充化镓。
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