WO2013080501A1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
WO2013080501A1
WO2013080501A1 PCT/JP2012/007505 JP2012007505W WO2013080501A1 WO 2013080501 A1 WO2013080501 A1 WO 2013080501A1 JP 2012007505 W JP2012007505 W JP 2012007505W WO 2013080501 A1 WO2013080501 A1 WO 2013080501A1
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Prior art keywords
semiconductor film
resist
conductive layer
forming
gate electrode
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PCT/JP2012/007505
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French (fr)
Japanese (ja)
Inventor
良行 伊藤
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シャープ株式会社
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Publication of WO2013080501A1 publication Critical patent/WO2013080501A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device.
  • liquid crystal display devices are generally used as display devices for personal computers and televisions, for example. Furthermore, the liquid crystal display device is widely used as a display device such as a PDA (Personal Digital Assistant). Research and development have also been conducted on organic EL display devices that can save more power than liquid crystal display devices, and some products have already been put into practical use.
  • PDA Personal Digital Assistant
  • liquid crystal display devices and organic EL display devices are roughly classified into a passive matrix method and an active matrix method depending on the driving method.
  • the active matrix method is actively researched and developed because it can respond faster and drive at a lower voltage than the passive matrix method.
  • a plurality of pixels are usually formed in a matrix, and each pixel is provided with a thin film transistor (hereinafter also referred to as TFT) which is a switching element. .
  • TFT thin film transistor
  • the TFT includes a semiconductor film formed on an insulating substrate, a gate insulating film formed on the semiconductor film, and a gate electrode formed on the gate insulating film. Note that in the case of a bottom gate TFT, the positions of the gate electrode and the semiconductor film are reversed.
  • this semiconductor film is formed of amorphous silicon, the carrier mobility of amorphous silicon is relatively small. Therefore, an IC for driving a display device (Integrated Circuit) is connected to the outside of the display panel. It is necessary to drive the display device.
  • Integrated Circuit Integrated Circuit
  • the semiconductor film is formed of polysilicon
  • the mobility of polysilicon carriers is relatively large, so that a driving circuit composed of TFTs can be integrally formed in the display panel. .
  • a source region and a drain region which are a pair of high-concentration impurity regions into which p-type impurities or n-type impurities are implanted, are formed using the gate electrode as a mask.
  • a leakage current (off-state current) is generated, and in order to prevent inconvenience such as an increase in power consumption, a semiconductor film is provided between a source region and a drain region. Then, adjacent to the channel region, an LDD (Lightly Doped Drain) region containing phosphorus as an n-type impurity at a low concentration is formed.
  • LDD Lightly Doped Drain
  • a semiconductor layer forming step of forming a semiconductor layer on an insulating substrate and a gate insulating film forming step of forming a gate insulating film on the semiconductor layer A conductive layer forming step of forming a conductive layer on the gate insulating film, a mask forming step of forming a mask of a size corresponding to the low concentration region formed in the semiconductor layer on the conductive layer, and the mask
  • the mask reduction process for reducing the mask in accordance with the size of the gate electrode to be formed, and high concentration impurity ions in the semiconductor layer by self-alignment with the etched conductive layer In accordance with the etching process for dry etching the conductive layer, the mask reduction process for reducing the mask in accordance with the size of the gate electrode to be formed, and high concentration impurity ions in the semiconductor layer by self-alignment with the etched conductive layer.
  • the process until the film of the part to be etched is completely removed
  • the etching process (that is, the over-etching process) is performed for a little longer time.
  • the ratio of the dry etching selectivity gate insulating film etching rate: conductive layer etching rate
  • the gate electrode is formed by dry-etching the conductive layer in the gate electrode formation step, the gate insulating film is etched in a portion where the conductive layer does not exist in the above-described etching step, and the gate insulating film becomes extremely It will be thinner.
  • wet etching as the etching in the gate electrode formation step, but the surface of the conductive layer is altered in the high concentration ion implantation step in which high concentration impurity ions are implanted into the semiconductor layer. Therefore, if wet etching is performed after this high-concentration ion implantation step, variations in wet etching (that is, variations in the line width of the gate electrode) occur, and as a result, it becomes difficult to form a desired gate electrode by wet etching. There was a problem of becoming.
  • An object of the present invention is to provide a method for manufacturing a semiconductor device.
  • a method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device including an n-type thin film transistor having a semiconductor film on a substrate, and the semiconductor film is formed on the substrate.
  • the gate is formed by performing wet etching on the conductive layer after the n-type impurity implantation step. Even when the electrodes are formed, it is possible to suppress the occurrence of variations in wet etching due to the altered layer. Therefore, a desired gate electrode can be formed by wet etching. As a result, it is possible to form a desired LDD region in a self-aligned manner when forming an LDD region in the semiconductor film by implanting phosphorus, which is an n-type impurity, into the semiconductor film using the gate electrode as a mask. .
  • the gate electrode is formed by performing wet etching on the conductive layer instead of forming the gate electrode by dry etching. It is possible to prevent inconvenience that the gate insulating film becomes extremely thin due to etching. Therefore, the thickness of the gate insulating film can be controlled, and as a result, the occurrence of activation failure due to impurity doping failure can be suppressed.
  • the conductive layer can be etched in the etching step and the gate electrode formation step using the same resist as a mask. Become.
  • the etching in the etching step may be wet etching.
  • the resist functions as a protective layer for protecting the side surface of the conductive layer, and the n-type impurity is implanted into the side surface of the conductive layer. Since it becomes difficult, formation of a deteriorated layer can be suppressed in the n-type impurity implantation step. As a result, it is possible to suppress the deterioration of the conductive layer due to the implantation of the n-type impurity.
  • the etching of the gate insulating film in the etching process can be effectively suppressed. Therefore, since the thickness of the gate insulating film can be easily controlled, the doping conditions for doping impurities can be easily controlled in accordance with the thickness of the gate insulating film.
  • the conductive layer may include at least one selected from the group consisting of molybdenum, tungsten, and aluminum.
  • the semiconductor film may be formed of polysilicon in the semiconductor film forming step.
  • the p-type impurity may be boron and the n-type impurity may be phosphorus.
  • a method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device including an n-type thin film transistor having a first semiconductor film and a p-type thin film transistor having a second semiconductor film on a substrate, A semiconductor film forming step for forming the first semiconductor film and the second semiconductor film, a gate insulating film forming step for forming a gate insulating film on the first semiconductor film and the second semiconductor film, and a conductive layer on the gate insulating film Forming a first resist on the conductive layer and above the first semiconductor film, and forming a second resist on the conductive layer and above the second semiconductor film.
  • a second resist forming step of forming a fourth resist above the second semiconductor film, and masking the third resist and the fourth resist Then, by etching the conductive layer, the second gate electrode forming step for forming the gate electrode of the p-type thin film transistor, and the second resist film as a p-type with the third resist and the fourth resist as a mask.
  • At least a p-type impurity implantation step for forming a source region and a drain region in the second semiconductor film by implanting impurities is provided.
  • the gate electrode is formed by performing wet etching on the conductive layer after the n-type impurity implantation step. Even so, it is possible to suppress the variation in wet etching caused by the altered layer. Therefore, a desired gate electrode can be formed by wet etching.
  • a desired LDD region is formed in the first semiconductor film by implanting phosphorus, which is an n-type impurity, into the first semiconductor film using the gate electrode as a mask, a desired LDD region is formed in a self-aligned manner. Is possible.
  • the gate electrode is formed by performing wet etching on the conductive layer instead of forming the gate electrode by dry etching. It is possible to prevent inconvenience that the gate insulating film becomes extremely thin due to etching. Therefore, the thickness of the gate insulating film can be controlled, and as a result, the occurrence of activation failure due to impurity doping failure can be suppressed.
  • a method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device including an n-type thin film transistor having a first semiconductor film and a p-type thin film transistor having a second semiconductor film on a substrate, A semiconductor film forming step for forming the first semiconductor film and the second semiconductor film, a gate insulating film forming step for forming a gate insulating film on the first semiconductor film and the second semiconductor film, and a conductive layer on the gate insulating film Forming a first resist on the conductive layer and above the first semiconductor film, and forming a second resist on the conductive layer and above the second semiconductor film.
  • a first gate electrode type for forming a gate electrode of a p-type thin film transistor by etching the conductive layer using the first resist and the second resist as a mask. And after removing the first resist and the second resist, a p-type impurity is implanted into the second semiconductor film using the gate electrode formed in the first gate electrode forming process as a mask.
  • the resist forming step 2 the third resist and the fourth resist as a mask, wet etching is performed on the conductive layer, and the conductive layer is patterned, and the third resist and the fourth resist are used as a mask.
  • the gate electrode of the n-type thin film transistor is formed.
  • the gate electrode of the n-type thin film transistor is obtained by performing wet etching on the conductive layer after the n-type impurity implantation step. Even when the film is formed, it is possible to suppress the occurrence of variations in wet etching due to the deteriorated layer. Therefore, a desired gate electrode can be formed by wet etching. As a result, when the LDD region is formed in the first semiconductor film by implanting phosphorus, which is an n-type impurity, into the first semiconductor film using the gate electrode as a mask, a desired LDD region is formed in a self-aligned manner. Is possible.
  • the gate electrode of the n-type thin film transistor is not formed by dry etching, but the gate electrode of the n-type thin film transistor is formed by performing wet etching on the conductive layer. It is possible to prevent an inconvenience that the gate insulating film is etched in a portion that does not exist and the gate insulating film becomes extremely thin. Therefore, the thickness of the gate insulating film can be controlled, and as a result, the occurrence of activation failure due to impurity doping failure can be suppressed.
  • the side portion of the conductive layer where the altered layer is easily formed can be covered with the third resist formed on the conductive layer due to the side shift by wet etching. Therefore, even when the n-type impurity implantation step is performed after this wet etching step, the third resist functions as a protective layer for protecting the side surface of the conductive layer, and the n-type impurity is present on the side surface of the conductive layer. Since it becomes difficult to implant, the alteration of the conductive layer due to the implantation of the n-type impurity can be suppressed. As a result, it is possible to suppress the formation of the altered layer in the n-type impurity implantation step.
  • the etching of the gate insulating film in the etching process can be effectively suppressed. Therefore, since the thickness of the gate insulating film can be easily controlled, the doping conditions for doping impurities can be easily controlled in accordance with the thickness of the gate insulating film.
  • the p-type impurity implantation step can be performed after removing the first resist and the second resist. Therefore, since the resist surface is not hardened by the p-type impurity implantation step, the resist can be easily removed as compared with the case of removing the resist after the p-type impurity implantation.
  • an n-type thin film transistor having a desired LDD region can be formed in a self-aligned manner, and an activation failure due to an impurity doping failure based on a gate insulating film thickness failure occurs. Can be suppressed.
  • FIG. 1 is a cross-sectional view for explaining the configuration of a semiconductor device according to the first embodiment of the present invention.
  • the semiconductor device 1 includes an n-type TFT 3 having a semiconductor film 2.
  • the n-type TFT 3 functions as an active element of a drive circuit such as a gate driver or a source driver provided in the liquid crystal display device, for example.
  • the n-type TFT 3 has a top gate type structure in which a gate electrode 7 is disposed on the opposite side of the semiconductor film 2 from the glass substrate 6 side.
  • a base insulating film 10 composed of a first insulating film 8 made of a silicon nitride film or the like and a second insulating film 9 made of a silicon oxide film or the like is formed. .
  • the semiconductor film 2 is formed on the surface of the base insulating film 10 to a thickness of, for example, 50 nm.
  • the semiconductor film 2 is composed of, for example, a crystalline silicon film formed of polysilicon or the like.
  • the semiconductor film 2 includes phosphorus which is a high concentration n-type impurity in the source region 2a and the drain region 2b.
  • an LDD region 2d that is an impurity region containing phosphorus that is an n-type impurity is formed between the source region 2a and the drain region 2b and adjacent to the channel region 2c.
  • Two LDD regions 2d are formed as shown in FIG.
  • a gate insulating film 11 is formed on the semiconductor film 2 so as to cover the semiconductor film 2.
  • the gate insulating film 11 is made of, for example, silicon oxide.
  • a gate electrode 7 is formed on the channel region 2 c of the semiconductor film 2 with a gate insulating film 11 interposed therebetween.
  • the gate electrode 7 is made of, for example, molybdenum, tungsten, aluminum, or an alloy containing at least one of them.
  • an interlayer insulating film 12 is formed so as to cover the gate insulating film 11 and the gate electrode 7.
  • the interlayer insulating film 12 is made of, for example, silicon nitride.
  • the gate insulating film 11 and the interlayer insulating film 12 are formed to a thickness of 400 nm, for example.
  • contact holes 13 penetrating the gate insulating film 11 and the interlayer insulating film 12 are formed on the source region 2a and the drain region 2b, respectively. These contact holes 13 are filled with a conductive material such as molybdenum, tungsten, aluminum, or an alloy containing at least one of them, and the contact holes are formed on the interlayer insulating film 12. 13, a source electrode 14 connected to the source region 2 a and a drain electrode 15 connected to the drain region 2 b are formed. The source electrode 14 and the drain electrode 15 are formed with a thickness of, for example, 380 nm, and the source electrode 14 and the drain electrode 15 are formed of the conductive material.
  • 2 to 11 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • a base insulating film 10 constituted by a first insulating film 8 made of a silicon nitride film or the like and a second insulating film 9 made of a silicon oxide film or the like on one surface of a glass substrate 6. Is formed by, for example, a sputtering method or the like.
  • an amorphous silicon film 30 which is an amorphous silicon film is formed on the base insulating film 10 by, for example, a CVD method.
  • the amorphous silicon film 30 is irradiated with laser light 31 to crystallize the amorphous silicon film 30, and a polysilicon film (crystalline material) as a semiconductor film is formed on the glass substrate 6. Silicon film) 32 is formed.
  • an excimer laser such as XeCl (308 nm), XeF (351 nm), KrF (248 nm), or a solid laser can be used.
  • the viewpoint of reducing the surface roughness of the polysilicon film 32 it is preferable to remove the natural oxide film formed on the surface of the amorphous silicon film 30 before the laser beam 31 is irradiated. From the same viewpoint, it is preferable to use an inert atmosphere such as nitrogen as the atmosphere when the laser beam 31 is irradiated.
  • the polysilicon film 32 is patterned into an island shape by photolithography to form the semiconductor film 2 on the glass substrate 6.
  • a silicon oxide film or the like is formed on the entire substrate on which the semiconductor film 2 is formed by plasma CVD, and the gate insulating film 11 is formed to a thickness of about 100 nm.
  • boron as a p-type impurity may be implanted into the entire semiconductor film 2 as shown in FIG.
  • An arrow 39 shown in FIG. 5 indicates the direction in which boron is implanted.
  • an ion doping method or the like is used for boron implantation.
  • the acceleration voltage is set to 25 kV and the dose amount is set to 2 ⁇ 10 12 cm ⁇ 2 .
  • the conductive layer 35 for example, molybdenum, tungsten, aluminum, and an alloy containing at least one of them can be used.
  • a positive type type in which an exposed portion is dissolved and removed by development processing
  • photosensitive resin for example, acrylic
  • System photosensitive resin is applied to a thickness of about 1 to 3 ⁇ m.
  • the conductive layer 35 is etched and patterned by dry etching using the photoresist 40 as a mask.
  • phosphorus which is an n-type impurity (high concentration impurity)
  • An arrow 42 shown in FIG. 8 indicates a direction in which phosphorus is injected.
  • an ion doping method or the like is used for phosphorus implantation.
  • the acceleration voltage is set to 50 kV and the dose is set to 2 ⁇ 10 15 cm ⁇ 2 .
  • the source region 2a and the drain region 2b which are high-concentration impurity regions, are formed in the semiconductor film 2 included in the n-type TFT 3 by phosphorus implantation.
  • the side surface of the conductive layer 35 is altered and the altered layer 44 is formed. It is considered that the altered layer 44 is formed due to alteration of the surface of the conductive layer 35 due to impurity implantation in the n-type impurity implantation step.
  • the altered layer 44 formed on the conductive layer 35 is formed by the plasma etching as shown in FIG. Removed.
  • the etching gas used in the plasma etching includes fluorine-based gases such as CF 4 , NF 3 , SF 6 , and CHF 3 , chlorine-based gases such as Cl 2 , BCl 3 , SiCl 4 , and CCl 4 , and oxygen gas. Or an inert gas such as helium or argon may be added.
  • the altered layer 44 formed in the n-type impurity implantation step is removed by the above-described plasma etching. Therefore, even if wet etching is performed after the n-type impurity implantation step, the alteration layer 44 is changed. The occurrence of variations in wet etching due to the layer 44 can be suppressed. Therefore, the desired gate electrode 7 can be formed by wet etching.
  • a desired LDD region 2d (that is, a desired LDD region 2d) is formed when an LDD region 2d is formed in the semiconductor film 2 by implanting phosphorus, which is an n-type impurity, into the semiconductor film 2 by using the gate electrode 7 described later as a mask. It is possible to form a self-aligned LDD region having a length of
  • LDD is caused by side shift by wet etching (a phenomenon in which etching proceeds not only in a direction perpendicular to the conductive layer 35 but also in a parallel direction (the direction of the arrow X shown in FIG. 10)).
  • wet etching a phenomenon in which etching proceeds not only in a direction perpendicular to the conductive layer 35 but also in a parallel direction (the direction of the arrow X shown in FIG. 10).
  • the gate electrode 7 having an optimum width as a mask can be obtained in a self-aligning manner.
  • the gate electrode 7 is formed by wet etching the conductive layer instead of forming the gate electrode by dry etching. Therefore, it is possible to prevent the disadvantage that the gate insulating film 11 is etched in a portion where the conductive layer 35 does not exist and the gate insulating film 11 becomes extremely thin. Therefore, the thickness of the gate insulating film 11 can be controlled, and as a result, it is possible to suppress the occurrence of activation failure due to impurity doping failure.
  • ⁇ LDD region forming step> After removing the photoresist 40 by dry etching or the like, phosphorus as an n-type impurity is implanted into the semiconductor film 2 using the gate electrode 7 as a mask as shown in FIG. An arrow 46 shown in FIG. 11 indicates a direction in which phosphorus is injected. Note that an ion doping method or the like is used for phosphorus implantation. For example, the acceleration voltage is set to 80 kV and the dose is set to 2 ⁇ 10 13 cm ⁇ 2 . Then, by implantation of phosphorus, as shown in FIG.
  • the LDD region 2d is formed in the semiconductor film 2, and the semiconductor film 2 including the source region 2a, the drain region 2b, the channel region 2c, and the LDD region 2d is formed.
  • the n-type TFT 3 having the semiconductor film 2 is formed.
  • contact holes 13 penetrating the gate insulating film 11 and the interlayer insulating film 12 respectively on the source region 2a and the drain region 2b are formed, for example, Or by etching or the like.
  • the source electrode 14 and the drain electrode 15 are formed inside each contact hole 13 and on the interlayer insulating film 12.
  • the source electrode 14 and the drain electrode 15 are formed by, for example, photolithography and dry etching, and the source electrode 14 is connected to the source region 2a through the contact hole 13 and the drain electrode 15 is connected to the drain region 2b. To do.
  • the semiconductor device 1 shown in FIG. 1 is manufactured.
  • FIG. 12 to 13 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the second embodiment of the present invention. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
  • This embodiment is characterized in that the conductive layer 35 is etched by using wet etching instead of the dry etching step described in the first embodiment.
  • the etching of the conductive layer 35 is performed by wet etching as shown in FIG. I do.
  • FIG. 1 the side surface 35a of the conductive layer 35 on which the altered layer 44 has been formed is covered with the photoresist 40 (that is, hidden under the photoresist 40).
  • the photoresist 40 is formed on the conductive layer 35 as shown in FIG. It functions as a protective layer for protecting the side surface 35a, and n-type impurities are hardly implanted into the side surface 35a of the conductive layer 35. Therefore, alteration of the surface of the conductive layer 35 due to impurity implantation can be suppressed. As a result, formation of the altered layer 44 can be suppressed in the n-type impurity implantation step.
  • the etching of the gate insulating film 11 can be effectively suppressed during the etching process. Therefore, since the thickness of the gate insulating film 11 can be easily controlled, the doping conditions for doping impurities can be easily controlled according to the thickness of the gate insulating film 11.
  • a resist reduction step is performed in the same manner as in the first embodiment described above.
  • the resist reduction step is performed as in the first embodiment. Therefore, the altered layer 44 formed on the conductive layer 35 can be surely removed. Further, unlike the first embodiment, the formation of the deteriorated layer 44 can be effectively suppressed in the above-described wet etching process, so that the deteriorated layer 44 can be easily removed in the resist reduction process. .
  • the semiconductor device 1 shown in FIG. 1 is manufactured by performing the above-described gate electrode forming step, LDD region forming step, contact hole forming step, and source / drain electrode forming step.
  • FIG. 14 is a cross-sectional view for explaining the configuration of a semiconductor device according to the third embodiment of the present invention. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
  • the semiconductor device 50 in this embodiment includes a CMOS, and the CMOS includes an n-type TFT 3 having the semiconductor film 2 described above as a first semiconductor film, and a semiconductor film that is a second semiconductor film.
  • P-type TFT 5 having 4. That is, the semiconductor device 50 includes the n-type TFT 3 and the p-type TFT 5.
  • n-type TFT 3 and p-type TFT 5 function as active elements of a drive circuit such as a gate driver or a source driver provided in a liquid crystal display device, for example.
  • the n-type TFT 3 and the p-type TFT 5 have a top gate type structure in which a gate electrode 7 is disposed on the opposite side of the semiconductor film 2 and the semiconductor film 4 from the glass substrate 6 side.
  • the semiconductor film 2 and the semiconductor film 4 are formed with a thickness of, for example, 50 nm, and a predetermined gap is provided between the semiconductor film 2 and the semiconductor film 4. Is provided.
  • the semiconductor film 2 and the semiconductor film 4 are composed of, for example, a crystalline silicon film (semiconductor film) formed of polysilicon or the like.
  • the semiconductor film 2 contains phosphorus which is an n-type impurity in the source region 2a and the drain region 2b.
  • the semiconductor film 4 includes boron which is a p-type impurity in the source region 4a and the drain region 4b.
  • an LDD region 2d that is an impurity region containing phosphorus that is an n-type impurity is formed between the source region 2a and the drain region 2b and adjacent to the channel region 2c. As shown in FIG. 14, two LDD regions 2d are formed.
  • a gate insulating film 11 is formed on the semiconductor film 2 and the semiconductor film 4 so as to cover the semiconductor film 2 and the semiconductor film 4.
  • the gate insulating film 11 is made of, for example, silicon oxide.
  • a gate electrode 7 is formed on each of the channel regions 2c and 4c of the semiconductor film 2 and the semiconductor film 4 with a gate insulating film 11 interposed therebetween.
  • an interlayer insulating film 12 is formed so as to cover the gate insulating film 11 and the gate electrode 7.
  • the interlayer insulating film 12 is made of, for example, silicon nitride.
  • the gate insulating film 11 and the interlayer insulating film 12 are formed to a thickness of 400 nm, for example.
  • contact holes 13 penetrating the gate insulating film 11 and the interlayer insulating film 12 are formed on the source regions 2a and 4a and the drain regions 2b and 4b, respectively. These contact holes 13 are filled with a conductive material such as molybdenum, tungsten, aluminum, or an alloy containing at least one of them, and the contact holes are formed on the interlayer insulating film 12. 13, a source electrode 14 connected to the source regions 2a and 4a and a drain electrode 15 connected to the drain regions 2b and 4b are formed.
  • the source electrode 14 and the drain electrode 15 are formed with a thickness of, for example, 380 nm, and the source electrode 14 and the drain electrode 15 are formed of the conductive material.
  • 15 to 26 are sectional views for explaining a method for manufacturing a semiconductor device according to the third embodiment of the present invention.
  • a base insulating film 10 composed of a first insulating film 8 made of a silicon nitride film or the like and a second insulating film 9 made of a silicon oxide film or the like on one surface of a glass substrate 6. Is formed by, for example, a sputtering method or the like.
  • an amorphous silicon film 30 that is an amorphous silicon film is formed on the base insulating film 10 by, for example, a CVD method, Next, as shown in FIG.
  • the amorphous silicon film 30 is irradiated with a laser beam 31 to crystallize the amorphous silicon film 30, and a polysilicon film (crystal) that is a semiconductor film on the glass substrate 6.
  • a quality silicon film) 32 is formed.
  • the polysilicon film 32 is patterned into an island shape by photolithography to form the semiconductor film 2 and the semiconductor film 4 on the glass substrate 6.
  • a silicon oxide film or the like is formed on the entire substrate on which the semiconductor film 2 and the semiconductor film 4 are formed by a plasma CVD method, and the gate insulating film 11 has a thickness of about 100 nm. Form.
  • boron which is a p-type impurity, may be implanted into the entire semiconductor film 2 and the semiconductor film 4 as shown in FIG.
  • An arrow 33 shown in FIG. 18 indicates a direction in which boron is injected.
  • an ion doping method or the like is used for boron implantation.
  • the acceleration voltage is set to 25 kV and the dose amount is set to 2 ⁇ 10 12 cm ⁇ 2 .
  • a positive photosensitive resin for example, acrylic photosensitive resin
  • a photomask to control the exposure amount irradiated to the photosensitive resin to perform an exposure process, and by performing a development process on the photosensitive resin subjected to the exposure process, As shown in FIG. 20, a first photoresist 52 and a second photoresist 53 are formed simultaneously.
  • the first photoresist 52 is formed on the conductive layer 35 and above the semiconductor film 2
  • the second photoresist is formed on the conductive layer 35 and above the semiconductor film 4. 53 is formed.
  • the conductive layer 35 is etched by dry etching or the like using the first photoresist 52 and the second photoresist 53 as a mask. At this time, as shown in FIG. 20, only the conductive layer 35 to be the gate electrode 7 on the n-type TFT 3 side is patterned.
  • phosphorus which is an n-type impurity (high concentration impurity)
  • An arrow 43 shown in FIG. 21 indicates a direction in which phosphorus is injected.
  • an ion doping method or the like is used for phosphorus implantation.
  • the acceleration voltage is set to 50 kV and the dose is set to 2 ⁇ 10 15 cm ⁇ 2 .
  • the source region 2a and the drain region 2b which are high-concentration impurity regions, are formed in the semiconductor film 2 included in the n-type TFT 3 by implanting phosphorus.
  • the side surface of the conductive layer 35 is altered and the altered layer 44 is formed.
  • the altered layer 44 formed in the n-type impurity implantation step is removed by the above-described plasma etching. Therefore, even if wet etching is performed after the n-type impurity implantation step, the alteration layer 44 is changed. Generation of variations in wet etching (that is, variations in the width of the gate electrode 7) due to the layer 44 can be suppressed. Therefore, the desired gate electrode 7 can be formed by wet etching.
  • LDD is caused by a side shift by wet etching (a phenomenon in which etching proceeds not only in a direction perpendicular to the conductive layer 35 but also in a parallel direction (the direction of the arrow X shown in FIG. 23)).
  • wet etching a phenomenon in which etching proceeds not only in a direction perpendicular to the conductive layer 35 but also in a parallel direction (the direction of the arrow X shown in FIG. 23)
  • the gate electrode 7 having an optimum width as a mask can be obtained in a self-aligning manner.
  • the gate electrode 7 is formed by wet etching the conductive layer 35 instead of forming the gate electrode 7 by dry etching. Therefore, it is possible to prevent the disadvantage that the gate insulating film 11 is etched in a portion where the conductive layer 35 does not exist and the gate insulating film 11 becomes extremely thin. Therefore, the thickness of the gate insulating film 11 can be controlled, and as a result, it is possible to suppress the occurrence of activation failure due to impurity doping failure.
  • phosphorus as an n-type impurity is implanted into the semiconductor film 2 using the gate electrode 7 as a mask as shown in FIG.
  • An arrow 47 shown in FIG. 24 indicates the direction in which phosphorus is injected.
  • an ion doping method or the like is used for phosphorus implantation.
  • the acceleration voltage is set to 80 kV and the dose is set to 2 ⁇ 10 13 cm ⁇ 2 .
  • the dose is set to 2 ⁇ 10 13 cm ⁇ 2 .
  • the LDD region 2d is formed in the semiconductor film 2, and the semiconductor film 2 including the source region 2a, the drain region 2b, the channel region 2c, and the LDD region 2d is formed.
  • the n-type TFT 3 having the semiconductor film 2 is formed.
  • a positive photosensitive resin for example, an acrylic photosensitive resin
  • a thickness of 1 to 4 by spin coating so as to cover the semiconductor films 2 and 4. It is applied by applying to about 3 ⁇ m.
  • a photomask (not shown) to control the exposure amount irradiated to the photosensitive resin to perform an exposure process, and by performing a development process on the photosensitive resin subjected to the exposure process, A third photoresist 54 and a fourth photoresist 55 are formed simultaneously.
  • the third photoresist 54 is formed so as to cover the n-type TFT 3, and the fourth photoresist 55 is formed on the conductive layer 35 and above the semiconductor film 4.
  • ⁇ Second gate electrode formation step> the conductive layer 35 formed above the semiconductor film 4 is etched by wet etching using the third photoresist 54 and the fourth photoresist 55 as a mask, and the p-type TFT 5 is formed.
  • the gate electrode 7 to be configured is formed.
  • only the conductive layer 35 to be the gate electrode 7 on the p-type TFT 5 side is patterned.
  • boron which is a p-type impurity
  • An arrow 48 shown in FIG. 26 indicates a direction in which boron is injected.
  • ion doping or the like is used for boron implantation.
  • the acceleration voltage is set to 80 kV and the dose amount is set to 2 ⁇ 10 15 cm ⁇ 2 .
  • the source region 4a and the drain region 4b which are high-concentration impurity regions are formed in the semiconductor film 4 included in the p-type TFT 5 by boron implantation, and the p-type TFT 5 including the semiconductor film 4 is formed. Will be formed.
  • the source electrode 14 and the drain electrode 15 are formed inside each contact hole 13 and on the interlayer insulating film 12.
  • the source electrode 14 and the drain electrode 15 are formed by, for example, photolithography and dry etching, and the source electrode 14 is connected to the source regions 2a and 4a through the contact holes 13, and the drain electrode 15 is connected to the drain region 2b. , 4b.
  • the semiconductor device 50 shown in FIG. 14 is manufactured.
  • FIG. 27 to 33 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. Note that the same components as those in the first to third embodiments are denoted by the same reference numerals and description thereof is omitted.
  • the n-type TFT 3 is manufactured first in the manufacturing process of the semiconductor device 50.
  • the present embodiment is characterized in that the p-type TFT 5 is manufactured first.
  • a positive photosensitive resin for example, acrylic photosensitive resin
  • a photomask to control the exposure amount irradiated to the photosensitive resin to perform an exposure process, and by performing a development process on the photosensitive resin subjected to the exposure process, As shown in FIG. 27, a first photoresist 56 and a second photoresist 57 are formed simultaneously.
  • a first photoresist 56 is formed on the conductive layer 35 and above the semiconductor film 2, and a second photoresist 57 is formed on the conductive layer 35 and above the semiconductor film 4. .
  • the conductive layer 35 is etched by dry etching or the like using the first photoresist 56 and the second photoresist 57 as a mask to form the gate electrode 7 constituting the p-type TFT 5. .
  • the conductive layer 35 to be the gate electrode 7 on the p-type TFT 5 side is patterned.
  • boron as a p-type impurity is implanted into the semiconductor film 4 using the gate electrode 7 as a mask as shown in FIG.
  • An arrow 49 shown in FIG. 28 indicates the direction in which boron is injected.
  • ion doping or the like is used for boron implantation.
  • the acceleration voltage is set to 80 kV and the dose amount is set to 2 ⁇ 10 15 cm ⁇ 2 . Then, as shown in FIG.
  • the source region 4a and the drain region 4b which are high concentration impurity regions are formed in the semiconductor film 4 included in the p-type TFT 5 by boron implantation, and the p-type TFT 5 including the semiconductor film 4 is formed. It is formed.
  • the semiconductor film 2 constituting the n-type TFT 3 is covered with the conductive layer 35, it is not necessary to provide a photomask above the semiconductor film 2. . Therefore, the first photoresist 56 may be removed by peeling cleaning or the like, and ashing of the first photoresist 56 becomes unnecessary.
  • a positive photosensitive resin for example, an acrylic photosensitive resin
  • a photomask to control the exposure amount irradiated to the photosensitive resin to perform an exposure process, and by performing a development process on the photosensitive resin subjected to the exposure process, As shown in FIG. 29, a third photoresist 58 and a fourth photoresist 59 are formed simultaneously.
  • a third photoresist 58 is formed on the conductive layer 35 and above the semiconductor film 2, and a fourth photoresist 59 is formed so as to cover the p-type TFT 5.
  • FIG. 29 As shown, as in the case of the second embodiment described above, in the first embodiment, the side surface 35a of the conductive layer 35 on which the altered layer 44 has been formed is covered with a third photoresist 58 (third). (Hidden below the photoresist 58).
  • phosphorus which is an n-type impurity (high concentration impurity)
  • An arrow 70 shown in FIG. 30 indicates a direction in which phosphorus is injected.
  • an ion doping method or the like is used for phosphorus implantation.
  • the acceleration voltage is set to 50 kV and the dose is set to 2 ⁇ 10 15 cm ⁇ 2 .
  • the source region 2a and the drain region 2b which are high-concentration impurity regions, are formed in the semiconductor film 2 included in the n-type TFT 3 by phosphorus implantation.
  • the photoresist 58 functions as a protective layer that protects the side surface 35 a of the conductive layer 35, and n-type impurities are less likely to be injected into the side surface 35 a of the conductive layer 35. Therefore, the surface modification of the conductive layer 35 due to the impurity implantation can be suppressed. As a result, formation of the altered layer 44 can be suppressed in the n-type impurity implantation step.
  • the etching of the gate insulating film 11 can be effectively suppressed during the etching process. Therefore, since the thickness of the gate insulating film 11 can be easily controlled, the doping conditions for doping impurities can be easily controlled according to the thickness of the gate insulating film 11.
  • the formation of the deteriorated layer can be effectively suppressed in the above-described wet etching process, there is an advantage that the deteriorated layer can be easily removed in the resist reduction process.
  • ⁇ Second gate electrode formation step> wet etching is performed on the conductive layer 35 using the third photoresist 58 as a mask, thereby forming the gate electrode 7 constituting the n-type TFT 3 as shown in FIG.
  • the altered layer 44 formed in the n-type impurity implantation step is removed by the above-described plasma etching. Therefore, even if wet etching is performed after the n-type impurity implantation step, the alteration layer 44 is changed. Generation of variations in wet etching (that is, variations in the width of the gate electrode 7) due to the layer 44 can be suppressed. Therefore, the desired gate electrode 7 can be formed by wet etching.
  • LDD is caused by side shift by wet etching (a phenomenon in which etching proceeds not only in a direction perpendicular to the conductive layer 35 but also in a parallel direction (the direction of the arrow X shown in FIG. 32)).
  • the gate electrode 7 having an optimum width as a mask can be obtained in a self-aligning manner.
  • the gate electrode 7 is formed by wet etching the conductive layer 35 instead of forming the gate electrode 7 by dry etching. Therefore, it is possible to prevent the disadvantage that the gate insulating film 11 is etched in a portion where the conductive layer 35 does not exist and the gate insulating film 11 becomes extremely thin. Therefore, the thickness of the gate insulating film 11 can be controlled, and as a result, it is possible to suppress the occurrence of activation failure due to impurity doping failure.
  • phosphorus as an n-type impurity is implanted into the semiconductor film 2 using the gate electrode 7 as a mask as shown in FIG.
  • An arrow 71 shown in FIG. 33 indicates the direction in which phosphorus is injected.
  • an ion doping method or the like is used for phosphorus implantation.
  • the acceleration voltage is set to 80 kV and the dose is set to 2 ⁇ 10 13 cm ⁇ 2 .
  • the dose is set to 2 ⁇ 10 13 cm ⁇ 2 .
  • the LDD region 2d is formed in the semiconductor film 2, and the semiconductor film 2 including the source region 2a, the drain region 2b, the channel region 2c, and the LDD region 2d is formed. At the same time, the n-type TFT 3 including the semiconductor film 2 is formed.
  • the source electrode 14 and the drain electrode 15 are formed inside each contact hole 13 and on the interlayer insulating film 12.
  • the source electrode 14 and the drain electrode 15 are formed by, for example, photolithography and dry etching, and the source electrode 14 is connected to the source regions 2a and 4a through the contact holes 13, and the drain electrode 15 is connected to the drain region 2b. , 4b.
  • the semiconductor device 50 shown in FIG. 14 is manufactured.
  • a method for manufacturing a semiconductor device provided with a switching element such as a thin film transistor there is a method for manufacturing a semiconductor device provided with a switching element such as a thin film transistor.

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Abstract

A method for manufacturing a semiconductor device comprises: a step of patterning a conductive layer (35), using the photoresist (40) as a mask; a step of forming a source region (2a) and a drain region (2b) on a semiconductor film (2) by injection of n-type impurity, using the photoresist (40) as a mask; a resist reduction step of reducing a photoresist (40) isotropically by performing plasma etching; a step of forming a gate electrode (7) by performing wet etching of the conductive layer (35), using the photoresist (40) as a mask; and a step of forming an LDD region (2d) on a semiconductor film (2) by injection of n-type impurity, using the gate electrode (7) as a mask.

Description

半導体装置の製造方法Manufacturing method of semiconductor device
　本発明は、半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device.
　近年、液晶表示装置は、例えば、パーソナルコンピュータ用の表示装置やテレビとして一般的に使用されている。さらに、液晶表示装置は、ＰＤＡ（Personal Digital Assistant）等の表示装置としても広く使用されている。また、液晶表示装置よりも省電力化が可能な有機ＥＬ表示装置についても研究開発が行われており、一部の製品では既に実用化されている。 In recent years, liquid crystal display devices are generally used as display devices for personal computers and televisions, for example. Furthermore, the liquid crystal display device is widely used as a display device such as a PDA (Personal Digital Assistant). Research and development have also been conducted on organic EL display devices that can save more power than liquid crystal display devices, and some products have already been put into practical use.
　これら液晶表示装置及び有機ＥＬ表示装置は、その駆動方法の違いにより、パッシブマトリクス方式とアクティブマトリクス方式とに大別される。特に、アクティブマトリクス方式は、パッシブマトリクス方式に比べて、高速応答及び低電圧駆動が可能であることから、研究開発が盛んに行われている。 These liquid crystal display devices and organic EL display devices are roughly classified into a passive matrix method and an active matrix method depending on the driving method. In particular, the active matrix method is actively researched and developed because it can respond faster and drive at a lower voltage than the passive matrix method.
　アクティブマトリクス方式の表示装置には、通常、複数の画素がマトリクス状に形成されており、各画素には、スイッチング素子である薄膜トランジスタ（Thin Film Transistor、以下、ＴＦＴともいう。）が設けられている。 In an active matrix display device, a plurality of pixels are usually formed in a matrix, and each pixel is provided with a thin film transistor (hereinafter also referred to as TFT) which is a switching element. .
　ＴＦＴは、絶縁性を有する基板上に形成された半導体膜と、半導体膜上に形成されたゲート絶縁膜と、ゲート絶縁膜上に形成されたゲート電極とを備えている。なお、ボトムゲート型のＴＦＴの場合には、ゲート電極と半導体膜との位置が逆に形成されている。 The TFT includes a semiconductor film formed on an insulating substrate, a gate insulating film formed on the semiconductor film, and a gate electrode formed on the gate insulating film. Note that in the case of a bottom gate TFT, the positions of the gate electrode and the semiconductor film are reversed.
　この半導体膜をアモルファスシリコンにより形成する場合には、アモルファスシリコンのキャリアの移動度が比較的小さいため、表示パネルの外側に表示装置駆動用のＩＣ（Integrated Circuit）を接続し、この駆動用ＩＣによって表示装置を駆動する必要がある。 When this semiconductor film is formed of amorphous silicon, the carrier mobility of amorphous silicon is relatively small. Therefore, an IC for driving a display device (Integrated Circuit) is connected to the outside of the display panel. It is necessary to drive the display device.
　これに対して、半導体膜をポリシリコンにより形成する場合には、ポリシリコンのキャリアの移動度が比較的大きいので、ＴＦＴで構成した駆動回路を表示パネルに一体的に作り込むことが可能になる。 On the other hand, when the semiconductor film is formed of polysilicon, the mobility of polysilicon carriers is relatively large, so that a driving circuit composed of TFTs can be integrally formed in the display panel. .
　ポリシリコンにより形成された半導体膜には、ゲート電極をマスクとしてｐ型不純物、又はｎ型不純物が注入された一対の高濃度不純物領域であるソース領域及びドレイン領域が形成されている。 In the semiconductor film formed of polysilicon, a source region and a drain region, which are a pair of high-concentration impurity regions into which p-type impurities or n-type impurities are implanted, are formed using the gate electrode as a mask.
　また、一般に、ｎチャネル型の薄膜トランジスタを形成する場合は、リーク電流（オフ電流）が生じて、消費電力が大きくなる等の不都合を防止するために、半導体膜において、ソース領域とドレイン領域の間であって、チャネル領域に隣接して、ｎ型不純物であるリンが低濃度で含まれるＬＤＤ（Lightly Doped Drain）領域が形成される。 In general, when an n-channel thin film transistor is formed, a leakage current (off-state current) is generated, and in order to prevent inconvenience such as an increase in power consumption, a semiconductor film is provided between a source region and a drain region. Then, adjacent to the channel region, an LDD (Lightly Doped Drain) region containing phosphorus as an n-type impurity at a low concentration is formed.
　そして、このようなＬＤＤ領域を有する半導体膜を形成する方法として、例えば、絶縁基板上に半導体層を形成する半導体層形成工程と、この半導体層上にゲート絶縁膜を形成するゲート絶縁膜形成工程と、このゲート絶縁膜上に導電層を形成する導電層形成工程と、この導電層上に半導体層に形成される低濃度領域に対応した大きさのマスクを形成するマスク形成工程と、このマスクに従い導電層をドライエッチングするエッチング工程と、形成するゲート電極の大きさに対応させてマスクを縮小するマスク縮小工程と、エッチングされた導電層に自己整合させて半導体層に高濃度の不純物イオンを注入する高濃度イオン注入工程と、縮小されたマスクにより導電層をドライエッチングしてゲート電極を形成するゲート電極形成工程と、この形成されたゲート電極に自己整合させて半導体層に低濃度の不純物イオンを注入してＬＤＤ領域を形成する低濃度イオン注入工程とを備えた方法が提案されている（例えば、特許文献１参照）。 As a method of forming a semiconductor film having such an LDD region, for example, a semiconductor layer forming step of forming a semiconductor layer on an insulating substrate and a gate insulating film forming step of forming a gate insulating film on the semiconductor layer A conductive layer forming step of forming a conductive layer on the gate insulating film, a mask forming step of forming a mask of a size corresponding to the low concentration region formed in the semiconductor layer on the conductive layer, and the mask In accordance with the etching process for dry etching the conductive layer, the mask reduction process for reducing the mask in accordance with the size of the gate electrode to be formed, and high concentration impurity ions in the semiconductor layer by self-alignment with the etched conductive layer. A high-concentration ion implantation step for implanting, and a gate electrode formation step for dry-etching the conductive layer with a reduced mask to form a gate electrode; And a low-concentration ion implantation process in which an LDD region is formed by implanting low-concentration impurity ions into a semiconductor layer in a self-aligned manner with the gate electrode formed (see, for example, Patent Document 1). ).
特開２００１－３３２７３３号公報JP 2001-332733 A
　ここで、上記従来の製造方法においては、マスクに従い導電層をドライエッチングするエッチング工程において、導電層の膜残りによる不良を抑制するために、エッチングする部分の膜が完全に除去されるまでの処理時間よりも少し長い時間、エッチング処理（即ち、オーバーエッチング処理）を行う。しかし、導電層として比較的安価な材料、例えば、モリブデン、タングステンを用いた合金やアルミニウムを用いた合金の場合、ドライエッチングの選択比（ゲート絶縁膜のエッチングレート：導電層のエッチングレート）の比率が小さくなるため、エッチング処理の際にゲート絶縁膜がエッチングされてしまう場合がある。 Here, in the above conventional manufacturing method, in the etching process of dry etching the conductive layer according to the mask, in order to suppress the defect due to the film residue of the conductive layer, the process until the film of the part to be etched is completely removed The etching process (that is, the over-etching process) is performed for a little longer time. However, in the case of a relatively inexpensive material for the conductive layer, for example, an alloy using molybdenum or tungsten or an alloy using aluminum, the ratio of the dry etching selectivity (gate insulating film etching rate: conductive layer etching rate) Therefore, the gate insulating film may be etched during the etching process.
　また、ゲート電極形成工程において、導電層をドライエッチングしてゲート電極を形成するため、上述のエッチング工程において、導電層が存在しない部分でゲート絶縁膜がエッチングされてしまい、ゲート絶縁膜が極端に薄くなってしまう。 In addition, since the gate electrode is formed by dry-etching the conductive layer in the gate electrode formation step, the gate insulating film is etched in a portion where the conductive layer does not exist in the above-described etching step, and the gate insulating film becomes extremely It will be thinner.
　従って、上記従来の製造方法においては、ゲート絶縁膜の膜厚の制御が困難になるため、ゲート絶縁膜の膜厚に対応させて、不純物をドーピングする際のドーピング条件を変化させなければならなくなり、結果として、活性化不良等が生じるという問題があった。 Therefore, in the above-described conventional manufacturing method, it becomes difficult to control the thickness of the gate insulating film. Therefore, the doping conditions for doping impurities must be changed according to the thickness of the gate insulating film. As a result, there is a problem that activation failure occurs.
　また、ゲート電極形成工程のエッチングとしてウェットエッチングを使用することも考えられるが、半導体層に高濃度の不純物イオンを注入する高濃度イオン注入工程において、導電層の表面が変質する。従って、この高濃度イオン注入工程後にウェットエッチングを行うと、ウェットエッチングにバラツキ（即ち、ゲート電極の線幅のバラツキ）が生じてしまい、結果として、ウェットエッチングにより所望のゲート電極の形成が困難になるという問題があった。 Also, it is conceivable to use wet etching as the etching in the gate electrode formation step, but the surface of the conductive layer is altered in the high concentration ion implantation step in which high concentration impurity ions are implanted into the semiconductor layer. Therefore, if wet etching is performed after this high-concentration ion implantation step, variations in wet etching (that is, variations in the line width of the gate electrode) occur, and as a result, it becomes difficult to form a desired gate electrode by wet etching. There was a problem of becoming.
　そこで、本発明は、上述の問題に鑑みてなされたものであり、ゲート絶縁膜の膜厚を制御して、エッチングにより所望のゲート電極とゲート電極に自己整合させてＬＤＤ領域を形成することができる半導体装置の製造方法を提供することを目的とする。 Therefore, the present invention has been made in view of the above-described problems, and it is possible to form an LDD region by controlling the film thickness of a gate insulating film and self-aligning a desired gate electrode with the gate electrode by etching. An object of the present invention is to provide a method for manufacturing a semiconductor device.
　上記の目的を達成するために、本発明の半導体装置の製造方法は、半導体膜を有するｎ型薄膜トランジスタを基板上に備える半導体装置を製造する方法であって、基板上に、半導体膜を形成する半導体膜形成工程と、半導体膜上にゲート絶縁膜を形成するゲート絶縁膜形成工程と、ゲート絶縁膜上に導電層を形成する導電層形成工程と、導電層上にレジストを形成するレジスト形成工程と、レジストをマスクとして、導電層に対してエッチングを行い、導電層をパターニングするエッチング工程と、レジストをマスクとして、半導体膜にｎ型不純物を注入して、半導体膜にソース領域とドレイン領域を形成するｎ型不純物注入工程と、プラズマエッチングを行うことにより、レジストを等方的に縮小するレジスト縮小工程と、縮小したレジストをマスクとして、導電層に対してウェットエッチングを行うことにより、ゲート電極を形成するゲート電極形成工程と、ゲート電極をマスクとして、半導体膜にｎ型不純物を注入して、半導体膜にＬＤＤ領域を形成するＬＤＤ領域形成工程とを少なくとも備えることを特徴とする。 In order to achieve the above object, a method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device including an n-type thin film transistor having a semiconductor film on a substrate, and the semiconductor film is formed on the substrate. Semiconductor film forming step, gate insulating film forming step for forming a gate insulating film on the semiconductor film, conductive layer forming step for forming a conductive layer on the gate insulating film, and resist forming step for forming a resist on the conductive layer And etching the conductive layer using the resist as a mask and patterning the conductive layer, and using the resist as a mask, implanting an n-type impurity into the semiconductor film, and forming a source region and a drain region in the semiconductor film An n-type impurity implantation step to be formed, a resist reduction step for isotropically reducing the resist by performing plasma etching, and a reduced resist A gate electrode forming step of forming a gate electrode by performing wet etching on the conductive layer using the gate as a mask, and implanting an n-type impurity into the semiconductor film using the gate electrode as a mask, thereby forming an LDD region in the semiconductor film. At least an LDD region forming step of forming.
　同構成によれば、レジスト縮小工程において、ｎ型不純物注入工程において形成された変質層が、プラズマエッチングにより除去されるため、ｎ型不純物注入工程後に導電層に対してウェットエッチングを行うことによりゲート電極を形成する場合であっても、変質層に起因するウェットエッチングのバラツキの発生を抑制することができる。従って、ウェットエッチングにより、所望のゲート電極の形成が可能になる。その結果、ゲート電極をマスクとして、半導体膜にｎ型不純物であるリンを注入して、半導体膜にＬＤＤ領域を形成する際に、所望のＬＤＤ領域を自己整合的に形成することが可能になる。 According to this configuration, since the altered layer formed in the n-type impurity implantation step is removed by plasma etching in the resist reduction step, the gate is formed by performing wet etching on the conductive layer after the n-type impurity implantation step. Even when the electrodes are formed, it is possible to suppress the occurrence of variations in wet etching due to the altered layer. Therefore, a desired gate electrode can be formed by wet etching. As a result, it is possible to form a desired LDD region in a self-aligned manner when forming an LDD region in the semiconductor film by implanting phosphorus, which is an n-type impurity, into the semiconductor film using the gate electrode as a mask. .
　また、上記従来技術とは異なり、ドライエッチングによりゲート電極を形成するのではなく、導電層に対してウェットエッチングを行うことによりゲート電極を形成するため、導電層が存在しない部分でゲート絶縁膜がエッチングされてしまい、ゲート絶縁膜が極端に薄くなってしまうという不都合の発生を防止することができる。従って、ゲート絶縁膜の膜厚を制御することができるため、結果として、不純物のドーピング不良に起因する活性化不良の発生を抑制することができる。 In addition, unlike the above-described prior art, the gate electrode is formed by performing wet etching on the conductive layer instead of forming the gate electrode by dry etching. It is possible to prevent inconvenience that the gate insulating film becomes extremely thin due to etching. Therefore, the thickness of the gate insulating film can be controlled, and as a result, the occurrence of activation failure due to impurity doping failure can be suppressed.
　また、プラズマエッチングを行うことにより、レジストを等方的に縮小するため、同一のレジストをマスクとして使用して、エッチング工程及びゲート電極形成工程において、導電層に対してエッチングを行うことが可能になる。 Since the resist is isotropically reduced by performing plasma etching, the conductive layer can be etched in the etching step and the gate electrode formation step using the same resist as a mask. Become.
　本発明の半導体装置の製造方法においては、エッチング工程におけるエッチングが、ウェットエッチングであってもよい。 In the method for manufacturing a semiconductor device of the present invention, the etching in the etching step may be wet etching.
　同構成によれば、ウェットエッチングによるサイドシフトにより、変質層が形成され易い導電層の側面の部分を、導電層上に形成されたレジストにより覆うことが可能になる。従って、このウェットエッチング工程の後、ｎ型不純物注入工程を行った場合であっても、レジストが、導電層の側面を保護する保護層として機能し、導電層の側面にｎ型不純物が注入されにくくなるため、ｎ型不純物注入工程において変質層の形成を抑制することが可能になる。その結果、ｎ型不純物の注入に起因する導電層の変質を抑制することが可能になる。 According to this configuration, it is possible to cover the side portion of the conductive layer where the altered layer is easily formed by the side shift by wet etching with the resist formed on the conductive layer. Therefore, even if the n-type impurity implantation step is performed after this wet etching step, the resist functions as a protective layer for protecting the side surface of the conductive layer, and the n-type impurity is implanted into the side surface of the conductive layer. Since it becomes difficult, formation of a deteriorated layer can be suppressed in the n-type impurity implantation step. As a result, it is possible to suppress the deterioration of the conductive layer due to the implantation of the n-type impurity.
　また、エッチング工程において、導電層のドライエッチングを行わないため、エッチング工程におけるゲート絶縁膜のエッチングを効果的に抑制することができる。従って、ゲート絶縁膜の膜厚の制御が容易になるため、ゲート絶縁膜の膜厚に対応させて、不純物をドーピングする際のドーピング条件を制御しやすくなる。 In addition, since the conductive layer is not dry-etched in the etching process, the etching of the gate insulating film in the etching process can be effectively suppressed. Therefore, since the thickness of the gate insulating film can be easily controlled, the doping conditions for doping impurities can be easily controlled in accordance with the thickness of the gate insulating film.
　本発明の半導体装置の製造方法においては、導電層が、モリブデン、タングステン、及びアルミニウムからなる群より選ばれる少なくとも１種を含む構成としてもよい。 In the method for manufacturing a semiconductor device of the present invention, the conductive layer may include at least one selected from the group consisting of molybdenum, tungsten, and aluminum.
　本発明の半導体装置の製造方法においては、半導体膜形成工程において、ポリシリコンにより半導体膜を形成する構成としてもよい。 In the method of manufacturing a semiconductor device of the present invention, the semiconductor film may be formed of polysilicon in the semiconductor film forming step.
　本発明の半導体装置の製造方法においては、ｐ型不純物がボロンであり、ｎ型不純物がリンであってもよい。 In the method for manufacturing a semiconductor device of the present invention, the p-type impurity may be boron and the n-type impurity may be phosphorus.
　本発明の半導体装置の製造方法は、第１半導体膜を有するｎ型薄膜トランジスタと、第２半導体膜を有するｐ型薄膜トランジスタとを基板上に備える半導体装置を製造する方法であって、基板上に、第１半導体膜及び第２半導体膜を形成する半導体膜形成工程と、第１半導体膜上及び第２半導体膜上にゲート絶縁膜を形成するゲート絶縁膜形成工程と、ゲート絶縁膜上に導電層を形成する導電層形成工程と、導電層上であって第１半導体膜の上方に第１レジストを形成するとともに、導電層上であって第２半導体膜の上方に第２レジストを形成する第１のレジスト形成工程と、第１レジスト及び第２レジストをマスクとして、導電層に対してエッチングを行い、導電層をパターニングするエッチング工程と、第１レジスト及び第２レジストをマスクとして、第１半導体膜にｎ型不純物を注入して、第１半導体膜にソース領域とドレイン領域を形成するｎ型不純物注入工程と、プラズマエッチングを行うことにより、第１レジストを等方的に縮小するレジスト縮小工程と、縮小した第１レジストをマスクとして、導電層に対してウェットエッチングを行うことにより、ｎ型薄膜トランジスタのゲート電極を形成する第１のゲート電極形成工程と、ゲート電極をマスクとして、第１半導体膜にｎ型不純物を注入して、第１半導体膜にＬＤＤ領域を形成するＬＤＤ領域形成工程と、ｎ型薄膜トランジスタを覆うように第３レジストを形成するとともに、導電層上であって第２半導体膜の上方に第４レジストを形成する第２のレジスト形成工程と、第３レジスト及び第４レジストをマスクとして、導電層に対してエッチングを行うことにより、ｐ型薄膜トランジスタのゲート電極を形成する第２のゲート電極形成工程と、第３レジスト及び第４レジストをマスクとして、第２半導体膜にｐ型不純物を注入して、第２半導体膜にソース領域とドレイン領域を形成するｐ型不純物注入工程とを少なくとも備えることを特徴とする。 A method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device including an n-type thin film transistor having a first semiconductor film and a p-type thin film transistor having a second semiconductor film on a substrate, A semiconductor film forming step for forming the first semiconductor film and the second semiconductor film, a gate insulating film forming step for forming a gate insulating film on the first semiconductor film and the second semiconductor film, and a conductive layer on the gate insulating film Forming a first resist on the conductive layer and above the first semiconductor film, and forming a second resist on the conductive layer and above the second semiconductor film. 1 resist forming step, an etching step of etching the conductive layer using the first resist and the second resist as a mask, and patterning the conductive layer, and the first resist and the second resist As a mask, an n-type impurity is implanted into the first semiconductor film, an n-type impurity implantation step for forming a source region and a drain region in the first semiconductor film, and plasma etching are performed to make the first resist isotropic. A first step of forming a gate electrode of an n-type thin film transistor by performing wet etching on the conductive layer using the reduced first resist as a mask, As a mask, an n-type impurity is implanted into the first semiconductor film to form an LDD region in the first semiconductor film, a third resist is formed so as to cover the n-type thin film transistor, and the conductive layer is formed on the conductive layer. A second resist forming step of forming a fourth resist above the second semiconductor film, and masking the third resist and the fourth resist Then, by etching the conductive layer, the second gate electrode forming step for forming the gate electrode of the p-type thin film transistor, and the second resist film as a p-type with the third resist and the fourth resist as a mask. At least a p-type impurity implantation step for forming a source region and a drain region in the second semiconductor film by implanting impurities is provided.
　同構成によれば、ｎ型不純物注入工程において形成された変質層が、プラズマエッチングにより除去されるため、ｎ型不純物注入工程後に導電層に対してウェットエッチングを行うことによりゲート電極を形成する場合であっても、変質層に起因するウェットエッチングのバラツキの発生を抑制することができる。従って、ウェットエッチングにより、所望のゲート電極の形成が可能になる。その結果、ゲート電極をマスクとして、第１半導体膜にｎ型不純物であるリンを注入して、第１半導体膜にＬＤＤ領域を形成する際に、所望のＬＤＤ領域を自己整合的に形成することが可能になる。 According to this configuration, since the altered layer formed in the n-type impurity implantation step is removed by plasma etching, the gate electrode is formed by performing wet etching on the conductive layer after the n-type impurity implantation step. Even so, it is possible to suppress the variation in wet etching caused by the altered layer. Therefore, a desired gate electrode can be formed by wet etching. As a result, when the LDD region is formed in the first semiconductor film by implanting phosphorus, which is an n-type impurity, into the first semiconductor film using the gate electrode as a mask, a desired LDD region is formed in a self-aligned manner. Is possible.
　また、上記従来技術とは異なり、ドライエッチングによりゲート電極を形成するのではなく、導電層に対してウェットエッチングを行うことによりゲート電極を形成するため、導電層が存在しない部分でゲート絶縁膜がエッチングされてしまい、ゲート絶縁膜が極端に薄くなってしまうという不都合の発生を防止することができる。従って、ゲート絶縁膜の膜厚を制御することができるため、結果として、不純物のドーピング不良に起因する活性化不良の発生を抑制することができる。 In addition, unlike the above-described prior art, the gate electrode is formed by performing wet etching on the conductive layer instead of forming the gate electrode by dry etching. It is possible to prevent inconvenience that the gate insulating film becomes extremely thin due to etching. Therefore, the thickness of the gate insulating film can be controlled, and as a result, the occurrence of activation failure due to impurity doping failure can be suppressed.
　本発明の半導体装置の製造方法は、第１半導体膜を有するｎ型薄膜トランジスタと、第２半導体膜を有するｐ型薄膜トランジスタとを基板上に備える半導体装置を製造する方法であって、基板上に、第１半導体膜及び第２半導体膜を形成する半導体膜形成工程と、第１半導体膜上及び第２半導体膜上にゲート絶縁膜を形成するゲート絶縁膜形成工程と、ゲート絶縁膜上に導電層を形成する導電層形成工程と、導電層上であって第１半導体膜の上方に第１レジストを形成するとともに、導電層上であって第２半導体膜の上方に第２レジストを形成する第１のレジスト形成工程と、第１レジスト及び第２レジストをマスクとして、導電層に対してエッチングを行うことにより、ｐ型薄膜トランジスタのゲート電極を形成する第１のゲート電極形成工程と、第１レジスト及び第２レジストを除去した後、第１のゲート電極形成工程により形成されたゲート電極をマスクとして、第２半導体膜にｐ型不純物を注入して、第２半導体膜にソース領域とドレイン領域を形成するｐ型不純物注入工程と、導電層上であって第１半導体膜の上方に第３レジストを形成するとともに、ｐ型薄膜トランジスタを覆うように第４レジストを形成する第２のレジスト形成工程と、第３レジスト及び第４レジストをマスクとして、導電層に対してウェットエッチングを行い、導電層をパターニングするエッチング工程と、第３レジスト及び第４レジストをマスクとして、第１半導体膜にｎ型不純物を注入して、第１半導体膜にソース領域とドレイン領域を形成するｎ型不純物注入工程と、プラズマエッチングを行うことにより、第３レジストを等方的に縮小するレジスト縮小工程と、縮小した第３レジストをマスクとして、導電層に対してウェットエッチングを行うことにより、ｎ型薄膜トランジスタのゲート電極を形成する第２のゲート電極形成工程と、第２のゲート電極形成工程により形成されたゲート電極をマスクとして、第１半導体膜にｎ型不純物を注入して、第１半導体膜にＬＤＤ領域を形成するＬＤＤ領域形成工程とを少なくとも備えることを特徴とする。 A method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device including an n-type thin film transistor having a first semiconductor film and a p-type thin film transistor having a second semiconductor film on a substrate, A semiconductor film forming step for forming the first semiconductor film and the second semiconductor film, a gate insulating film forming step for forming a gate insulating film on the first semiconductor film and the second semiconductor film, and a conductive layer on the gate insulating film Forming a first resist on the conductive layer and above the first semiconductor film, and forming a second resist on the conductive layer and above the second semiconductor film. 1 and a first gate electrode type for forming a gate electrode of a p-type thin film transistor by etching the conductive layer using the first resist and the second resist as a mask. And after removing the first resist and the second resist, a p-type impurity is implanted into the second semiconductor film using the gate electrode formed in the first gate electrode forming process as a mask. A p-type impurity implantation step for forming a source region and a drain region; a third resist is formed on the conductive layer and above the first semiconductor film; and a fourth resist is formed to cover the p-type thin film transistor The resist forming step 2, the third resist and the fourth resist as a mask, wet etching is performed on the conductive layer, and the conductive layer is patterned, and the third resist and the fourth resist are used as a mask. An n-type impurity implantation step of implanting an n-type impurity into the semiconductor film to form a source region and a drain region in the first semiconductor film; and plasma etching By performing the resist reduction process for isotropically reducing the third resist, and performing the wet etching on the conductive layer using the reduced third resist as a mask, the gate electrode of the n-type thin film transistor is formed. An LDD region for forming an LDD region in the first semiconductor film by implanting an n-type impurity into the first semiconductor film using the gate electrode formed in the second gate electrode forming step and the second gate electrode forming step as a mask And a forming step.
　同構成によれば、ｎ型不純物注入工程において形成された変質層が、プラズマエッチングにより除去されるため、ｎ型不純物注入工程後に導電層に対してウェットエッチングを行うことによりｎ型薄膜トランジスタのゲート電極を形成する場合であっても、変質層に起因するウェットエッチングのバラツキの発生を抑制することができる。従って、ウェットエッチングにより、所望のゲート電極の形成が可能になる。その結果、ゲート電極をマスクとして、第１半導体膜にｎ型不純物であるリンを注入して、第１半導体膜にＬＤＤ領域を形成する際に、所望のＬＤＤ領域を自己整合的に形成することが可能になる。 According to this configuration, since the altered layer formed in the n-type impurity implantation step is removed by plasma etching, the gate electrode of the n-type thin film transistor is obtained by performing wet etching on the conductive layer after the n-type impurity implantation step. Even when the film is formed, it is possible to suppress the occurrence of variations in wet etching due to the deteriorated layer. Therefore, a desired gate electrode can be formed by wet etching. As a result, when the LDD region is formed in the first semiconductor film by implanting phosphorus, which is an n-type impurity, into the first semiconductor film using the gate electrode as a mask, a desired LDD region is formed in a self-aligned manner. Is possible.
　また、上記従来技術とは異なり、ドライエッチングによりｎ型薄膜トランジスタのゲート電極を形成するのではなく、導電層に対してウェットエッチングを行うことによりｎ型薄膜トランジスタのゲート電極を形成するため、導電層が存在しない部分でゲート絶縁膜がエッチングされてしまい、ゲート絶縁膜が極端に薄くなってしまうという不都合の発生を防止することができる。従って、ゲート絶縁膜の膜厚を制御することができるため、結果として、不純物のドーピング不良に起因する活性化不良の発生を抑制することができる。 In addition, unlike the conventional technique, the gate electrode of the n-type thin film transistor is not formed by dry etching, but the gate electrode of the n-type thin film transistor is formed by performing wet etching on the conductive layer. It is possible to prevent an inconvenience that the gate insulating film is etched in a portion that does not exist and the gate insulating film becomes extremely thin. Therefore, the thickness of the gate insulating film can be controlled, and as a result, the occurrence of activation failure due to impurity doping failure can be suppressed.
　また、エッチング工程において、ウェットエッチングによるサイドシフトにより、変質層が形成され易い導電層の側面の部分を、導電層上に形成された第３レジストにより覆うことが可能になる。従って、このウェットエッチング工程の後、ｎ型不純物注入工程を行った場合であっても、第３レジストが、導電層の側面を保護する保護層として機能し、導電層の側面にｎ型不純物が注入されにくくなるため、ｎ型不純物の注入に起因する導電層の変質を抑制することが可能になる。その結果、ｎ型不純物注入工程において変質層の形成を抑制することが可能になる。 Further, in the etching process, the side portion of the conductive layer where the altered layer is easily formed can be covered with the third resist formed on the conductive layer due to the side shift by wet etching. Therefore, even when the n-type impurity implantation step is performed after this wet etching step, the third resist functions as a protective layer for protecting the side surface of the conductive layer, and the n-type impurity is present on the side surface of the conductive layer. Since it becomes difficult to implant, the alteration of the conductive layer due to the implantation of the n-type impurity can be suppressed. As a result, it is possible to suppress the formation of the altered layer in the n-type impurity implantation step.
　また、エッチング工程において、導電層のドライエッチングを行わないため、エッチング工程におけるゲート絶縁膜のエッチングを効果的に抑制することができる。従って、ゲート絶縁膜の膜厚の制御が容易になるため、ゲート絶縁膜の膜厚に対応させて、不純物をドーピングする際のドーピング条件を制御しやすくなる。 In addition, since the conductive layer is not dry-etched in the etching process, the etching of the gate insulating film in the etching process can be effectively suppressed. Therefore, since the thickness of the gate insulating film can be easily controlled, the doping conditions for doping impurities can be easily controlled in accordance with the thickness of the gate insulating film.
　また、ｐ型薄膜トランジスタのゲート電極の形成をｎ型薄膜トランジスタのゲート電極の形成前に行うことにより、第１レジスト及び第２レジストを除去した後にｐ型不純物注入工程を行うことができる。従って、レジストの表面がｐ型不純物注入工程により硬化することがないため、ｐ型不純物注入後にレジストを除去する場合に比べて、レジストを簡単に除去することが可能になる。 Further, by forming the gate electrode of the p-type thin film transistor before forming the gate electrode of the n-type thin film transistor, the p-type impurity implantation step can be performed after removing the first resist and the second resist. Therefore, since the resist surface is not hardened by the p-type impurity implantation step, the resist can be easily removed as compared with the case of removing the resist after the p-type impurity implantation.
　本発明によれば、所望のＬＤＤ領域を有するｎ型薄膜トランジスタを自己整合的に形成することが可能になるとともに、ゲート絶縁膜の膜厚不良に基づく不純物のドーピング不良に起因する活性化不良の発生を抑制することができる。 According to the present invention, an n-type thin film transistor having a desired LDD region can be formed in a self-aligned manner, and an activation failure due to an impurity doping failure based on a gate insulating film thickness failure occurs. Can be suppressed.
本発明の第１の実施形態に係る半導体装置の構成を説明するための断面図である。It is sectional drawing for demonstrating the structure of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の構成を説明するための断面図である。It is sectional drawing for demonstrating the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第４の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. 本発明の第４の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. 本発明の第４の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. 本発明の第４の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. 本発明の第４の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. 本発明の第４の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. 本発明の第４の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention.
　以下、本発明の実施形態を図面に基づいて詳細に説明する。尚、本発明は、以下の実施形態に限定されるものではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.
　（第１の実施形態）
　図１は、本発明の第１の実施形態に係る半導体装置の構成を説明するための断面図である。図１に示すように、半導体装置１は半導体膜２を有するｎ型ＴＦＴ３を備えている。このｎ型ＴＦＴ３は、例えば、液晶表示装置に設けられたゲートドライバやソースドライバ等の駆動回路の能動素子として機能するものである。 (First embodiment)
FIG. 1 is a cross-sectional view for explaining the configuration of a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device 1 includes an n-type TFT 3 having a semiconductor film 2. The n-type TFT 3 functions as an active element of a drive circuit such as a gate driver or a source driver provided in the liquid crystal display device, for example.
　このｎ型ＴＦＴ３は、半導体膜２のガラス基板６側とは反対側にゲート電極７が配置されたトップゲート型の構造を有している。 The n-type TFT 3 has a top gate type structure in which a gate electrode 7 is disposed on the opposite side of the semiconductor film 2 from the glass substrate 6 side.
　また、ガラス基板６の表面上には、例えば、窒化シリコン膜等からなる第１絶縁膜８と酸化シリコン膜等からなる第２絶縁膜９とにより構成された下地絶縁膜１０が形成されている。 On the surface of the glass substrate 6, for example, a base insulating film 10 composed of a first insulating film 8 made of a silicon nitride film or the like and a second insulating film 9 made of a silicon oxide film or the like is formed. .
　また、下地絶縁膜１０の表面上には、半導体膜２が、例えば、５０ｎｍ等の厚みに形成されている。この半導体膜２は、例えば、ポリシリコン等により形成された結晶質シリコン膜により構成されている。 Further, the semiconductor film 2 is formed on the surface of the base insulating film 10 to a thickness of, for example, 50 nm. The semiconductor film 2 is composed of, for example, a crystalline silicon film formed of polysilicon or the like.
　半導体膜２には、一対の高濃度不純物領域であるソース領域２ａ及びドレイン領域２ｂが、チャネル領域２ｃを挟んで形成されている。また、チャネル領域２ｃには、閾値電圧を制御するためのｐ型不純物であるボロンが含まれている。 In the semiconductor film 2, a pair of high concentration impurity regions, a source region 2a and a drain region 2b, are formed with a channel region 2c interposed therebetween. Further, the channel region 2c contains boron which is a p-type impurity for controlling the threshold voltage.
　また、半導体膜２は、ソース領域２ａ及びドレイン領域２ｂに高濃度のｎ型不純物であるリンが含まれている。 Further, the semiconductor film 2 includes phosphorus which is a high concentration n-type impurity in the source region 2a and the drain region 2b.
　また、半導体膜２には、ソース領域２ａとドレイン領域２ｂの間であって、チャネル領域２ｃに隣接して、ｎ型不純物であるリンが含まれる不純物領域であるＬＤＤ領域２ｄが形成されている。このＬＤＤ領域２ｄは、図１に示すように、２つ形成されている。 Also, in the semiconductor film 2, an LDD region 2d that is an impurity region containing phosphorus that is an n-type impurity is formed between the source region 2a and the drain region 2b and adjacent to the channel region 2c. . Two LDD regions 2d are formed as shown in FIG.
　半導体膜２上には、半導体膜２を覆うようにゲート絶縁膜１１が形成されている。このゲート絶縁膜１１は、例えば、酸化シリコン等により形成されている。 A gate insulating film 11 is formed on the semiconductor film 2 so as to cover the semiconductor film 2. The gate insulating film 11 is made of, for example, silicon oxide.
　また、半導体膜２のチャネル領域２ｃ上には、ゲート絶縁膜１１を介してゲート電極７が形成されている。このゲート電極７は、例えば、モリブデン、タングステン、アルミニウム、及びこれらのうち少なくとも１つを含む合金等により形成されている。 A gate electrode 7 is formed on the channel region 2 c of the semiconductor film 2 with a gate insulating film 11 interposed therebetween. The gate electrode 7 is made of, for example, molybdenum, tungsten, aluminum, or an alloy containing at least one of them.
　また、ゲート絶縁膜１１及びゲート電極７を覆うように、層間絶縁膜１２が形成されている。この層間絶縁膜１２は、例えば、窒化シリコン等により形成されている。また、ゲート絶縁膜１１及び層間絶縁膜１２は、例えば、４００ｎｍの厚みに形成されている。 Further, an interlayer insulating film 12 is formed so as to cover the gate insulating film 11 and the gate electrode 7. The interlayer insulating film 12 is made of, for example, silicon nitride. The gate insulating film 11 and the interlayer insulating film 12 are formed to a thickness of 400 nm, for example.
　また、ソース領域２ａ及びドレイン領域２ｂ上には、ゲート絶縁膜１１及び層間絶縁膜１２を貫通するコンタクトホール１３がそれぞれ形成されている。そして、これらのコンタクトホール１３には、例えば、モリブデン、タングステン、アルミニウム、及びこれらのうち少なくとも１つを含む合金等の導電性材料が充填されており、層間絶縁膜１２上には、上記コンタクトホール１３を介して、ソース領域２ａに接続されたソース電極１４と、ドレイン領域２ｂに接続されたドレイン電極１５とが形成されている。これらのソース電極１４、及びドレイン電極１５は、例えば、３８０ｎｍの厚みに形成されており、ソース電極１４及びドレイン電極１５は、上記導電性材料により形成されている。 Further, contact holes 13 penetrating the gate insulating film 11 and the interlayer insulating film 12 are formed on the source region 2a and the drain region 2b, respectively. These contact holes 13 are filled with a conductive material such as molybdenum, tungsten, aluminum, or an alloy containing at least one of them, and the contact holes are formed on the interlayer insulating film 12. 13, a source electrode 14 connected to the source region 2 a and a drain electrode 15 connected to the drain region 2 b are formed. The source electrode 14 and the drain electrode 15 are formed with a thickness of, for example, 380 nm, and the source electrode 14 and the drain electrode 15 are formed of the conductive material.
　次いで、半導体装置の製造方法について説明する。図２～図１１は、本発明の第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。 Next, a method for manufacturing a semiconductor device will be described. 2 to 11 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
　＜半導体膜形成工程＞
　まず、図２に示すように、ガラス基板６の一方の面に、窒化シリコン膜等からなる第１絶縁膜８と酸化シリコン膜等からなる第２絶縁膜９とにより構成された下地絶縁膜１０を、例えば、スパッタリング法等により形成する。次に、非結晶質シリコン膜であるアモルファスシリコン膜３０を下地絶縁膜１０上に、例えば、ＣＶＤ法等により形成する。 <Semiconductor film formation process>
First, as shown in FIG. 2, a base insulating film 10 constituted by a first insulating film 8 made of a silicon nitride film or the like and a second insulating film 9 made of a silicon oxide film or the like on one surface of a glass substrate 6. Is formed by, for example, a sputtering method or the like. Next, an amorphous silicon film 30 which is an amorphous silicon film is formed on the base insulating film 10 by, for example, a CVD method.
　次いで、図３に示すように、アモルファスシリコン膜３０に対してレーザー光３１の照射を行うことにより、アモルファスシリコン膜３０を結晶化して、ガラス基板６上に半導体膜であるポリシリコン膜（結晶質シリコン膜）３２を形成する。 Next, as shown in FIG. 3, the amorphous silicon film 30 is irradiated with laser light 31 to crystallize the amorphous silicon film 30, and a polysilicon film (crystalline material) as a semiconductor film is formed on the glass substrate 6. Silicon film) 32 is formed.
　なお、使用するレーザー光３１としては、ＸｅＣｌ（３０８ｎｍ）、ＸｅＦ（３５１ｎｍ）やＫｒＦ（２４８ｎｍ）等のエキシマレーザーや固体レーザーによるレーザー光を使用することができる。 As the laser beam 31 to be used, an excimer laser such as XeCl (308 nm), XeF (351 nm), KrF (248 nm), or a solid laser can be used.
　また、ポリシリコン膜３２の表面粗さを低減するとの観点から、レーザー光３１を照射する前に、アモルファスシリコン膜３０の表面上に形成された自然酸化膜を除去することが好ましい。また、同様の観点から、レーザー光３１を照射する際の雰囲気としては、窒素等の不活性雰囲気を使用することが好ましい。 Further, from the viewpoint of reducing the surface roughness of the polysilicon film 32, it is preferable to remove the natural oxide film formed on the surface of the amorphous silicon film 30 before the laser beam 31 is irradiated. From the same viewpoint, it is preferable to use an inert atmosphere such as nitrogen as the atmosphere when the laser beam 31 is irradiated.
　次いで、図４に示すように、フォトリソグラフィにより、ポリシリコン膜３２を島状にパターニングして、ガラス基板６上に半導体膜２を形成する。 Next, as shown in FIG. 4, the polysilicon film 32 is patterned into an island shape by photolithography to form the semiconductor film 2 on the glass substrate 6.
　＜ゲート絶縁膜形成工程＞
　次いで、図５に示すように、半導体膜２が形成された基板全体に、プラズマＣＶＤ法により、例えば、酸化シリコン膜などを成膜し、ゲート絶縁膜１１を厚さ１００ｎｍ程度に形成する。 <Gate insulation film formation process>
Next, as shown in FIG. 5, for example, a silicon oxide film or the like is formed on the entire substrate on which the semiconductor film 2 is formed by plasma CVD, and the gate insulating film 11 is formed to a thickness of about 100 nm.
　ここで、ｎ型ＴＦＴの閾値電圧を制御する目的で、図５に示すように、半導体膜２の全体に、ｐ型不純物であるボロンを注入してもよい。図５に示す矢印３９は、ボロンを注入する方向を示している。なお、ボロンの注入には、イオンドーピング法等が用いられ、例えば、加速電圧を２５ｋＶにするとともに、ドーズ量を２×１０１２ｃｍ－２とする。 Here, for the purpose of controlling the threshold voltage of the n-type TFT, boron as a p-type impurity may be implanted into the entire semiconductor film 2 as shown in FIG. An arrow 39 shown in FIG. 5 indicates the direction in which boron is implanted. Note that an ion doping method or the like is used for boron implantation. For example, the acceleration voltage is set to 25 kV and the dose amount is set to 2 × 10 12 cm −2 .
　＜導電層形成工程＞
　次いで、図６に示すように、ゲート絶縁膜１１の全体に、スパッタリング法により、例えば、モリブテンとタングステンの合金を成膜して、ゲート絶縁膜１１上に、例えば、３５０ｎｍの厚みを有する導電層３５を形成する。 <Conductive layer formation process>
Next, as shown in FIG. 6, for example, an alloy of molybdenum and tungsten is formed on the entire gate insulating film 11 by a sputtering method, and a conductive layer having a thickness of, for example, 350 nm is formed on the gate insulating film 11. 35 is formed.
　なお、導電層３５を形成する材料としては、例えば、モリブデン、タングステン、アルミニウム、及びこれらのうち少なくとも１つを含む合金を使用することができる。 As a material for forming the conductive layer 35, for example, molybdenum, tungsten, aluminum, and an alloy containing at least one of them can be used.
　＜レジスト形成工程＞
　次いで、導電層３５上に、半導体膜２を覆うように、スピンコート法により、例えば、ポジ型（露光された部分が現像処理により溶解して除去される型）の感光性樹脂（例えば、アクリル系の感光性樹脂）を厚さ１～３μｍ程度に塗布して設ける。そして、フォトマスク（不図示）を用いて感光性樹脂に対して照射される露光量を制御して露光処理を行い、露光処理が行われた感光性樹脂に対して現像処理を行うことにより、図７に示すように、フォトレジスト４０を形成する。 <Resist formation process>
Next, on the conductive layer 35, for example, a positive type (type in which an exposed portion is dissolved and removed by development processing) photosensitive resin (for example, acrylic) by spin coating so as to cover the semiconductor film 2. System photosensitive resin) is applied to a thickness of about 1 to 3 μm. Then, using a photomask (not shown) to control the exposure amount irradiated to the photosensitive resin to perform an exposure process, and by performing a development process on the photosensitive resin subjected to the exposure process, As shown in FIG. 7, a photoresist 40 is formed.
　＜ドライエッチング工程＞
　次いで、図７に示すように、フォトレジスト４０をマスクとして、ドライエッチングにより、導電層３５をエッチングして、パターニングする。 <Dry etching process>
Next, as shown in FIG. 7, the conductive layer 35 is etched and patterned by dry etching using the photoresist 40 as a mask.
　＜ｎ型不純物注入工程＞
　次いで、図８に示すように、フォトレジスト４０をマスクとして、半導体膜２に、ｎ型不純物（高濃度不純物）であるリンを注入する。図８に示す矢印４２は、リンを注入する方向を示している。なお、リンの注入には、イオンドーピング法等が用いられ、例えば、加速電圧を５０ｋＶにするとともに、ドーズ量を２×１０１５ｃｍ－２とする。そして、リンの注入により、図８に示すように、ｎ型ＴＦＴ３が有する半導体膜２において、高濃度不純物領域であるソース領域２ａ及びドレイン領域２ｂが形成される。 <N-type impurity implantation process>
Next, as shown in FIG. 8, phosphorus, which is an n-type impurity (high concentration impurity), is implanted into the semiconductor film 2 using the photoresist 40 as a mask. An arrow 42 shown in FIG. 8 indicates a direction in which phosphorus is injected. Note that an ion doping method or the like is used for phosphorus implantation. For example, the acceleration voltage is set to 50 kV and the dose is set to 2 × 10 15 cm −2 . Then, as shown in FIG. 8, the source region 2a and the drain region 2b, which are high-concentration impurity regions, are formed in the semiconductor film 2 included in the n-type TFT 3 by phosphorus implantation.
　なお、この際、図８に示すように、半導体膜２に高濃度の不純物イオンを注入する高濃度イオン注入工程において、導電層３５の側面が変質して、変質層４４が形成される。この変質層４４が形成されるのは、ｎ型不純物注入工程において、不純物注入による導電層３５の表面の変質が原因であるものと考えられる。 At this time, as shown in FIG. 8, in the high concentration ion implantation step of implanting high concentration impurity ions into the semiconductor film 2, the side surface of the conductive layer 35 is altered and the altered layer 44 is formed. It is considered that the altered layer 44 is formed due to alteration of the surface of the conductive layer 35 due to impurity implantation in the n-type impurity implantation step.
　＜レジスト縮小工程＞
　次いで、フォトレジスト４０に対してプラズマエッチングを行うことにより、図９に示すようにフォトレジスト４０を等方的にエッチングして、フォトレジスト４０を縮小する。 <Resist reduction process>
Next, by performing plasma etching on the photoresist 40, the photoresist 40 is isotropically etched to reduce the photoresist 40 as shown in FIG.
　この際、表面に変質層４４が形成された導電層３５に対しても、プラズマエッチングが行われるため、図９に示すように、当該プラズマエッチングにより、導電層３５に形成された変質層４４が除去される。 At this time, since the plasma etching is also performed on the conductive layer 35 having the altered layer 44 formed on the surface, the altered layer 44 formed on the conductive layer 35 is formed by the plasma etching as shown in FIG. Removed.
　なお、プラズマエッチングの際に使用するエッチングガスとしては、ＣＦ４、ＮＦ３、ＳＦ６、ＣＨＦ３等のフッ素系ガス、Ｃｌ２、ＢＣｌ３、ＳｉＣｌ４、ＣＣｌ４等の塩素系ガス、酸素ガス等を使用することができ、ヘリウムやアルゴン等の不活性ガスを添加する構成としても良い。 The etching gas used in the plasma etching includes fluorine-based gases such as CF 4 , NF 3 , SF 6 , and CHF 3 , chlorine-based gases such as Cl 2 , BCl 3 , SiCl 4 , and CCl 4 , and oxygen gas. Or an inert gas such as helium or argon may be added.
　＜ゲート電極形成工程＞
　次いで、縮小したフォトレジスト４０をマスクとして、導電層３５に対してウェットエッチングを行うことにより、図１０に示すように、ゲート電極７を形成する。 <Gate electrode formation process>
Next, wet etching is performed on the conductive layer 35 using the reduced photoresist 40 as a mask, thereby forming the gate electrode 7 as shown in FIG.
　この際、上述のごとく、ｎ型不純物注入工程において形成された変質層４４が、上述のプラズマエッチングにより除去されているため、ｎ型不純物注入工程後にウェットエッチングを行った場合であっても、変質層４４に起因するウェットエッチングのバラツキの発生を抑制することができる。従って、ウェットエッチングにより、所望のゲート電極７の形成が可能になる。その結果、後述する、ゲート電極７をマスクとして、半導体膜２にｎ型不純物であるリンを注入して、半導体膜２にＬＤＤ領域２ｄを形成する際に、所望のＬＤＤ領域２ｄ（即ち、所望の長さを有するＬＤＤ領域）を自己整合的に形成することが可能になる。 At this time, as described above, the altered layer 44 formed in the n-type impurity implantation step is removed by the above-described plasma etching. Therefore, even if wet etching is performed after the n-type impurity implantation step, the alteration layer 44 is changed. The occurrence of variations in wet etching due to the layer 44 can be suppressed. Therefore, the desired gate electrode 7 can be formed by wet etching. As a result, a desired LDD region 2d (that is, a desired LDD region 2d) is formed when an LDD region 2d is formed in the semiconductor film 2 by implanting phosphorus, which is an n-type impurity, into the semiconductor film 2 by using the gate electrode 7 described later as a mask. It is possible to form a self-aligned LDD region having a length of
　なお、本工程においては、ウェットエッチングによるサイドシフト（導電層３５に対して、垂直な方向だけではなく、平行な方向（図１０に示す矢印Ｘの方向）にもエッチングが進む現象）により、ＬＤＤ領域形成工程において、マスクとして最適な幅を有するゲート電極７を自己整合的に得ることが可能になる。 In this step, LDD is caused by side shift by wet etching (a phenomenon in which etching proceeds not only in a direction perpendicular to the conductive layer 35 but also in a parallel direction (the direction of the arrow X shown in FIG. 10)). In the region forming step, the gate electrode 7 having an optimum width as a mask can be obtained in a self-aligning manner.
　また、本実施形態においては、上記従来技術とは異なり、ドライエッチングによりゲート電極を形成するのではなく、導電層をウェットエッチングすることによりゲート電極７を形成する。従って、導電層３５が存在しない部分でゲート絶縁膜１１がエッチングされてしまい、ゲート絶縁膜１１が極端に薄くなってしまうという不都合の発生を防止することができる。従って、ゲート絶縁膜１１の膜厚を制御することができるため、結果として、不純物のドーピング不良に起因する活性化不良の発生を抑制することができる。 In the present embodiment, unlike the above-described conventional technique, the gate electrode 7 is formed by wet etching the conductive layer instead of forming the gate electrode by dry etching. Therefore, it is possible to prevent the disadvantage that the gate insulating film 11 is etched in a portion where the conductive layer 35 does not exist and the gate insulating film 11 becomes extremely thin. Therefore, the thickness of the gate insulating film 11 can be controlled, and as a result, it is possible to suppress the occurrence of activation failure due to impurity doping failure.
　＜ＬＤＤ領域形成工程＞
　次いで、ドライエッチング等によりフォトレジスト４０を除去した後、図１１に示すように、ゲート電極７をマスクとして、半導体膜２にｎ型不純物であるリンを注入する。図１１に示す矢印４６は、リンを注入する方向を示している。なお、リンの注入には、イオンドーピング法等が用いられ、例えば、加速電圧を８０ｋＶにするとともに、ドーズ量を２×１０１３ｃｍ－２とする。そして、リンの注入により、図１１に示すように、半導体膜２において、ＬＤＤ領域２ｄが形成され、ソース領域２ａ、ドレイン領域２ｂ、チャネル領域２ｃ、及びＬＤＤ領域２ｄからなる半導体膜２が形成され、半導体膜２を有するｎ型ＴＦＴ３が形成されることになる。 <LDD region forming step>
Next, after removing the photoresist 40 by dry etching or the like, phosphorus as an n-type impurity is implanted into the semiconductor film 2 using the gate electrode 7 as a mask as shown in FIG. An arrow 46 shown in FIG. 11 indicates a direction in which phosphorus is injected. Note that an ion doping method or the like is used for phosphorus implantation. For example, the acceleration voltage is set to 80 kV and the dose is set to 2 × 10 13 cm −2 . Then, by implantation of phosphorus, as shown in FIG. 11, the LDD region 2d is formed in the semiconductor film 2, and the semiconductor film 2 including the source region 2a, the drain region 2b, the channel region 2c, and the LDD region 2d is formed. Thus, the n-type TFT 3 having the semiconductor film 2 is formed.
　＜コンタクトホール形成工程＞
　次いで、ゲート電極７及びゲート絶縁膜１１を覆う層間絶縁膜１２を形成した後、ソース領域２ａ及びドレイン領域２ｂ上に、それぞれゲート絶縁膜１１及び層間絶縁膜１２を貫通するコンタクトホール１３を、例えば、エッチング等により形成する。 <Contact hole formation process>
Next, after forming the interlayer insulating film 12 covering the gate electrode 7 and the gate insulating film 11, contact holes 13 penetrating the gate insulating film 11 and the interlayer insulating film 12 respectively on the source region 2a and the drain region 2b are formed, for example, Or by etching or the like.
　＜ソース電極・ドレイン電極形成工程＞
　次に、各コンタクトホール１３の内部及び層間絶縁膜１２上に、ソース電極１４及びドレイン電極１５を形成する。ソース電極１４及びドレイン電極１５は、例えば、フォトリソグラフィ法及びドライエッチング等により形成し、コンタクトホール１３を介して、ソース電極１４をソース領域２ａに接続するとともに、ドレイン電極１５をドレイン領域２ｂに接続する。 <Source electrode / drain electrode formation process>
Next, the source electrode 14 and the drain electrode 15 are formed inside each contact hole 13 and on the interlayer insulating film 12. The source electrode 14 and the drain electrode 15 are formed by, for example, photolithography and dry etching, and the source electrode 14 is connected to the source region 2a through the contact hole 13 and the drain electrode 15 is connected to the drain region 2b. To do.
　以上より、図１に示す半導体装置１が製造される。 Thus, the semiconductor device 1 shown in FIG. 1 is manufactured.
　（第２の実施形態）
　次に、本発明の第２の実施形態について説明する。図１２～図１３は、本発明の第２の実施形態に係る半導体装置の製造方法を説明するための断面図である。なお、上記第１の実施形態と同様の構成部分については同一の符号を付してその説明を省略する。 (Second Embodiment)
Next, a second embodiment of the present invention will be described. 12 to 13 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the second embodiment of the present invention. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
　本実施形態においては、上述の第１の実施形態において説明したドライエッチング工程の代わりに、ウェットエッチングを使用して、導電層３５のエッチングを行う点に特徴がある。 This embodiment is characterized in that the conductive layer 35 is etched by using wet etching instead of the dry etching step described in the first embodiment.
　より具体的には、上述の図６に示す導電層形成工程、及び図７に示すレジスト形成工程を行った後、エッチング工程として、図１２に示すように、ウェットエッチングにより、導電層３５のエッチングを行う。 More specifically, after the conductive layer forming step shown in FIG. 6 and the resist forming step shown in FIG. 7 are performed, the etching of the conductive layer 35 is performed by wet etching as shown in FIG. I do.
　この際、上述のウェットエッチングによるサイドシフト（導電層３５に対して、垂直な方向だけではなく、平行な方向（図１２に示す矢印Ｘの方向）にもエッチングが進む現象）により、図１２に示すように、第１の実施形態において、変質層４４が形成されていた導電層３５の側面３５ａがフォトレジスト４０により覆われる（即ち、フォトレジスト４０の下方に隠れる）構成となる。 At this time, due to the above-described side shift by wet etching (a phenomenon in which etching proceeds not only in a direction perpendicular to the conductive layer 35 but also in a parallel direction (the direction of the arrow X shown in FIG. 12)), FIG. As shown, in the first embodiment, the side surface 35a of the conductive layer 35 on which the altered layer 44 has been formed is covered with the photoresist 40 (that is, hidden under the photoresist 40).
　従って、このウェットエッチング工程の後、上述の第１の実施形態と同様に、ｎ型不純物注入工程を行った場合であっても、図１３に示すように、フォトレジスト４０が、導電層３５の側面３５ａを保護する保護層として機能し、導電層３５の側面３５ａにｎ型不純物が注入されにくくなる。従って、不純物注入による導電層３５の表面の変質が抑制することができる。その結果、ｎ型不純物注入工程において変質層４４の形成を抑制することが可能になる。 Therefore, after the wet etching step, as in the first embodiment described above, even when the n-type impurity implantation step is performed, the photoresist 40 is formed on the conductive layer 35 as shown in FIG. It functions as a protective layer for protecting the side surface 35a, and n-type impurities are hardly implanted into the side surface 35a of the conductive layer 35. Therefore, alteration of the surface of the conductive layer 35 due to impurity implantation can be suppressed. As a result, formation of the altered layer 44 can be suppressed in the n-type impurity implantation step.
　また、導電層３５のドライエッチングを行わないため、エッチング処理の際にゲート絶縁膜１１のエッチングを効果的に抑制することができる。従って、ゲート絶縁膜１１の膜厚の制御が容易になるため、ゲート絶縁膜１１の膜厚に対応させて、不純物をドーピングする際のドーピング条件を制御しやすくなる。 Further, since the conductive layer 35 is not dry etched, the etching of the gate insulating film 11 can be effectively suppressed during the etching process. Therefore, since the thickness of the gate insulating film 11 can be easily controlled, the doping conditions for doping impurities can be easily controlled according to the thickness of the gate insulating film 11.
　ｎ型不純物注入工程の後、上述の第１の実施形態の場合と同様にして、レジスト縮小工程を行う。この際、本実施形態においても、上述のウェットエッチング工程において、仮に、導電層３５の側面３５ａに変質層４４が形成された場合であっても、第１の実施形態と同様にレジスト縮小工程を行うため、導電層３５に形成された変質層４４を確実に除去することができる。また、第１の実施形態と異なり、上述のウェットエッチング工程において、変質層４４の形成を効果的に抑制することができるため、レジスト縮小工程において、変質層４４を除去しやすくなるという利点を有する。 After the n-type impurity implantation step, a resist reduction step is performed in the same manner as in the first embodiment described above. At this time, in this embodiment as well, even if the altered layer 44 is formed on the side surface 35a of the conductive layer 35 in the above-described wet etching step, the resist reduction step is performed as in the first embodiment. Therefore, the altered layer 44 formed on the conductive layer 35 can be surely removed. Further, unlike the first embodiment, the formation of the deteriorated layer 44 can be effectively suppressed in the above-described wet etching process, so that the deteriorated layer 44 can be easily removed in the resist reduction process. .
　そして、上述のゲート電極形成工程、ＬＤＤ領域形成工程、コンタクトホール形成工程、及びソース電極・ドレイン電極形成工程を行うことにより、図１に示す半導体装置１が製造される構成となっている。 Then, the semiconductor device 1 shown in FIG. 1 is manufactured by performing the above-described gate electrode forming step, LDD region forming step, contact hole forming step, and source / drain electrode forming step.
　（第３の実施形態）
　次に、本発明の第３の実施形態について説明する。図１４は、本発明の第３の実施形態に係る半導体装置の構成を説明するための断面図である。なお、上記第１の実施形態と同様の構成部分については同一の符号を付してその説明を省略する。 (Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 14 is a cross-sectional view for explaining the configuration of a semiconductor device according to the third embodiment of the present invention. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
　図１４に示すように、本実施形態における半導体装置５０はＣＭＯＳを有しており、ＣＭＯＳは、上述の半導体膜２を第１半導体膜として有するｎ型ＴＦＴ３と、第２半導体膜である半導体膜４を有するｐ型ＴＦＴ５とを備えている。つまり、半導体装置５０は、ｎ型ＴＦＴ３及びｐ型ＴＦＴ５を有している。 As shown in FIG. 14, the semiconductor device 50 in this embodiment includes a CMOS, and the CMOS includes an n-type TFT 3 having the semiconductor film 2 described above as a first semiconductor film, and a semiconductor film that is a second semiconductor film. P-type TFT 5 having 4. That is, the semiconductor device 50 includes the n-type TFT 3 and the p-type TFT 5.
　これらのｎ型ＴＦＴ３及びｐ型ＴＦＴ５は、例えば、液晶表示装置に設けられたゲートドライバやソースドライバ等の駆動回路の能動素子として機能するものである。 These n-type TFT 3 and p-type TFT 5 function as active elements of a drive circuit such as a gate driver or a source driver provided in a liquid crystal display device, for example.
　このｎ型ＴＦＴ３及びｐ型ＴＦＴ５は、それぞれ半導体膜２及び半導体膜４のガラス基板６側とは反対側にゲート電極７が配置されたトップゲート型の構造を有している。 The n-type TFT 3 and the p-type TFT 5 have a top gate type structure in which a gate electrode 7 is disposed on the opposite side of the semiconductor film 2 and the semiconductor film 4 from the glass substrate 6 side.
　また、下地絶縁膜１０の表面上には、半導体膜２及び半導体膜４が、例えば、５０ｎｍ等の厚みに形成されており、この半導体膜２と半導体膜４との間には、所定の間隔が設けられている。この半導体膜２及び半導体膜４は、例えば、ポリシリコン等により形成された結晶質シリコン膜（半導体膜）により構成されている。 On the surface of the base insulating film 10, the semiconductor film 2 and the semiconductor film 4 are formed with a thickness of, for example, 50 nm, and a predetermined gap is provided between the semiconductor film 2 and the semiconductor film 4. Is provided. The semiconductor film 2 and the semiconductor film 4 are composed of, for example, a crystalline silicon film (semiconductor film) formed of polysilicon or the like.
　半導体膜２及び半導体膜４には、それぞれ一対の高濃度不純物領域であるソース領域２ａ，４ａ及びドレイン領域２ｂ，４ｂが、チャネル領域２ｃ，４ｃを挟んで形成されている。また、チャネル領域２ｃ，４ｃには、閾値電圧を制御するためのｐ型不純物であるボロンが含まれている。 In the semiconductor film 2 and the semiconductor film 4, a pair of high-concentration impurity regions, source regions 2a and 4a and drain regions 2b and 4b, are formed with the channel regions 2c and 4c interposed therebetween. The channel regions 2c and 4c contain boron which is a p-type impurity for controlling the threshold voltage.
　また、半導体膜２は、ソース領域２ａ及びドレイン領域２ｂにｎ型不純物であるリンが含まれている。また、半導体膜４は、ソース領域４ａ及びドレイン領域４ｂにｐ型不純物であるボロンが含まれている。 Further, the semiconductor film 2 contains phosphorus which is an n-type impurity in the source region 2a and the drain region 2b. Further, the semiconductor film 4 includes boron which is a p-type impurity in the source region 4a and the drain region 4b.
　また、半導体膜２には、ソース領域２ａとドレイン領域２ｂの間であって、チャネル領域２ｃに隣接して、ｎ型不純物であるリンが含まれる不純物領域であるＬＤＤ領域２ｄが形成されている。このＬＤＤ領域２ｄは、図１４に示すように、２つ形成されている。 Also, in the semiconductor film 2, an LDD region 2d that is an impurity region containing phosphorus that is an n-type impurity is formed between the source region 2a and the drain region 2b and adjacent to the channel region 2c. . As shown in FIG. 14, two LDD regions 2d are formed.
　また、半導体膜２及び半導体膜４上には、半導体膜２及び半導体膜４を覆うようにゲート絶縁膜１１が形成されている。このゲート絶縁膜１１は、例えば、酸化シリコン等により形成されている。 Further, a gate insulating film 11 is formed on the semiconductor film 2 and the semiconductor film 4 so as to cover the semiconductor film 2 and the semiconductor film 4. The gate insulating film 11 is made of, for example, silicon oxide.
　また、半導体膜２及び半導体膜４のチャネル領域２ｃ，４ｃ上には、それぞれゲート絶縁膜１１を介してゲート電極７が形成されている。 A gate electrode 7 is formed on each of the channel regions 2c and 4c of the semiconductor film 2 and the semiconductor film 4 with a gate insulating film 11 interposed therebetween.
　また、ゲート絶縁膜１１及びゲート電極７を覆うように、層間絶縁膜１２が形成されている。この層間絶縁膜１２は、例えば、窒化シリコン等により形成されている。また、ゲート絶縁膜１１及び層間絶縁膜１２は、例えば、４００ｎｍの厚みに形成されている。 Further, an interlayer insulating film 12 is formed so as to cover the gate insulating film 11 and the gate electrode 7. The interlayer insulating film 12 is made of, for example, silicon nitride. The gate insulating film 11 and the interlayer insulating film 12 are formed to a thickness of 400 nm, for example.
　また、ソース領域２ａ，４ａ及びドレイン領域２ｂ，４ｂ上には、ゲート絶縁膜１１及び層間絶縁膜１２を貫通するコンタクトホール１３がそれぞれ形成されている。そして、これらのコンタクトホール１３には、例えば、モリブデン、タングステン、アルミニウム、及びこれらのうち少なくとも１つを含む合金等の導電性材料が充填されており、層間絶縁膜１２上には、上記コンタクトホール１３を介して、ソース領域２ａ，４ａに接続されたソース電極１４と、ドレイン領域２ｂ，４ｂに接続されたドレイン電極１５とが形成されている。 Further, contact holes 13 penetrating the gate insulating film 11 and the interlayer insulating film 12 are formed on the source regions 2a and 4a and the drain regions 2b and 4b, respectively. These contact holes 13 are filled with a conductive material such as molybdenum, tungsten, aluminum, or an alloy containing at least one of them, and the contact holes are formed on the interlayer insulating film 12. 13, a source electrode 14 connected to the source regions 2a and 4a and a drain electrode 15 connected to the drain regions 2b and 4b are formed.
　これらのソース電極１４、及びドレイン電極１５は、例えば、３８０ｎｍの厚みに形成されており、ソース電極１４及びドレイン電極１５は、上記導電性材料により形成されている。 The source electrode 14 and the drain electrode 15 are formed with a thickness of, for example, 380 nm, and the source electrode 14 and the drain electrode 15 are formed of the conductive material.
　次いで、半導体装置５０の製造方法について説明する。図１５～図２６は、本発明の第３の実施形態に係る半導体装置の製造方法を説明するための断面図である。 Next, a method for manufacturing the semiconductor device 50 will be described. 15 to 26 are sectional views for explaining a method for manufacturing a semiconductor device according to the third embodiment of the present invention.
　＜半導体膜形成工程＞
　まず、図１５に示すように、ガラス基板６の一方の面に、窒化シリコン膜等からなる第１絶縁膜８と酸化シリコン膜等からなる第２絶縁膜９とにより構成された下地絶縁膜１０を、例えば、スパッタリング法等により形成する。次に、非結晶質シリコン膜であるアモルファスシリコン膜３０を下地絶縁膜１０上に、例えば、ＣＶＤ法等により形成する、
　次いで、図１６に示すように、アモルファスシリコン膜３０に対して、レーザー光３１の照射を行うことにより、アモルファスシリコン膜３０を結晶化して、ガラス基板６上に半導体膜であるポリシリコン膜（結晶質シリコン膜）３２を形成する。 <Semiconductor film formation process>
First, as shown in FIG. 15, a base insulating film 10 composed of a first insulating film 8 made of a silicon nitride film or the like and a second insulating film 9 made of a silicon oxide film or the like on one surface of a glass substrate 6. Is formed by, for example, a sputtering method or the like. Next, an amorphous silicon film 30 that is an amorphous silicon film is formed on the base insulating film 10 by, for example, a CVD method,
Next, as shown in FIG. 16, the amorphous silicon film 30 is irradiated with a laser beam 31 to crystallize the amorphous silicon film 30, and a polysilicon film (crystal) that is a semiconductor film on the glass substrate 6. A quality silicon film) 32 is formed.
　次いで、図１７に示すように、フォトリソグラフィにより、ポリシリコン膜３２を島状にパターニングして、ガラス基板６上に半導体膜２及び半導体膜４を形成する。 Next, as shown in FIG. 17, the polysilicon film 32 is patterned into an island shape by photolithography to form the semiconductor film 2 and the semiconductor film 4 on the glass substrate 6.
　＜ゲート絶縁膜形成工程＞
　次いで、図１８に示すように、半導体膜２及び半導体膜４が形成された基板全体に、プラズマＣＶＤ法により、例えば、酸化シリコン膜などを成膜し、ゲート絶縁膜１１を厚さ１００ｎｍ程度に形成する。 <Gate insulation film formation process>
Next, as shown in FIG. 18, for example, a silicon oxide film or the like is formed on the entire substrate on which the semiconductor film 2 and the semiconductor film 4 are formed by a plasma CVD method, and the gate insulating film 11 has a thickness of about 100 nm. Form.
　ここで、ｎ型及びｐ型ＴＦＴの閾値電圧を制御する目的で、図１８に示すように、半導体膜２及び半導体膜４の全体に、ｐ型不純物であるボロンを注入してもよい。図１８に示す矢印３３は、ボロンを注入する方向を示している。なお、ボロンの注入には、イオンドーピング法等が用いられ、例えば、加速電圧を２５ｋＶにするとともに、ドーズ量を２×１０１２ｃｍ－２とする。 Here, for the purpose of controlling the threshold voltage of the n-type and p-type TFTs, boron, which is a p-type impurity, may be implanted into the entire semiconductor film 2 and the semiconductor film 4 as shown in FIG. An arrow 33 shown in FIG. 18 indicates a direction in which boron is injected. Note that an ion doping method or the like is used for boron implantation. For example, the acceleration voltage is set to 25 kV and the dose amount is set to 2 × 10 12 cm −2 .
　＜導電層形成工程＞
　次いで、図１９に示すように、ゲート絶縁膜１１の全体に、スパッタリング法により、例えば、モリブテンとタングステンの合金を成膜して、ゲート絶縁膜１１上に、例えば、３５０ｎｍの厚みを有する導電層３５を形成する。 <Conductive layer formation process>
Next, as shown in FIG. 19, for example, an alloy of molybdenum and tungsten is formed on the entire gate insulating film 11 by a sputtering method, and a conductive layer having a thickness of, for example, 350 nm is formed on the gate insulating film 11. 35 is formed.
　＜第１のレジスト形成工程＞
　次いで、導電層３５上に、半導体膜２，４を覆うように、スピンコート法により、例えば、ポジ型の感光性樹脂（例えば、アクリル系の感光性樹脂）を厚さ１～３μｍ程度に塗布して設ける。そして、フォトマスク（不図示）を用いて感光性樹脂に対して照射される露光量を制御して露光処理を行い、露光処理が行われた感光性樹脂に対して現像処理を行うことにより、図２０に示すように、第１フォトレジスト５２と第２フォトレジスト５３とを同時に形成する。 <First resist forming step>
Next, on the conductive layer 35, for example, a positive photosensitive resin (for example, acrylic photosensitive resin) is applied to a thickness of about 1 to 3 μm by spin coating so as to cover the semiconductor films 2 and 4. Provide. Then, using a photomask (not shown) to control the exposure amount irradiated to the photosensitive resin to perform an exposure process, and by performing a development process on the photosensitive resin subjected to the exposure process, As shown in FIG. 20, a first photoresist 52 and a second photoresist 53 are formed simultaneously.
　なお、図２０に示すように、導電層３５上であって半導体膜２の上方に第１フォトレジスト５２が形成されるとともに、導電層３５上であって半導体膜４の上方に第２フォトレジスト５３が形成される。 As shown in FIG. 20, the first photoresist 52 is formed on the conductive layer 35 and above the semiconductor film 2, and the second photoresist is formed on the conductive layer 35 and above the semiconductor film 4. 53 is formed.
　＜エッチング工程＞
　次いで、図２０に示すように、第１フォトレジスト５２、及び第２フォトレジスト５３をマスクとして、ドライエッチング等により、導電層３５をエッチングする。この際、図２０に示すように、ｎ型ＴＦＴ３側のゲート電極７となる導電層３５のみがパターニングされる。 <Etching process>
Next, as shown in FIG. 20, the conductive layer 35 is etched by dry etching or the like using the first photoresist 52 and the second photoresist 53 as a mask. At this time, as shown in FIG. 20, only the conductive layer 35 to be the gate electrode 7 on the n-type TFT 3 side is patterned.
　＜ｎ型不純物注入工程＞
　次いで、図２１に示すように、第１フォトレジスト５２、及び第２フォトレジスト５３をマスクとして、半導体膜２に、ｎ型不純物（高濃度不純物）であるリンを注入する。図２１に示す矢印４３は、リンを注入する方向を示している。なお、リンの注入には、イオンドーピング法等が用いられ、例えば、加速電圧を５０ｋＶにするとともに、ドーズ量を２×１０１５ｃｍ－２とする。そして、リンの注入により、図２１に示すように、ｎ型ＴＦＴ３が有する半導体膜２において、高濃度不純物領域であるソース領域２ａ及びドレイン領域２ｂが形成される。 <N-type impurity implantation process>
Next, as shown in FIG. 21, phosphorus, which is an n-type impurity (high concentration impurity), is implanted into the semiconductor film 2 using the first photoresist 52 and the second photoresist 53 as a mask. An arrow 43 shown in FIG. 21 indicates a direction in which phosphorus is injected. Note that an ion doping method or the like is used for phosphorus implantation. For example, the acceleration voltage is set to 50 kV and the dose is set to 2 × 10 15 cm −2 . Then, as shown in FIG. 21, the source region 2a and the drain region 2b, which are high-concentration impurity regions, are formed in the semiconductor film 2 included in the n-type TFT 3 by implanting phosphorus.
　なお、この際、図２１に示すように、半導体膜２に高濃度の不純物イオンを注入する高濃度イオン注入工程において、導電層３５の側面が変質して、変質層４４が形成される。 At this time, as shown in FIG. 21, in the high concentration ion implantation step of implanting high concentration impurity ions into the semiconductor film 2, the side surface of the conductive layer 35 is altered and the altered layer 44 is formed.
　＜レジスト縮小工程＞
　次いで、第１及び第２フォトレジスト５２，５３に対してプラズマエッチングを行うことにより、図２２に示すように第１及び第２フォトレジスト５２，５３を等方的にエッチングして、第１及び第２フォトレジスト５２，５３を縮小する。 <Resist reduction process>
Next, by performing plasma etching on the first and second photoresists 52 and 53, the first and second photoresists 52 and 53 are isotropically etched as shown in FIG. The second photoresists 52 and 53 are reduced.
　この際、表面に変質層４４が形成された導電層３５に対しても、プラズマエッチングが行われるため、図２２に示すように、当該プラズマエッチングにより、導電層３５の表面に形成された変質層４４が除去される。 At this time, since the plasma etching is also performed on the conductive layer 35 having the altered layer 44 formed on the surface, the altered layer formed on the surface of the conductive layer 35 by the plasma etching as shown in FIG. 44 is removed.
　＜第１のゲート電極形成工程＞
　次いで、縮小した第１フォトレジスト５２をマスクとして、導電層３５に対してウェットエッチングを行うことにより、図２３に示すように、ｎ型ＴＦＴ３を構成するゲート電極７を形成する。 <First gate electrode formation step>
Next, wet etching is performed on the conductive layer 35 using the reduced first photoresist 52 as a mask, thereby forming the gate electrode 7 constituting the n-type TFT 3 as shown in FIG.
　この際、上述のごとく、ｎ型不純物注入工程において形成された変質層４４が、上述のプラズマエッチングにより除去されているため、ｎ型不純物注入工程後にウェットエッチングを行った場合であっても、変質層４４に起因するウェットエッチングのバラツキ（即ち、ゲート電極７の幅のバラツキ）の発生を抑制することができる。従って、ウェットエッチングにより、所望のゲート電極７の形成が可能になる。 At this time, as described above, the altered layer 44 formed in the n-type impurity implantation step is removed by the above-described plasma etching. Therefore, even if wet etching is performed after the n-type impurity implantation step, the alteration layer 44 is changed. Generation of variations in wet etching (that is, variations in the width of the gate electrode 7) due to the layer 44 can be suppressed. Therefore, the desired gate electrode 7 can be formed by wet etching.
　なお、本工程においては、ウェットエッチングによるサイドシフト（導電層３５に対して、垂直な方向だけではなく、平行な方向（図２３に示す矢印Ｘの方向）にもエッチングが進む現象）により、ＬＤＤ領域形成工程において、マスクとして最適な幅を有するゲート電極７を自己整合的に得ることが可能になる。 In this step, LDD is caused by a side shift by wet etching (a phenomenon in which etching proceeds not only in a direction perpendicular to the conductive layer 35 but also in a parallel direction (the direction of the arrow X shown in FIG. 23)). In the region forming step, the gate electrode 7 having an optimum width as a mask can be obtained in a self-aligning manner.
　また、本実施形態においては、上記従来技術とは異なり、ドライエッチングによりゲート電極７を形成するのではなく、導電層３５をウェットエッチングすることによりゲート電極７を形成する。従って、導電層３５が存在しない部分でゲート絶縁膜１１がエッチングされてしまい、ゲート絶縁膜１１が極端に薄くなってしまうという不都合の発生を防止することができる。従って、ゲート絶縁膜１１の膜厚を制御することができるため、結果として、不純物のドーピング不良に起因する活性化不良の発生を抑制することができる。 Further, in the present embodiment, unlike the conventional technique, the gate electrode 7 is formed by wet etching the conductive layer 35 instead of forming the gate electrode 7 by dry etching. Therefore, it is possible to prevent the disadvantage that the gate insulating film 11 is etched in a portion where the conductive layer 35 does not exist and the gate insulating film 11 becomes extremely thin. Therefore, the thickness of the gate insulating film 11 can be controlled, and as a result, it is possible to suppress the occurrence of activation failure due to impurity doping failure.
　＜ＬＤＤ領域形成工程＞
　次いで、ドライエッチング等により第１及び第２フォトレジスト５２，５３を除去した後、図２４に示すように、ゲート電極７をマスクとして、半導体膜２にｎ型不純物であるリンを注入する。図２４に示す矢印４７は、リンを注入する方向を示している。なお、リンの注入には、イオンドーピング法等が用いられ、例えば、加速電圧を８０ｋＶにするとともに、ドーズ量を２×１０１３ｃｍ－２とする。そして、リンの注入により、図２４に示すように、半導体膜２において、ＬＤＤ領域２ｄが形成され、ソース領域２ａ、ドレイン領域２ｂ、チャネル領域２ｃ、及びＬＤＤ領域２ｄからなる半導体膜２が形成され、半導体膜２を有するｎ型ＴＦＴ３が形成されることになる。 <LDD region forming step>
Next, after removing the first and second photoresists 52 and 53 by dry etching or the like, phosphorus as an n-type impurity is implanted into the semiconductor film 2 using the gate electrode 7 as a mask as shown in FIG. An arrow 47 shown in FIG. 24 indicates the direction in which phosphorus is injected. Note that an ion doping method or the like is used for phosphorus implantation. For example, the acceleration voltage is set to 80 kV and the dose is set to 2 × 10 13 cm −2 . Then, by implantation of phosphorus, as shown in FIG. 24, the LDD region 2d is formed in the semiconductor film 2, and the semiconductor film 2 including the source region 2a, the drain region 2b, the channel region 2c, and the LDD region 2d is formed. Thus, the n-type TFT 3 having the semiconductor film 2 is formed.
　＜第２のレジスト形成工程＞
　次いで、ゲート電極７及び導電層３５上に、半導体膜２，４を覆うように、スピンコート法により、例えば、ポジ型の感光性樹脂（例えば、アクリル系の感光性樹脂）を厚さ１～３μｍ程度に塗布して設ける。そして、フォトマスク（不図示）を用いて感光性樹脂に対して照射される露光量を制御して露光処理を行い、露光処理が行われた感光性樹脂に対して現像処理を行うことにより、第３フォトレジスト５４と第４フォトレジスト５５とを同時に形成する。 <Second resist formation step>
Next, on the gate electrode 7 and the conductive layer 35, for example, a positive photosensitive resin (for example, an acrylic photosensitive resin) is formed with a thickness of 1 to 4 by spin coating so as to cover the semiconductor films 2 and 4. It is applied by applying to about 3 μm. Then, using a photomask (not shown) to control the exposure amount irradiated to the photosensitive resin to perform an exposure process, and by performing a development process on the photosensitive resin subjected to the exposure process, A third photoresist 54 and a fourth photoresist 55 are formed simultaneously.
　なお、第３フォトレジスト５４は、ｎ型ＴＦＴ３を覆うように形成され、第４フォトレジスト５５は、導電層３５上であって、半導体膜４の上方に形成される。 The third photoresist 54 is formed so as to cover the n-type TFT 3, and the fourth photoresist 55 is formed on the conductive layer 35 and above the semiconductor film 4.
　＜第２のゲート電極形成工程＞
　次いで、図２５に示すように、第３フォトレジスト５４、及び第４フォトレジスト５５をマスクとして、ウェットエッチングにより、半導体膜４の上方に形成された導電層３５をエッチングして、ｐ型ＴＦＴ５を構成するゲート電極７を形成する。この際、図２５に示すように、ｐ型ＴＦＴ５側のゲート電極７となる導電層３５のみがパターニングされる。 <Second gate electrode formation step>
Next, as shown in FIG. 25, the conductive layer 35 formed above the semiconductor film 4 is etched by wet etching using the third photoresist 54 and the fourth photoresist 55 as a mask, and the p-type TFT 5 is formed. The gate electrode 7 to be configured is formed. At this time, as shown in FIG. 25, only the conductive layer 35 to be the gate electrode 7 on the p-type TFT 5 side is patterned.
　＜ｐ型不純物注入工程＞
　次いで、図２６に示すように、第３フォトレジスト５４、及び第４フォトレジスト５５をマスクとして、半導体膜４に、ｐ型不純物であるボロンを注入する。図２６に示す矢印４８は、ボロンを注入する方向を示している。なお、ボロンの注入には、イオンドーピング法等が用いられ、例えば、加速電圧を８０ｋＶにするとともに、ドーズ量を２×１０１５ｃｍ－２とする。そして、ボロンの注入により、図２６に示すように、ｐ型ＴＦＴ５が有する半導体膜４において、高濃度不純物領域であるソース領域４ａ及びドレイン領域４ｂが形成され、半導体膜４を有するｐ型ＴＦＴ５が形成されることになる。 <P-type impurity implantation step>
Next, as shown in FIG. 26, boron, which is a p-type impurity, is implanted into the semiconductor film 4 using the third photoresist 54 and the fourth photoresist 55 as a mask. An arrow 48 shown in FIG. 26 indicates a direction in which boron is injected. Note that ion doping or the like is used for boron implantation. For example, the acceleration voltage is set to 80 kV and the dose amount is set to 2 × 10 15 cm −2 . Then, as shown in FIG. 26, the source region 4a and the drain region 4b which are high-concentration impurity regions are formed in the semiconductor film 4 included in the p-type TFT 5 by boron implantation, and the p-type TFT 5 including the semiconductor film 4 is formed. Will be formed.
　＜コンタクトホール形成工程＞
　次いで、ドライエッチング等により第３及び第４フォトレジスト５４，５５を除去した後、ゲート電極７及びゲート絶縁膜１１を覆う層間絶縁膜１２を形成した後、ソース領域２ａ，４ａ及びドレイン領域２ｂ，４ｂ上に、それぞれゲート絶縁膜１１及び層間絶縁膜１２を貫通するコンタクトホール１３を、例えば、エッチング等により形成する。 <Contact hole formation process>
Next, after removing the third and fourth photoresists 54 and 55 by dry etching or the like, an interlayer insulating film 12 covering the gate electrode 7 and the gate insulating film 11 is formed, and then the source regions 2a and 4a and the drain regions 2b, On 4b, contact holes 13 penetrating the gate insulating film 11 and the interlayer insulating film 12 are formed by, for example, etching.
　＜ソース電極・ドレイン電極形成工程＞
　次に、各コンタクトホール１３の内部及び層間絶縁膜１２上に、ソース電極１４及びドレイン電極１５を形成する。ソース電極１４及びドレイン電極１５は、例えば、フォトリソグラフィ法及びドライエッチング等により形成し、コンタクトホール１３を介して、ソース電極１４をソース領域２ａ，４ａに接続するとともに、ドレイン電極１５をドレイン領域２ｂ，４ｂに接続する。 <Source electrode / drain electrode formation process>
Next, the source electrode 14 and the drain electrode 15 are formed inside each contact hole 13 and on the interlayer insulating film 12. The source electrode 14 and the drain electrode 15 are formed by, for example, photolithography and dry etching, and the source electrode 14 is connected to the source regions 2a and 4a through the contact holes 13, and the drain electrode 15 is connected to the drain region 2b. , 4b.
　以上より、図１４に示す半導体装置５０が製造される。 Thus, the semiconductor device 50 shown in FIG. 14 is manufactured.
　（第４の実施形態）
　次に、本発明の第４の実施形態について説明する。図２７～図３３は、本発明の第４の実施形態に係る半導体装置の製造方法を説明するための断面図である。なお、上記第１～第３の実施形態と同様の構成部分については同一の符号を付してその説明を省略する。 (Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. 27 to 33 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. Note that the same components as those in the first to third embodiments are denoted by the same reference numerals and description thereof is omitted.
　上記第３の実施形態においては、半導体装置５０の製造工程において、ｎ型ＴＦＴ３を先に作製する構成としたが、本実施形態においては、ｐ型ＴＦＴ５を先に作製する点に特徴がある。 In the third embodiment, the n-type TFT 3 is manufactured first in the manufacturing process of the semiconductor device 50. However, the present embodiment is characterized in that the p-type TFT 5 is manufactured first.
　以下、本実施形態における半導体装置５０の製造方法について説明する。 Hereinafter, a method for manufacturing the semiconductor device 50 in the present embodiment will be described.
　まず、上述の第３の実施形態において説明した半導体膜形成工程、ゲート絶縁膜形成工程、及び導電層形成工程を行うことにより、図１９に示すように、ゲート絶縁膜１１上に、例えば、３５０ｎｍの厚みを有する導電層３５を形成する。 First, by performing the semiconductor film forming step, the gate insulating film forming step, and the conductive layer forming step described in the third embodiment, as shown in FIG. 19, on the gate insulating film 11, for example, 350 nm. A conductive layer 35 having a thickness of 1 mm is formed.
　＜第１のレジスト形成工程＞
　次いで、導電層３５上に、半導体膜２，４を覆うように、スピンコート法により、例えば、ポジ型の感光性樹脂（例えば、アクリル系の感光性樹脂）を厚さ１～３μｍ程度に塗布して設ける。そして、フォトマスク（不図示）を用いて感光性樹脂に対して照射される露光量を制御して露光処理を行い、露光処理が行われた感光性樹脂に対して現像処理を行うことにより、図２７に示すように、第１フォトレジスト５６と第２フォトレジスト５７とを同時に形成する。 <First resist forming step>
Next, on the conductive layer 35, for example, a positive photosensitive resin (for example, acrylic photosensitive resin) is applied to a thickness of about 1 to 3 μm by spin coating so as to cover the semiconductor films 2 and 4. Provide. Then, using a photomask (not shown) to control the exposure amount irradiated to the photosensitive resin to perform an exposure process, and by performing a development process on the photosensitive resin subjected to the exposure process, As shown in FIG. 27, a first photoresist 56 and a second photoresist 57 are formed simultaneously.
　なお、導電層３５上であって半導体膜２の上方に、第１フォトレジスト５６が形成されるとともに、導電層３５上であって半導体膜４の上方に、第２フォトレジスト５７が形成される。 A first photoresist 56 is formed on the conductive layer 35 and above the semiconductor film 2, and a second photoresist 57 is formed on the conductive layer 35 and above the semiconductor film 4. .
　＜第１のゲート電極形成工程＞
　次いで、図２７に示すように、第１フォトレジスト５６、及び第２フォトレジスト５７をマスクとして、ドライエッチング等により、導電層３５をエッチングして、ｐ型ＴＦＴ５を構成するゲート電極７を形成する。この際、図２７に示すように、ｐ型ＴＦＴ５側のゲート電極７となる導電層３５のみがパターニングされる。 <First gate electrode formation step>
Next, as shown in FIG. 27, the conductive layer 35 is etched by dry etching or the like using the first photoresist 56 and the second photoresist 57 as a mask to form the gate electrode 7 constituting the p-type TFT 5. . At this time, as shown in FIG. 27, only the conductive layer 35 to be the gate electrode 7 on the p-type TFT 5 side is patterned.
　＜ｐ型不純物注入工程＞
　次いで、ドライエッチング等により第１及び第２フォトレジスト５６，５７を除去した後、図２８に示すように、ゲート電極７をマスクとして、半導体膜４にｐ型不純物であるボロンを注入する。図２８に示す矢印４９は、ボロンを注入する方向を示している。なお、ボロンの注入には、イオンドーピング法等が用いられ、例えば、加速電圧を８０ｋＶにするとともに、ドーズ量を２×１０１５ｃｍ－２とする。そして、ボロンの注入により、図２８に示すように、ｐ型ＴＦＴ５が有する半導体膜４において、高濃度不純物領域であるソース領域４ａ及びドレイン領域４ｂが形成され、半導体膜４を備えるｐ型ＴＦＴ５が形成される。 <P-type impurity implantation step>
Next, after removing the first and second photoresists 56 and 57 by dry etching or the like, boron as a p-type impurity is implanted into the semiconductor film 4 using the gate electrode 7 as a mask as shown in FIG. An arrow 49 shown in FIG. 28 indicates the direction in which boron is injected. Note that ion doping or the like is used for boron implantation. For example, the acceleration voltage is set to 80 kV and the dose amount is set to 2 × 10 15 cm −2 . Then, as shown in FIG. 28, the source region 4a and the drain region 4b which are high concentration impurity regions are formed in the semiconductor film 4 included in the p-type TFT 5 by boron implantation, and the p-type TFT 5 including the semiconductor film 4 is formed. It is formed.
　なお、このｐ型不純物注入工程において、図２８に示すように、ｎ型ＴＦＴ３を構成する半導体膜２が導電層３５により覆われているため、半導体膜２の上方にフォトマスクを設ける必要がない。従って、剥離洗浄等により第１フォトレジスト５６を除去すればよく、当該第１フォトレジスト５６のアッシングが不要になるという利点を有する。 In this p-type impurity implantation step, as shown in FIG. 28, since the semiconductor film 2 constituting the n-type TFT 3 is covered with the conductive layer 35, it is not necessary to provide a photomask above the semiconductor film 2. . Therefore, the first photoresist 56 may be removed by peeling cleaning or the like, and ashing of the first photoresist 56 becomes unnecessary.
　＜第２のレジスト形成工程＞
　次いで、ゲート電極７及び導電層３５上に、半導体膜２，４を覆うように、スピンコート法により、例えば、ポジ型の感光性樹脂（例えば、アクリル系の感光性樹脂）を厚さ１～３μｍ程度に塗布して設ける。そして、フォトマスク（不図示）を用いて感光性樹脂に対して照射される露光量を制御して露光処理を行い、露光処理が行われた感光性樹脂に対して現像処理を行うことにより、図２９に示すように、第３フォトレジスト５８と第４フォトレジスト５９とを同時に形成する。 <Second resist formation step>
Next, on the gate electrode 7 and the conductive layer 35, for example, a positive photosensitive resin (for example, an acrylic photosensitive resin) is formed with a thickness of 1 to 4 by spin coating so as to cover the semiconductor films 2 and 4. It is applied by applying to about 3 μm. Then, using a photomask (not shown) to control the exposure amount irradiated to the photosensitive resin to perform an exposure process, and by performing a development process on the photosensitive resin subjected to the exposure process, As shown in FIG. 29, a third photoresist 58 and a fourth photoresist 59 are formed simultaneously.
　なお、図２９に示すように、導電層３５上であって半導体膜２の上方に、第３フォトレジスト５８が形成されるとともに、ｐ型ＴＦＴ５を覆うように、第４フォトレジスト５９が形成される。 As shown in FIG. 29, a third photoresist 58 is formed on the conductive layer 35 and above the semiconductor film 2, and a fourth photoresist 59 is formed so as to cover the p-type TFT 5. The
　＜エッチング工程＞
　次いで、図２９に示すように、第３フォトレジスト５８、及び第４フォトレジスト５９をマスクとして、ウェットエッチングにより、半導体膜２の上方に形成された導電層３５のエッチングを行う。 <Etching process>
Next, as shown in FIG. 29, the conductive layer 35 formed above the semiconductor film 2 is etched by wet etching using the third photoresist 58 and the fourth photoresist 59 as a mask.
　この際、上述のウェットエッチングによるサイドシフト（導電層３５に対して、垂直な方向だけではなく、平行な方向（図２９に示す矢印Ｘの方向）にもエッチングが進む現象）により、図２９に示すように、上述の第２の実施形態の場合と同様に、第１の実施形態において、変質層４４が形成されていた導電層３５の側面３５ａが第３フォトレジスト５８により覆われる（第３フォトレジスト５８の下方に隠れる）構成となる。 At this time, due to the above-described side shift by wet etching (a phenomenon in which etching proceeds not only in a direction perpendicular to the conductive layer 35 but also in a parallel direction (the direction of the arrow X shown in FIG. 29)), FIG. As shown, as in the case of the second embodiment described above, in the first embodiment, the side surface 35a of the conductive layer 35 on which the altered layer 44 has been formed is covered with a third photoresist 58 (third). (Hidden below the photoresist 58).
　＜ｎ型不純物注入工程＞
　次いで、図３０に示すように、第３フォトレジスト５８、及び第４フォトレジスト５９をマスクとして、半導体膜２に、ｎ型不純物（高濃度不純物）であるリンを注入する。図３０に示す矢印７０は、リンを注入する方向を示している。なお、リンの注入には、イオンドーピング法等が用いられ、例えば、加速電圧を５０ｋＶにするとともに、ドーズ量を２×１０１５ｃｍ－２とする。そして、リンの注入により、図３０に示すように、ｎ型ＴＦＴ３が有する半導体膜２において、高濃度不純物領域であるソース領域２ａ及びドレイン領域２ｂが形成される。 <N-type impurity implantation process>
Next, as shown in FIG. 30, phosphorus, which is an n-type impurity (high concentration impurity), is implanted into the semiconductor film 2 using the third photoresist 58 and the fourth photoresist 59 as a mask. An arrow 70 shown in FIG. 30 indicates a direction in which phosphorus is injected. Note that an ion doping method or the like is used for phosphorus implantation. For example, the acceleration voltage is set to 50 kV and the dose is set to 2 × 10 15 cm −2 . Then, as shown in FIG. 30, the source region 2a and the drain region 2b, which are high-concentration impurity regions, are formed in the semiconductor film 2 included in the n-type TFT 3 by phosphorus implantation.
　このように、本実施形態においては、上述の第２の実施形態と同様に、ウェットエッチング工程の後、ｎ型不純物注入工程を行った場合であっても、図３０に示すように、第３フォトレジスト５８が、導電層３５の側面３５ａを保護する保護層として機能し、導電層３５の側面３５ａにｎ型不純物が注入されにくくなる。従って、不純物注入による導電層３５の表面の変質を抑制することができる。その結果、ｎ型不純物注入工程において変質層４４の形成を抑制することが可能になる。 Thus, in the present embodiment, as in the second embodiment described above, even if the n-type impurity implantation step is performed after the wet etching step, as shown in FIG. The photoresist 58 functions as a protective layer that protects the side surface 35 a of the conductive layer 35, and n-type impurities are less likely to be injected into the side surface 35 a of the conductive layer 35. Therefore, the surface modification of the conductive layer 35 due to the impurity implantation can be suppressed. As a result, formation of the altered layer 44 can be suppressed in the n-type impurity implantation step.
　また、導電層３５のドライエッチングを行わないため、エッチング処理の際にゲート絶縁膜１１のエッチングを効果的に抑制することができる。従って、ゲート絶縁膜１１の膜厚の制御が容易になるため、ゲート絶縁膜１１の膜厚に対応させて、不純物をドーピングする際のドーピング条件を制御しやすくなる。 Further, since the conductive layer 35 is not dry etched, the etching of the gate insulating film 11 can be effectively suppressed during the etching process. Therefore, since the thickness of the gate insulating film 11 can be easily controlled, the doping conditions for doping impurities can be easily controlled according to the thickness of the gate insulating film 11.
　＜レジスト縮小工程＞
　次いで、第３及び第４フォトレジスト５８，５９に対してプラズマエッチングを行うことにより、図３１に示すように第３及び第４フォトレジスト５８，５９を等方的にエッチングして、第３及び第４フォトレジスト５８，５９を縮小する。 <Resist reduction process>
Next, by performing plasma etching on the third and fourth photoresists 58 and 59, the third and fourth photoresists 58 and 59 are isotropically etched as shown in FIG. The fourth photoresists 58 and 59 are reduced.
　この際、本実施形態においても、上述の第２の実施形態と同様に、上述のウェットエッチング工程において、仮に、導電層３５の側面３５ａに変質層４４が形成された場合であっても、レジスト縮小工程を行うため、導電層３５に形成された変質層を確実に除去することができる。 At this time, in this embodiment as well, as in the second embodiment described above, even if the altered layer 44 is formed on the side surface 35a of the conductive layer 35 in the wet etching process described above, Since the reduction process is performed, the altered layer formed on the conductive layer 35 can be reliably removed.
　また、第１の実施形態と異なり、上述のウェットエッチング工程において、変質層の形成を効果的に抑制することができるため、レジスト縮小工程において、変質層を除去しやすくなるという利点を有する。 Further, unlike the first embodiment, since the formation of the deteriorated layer can be effectively suppressed in the above-described wet etching process, there is an advantage that the deteriorated layer can be easily removed in the resist reduction process.
　＜第２のゲート電極形成工程＞
　次いで、第３フォトレジスト５８をマスクとして、導電層３５に対してウェットエッチングを行うことにより、図３２に示すように、ｎ型ＴＦＴ３を構成するゲート電極７を形成する。 <Second gate electrode formation step>
Next, wet etching is performed on the conductive layer 35 using the third photoresist 58 as a mask, thereby forming the gate electrode 7 constituting the n-type TFT 3 as shown in FIG.
　この際、上述のごとく、ｎ型不純物注入工程において形成された変質層４４が、上述のプラズマエッチングにより除去されているため、ｎ型不純物注入工程後にウェットエッチングを行った場合であっても、変質層４４に起因するウェットエッチングのバラツキ（即ち、ゲート電極７の幅のバラツキ）の発生を抑制することができる。従って、ウェットエッチングにより、所望のゲート電極７の形成が可能になる。 At this time, as described above, the altered layer 44 formed in the n-type impurity implantation step is removed by the above-described plasma etching. Therefore, even if wet etching is performed after the n-type impurity implantation step, the alteration layer 44 is changed. Generation of variations in wet etching (that is, variations in the width of the gate electrode 7) due to the layer 44 can be suppressed. Therefore, the desired gate electrode 7 can be formed by wet etching.
　なお、本工程においては、ウェットエッチングによるサイドシフト（導電層３５に対して、垂直な方向だけではなく、平行な方向（図３２に示す矢印Ｘの方向）にもエッチングが進む現象）により、ＬＤＤ領域形成工程において、マスクとして最適な幅を有するゲート電極７を自己整合的に得ることが可能になる。 In this step, LDD is caused by side shift by wet etching (a phenomenon in which etching proceeds not only in a direction perpendicular to the conductive layer 35 but also in a parallel direction (the direction of the arrow X shown in FIG. 32)). In the region forming step, the gate electrode 7 having an optimum width as a mask can be obtained in a self-aligning manner.
　また、本実施形態においては、上記従来技術とは異なり、ドライエッチングによりゲート電極を７形成するのではなく、導電層３５をウェットエッチングすることによりゲート電極７を形成する。従って、導電層３５が存在しない部分でゲート絶縁膜１１がエッチングされてしまい、ゲート絶縁膜１１が極端に薄くなってしまうという不都合の発生を防止することができる。従って、ゲート絶縁膜１１の膜厚を制御することができるため、結果として、不純物のドーピング不良に起因する活性化不良の発生を抑制することができる。 Also, in this embodiment, unlike the above-described conventional technique, the gate electrode 7 is formed by wet etching the conductive layer 35 instead of forming the gate electrode 7 by dry etching. Therefore, it is possible to prevent the disadvantage that the gate insulating film 11 is etched in a portion where the conductive layer 35 does not exist and the gate insulating film 11 becomes extremely thin. Therefore, the thickness of the gate insulating film 11 can be controlled, and as a result, it is possible to suppress the occurrence of activation failure due to impurity doping failure.
　＜ＬＤＤ領域形成工程＞
　次いで、ドライエッチング等により第３及び第４フォトレジスト５８，５９を除去した後、図３３に示すように、ゲート電極７をマスクとして、半導体膜２にｎ型不純物であるリンを注入する。図３３に示す矢印７１は、リンを注入する方向を示している。なお、リンの注入には、イオンドーピング法等が用いられ、例えば、加速電圧を８０ｋＶにするとともに、ドーズ量を２×１０１３ｃｍ－２とする。そして、リンの注入により、図３３に示すように、半導体膜２において、ＬＤＤ領域２ｄが形成され、ソース領域２ａ、ドレイン領域２ｂ、チャネル領域２ｃ、及びＬＤＤ領域２ｄからなる半導体膜２が形成されるとともに、半導体膜２を備えるｎ型ＴＦＴ３が形成されることになる。 <LDD region forming step>
Next, after removing the third and fourth photoresists 58 and 59 by dry etching or the like, phosphorus as an n-type impurity is implanted into the semiconductor film 2 using the gate electrode 7 as a mask as shown in FIG. An arrow 71 shown in FIG. 33 indicates the direction in which phosphorus is injected. Note that an ion doping method or the like is used for phosphorus implantation. For example, the acceleration voltage is set to 80 kV and the dose is set to 2 × 10 13 cm −2 . Then, by implantation of phosphorus, as shown in FIG. 33, the LDD region 2d is formed in the semiconductor film 2, and the semiconductor film 2 including the source region 2a, the drain region 2b, the channel region 2c, and the LDD region 2d is formed. At the same time, the n-type TFT 3 including the semiconductor film 2 is formed.
　＜コンタクトホール形成工程＞
　次いで、ゲート電極７及びゲート絶縁膜１１を覆う層間絶縁膜１２を形成した後、ソース領域２ａ，４ａ及びドレイン領域２ｂ，４ｂ上に、それぞれゲート絶縁膜１１及び層間絶縁膜１２を貫通するコンタクトホール１３を、例えば、エッチング等により形成する。 <Contact hole formation process>
Next, after forming an interlayer insulating film 12 covering the gate electrode 7 and the gate insulating film 11, contact holes penetrating the gate insulating film 11 and the interlayer insulating film 12 on the source regions 2a and 4a and the drain regions 2b and 4b, respectively. 13 is formed by etching, for example.
　＜ソース電極・ドレイン電極形成工程＞
　次に、各コンタクトホール１３の内部及び層間絶縁膜１２上に、ソース電極１４及びドレイン電極１５を形成する。ソース電極１４及びドレイン電極１５は、例えば、フォトリソグラフィ法及びドライエッチング等により形成し、コンタクトホール１３を介して、ソース電極１４をソース領域２ａ，４ａに接続するとともに、ドレイン電極１５をドレイン領域２ｂ，４ｂに接続する。 <Source electrode / drain electrode formation process>
Next, the source electrode 14 and the drain electrode 15 are formed inside each contact hole 13 and on the interlayer insulating film 12. The source electrode 14 and the drain electrode 15 are formed by, for example, photolithography and dry etching, and the source electrode 14 is connected to the source regions 2a and 4a through the contact holes 13, and the drain electrode 15 is connected to the drain region 2b. , 4b.
　以上より、図１４に示す半導体装置５０が製造される。 Thus, the semiconductor device 50 shown in FIG. 14 is manufactured.
　なお、上記実施形態は、イオンドーピング法により不純物を注入する構成としたが、本発明はこれに限られず、他の公知の方法により注入してもよい。 In addition, although the said embodiment was set as the structure which implants an impurity by the ion doping method, this invention is not restricted to this, You may implant | synthesize by another well-known method.
　本発明の活用例としては、薄膜トランジスタ等のスイッチング素子を備えた半導体装置の製造方法が挙げられる。 As an application example of the present invention, there is a method for manufacturing a semiconductor device provided with a switching element such as a thin film transistor.
　１　　半導体装置
　２　　半導体膜（第１半導体膜）
　２ａ　　ソース領域
　２ｂ　　ドレイン領域
　２ｃ　　チャネル領域
　２ｄ　　ＬＤＤ領域
　３　　ｎ型ＴＦＴ（ｎ型薄膜トランジスタ）
　４　　半導体膜（第２半導体膜）
　４ａ　　ソース領域
　４ｂ　　ドレイン領域
　４ｃ　　チャネル領域
　５　　ｐ型ＴＦＴ（ｐ型薄膜トランジスタ）
　６　　ガラス基板（基板）
　７　　ゲート電極
　１０　　下地絶縁膜（絶縁膜）
　１１　　ゲート絶縁膜
　１４　　ソース電極 
　１５　　ドレイン電極 
　３０　　アモルファスシリコン膜 
　３２　　ポリシリコン膜 
　３５　　導電層 
　３５ａ　　導電層の側面　
　４０　　フォトレジスト 
　４４　　変質層 
　５０　　半導体装置 
　５２　　第１フォトレジスト 
　５３　　第２フォトレジスト 
　５４　　第３フォトレジスト 
　５５　　第４フォトレジスト 
　５６　　第１フォトレジスト 
　５７　　第２フォトレジスト 
　５８　　第３フォトレジスト 
　５９　　第４フォトレジスト  DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor film (1st semiconductor film)
2a source region 2b drain region 2c channel region 2d LDD region 3 n-type TFT (n-type thin film transistor)
4 Semiconductor film (second semiconductor film)
4a source region 4b drain region 4c channel region 5 p-type TFT (p-type thin film transistor)
6 Glass substrate (substrate)
7 Gate electrode 10 Underlying insulating film (insulating film)
11 Gate insulating film 14 Source electrode
15 Drain electrode
30 Amorphous silicon film
32 Polysilicon film
35 Conductive layer
35a Side surface of conductive layer
40 photoresist
44 Altered layer
50 Semiconductor devices
52 First photoresist
53 Second photoresist
54 Third Photoresist
55 4th photoresist
56 First photoresist
57 Second photoresist
58 Third Photoresist
59 4th photoresist

Claims (7)

  1. 　半導体膜を有するｎ型薄膜トランジスタを基板上に備える半導体装置を製造する方法であって、
    　前記基板上に、前記半導体膜を形成する半導体膜形成工程と、
    　前記半導体膜上にゲート絶縁膜を形成するゲート絶縁膜形成工程と、
    　前記ゲート絶縁膜上に導電層を形成する導電層形成工程と、
    　前記導電層上にレジストを形成するレジスト形成工程と、
    　前記レジストをマスクとして、前記導電層に対してエッチングを行い、該導電層をパターニングするエッチング工程と、
    　 前記レジストをマスクとして、前記半導体膜にｎ型不純物を注入して、前記半導体膜にソース領域とドレイン領域を形成するｎ型不純物注入工程と、
    　プラズマエッチングを行うことにより、前記レジストを等方的に縮小するレジスト縮小工程と、
    　縮小した前記レジストをマスクとして、前記導電層に対してウェットエッチングを行うことにより、ゲート電極を形成するゲート電極形成工程と、
    　前記ゲート電極をマスクとして、前記半導体膜にｎ型不純物を注入して、前記半導体膜にＬＤＤ領域を形成するＬＤＤ領域形成工程と
    　を少なくとも備えることを特徴とする半導体装置の製造方法。     A method of manufacturing a semiconductor device comprising an n-type thin film transistor having a semiconductor film on a substrate,
    A semiconductor film forming step of forming the semiconductor film on the substrate;
    A gate insulating film forming step of forming a gate insulating film on the semiconductor film;
    A conductive layer forming step of forming a conductive layer on the gate insulating film;
    A resist forming step of forming a resist on the conductive layer;
    Etching the conductive layer using the resist as a mask and patterning the conductive layer; and
    Using the resist as a mask, implanting an n-type impurity into the semiconductor film to form a source region and a drain region in the semiconductor film;
    A resist reduction step of isotropically reducing the resist by performing plasma etching;
    A gate electrode forming step of forming a gate electrode by performing wet etching on the conductive layer using the reduced resist as a mask;
    And a step of forming an LDD region in the semiconductor film by injecting an n-type impurity into the semiconductor film using the gate electrode as a mask.
  2. 　前記エッチング工程におけるエッチングが、ウェットエッチングであることを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching in the etching step is wet etching.
  3. 　前記導電層が、モリブデン、タングステン、及びアルミニウムからなる群より選ばれる少なくとも１種を含むことを特徴とする請求項１または請求項２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive layer includes at least one selected from the group consisting of molybdenum, tungsten, and aluminum.
  4. 　前記半導体膜形成工程において、ポリシリコンにより前記半導体膜を形成することを特徴とする請求項１～請求項３のいずれか１項に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein, in the semiconductor film forming step, the semiconductor film is formed of polysilicon.
  5. 　前記ｐ型不純物がボロンであり、前記ｎ型不純物がリンであることを特徴とする請求項１～請求項４のいずれか１項に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 1, wherein the p-type impurity is boron and the n-type impurity is phosphorus.
  6. 　第１半導体膜を有するｎ型薄膜トランジスタと、第２半導体膜を有するｐ型薄膜トランジスタとを基板上に備える半導体装置を製造する方法であって、
    　前記基板上に、前記第１半導体膜及び前記第２半導体膜を形成する半導体膜形成工程と、
    　前記第１半導体膜上及び前記第２半導体膜上にゲート絶縁膜を形成するゲート絶縁膜形成工程と、
    　前記ゲート絶縁膜上に導電層を形成する導電層形成工程と、
    　前記導電層上であって前記第１半導体膜の上方に第１レジストを形成するとともに、前記導電層上であって前記第２半導体膜の上方に第２レジストを形成する第１のレジスト形成工程と、
    　前記第１レジスト及び前記第２レジストをマスクとして、前記導電層に対してエッチングを行い、該導電層をパターニングするエッチング工程と、
    　 前記第１レジスト及び前記第２レジストをマスクとして、前記第１半導体膜にｎ型不純物を注入して、前記第１半導体膜にソース領域とドレイン領域を形成するｎ型不純物注入工程と、
    　プラズマエッチングを行うことにより、前記第１レジストを等方的に縮小するレジスト縮小工程と、
    　縮小した前記第１レジストをマスクとして、前記導電層に対してウェットエッチングを行うことにより、前記ｎ型薄膜トランジスタのゲート電極を形成する第１のゲート電極形成工程と、
    　前記ゲート電極をマスクとして、前記第１半導体膜にｎ型不純物を注入して、前記第１半導体膜にＬＤＤ領域を形成するＬＤＤ領域形成工程と、
    　前記ｎ型薄膜トランジスタを覆うように第３レジストを形成するとともに、前記導電層上であって前記第２半導体膜の上方に第４レジストを形成する第２のレジスト形成工程と、
    　前記第３レジスト及び前記第４レジストをマスクとして、前記導電層に対してエッチングを行うことにより、ｐ型薄膜トランジスタのゲート電極を形成する第２のゲート電極形成工程と、
    　前記第３レジスト及び前記第４レジストをマスクとして、前記第２半導体膜にｐ型不純物を注入して、前記第２半導体膜にソース領域とドレイン領域を形成するｐ型不純物注入工程と
    　を少なくとも備えることを特徴とする半導体装置の製造方法。     A method of manufacturing a semiconductor device comprising an n-type thin film transistor having a first semiconductor film and a p-type thin film transistor having a second semiconductor film on a substrate,
    A semiconductor film forming step of forming the first semiconductor film and the second semiconductor film on the substrate;
    Forming a gate insulating film on the first semiconductor film and the second semiconductor film; and
    A conductive layer forming step of forming a conductive layer on the gate insulating film;
    A first resist forming step of forming a first resist on the conductive layer and above the first semiconductor film, and forming a second resist on the conductive layer and above the second semiconductor film When,
    Etching to etch the conductive layer using the first resist and the second resist as a mask and pattern the conductive layer; and
    Using the first resist and the second resist as a mask, implanting an n-type impurity into the first semiconductor film to form a source region and a drain region in the first semiconductor film;
    A resist reduction step of isotropically reducing the first resist by performing plasma etching;
    A first gate electrode forming step of forming a gate electrode of the n-type thin film transistor by performing wet etching on the conductive layer using the reduced first resist as a mask;
    An LDD region forming step of forming an LDD region in the first semiconductor film by injecting an n-type impurity into the first semiconductor film using the gate electrode as a mask;
    Forming a third resist so as to cover the n-type thin film transistor, and forming a fourth resist on the conductive layer and above the second semiconductor film;
    A second gate electrode formation step of forming a gate electrode of a p-type thin film transistor by etching the conductive layer using the third resist and the fourth resist as a mask;
    At least a p-type impurity implantation step of implanting a p-type impurity into the second semiconductor film using the third resist and the fourth resist as a mask to form a source region and a drain region in the second semiconductor film. A method for manufacturing a semiconductor device.
  7. 　第１半導体膜を有するｎ型薄膜トランジスタと、第２半導体膜を有するｐ型薄膜トランジスタとを基板上に備える半導体装置を製造する方法であって、
    　前記基板上に、前記第１半導体膜及び前記第２半導体膜を形成する半導体膜形成工程と、
    　前記第１半導体膜上及び前記第２半導体膜上にゲート絶縁膜を形成するゲート絶縁膜形成工程と、
    　前記ゲート絶縁膜上に導電層を形成する導電層形成工程と、
    　前記導電層上であって前記第１半導体膜の上方に第１レジストを形成するとともに、前記導電層上であって前記第２半導体膜の上方に第２レジストを形成する第１のレジスト形成工程と、
    　前記第１レジスト及び前記第２レジストをマスクとして、前記導電層に対してエッチングを行うことにより、前記ｐ型薄膜トランジスタのゲート電極を形成する第１のゲート電極形成工程と、
    　前記第１レジスト及び前記第２レジストを除去した後、前記第１のゲート電極形成工程により形成されたゲート電極をマスクとして、前記第２半導体膜にｐ型不純物を注入して、前記第２半導体膜にソース領域とドレイン領域を形成するｐ型不純物注入工程と、
    　前記導電層上であって前記第１半導体膜の上方に第３レジストを形成するとともに、前記ｐ型薄膜トランジスタを覆うように第４レジストを形成する第２のレジスト形成工程と、
    　前記第３レジスト及び前記第４レジストをマスクとして、前記導電層に対してウェットエッチングを行い、該導電層をパターニングするエッチング工程と、
    　前記第３レジスト及び前記第４レジストをマスクとして、前記第１半導体膜にｎ型不純物を注入して、前記第１半導体膜にソース領域とドレイン領域を形成するｎ型不純物注入工程と、
    　プラズマエッチングを行うことにより、前記第３レジストを等方的に縮小するレジスト縮小工程と、
    　縮小した前記第３レジストをマスクとして、前記導電層に対してウェットエッチングを行うことにより、前記ｎ型薄膜トランジスタのゲート電極を形成する第２のゲート電極形成工程と、
    　前記第２のゲート電極形成工程により形成されたゲート電極をマスクとして、前記第１半導体膜にｎ型不純物を注入して、前記第１半導体膜にＬＤＤ領域を形成するＬＤＤ領域形成工程と
    　を少なくとも備えることを特徴とする半導体装置の製造方法。     A method of manufacturing a semiconductor device comprising an n-type thin film transistor having a first semiconductor film and a p-type thin film transistor having a second semiconductor film on a substrate,
    A semiconductor film forming step of forming the first semiconductor film and the second semiconductor film on the substrate;
    Forming a gate insulating film on the first semiconductor film and the second semiconductor film; and
    A conductive layer forming step of forming a conductive layer on the gate insulating film;
    A first resist forming step of forming a first resist on the conductive layer and above the first semiconductor film, and forming a second resist on the conductive layer and above the second semiconductor film When,
    Forming a gate electrode of the p-type thin film transistor by etching the conductive layer using the first resist and the second resist as a mask;
    After removing the first resist and the second resist, a p-type impurity is implanted into the second semiconductor film using the gate electrode formed in the first gate electrode formation step as a mask, and the second semiconductor A p-type impurity implantation step for forming a source region and a drain region in the film;
    Forming a third resist on the conductive layer and above the first semiconductor film, and forming a fourth resist so as to cover the p-type thin film transistor;
    An etching step of performing wet etching on the conductive layer using the third resist and the fourth resist as a mask, and patterning the conductive layer;
    Using the third resist and the fourth resist as a mask, implanting an n-type impurity into the first semiconductor film to form a source region and a drain region in the first semiconductor film;
    A resist reduction step of isotropically reducing the third resist by performing plasma etching;
    A second gate electrode forming step of forming a gate electrode of the n-type thin film transistor by performing wet etching on the conductive layer using the reduced third resist as a mask;
    At least an LDD region forming step of forming an LDD region in the first semiconductor film by injecting an n-type impurity into the first semiconductor film using the gate electrode formed in the second gate electrode forming step as a mask. A method for manufacturing a semiconductor device, comprising:
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003282880A (en) * 2002-03-22 2003-10-03 Hitachi Displays Ltd Display
JP2007258453A (en) * 2006-03-23 2007-10-04 Toshiba Matsushita Display Technology Co Ltd Thin-film transistor and method of fabricating the same
JP2010212673A (en) * 2009-02-13 2010-09-24 Semiconductor Energy Lab Co Ltd Transistor and semiconductor device with the same, and method of manufacturing the transistor and semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003282880A (en) * 2002-03-22 2003-10-03 Hitachi Displays Ltd Display
JP2007258453A (en) * 2006-03-23 2007-10-04 Toshiba Matsushita Display Technology Co Ltd Thin-film transistor and method of fabricating the same
JP2010212673A (en) * 2009-02-13 2010-09-24 Semiconductor Energy Lab Co Ltd Transistor and semiconductor device with the same, and method of manufacturing the transistor and semiconductor device

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