WO2013067958A1

WO2013067958A1 - Headset circuit

Info

Publication number: WO2013067958A1
Application number: PCT/CN2012/084362
Authority: WO
Inventors: 陈锋; 奚剑雄
Original assignee: 杭州硅星科技有限公司
Priority date: 2011-11-11
Filing date: 2012-11-09
Publication date: 2013-05-16
Also published as: CN102395084B; CN102395084A

Abstract

Disclosed is a headset circuit comprising a headset interface circuit, an audio codec/baseband processor, and a control software module. The headset interface circuit comprises: a voltage converter module, a clock shaping and generator circuit, and a function switching module. The present invention adds to the headset interface circuit the voltage converter module, the clock shaping and generator circuit, and the function switching module, and uses five control signals to control states of seven switches of the function switching module, while at the same time, uses the control software module to control a working state in the audio codex/baseband processor. This, on the basis of a conventional headset and headset interface, without modification of any hardware such as the audio codex/baseband processor but with modification of a control software only, allows the present invention to extract electricity and clock via the headset interface circuit and an externally-connected circuit, thus allowing for the provision of power supply and clock to a large number of peripherals, and for extended set of headset functions.

Description

Headset circuit

The present invention relates to an audio device, and more particularly to a headset circuit. Background technique

Headsets, as the name suggests, are the integration of headphones and microphones. Currently, with the development of audio devices, headsets are widely used, games, music, video, and it is ubiquitous.

Currently, the headset circuit in the prior art generally includes an audio codec/baseband processor and a headset excuses, wherein the audio codec/baseband processor drives the external earphone and the microphone through the headset interface to realize the input and output of the sound signal. . However, prior art headset circuits tend to have only conventional headset functions, failing to extend the functionality of the headset, and limiting the use of the headset.

In summary, it can be seen that the prior art headset circuit has the problem that the headset function cannot be expanded. Therefore, it is necessary to propose an improved technical means to solve this problem. Summary of the invention

In order to overcome the problem that the prior art headset circuit cannot expand the function of the headset, the main object of the present invention is to provide a headset circuit which can be based on the traditional headset and headset interface without changing any audio codec/baseband. Hardware such as a processor, only changing the control software, extracting power and clock through the headset interface and external circuit, can provide power and clock to a large number of peripherals, and expand the function of the headset.

To achieve the above and other objects, the present invention provides a headset circuit including a headset interface circuit, an audio codec/baseband processor, and a control software module. The headset interface circuit includes at least: a voltage conversion module connected to a function switching module Converting, by the function switching module, a clock signal generated by the control software module and processed by the audio codec/baseband processor into a DC voltage output, wherein when the clock signal frequency is zero, the clock The signal is always high Level

a clock shaping and generating circuit is connected to the function switching module to process a clock signal generated by the control software module and processed by the audio codec/baseband processor under the control of the function switching module to generate a new clock signal Output;

The function switching module is connected to the external earphone and the microphone, and is connected to the audio codec/baseband processor through a headset plug module for realizing state switching.

The headset circuit controls the state of the control audio codec/baseband processor by using the function switching of the function switching module, and simultaneously controls switching between different functions.

Further, the headset circuit realizes the traditional headset function, the dual-end mode of the headphone port generates the power and the clock function, the independent single-ended input of the headphone port generates the power and the independent single-ended input generates the clock function, and the headphone port generates the power and the clock separately. Keep switching between mono headset functions.

Further, the voltage conversion module is an AC to DC voltage conversion module.

Further, the function switching module implements state switching by turning on and off of the plurality of control switches. Further, the function switching module includes a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, and a seventh control controlled by the first to fifth control signals. a control switch, the first control switch is disposed between the headset plug module and the right channel earphone, the second control switch is disposed between the headset plug module and the left channel earphone, and the fifth control switch is connected to the left end The other end is connected to one end of the first control switch connected to the headset plug module, and the other end of the third control switch is connected to one end of the first control switch connected to the headset plug module, and the other end is connected to the voltage The conversion module and the clock shaping and generating circuit are grounded through the sixth control switch, and one end of the fourth control switch is connected to one end of the second control switch connected to the headset plug module, and the other end is connected to the voltage conversion module and The clock shaping and generating circuit is grounded through the seventh control switch.

Further, the first control signal controls the first control switch and the sixth control switch, the first The second control signal is used to control the second control switch and the seventh control switch, the third control signal controls the third control switch, the fourth control signal controls the fourth control switch, and the fifth control signal controls the first Five control switches.

Further, between the first control signal and the third control signal, the second control signal and the fourth control signal are in an inverse relationship, and the fifth control signal is the fourth control signal and the first control The signals are combined.

Further, the headset circuit controls the second control signal to be a high level, the first control signal is a high level, the fourth control signal is a low level, and the third control signal is a low level by the control software module The fifth control signal is low and the traditional headset function is switched.

Further, the headset circuit controls the second control signal to be a low level, the first control signal is a low level, the fourth control signal is a high level, and the third control signal can be switched by the control software module. .

Further, the headset circuit controls the second control signal to be a low level by the control software module, the first control signal is a low level, the fourth control signal is a high level, and the second control signal is a high level Ping, the fifth control signal is low, and the negative input of the voltage conversion module is valid, the positive input input does not respond, and the positive input of the clock shaping and generating circuit is valid, and the negative input does not respond. The independent single-ended input of the headphone port generates power and the independent single-ended input generates the switching function of the clock function.

Further, the headset circuit controls the second control signal to be a low level, the first control signal is a high level, the fourth control signal is a high level, and the third control signal is a low level by the control software module The fifth control signal is at a high level to realize the switching of the headphone port in a separate manner to generate power and clock while retaining the function of the mono headset.

Further, the clock shaping and generating circuit processes the input clock signal, and outputs a new clock signal that shapes the input clock signal and a new clock signal that multiplies the input clock signal. Further, the headset circuit can be configured to communicate with the host device using the DC voltage and the new clock signal, and the headset circuit uses the control software module to generalize the audio codec/baseband processor. The input/output interface is configured to meet a data port required by the specified bus, and the output of the left channel power amplifier and/or the right channel power amplifier is configured by the control software module to be a clock and/or a divided clock that specifies the bus requirement. .

Compared with the prior art, the headset circuit of the present invention controls the state of the seven switches of the function switching module by using five control signals by adding a voltage conversion module, a clock shaping and generating circuit, and a function switching module in the headset interface circuit. The control software module is used to control the working state in the audio codec/baseband processor, so that the invention can be based on the traditional headset and headset interface, without changing any audio codec/baseband processor and other hardware, only changing the control software. The power and clock are extracted through the headset interface circuit and the external circuit, which can provide power and clock to a large number of peripherals, and expand the function of the headset. DRAWINGS

1 is a circuit structural diagram of a preferred embodiment of a headset circuit of the present invention;

2 is a conventional headset circuit configured by FIG. 1;

3 is a circuit for generating a power source and a clock in a double-ended manner according to FIG. 1;

FIG. 4 is a single-ended input power supply and a single-ended input clock generating circuit which are changed by FIG. 3; FIG. 5 is a single-ended power supply and clock circuit configured by FIG. detailed description

The embodiments of the present invention will be described by way of specific examples and the accompanying drawings, and those skilled in the art can readily understand the advantages and advantages of the present invention. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. 1 is a circuit structural diagram of a preferred embodiment of a headset circuit of the present invention. As shown in FIG. 2, the headset circuit of the present invention can realize the input and output of the sound signal through the external earphone and the microphone, and can realize the switching between the traditional headset function and the energy extracted by the earphone and the clock function, which at least includes : a headset interface circuit 11, an audio codec/baseband processor 12, and a control software module 13.

The headset interface circuit 11 includes a voltage conversion module 110, a clock shaping and generating circuit 111, a function switching module 112, and a headset plug module 113. The voltage conversion module 110 is a module for converting an alternating current voltage into a direct current voltage, which is used for switching. Under the control of the function module 112, the clock signal generated by the control software module 13 and processed by the audio codec/baseband processor 12 is converted into a DC voltage VDDL; the clock shaping and generating circuit 111 is used to switch the function module. Under the control of 112, the control software module 13 generates and processes a clock signal processed by the audio codec/baseband processor 12 to generate a new clock signal; the switching function module 112 is connected to the voltage conversion module 110, clock shaping and The generating circuit 111, the earphone, the microphone, and the audio codec/baseband processor 12 are connected through the headset plug module 112, and the audio codec/baseband processor 12 is controlled by the state switching of the function switching module 112 and simultaneously using the control software 13. Working status, can achieve two functions Switching.

In a preferred embodiment of the present invention, the function switching module 112 includes first to seventh control switches (K1-K7), wherein the first to seventh control switches are controlled by five control signals, that is, the first control signal CTRL- R controls the first control switch K1 and the sixth control switch K6, the second control signal CTRL-L is used to control the second control switch K2 and the seventh control switch K7, and the third control signal controls CTRL-RB to control the third control switch K3 The fourth control signal CTRL_LB controls the fourth control switch Κ4, and the fifth control signal CTRL_LB&CTRL-R controls the fifth control switch K5, wherein the first control switch K1 is disposed between the headset plug module 112 and the right channel earphone The second control switch K2 is disposed between the headset plug module 112 and the left channel earphone, the fifth control switch K5 is connected to the left channel earphone, and the other end is connected to the first control switch K1 and the headset plug module 112. One end, third control switch One end of the K3 is connected to one end of the first control switch K1 and the headset plug module 112, and the other end is connected to the voltage conversion module 110 and the clock shaping and generating circuit 111, and is grounded through the sixth control switch Κ6, and the fourth control switch Κ4 is connected at one end. The second control switch Κ2 is connected to the headset plug module 112, and the other end is connected to the voltage conversion module 110 and the clock shaping and generating circuit 111, and is grounded through the seventh control switch Κ7. Thus, the function switching module 112 is switched. First to fifth control signals (CTRL-R, CTRL-L, CTRL-RB, CTRL-LB, and CTRL-LB&CTRL-R) control the first to seventh control switches (K1-K7) states, while controlling the software module 13 By controlling the operating state within the audio decoder/baseband processor 12, switching between the two functions is achieved.

The working principle of the present invention will be further described below with reference to FIG. 1. For the audio decoder/baseband processor 12 part, the amplifier (AMPB) realizes the output of the microphone bias voltage, and controls the working state through the internal register, FIG. 1 shows the AMPB. The control signal of the internal register is abstracted into CB. For convenience of explanation, when CB is high, AMPB is turned off, and MICBIAS is set to high impedance. When CB is low, AMPB is turned on, and VDD voltage is regulated. After output to the MICBIAS„ Programmable Gain Amplifier (PGA), the electrical signal of the AIN microphone is amplified, and then input to an analog-to-digital converter (ADC). The power amplifier (AMPL) realizes the external left-channel headphone coil. The electric drive controls the working state through the internal register, and abstracts the control signal of the internal memory of the left channel power amplifier into CL. When the CL high level is specified, the power amplifier of the left channel is turned off, and the output HPLOUT is set. High impedance, CL low, the left channel power amplifier is turned on, puts the internal left channel digital-to-analog converter (Left The signal VSIGL from Ch DAC is driven to the output HPLOUT. The power amplifier (AMPR) realizes the electric drive of the external right-channel earphone coil, controls the working state through the internal register, and abstracts the control signal of the internal register of the right channel power amplifier. In CR, when the CR level is specified, the right channel power amplifier is turned off, and the output HPROUT is set to a high impedance state. When the CR level is low, the right channel power amplifier is turned on, and the right channel number is turned on. The signal VSIGR from the analog converter (Right Ch DAC) is driven to the output HPROUT. In Figure 1, RB is the resistor for biasing the microphone port, and C1 is for the microphone. Into the isolated DC, the GPIO port is used to input and output data through the microphone port, CL provides the blocking for the left channel headphone output, of course, in some applications, there may be no CL, CR is for the right channel The headphone output provides for blocking. In some applications, there is no CR. The control software module 13 is used to control the audio codec/baseband processor to implement traditional headset functions and to switch energy and clock functions with headphones. For the headset interface circuit 11 part, the first to seventh control switches (K1) are controlled by switching the first to fifth control signals (CTRL_R, CTRL_L, CTRL_RB, CTRL_LB, CTRL-LB&CTRL-R) -K7) The state simultaneous control software module 13 controls the operating state in the audio codec/baseband processor 12, and can switch between the two functions, where the first to seventh control switches can be physical switches, such as electrical switches. The mechanical switch can also be a switch that is equivalent to everything. The ACDC CONV is an AC to DC voltage conversion module 110, and VDDL is a local power supply. CLK GEN is a clock shaping and generating circuit 111. CLKBUF is the shaping of the input clock signal. CLKHS is a multiplication of the input clock signal. Of course, it can also generate more output frequency clocks. The clock generated by CLKGEN includes but is not limited to CLKBUF and CLKHS, where VDDL, CLKBUF and CLKHS can be used to build many practical application circuits.

2 is a conventional headset circuit configured by FIG. The 12-end configuration of the audio codec/baseband processor is as follows: CB low level, AMPB open, MICBIAS port has microphone bias voltage, MICBIAS connection RB provides bias to MIC point, while MIC point reaches AIN via C1, The audio electrical signal from the microphone is passed to the input of the PGA, and the output of the PGA is connected to the input of the ADC. The CL low level AMPL is turned on, and the internal left channel audio signal reaches the VSIGL point via the Left Ch DAC, then reaches the HPLOUT point via AMPL and then reaches the HPL point via CL. The CR 氐 level AMPR is turned on, and the internal right channel audio signal reaches the VSIGR point via the Right Ch DAC, then reaches the HPROUT point via the AMPR and reaches the HPR point via the CR. The configuration of the headset interface circuit 11 is as follows: First, five control signals of the first to seventh control switches (first to fifth control signals CTRL_R, CTRL_L, CTRL_RB, CTRL_LB, CTRL-LB&CTRL) — R ) is correlated between the first control signal CTRL R and the third control signal CTRL RB Is a negation relationship, the second control signal CTRL_L is in inverse relationship with the fourth control signal CTRL_LB, and the fifth control signal CTRL_LB&CTRL_R is the fourth control signal CTRL_LB and the first control signal CTRL — R phase is formed. For convenience of explanation, the high and low levels of the abstracted switch control signal are used to describe the closing and opening of the switch. The high level control signal is specified to be closed, and the low level control signal is correspondingly disconnected. The second control signal CTRL_L is at a high level, and the first control signal CTRL_R is at a high level, and accordingly, the fourth control signal CTRL_LB is at a low level, and the third control signal CTRL RB is at a low level. The fifth control signal CTRL_LB&CTRL-R is at a low level. Therefore, the equivalent circuit is as shown in FIG. 2, that is, FIG. 2 is a headset circuit having a conventional headset function configured by the configuration of the present invention.

3 is a circuit for generating a power supply and a clock in the double-ended manner of FIG. The audio codec/baseband processor 12-side configuration is as follows: CB level, AMPB on, MICBIAS port has microphone bias voltage, MICBIAS connection RB provides bias to MIC point, while MIC point reaches AIN via C1, The audio signal from the microphone is passed to the input of the PGA, and the output of the PGA is connected to the input of the ADC. The CL low level AMPL is turned on, the internal left channel does not take the audio signal, and the control software generates the AC clock signal, which reaches the VSIGL point via the Left Ch DAC, then reaches the HPLOUT point via the AMPL and then reaches the HPL point via the CL, CR The low-level AMPR is turned on, and the internal right channel does not take the audio signal. The control software generates an AC clock signal, which reaches the VSIGR point via the Right Ch DAC, reaches the HPROUT point via the AMPR, and reaches the HPR point via the CR. The 11-end configuration of the headset interface is as follows: The second control signal CTRL_L is low level, the first control signal CTRG-R is low level, then correspondingly, the fourth control signal CTRL-LB is high level, the third control The signal CTRL-RB is high, the fifth control signal CTRL-LB&CTRL-R is 氐 level, ACDC CONV is the voltage conversion module of the double-ended AC input to the DC output, VDDL is the local power supply, CLK GEN is the clock shaping and generation The circuit, CLKBUF is the shaping of the double-ended input clock signal, CLKHS is the multiplication of the input clock signal, therefore, the equivalent circuit is shown in Figure 3. That is: Figure 3 is the headphone port double-ended mode to generate power VDDL And the equivalent circuit of the clock CLKBUF, CLKHS, the advantage of the double-ended mode power supply is that it can get stronger driving ability than single-ended.

FIG. 4 is an independent single-ended input power supply and a single-ended input clock generation circuit of FIG. The audio codec/baseband processor 12-end configuration is the same as the circuit configuration corresponding to FIG. 3, and the configuration of the headset interface 11 end is the same as that of FIG. 3, except that the ACDC CONV of the double-ended input in FIG. 3 is changed to ACDC CONV with single-ended input, although there are two wires connected to the ACDC CONV, only one of them works, and the CLK GEN of the double-ended input in Figure 3 is changed to the CLK GEN of the single-ended input. Specifically, instead of using one earphone cable to generate power independently, the other earphone cable independently generates a clock. The audio codec/baseband processor 12-side configuration is as follows: CB low level, AMPB open, MICBIAS port has microphone bias voltage, MICBIAS connection RB provides bias to MIC point, while MIC point reaches AIN via C1, The audio electrical signal from the microphone is passed to the input of the PGA, and the output of the PGA is connected to the input of the ADC. The CL low level AMPL is turned on, the internal left channel does not take the audio signal, and the control software generates an AC clock signal, which reaches the VSIGL point via the Left Ch DAC, then reaches the HPLOUT point via the AMPL and then reaches the HPL point via the CL. The CR low level AMPR is turned on, the internal right channel does not take the audio signal, and the control software module 13 generates an AC clock signal, which reaches the VSIGR point via the Right Ch DAC, reaches the HPROUT point via the AMPR, and reaches the HPR point via the CR. . It should be noted that when the clock signal frequency is 0, that is, the clock signal is a high-current current level, at this time, the corresponding DC blocking capacitor CR is short-circuited, and the ACDC CONV module only needs to convert the DC voltage into a DC voltage output. . The 11-end configuration of the headset interface is as follows: The second control signal CTRL_L and the first control signal CTRL-R are low level, then correspondingly, the fourth control signal CTRL_LB is high level, and the second control signal CTRL_RB High level, the fifth control signal CTRL-LB&CTRL-R is low level, the negative input of ACDC CONV is specified to be valid, and the positive input of ACDC CONV specifies that ACDC CONV does not respond, that is, external connection to ACDC CONV The positive terminal is disconnected from the internal circuit. Similarly, the positive input of CLK GEN is valid and the negative input is not responding. Therefore, the equivalent circuit is shown in Figure 4. Figure 4 is the headset The port independent single-ended input HPR generates the power supply VDDL and the independent single-ended input HPL generates the equivalent circuit of the clocks CLKBUF, CLKHS. (Note, HPR and HPL are interchangeable here, Figure 4 is one of two implementations.) The benefit of independent power and clock generation is the higher quality of the clock and power supply.

Figure 5 is a single-ended power supply and clock circuit configured in Figure 1, while retaining the monophonic headphone function. The audio codec/baseband processor 12-side configuration is as follows: CB low level, AMPB open, MICBIAS port has microphone bias voltage, MICBIAS connection RB provides bias to MIC point, while MIC point reaches AIN via C1, The audio signal from the microphone is input to the input of the PGA, and the output of the PGA is connected to the input of the ADC, the CL 氐 level AMPL is turned on, the internal left channel does not take the audio signal, and the control software module 13 generates an AC clock signal. This signal reaches the VSIGL point via the Left Ch DAC, then reaches the HPLOUT point via AMPL and then reaches the HPL point via CL. CR low level AMPR is turned on, the internal right channel still goes the audio signal, this signal reaches the VSIGR point via the Right Ch DAC, then reaches the HPROUT point via AMPR and then reaches the HPR point via CR (the left and right channels are interchangeable here) , for the sake of explanation, a possible way is chosen). The terminal end of the headset interface circuit 11 is configured as follows: The second control signal CTRL_L is low level, and the first control signal CTRL_R is high level, then correspondingly, the fourth control signal CTRL_LB is high level, third The control signal CTRL-RB is low, and the fifth control signal CTRL-LB&CTRL-R is high. Therefore, the equivalent circuit is shown in FIG. Figure 5 shows the equivalent circuit for generating the power supply VDDL and the clocks CLKBUF and CLKHS in a separate manner, while preserving the mono headphone function.

Here, it should be noted that the functional circuits corresponding to FIG. 3, FIG. 4 and FIG. 5 can be configured to utilize the bus communication between the external devices of VDDL, CLKBUF, and CLKHS and the host. Specifically, the GPIO port of the audio codec/baseband processor 12 is configured by the control software module 13 to conform to the data port of the specified bus requirement, and the HPLOUT and/or HPROUT are configured to the specified bus requirements by the control software module 13. Clock and/or divided clock, so that the bus is available The physical basis of communication, there are synchronous clocks, power supplies, and bidirectional data lines with input and output. It can be configured as an I2C-compatible bus, as well as a bus compatible with a two-wire bus, or as a bus.

In summary, the headset circuit of the present invention increases the voltage conversion module, the clock shaping and generating circuit, and the function switching module in the headset interface circuit, and controls the state of the seven switches of the function switching module by using five control signals while using the control. The software module controls the working state in the audio codec/baseband processor, so that the invention can be based on the traditional headset and headset interface, without changing any hardware such as an audio codec/baseband processor, only changing the control software, The headset interface circuit and the external circuit extract power and clock, which can supply power and clock to a large number of peripherals, and expand the function of the headset.

The above-described embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

Rights request

A headset circuit, comprising a headset interface circuit, an audio codec/baseband processor, and a control software module, wherein the headset interface circuit comprises at least:

The voltage conversion module is connected to a function switching module, and the clock signal generated by the control software module and processed by the audio codec/baseband processor is converted into a DC voltage output under the control of the function switching module, wherein When the clock signal frequency is zero, the clock signal is a high level;

2. The headset circuit according to claim 1, wherein: the headset circuit implements a traditional headset function, a dual-end mode of the headphone port generates a power source and a clock function, and the headphone port independently generates a single-ended input to generate power and an independent single-ended input. The function of the clock and the separate way of the headphone port generate power and clock while maintaining the switching between the mono headphone functions.

3. The headset circuit of claim 2, wherein: the voltage conversion module is a voltage conversion module that is AC-DC.

4. The headset circuit according to claim 2, wherein: the function switching module implements state switching by switching on and off of the plurality of control switches.

5. The headset circuit according to claim 4, wherein: the function switching module includes a first control switch, a second control switch, a third control switch, and a fourth control switch controlled by the first to fifth control signals. a fifth control switch, a sixth control switch, and a seventh control switch, the first control switch is disposed between the headset plug module and the right channel earphone, and the second control switch is disposed on the headset plug module and the left channel Between the earphones, the fifth control switch is connected to the left channel earphone at one end, and the other end is connected to one end of the first control switch connected to the headset plug module, and the third control switch is connected at one end to the first control switch and the One end of the headset plug module is connected, the other end is connected to the voltage conversion module and the clock shaping and generating circuit, and is grounded through the sixth control switch, and the fourth control switch is connected at one end to the second control switch and the headset plug module a connected end, the other end being connected to the voltage conversion module and the clock shaping and generating circuit, and passing the seventh Switch system ground.

6. The headset circuit of claim 5, wherein: the first control signal controls the first control switch and the sixth control switch, the second control signal is used to control the second control switch and the seventh control a switch, the third control signal controls the third control switch, the fourth control signal controls the fourth control switch, and the fifth control signal controls the fifth control switch.

The headset circuit according to claim 6, wherein: the first control signal and the third control signal are in an inverse relationship between the second control signal and the fourth control signal, The five control signals are formed by the fourth control signal and the first control signal.

8. The headset circuit according to claim 7, wherein: the headset circuit controls the second control signal to be a high level, the first control signal is a high level, and the fourth control signal is controlled by the control software module. The low level, the third control signal is low level, and the fifth control signal is low level to realize switching of the traditional headset function.

The headset circuit according to claim 7, wherein: the headset circuit controls the second control signal to be a low level by the control software module, the first control signal is a low level, the first The four control signals are at a high level, the third control signal is at a high level, and the fifth control signal is at a low level, so that the headphone port double-end mode generates power and clock function switching.

The headset circuit according to claim 7, wherein: the headset circuit controls the second control signal to be a low level, the first control signal is a low level, and the fourth control signal is controlled by the control software module Is high level, the second control signal is high level, the fifth control signal is low level, and the negative input input of the voltage conversion module is specified to be valid, the positive input input is not responding, and the clock shaping is specified and The positive input of the generating circuit is valid, and the negative input does not respond to realize the switching of the clock function by the independent single-ended input of the headphone port and the independent single-ended input.

The headset circuit according to claim 7, wherein: the headset circuit controls the second control signal to be low level, the first control signal is high level, and the fourth control signal is The high level, the third control signal is a low level, and the fifth control signal is a high level, so that the headphone port generates a power source and a clock separately while maintaining the switching of the mono headphone function.

12. The headset circuit of claim 1 wherein: the clock shaping and generating circuit processes the input clock signal, outputs a new clock signal shaped for the input clock signal, and a new multiplier for the input clock signal Clock signal.

13. The headset circuit of claim 1 wherein: the headset circuit is configurable to communicate with a bus between an external device using the DC voltage and a new clock signal, the headset circuit passing the control software module Configuring the general basic input/output interface of the audio codec/baseband processor to a data port conforming to a specified bus requirement, and configuring the output of the left channel power amplifier and/or the right channel power amplifier through the control software module a clock that specifies the bus requirements and

(or) divided clock.