WO2013065493A1 - Impact detection and recording device - Google Patents

Impact detection and recording device Download PDF

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Publication number
WO2013065493A1
WO2013065493A1 PCT/JP2012/076908 JP2012076908W WO2013065493A1 WO 2013065493 A1 WO2013065493 A1 WO 2013065493A1 JP 2012076908 W JP2012076908 W JP 2012076908W WO 2013065493 A1 WO2013065493 A1 WO 2013065493A1
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Prior art keywords
voltage
ferroelectric
impact
ferroelectric memory
state
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PCT/JP2012/076908
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French (fr)
Japanese (ja)
Inventor
廣瀬　左京
靖浩 近藤
慎一郎 川田
睦弘 堀口
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株式会社村田製作所
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Priority to JP2013541698A priority Critical patent/JP5545417B2/en
Publication of WO2013065493A1 publication Critical patent/WO2013065493A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/09—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by piezoelectric pick-up
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P1/00—Details of instruments
    • G01P1/12—Recording devices
    • G01P1/127—Recording devices for acceleration values
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/0891—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values with indication of predetermined acceleration values
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02N—ELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
    • H02N2/00—Electric machines in general using piezoelectric effect, electrostriction or magnetostriction
    • H02N2/18—Electric machines in general using piezoelectric effect, electrostriction or magnetostriction producing electrical output from mechanical input, e.g. generators
    • H02N2/183—Electric machines in general using piezoelectric effect, electrostriction or magnetostriction producing electrical output from mechanical input, e.g. generators using impacting bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/30—Piezoelectric or electrostrictive devices with mechanical input and electrical output, e.g. functioning as generators or sensors
    • H10N30/302—Sensors

Definitions

  • the present invention relates to an impact detection / recording apparatus capable of detecting and recording an external impact, and more particularly to an impact detection / recording apparatus including a piezoelectric element and a ferroelectric memory.
  • Patent Document 1 discloses a piezoelectric vibration energy sensor including a charge generating piezoelectric body that converts vibration energy into electric energy and a ferroelectric memory that repeats polarization inversion by the generated charge.
  • the piezoelectric body When vibration such as impact is applied, the piezoelectric body generates electric charges. This charge reverses the polarization of the ferroelectric memory.
  • the polarization inversion When a large number of vibrations are repeatedly applied, the polarization inversion is repeated, and the residual polarization decreases due to fatigue.
  • the number of applied vibrations can be determined from the degree of decrease in remanent polarization. Since the piezoelectric body and the ferroelectric memory are provided, the number of vibrations applied without a power source can be measured.
  • the piezoelectric vibration energy sensor described in Patent Document 1 can measure the number of applied vibrations without a power source.
  • the number of vibrations is measured over a long period of time due to fatigue due to polarization reversal, ie, a decrease in residual polarization. Therefore, in Patent Document 1, even if a large impact is applied once, the single impact cannot be detected and recorded.
  • An object of the present invention is to provide an impact detection / recording device that does not require a power source, and can detect and record a single impact and hold it. .
  • An impact detection / recording apparatus converts an impact energy into electrical energy and outputs the piezoelectric element, and is connected to the piezoelectric element and has one main surface and the other main surface facing the one main surface.
  • the ferroelectric memory can record at least one of the first and second states derived from the electronic polarization of the ferroelectric.
  • the capacitance-voltage characteristic of the ferroelectric memory has hysteresis.
  • first and second electrodes are respectively formed on the one main surface side and the other main surface side of the ferroelectric is not limited to that each electrode is formed directly on the ferroelectric. Instead, it may be via a semiconductor or a buffer layer as in the embodiment.
  • an inversion voltage required to invert the ferroelectric memory from the first state to the second state is V 0
  • the second state is the second state.
  • the inversion voltage for inverting the first state when the V 1, V 0 ⁇ 0 ⁇ V 1 or V 0>0> is V 1.
  • the polarization state is reversed and recorded with time, and there is no possibility that information is lost.
  • the absolute value of the threshold voltage Vth of the ferroelectric memory is in a range of 0.5V to 3V. Within this range, the threshold voltage can be easily shifted from 0V to detect and record the impact, and the impact can be more reliably recorded by the charge generated by the piezoelectric element.
  • the ferroelectric memory further includes a semiconductor layer in which the ferroelectric is stacked between a second electrode.
  • a diode structure is formed by joining the ferroelectric and the semiconductor layer. Therefore, the threshold voltage Vth can be easily shifted from 0 by selecting the material constituting the diode structure.
  • a buffer layer is provided between the semiconductor layer and the ferroelectric.
  • the value of the threshold voltage Vth can be easily controlled by selecting the material and thickness of the buffer layer.
  • the inversion voltage V necessary for inversion from the first state to the second state since the threshold voltage Vth in the ferroelectric memory is shifted from 0V, the inversion voltage V necessary for inversion from the first state to the second state.
  • the absolute value of the inversion voltage V 1 necessary for inversion from 0 to the first state is different from 0. Therefore, when V 0 > V 1 or V 1 > V 0 , the initial state is set to the first state or the second state, and when an impact is applied, the state is switched to the second state or the first state. Thus, a single impact can be reliably recorded and held.
  • a single impact can be detected with no power source, and can be reliably recorded and held in the ferroelectric memory.
  • FIG. 1 is a front view showing a ferroelectric memory used in the impact detection / recording apparatus according to the first embodiment of the present invention.
  • FIG. 2 is a circuit diagram of the impact detection / recording apparatus according to the first embodiment of the present invention.
  • FIG. 3 is a diagram showing the capacitance-voltage characteristics of the ferroelectric memory used in the first embodiment of the present invention.
  • FIG. 4 is a diagram showing an X-ray diffraction profile of the ferroelectric frame manufactured in the first embodiment of the present invention.
  • FIG. 5 is a diagram for explaining the memory operation of the ferroelectric memory used in the impact detection / recording apparatus according to the first embodiment of the present invention.
  • FIG. 1 is a front view showing a ferroelectric memory used in the impact detection / recording apparatus according to the first embodiment of the present invention.
  • FIG. 2 is a circuit diagram of the impact detection / recording apparatus according to the first embodiment of the present invention.
  • FIG. 3 is a diagram showing the capacitance-voltage characteristics of
  • FIG. 6 is a diagram for explaining the threshold voltage Vth and the first and second inversion voltages in the impact detection / recording apparatus according to the first embodiment of the present invention.
  • FIG. 7 is a diagram showing the capacitance-voltage characteristics of the ferroelectric memory of the comparative example in which the threshold voltage V is 0V.
  • FIG. 8 is a schematic diagram showing a circuit configuration for evaluating the impact detection / recording apparatus according to the first embodiment of the present invention.
  • FIG. 9 is a schematic diagram for explaining an impact generation jig for measuring the descent of the impact detection / recording apparatus according to the first embodiment of the present invention.
  • FIG. 10 is a diagram showing impact recording results in an experimental example of the impact detection / recording apparatus according to the first embodiment of the present invention.
  • FIG. 11 is a diagram showing an impact recording result in an experimental example of the impact detection / recording apparatus of the first comparative example of the present invention.
  • FIG. 12 is a diagram showing impact recording characteristics when a ferroelectric memory of sample number 2 as a comparative example is used.
  • FIG. 13 is a diagram showing impact recording characteristics when a ferroelectric memory of Sample No. 2 as a comparative example is used.
  • FIG. 2 is a schematic configuration diagram of an impact detection / recording apparatus according to the first embodiment of the present invention.
  • the impact detection / recording apparatus 1 includes a piezoelectric element 2 and a ferroelectric memory 3.
  • the piezoelectric element 2 converts the applied impact energy into electrical energy and outputs it.
  • Examples of such piezoelectric elements include various piezoelectric elements that have been used as well-known impact sensors. For example, a bimorph type piezoelectric element, a unimorph type piezoelectric element, etc. can be mentioned.
  • the impact detection / recording apparatus 1 of the present embodiment includes a ferroelectric memory 3 connected in parallel to the piezoelectric element 2.
  • the ferroelectric memory 3 records and holds a single impact based on the electric energy applied from the piezoelectric element 2.
  • the structure of the ferroelectric memory 3 will be described with reference to FIG.
  • FIG. 1 is a front view of a ferroelectric memory 3 used in this embodiment.
  • the ferroelectric memory 3 has a ferroelectric thin film 4 as a ferroelectric layer.
  • the ferroelectric material constituting the ferroelectric thin film 4 is not particularly limited.
  • SrBi 2 Ta 2 O 9 , Pb (Zr, Ti) O 3 , (Bi, La) 4 Ti 3 O 12 , BiFeO 3 and the like can be mentioned.
  • the ferroelectric thin film 4 is made of SrBi 2 Ta 2 O 9 .
  • a first electrode 5 is formed on one main surface of the ferroelectric thin film 4.
  • the other main surface of the ferroelectric thin film 4 is laminated on the upper surface of the semiconductor substrate 6 with a buffer layer 7 interposed therebetween.
  • the semiconductor substrate 6 is made of an appropriate semiconductor that can form a diode junction with the ferroelectric thin film 4.
  • the semiconductor substrate 6 is made of Si.
  • the buffer layer 7 is provided in order to suppress deterioration due to mutual diffusion between the ferroelectric thin film 4 and the semiconductor substrate 6.
  • the material constituting the buffer layer 7 is not particularly limited, HfO x, Al 2 O 3 , etc. ZrO 2, CeO 2, LaAlO 3, or La 2 O 3 and the like.
  • the buffer layer 7 is made of HfO x (where x is about 2). What is necessary is just to select suitably the material which comprises the buffer layer 7 according to the ferroelectric material which comprises the ferroelectric thin film 4, the semiconductor material which comprises the semiconductor substrate 6, etc. FIG.
  • the threshold voltage described later can be controlled by selecting the material of the buffer layer 7.
  • the buffer layer made of a plurality of materials may be laminated, or a solid solution of a plurality of materials may be used, thereby making the threshold voltage Vth an appropriate value.
  • a second electrode 8 is formed on the lower surface of the semiconductor substrate 6, that is, on the other main surface side of the ferroelectric thin film 4. Therefore, the ferroelectric thin film 4 is sandwiched between the first electrode 5 and the second electrode 8.
  • the first electrode 5 and the second electrode 8 are formed at positions facing each other with the ferroelectric thin film 4 therebetween, but one main surface and the other main surface of the ferroelectric thin film 4 If a voltage can be applied between them, it is not always necessary to form them at positions facing each other.
  • the first electrode 5 and the second electrode 8 can be formed of an appropriate metal material.
  • the first electrode 5 and the second electrode 8 are made of Pt.
  • an appropriate metal or alloy such as Au, Ag, Al, Pd, Ir, or Cu, or an oxide such as SrRuO 3 , PtO x (where x is an integer of 1 to 3), IrO 2 , or PdO. Can be used.
  • the threshold voltage Vth described later can be adjusted by adjusting the materials of the first and second electrodes 5 and 8.
  • the first electrode 5 and the second electrode 8 are disposed so as to face each other with the ferroelectric thin film 4, the buffer layer 7 and the semiconductor substrate 6 therebetween.
  • the form of the two electrodes 5 and 8 facing each other via the ferroelectric thin film 4 is not limited to this.
  • the ferroelectric memory 3 it is necessary for the ferroelectric memory 3 to record and hold the impact based on the electrical energy given from the piezoelectric element 2. Therefore, as described below, the threshold voltage Vth is shifted from 0V. That is, Vth> 0 or Vth ⁇ 0, whereby a single impact can be recorded and held. Therefore, the ferroelectric thin film 4 is bonded to the semiconductor substrate 6 via the buffer layer 7, or the ferroelectric thin film 4 is directly stacked on the semiconductor substrate 6 to have the diode junction. It is desirable. Thereby, the threshold voltage Vth can be easily shifted from 0V.
  • FIG. 3 is a diagram showing the capacitance-voltage characteristics of the ferroelectric memory 3. As illustrated, the capacitance-voltage characteristic curve has hysteresis. That is, the curve at the time of voltage rise and the curve at the time of voltage drop are not coincident and are shifted.
  • the threshold voltage Vth is about 1.2V, and Vth> 0V.
  • the threshold voltage Vth refers to a voltage value at which the difference in capacitance is the largest between the curve at the time of voltage rise and the curve at the time of voltage drop in the hysteresis of the capacitance-voltage characteristic.
  • the applied voltage at the portion where the difference in applied voltage is the same with the same capacitance value between the curve at the time of voltage rise and the curve at the time of voltage drop is defined as a memory window.
  • the size of this memory window is 0.6V.
  • the capacitance increases to about 150 pF when the applied voltage is around -3V to -4V, and the applied voltage is + 2V. When it is about 4V, it can be seen that the capacitance is as low as about 14 pF.
  • the “0” state is a case where the electronic polarization of the ferroelectric thin film 4 is directed to the first electrode side
  • the “1” state is a state where the electronic polarization direction is directed to the semiconductor substrate 6 side. It corresponds.
  • polarization inversion can be caused by applying a voltage. That is, when a voltage is applied, the first state is “0” or the second state, ie, “1”, or the electronic polarization of the ferroelectric is completely “0” or “1”. In other words, an intermediate state in which most of the states are “0” and “1” can be obtained.
  • the voltage for switching to the first state that is, the state of “0” is the inverted voltage V 0, and the voltage for switching to the “1” state is the inverted voltage V 1 .
  • V 0 and V 1 exist at positions symmetrical with respect to the threshold voltage Vth.
  • the threshold voltage Vth is shifted to 1.2V instead of 0V. Therefore, V 0 is ⁇ 1V and V 1 is about + 4V. That is, the absolute values of the inversion voltage V 0 and the inversion voltage V 1 are different.
  • the reset voltage V 0 and the inverted voltage V 1 are reset so that the state of “1” having a high absolute value is set as the initial state. Even if it is left in the “1” state, it has a memory characteristic, so that state is maintained.
  • the first impact record is reliably maintained. That is, as described above, the threshold voltage Vth is shifted from 0 to 1.2 V in the hysteresis of the capacitance-voltage characteristics. Therefore, the stability of the “0” state and the “1” state are different. More specifically, a voltage having a small absolute value may be applied to make the state “0”, and a voltage larger than “0” is needed to make the state “1”. . In other words, a larger voltage is required to return to the “1” state.
  • the voltage that can be extracted by the piezoelectric effect by the piezoelectric element is usually about 3 V or less in the piezoelectric element used in this type of impact sensor. Therefore, even after a large impact is applied once as described above after being reset to the “1” state, the electric energy from the piezoelectric element 2 is reset even if the state is reset to the “0” state or an intermediate state between the two states. Then, a large voltage that cannot be reset to the “1” state is required. Therefore, even if a large impact is recorded in the ferroelectric memory 3 and then a plurality of impacts are applied to the piezoelectric element 2 a plurality of times, the recording due to the one impact described above is not erased.
  • the present embodiment it is possible to detect a single impact with no power source, and to record and hold the impact. Further, even if a large number of impacts are applied later, it is not reset, and the ferroelectric memory 3 is not reset without applying a reset voltage from the outside. Therefore, according to the present embodiment, it is possible to record and hold that a large impact that causes a failure is applied to, for example, an electronic device in which the impact detection / recording apparatus of the present embodiment is mounted. As a result, it is possible to reliably detect and record the occurrence of a large impact caused by use or an accident that would normally not be considered.
  • a general ferroelectric memory uses a “0” or “1” state, that is, a binary value, whereas in this embodiment, a “0” state and a “1” state Intermediate states can also be used.
  • the inversion voltage V 0 required for the state of “0” is ⁇ 1V
  • the magnitude of the inversion voltage V 1 for the state of “1” is about + 4V. Since the threshold voltage Vth and the inverted voltage V 0 and the inverted voltage V 1 appear symmetrically as described above, the values can be read from the capacitance-voltage polarity in FIG. -1V and 4V are not necessarily required.
  • Vth is a positive voltage of about 1.2 V, but Vth may be a negative voltage, that is, Vth ⁇ 0. Even in that case, since the absolute values of the inversion voltage V 0 and the inversion voltage V 1 are different, it is possible to detect and record that a large impact has been applied once as in the above embodiment.
  • the characteristic of the impact detection / recording apparatus of this embodiment is that the threshold voltage Vth of the ferroelectric memory 3 is shifted from 0V.
  • the threshold voltage Vth can be shifted from 0 V by selecting the type of each material constituting the ferroelectric memory 3 and the thickness of each material layer. This will be explained in more detail by giving specific examples below.
  • a ferroelectric memory 3 was manufactured using a ferroelectric thin film 4 made of SBT (SrBi 2 Ta 2 O 9 ), which is known as a representative ferroelectric material.
  • SBT Strontium carbonate
  • Ta 2 O 5 tantalum oxide
  • Bi 2 O 3 bismuth oxide
  • the mixed powder placed as described above was dried and calcined in the atmosphere at a temperature of 900 ° C. for 2 hours.
  • the calcined material was pulverized using PSZ balls to obtain a calcined powder.
  • the calcined powder was mixed with water and polyvinyl alcohol and dried to obtain a press raw material.
  • the press raw material was formed into a disk having a diameter of 20 mm and a thickness of 5 mm by a pressing device.
  • the formed disk-shaped molded body was heated in the atmosphere at 400 ° C. to remove the binder. Thereafter, it was fired in the air at 1150 ° C. for 4 hours in a sealed cage to obtain a sintered compact target.
  • a p-type Si semiconductor substrate was prepared as the semiconductor substrate 6.
  • HfO x was deposited by sputtering to form a buffer layer 7.
  • the ferroelectric thin film 4 was formed on the buffer layer 7 of the semiconductor substrate 6 on which the buffer layer 7 was formed, using the sintered body target by a pulse laser deposition method.
  • a KrF excimer laser was used as the laser.
  • the ferroelectric thin film 4 was formed at a substrate temperature of 750 ° C., an oxygen partial pressure of 33 Pa, and a laser energy of 120 mA.
  • the powder obtained by pulverizing the formed ferroelectric thin film 4 was evaluated by X-ray diffraction measurement. The results are shown in FIG.
  • the SrBi 2 Ta 2 O 9 film is formed from 2 ⁇ of X-ray diffraction.
  • the first electrode and the second electrode made of Pt were formed to a thickness of 20 nm.
  • the ferroelectric memory elements 11 to 14 shown in Table 1 below were obtained by setting the film thickness of the ferroelectric thin film 4 to 130, 250, 400 or 600 mm.
  • the capacitance-voltage characteristics of the ferroelectric memory element 12 were measured using an LCR meter (manufactured by Hewlett-Packard Company, product number: HP4284).
  • LCR meter manufactured by Hewlett-Packard Company, product number: HP4284.
  • a probe using a W probe was used to apply a voltage between the first electrode and the second electrode in steps of 0.1 V from ⁇ 3 V to +3 V to ⁇ 3 V with a frequency of 1 MHz and an amplitude of 50 mV. .
  • the capacitance in this case was measured, and the voltage dependency of the capacitance was evaluated.
  • the measurement was performed with the second electrode connected to the ground potential.
  • the capacitance-voltage characteristics obtained as described above are the characteristics shown in FIGS. 3, 5 and 6 described above.
  • FIG. 7 shows a capacitance-voltage curve of a ferroelectric memory in which the threshold voltage Vth is not shifted. In FIG. 7, hysteresis appears, but the threshold voltage Vth is 0V.
  • the impact detection / recording apparatus of the present embodiment uses the hysteresis on the CV characteristic in the ferroelectric memory 3. Therefore, the ferroelectric memory in which the hysteresis does not appear cannot be used in the present invention. For example, when the voltage is swept in a very small voltage range such as -1V ⁇ 1V ⁇ -1V during measurement, no hysteresis appears. This is because the electronic polarization of the ferroelectric does not reverse. Therefore, in order to detect and record an impact as described above using the ferroelectric memory 3, it is necessary to apply a voltage higher than the coercive electric field to the ferroelectric thin film so that the hysteresis appears.
  • the threshold voltage Vth is located at 0V.
  • the ferroelectric memory used in this embodiment has the diode junction and the MFIS structure, all applied voltages are not applied to the ferroelectric thin film 4. Therefore, when the hysteresis appears and the memory window becomes the largest, the voltage at which the memory window becomes 0.3 V or more is defined as the inverted voltages V 0 and V 1 .
  • the threshold voltage Vth of the ferroelectric memory 3 can be adjusted in the amount of shift by selecting the material.
  • the change in threshold voltage in such a ferroelectric memory for example, (Jpn. -Conventionally known as described in Semiconductor Structure for One Transistor-Type Ferroelectric Memory by Rapid Thermal Annealing). That is, it has been conventionally known that the threshold voltage Vth changes in the MFIS structure using the ferroelectric thin film by changing the heat treatment condition. Therefore, the conditions for shifting the threshold voltage Vth in the ferroelectric memory 3 can be known in accordance with a conventionally known technique. However, the technique that actively uses such a shift of the threshold voltage Vth is not described in the above-mentioned document.
  • the effect of the above embodiment was evaluated by applying an actual impact. That is, as shown in FIG. 8, the LCR meter 22 and the piezoelectric element 2 were connected to the ferroelectric memory 3 via the switch 21. Further, an impact generating jig 31 shown in FIG. 9 was prepared. In the impact generating jig 31, a post 33 is erected on an iron plate 32. A guide 34 that can slide up and down along the post 33 is provided. The piezoelectric element 2 was fixed to the guide 34, and the guide 34 was dropped onto the iron plate 32 from a position having a height of 25 cm, 80 cm, or 120 cm. The impact due to the drop was detected and recorded by the circuit of FIG. 8 including the piezoelectric element 2 and the ferroelectric memory 3.
  • the ferroelectric memory 3 was connected to the LCR meter 22 and a voltage was applied so as to be in a reset state. The capacitance at that time was read.
  • the LCR meter 22 was disconnected from the ferroelectric memory 3 by the switch 21 and connected to the piezoelectric element 2.
  • the piezoelectric element 2 was fixed to the guide 34 in a state where the piezoelectric element 2 was connected to the ferroelectric memory 3 by wiring or the like, and the impact due to the dropping as described above was applied.
  • electric energy generated by the impact was written in the ferroelectric memory 3.
  • the switch 21 was switched, and the ferroelectric memory 3 was reconnected to the LCR meter 22 to read the capacitance. Thereby, it was evaluated whether or not the impact could be recorded.
  • the piezoelectric element 2 includes a first piezoelectric element having an acceleration detection sensitivity of 0.35 pC / G and a capacitance of 740 pF, and a second piezoelectric element having an acceleration detection sensitivity of 0.84 pC / G and a capacitance of 770 pF. And prepared. The greater the acceleration detection sensitivity, the greater the charge generated by the same magnitude of impact. The results are shown in Table 2 below.
  • Sample numbers 1 and 2 in Table 2 correspond to comparative examples, and even when dropped from any height, no impact could be recorded. In contrast, Sample Nos. 3 to 10 were able to detect and record an impact when dropped from at least one of the height positions.
  • sample No. 7 could not record an impact when dropped from a height of 25 cm.
  • sample No. 9 the impact could not be recorded when dropped from a height of 25 cm and 80 cm.
  • the impact can be recorded when dropped from a height of 80 cm or 120 cm. Therefore, it can be seen that one impact can be detected and recorded according to the present invention by adjusting the threshold voltage and the reverse voltage according to the magnitude of the impact to be recorded.
  • FIG.10 and FIG.11 shows the result at the time of dropping the said sample number 5 from 80 cm.
  • the capacitance of the ferroelectric memory is 117 pF, and this state corresponds to a state of “1”.
  • FIG. 10 and FIG.11 shows the result at the time of dropping the said sample number 5 from 80 cm.
  • the capacitance of the ferroelectric memory was measured to be 138.8 pF. This is a state of “0”.
  • the connection is switched again by the switch 21, and the piezoelectric element 2 is dropped from the height of 80 cm at the timing of the arrows B1 and B2. I read it.
  • the electrostatic capacitance hardly changed to 139.3 pF, and recording could not be performed.
  • the impact can be recorded and held by the electric energy from the piezoelectric element. I understand. Further, it is possible to detect and record a single impact as described above. In addition, since the sensitivity is very high, not only can one impact be recorded, but a small piezoelectric element of 3 ⁇ 3 ⁇ 0.5 mm type can be used as a sensor. Therefore, it can be seen that an impact detection / recording apparatus that can be mounted on a small portable terminal or the like can be configured.
  • FIGS. 12 and 13 show the results when a ferroelectric memory of sample number 2 was used and dropped from a piezoelectric element of 80 cm in the same manner as described above.
  • FIG. 12 shows the result when the impact is applied at the timing of the arrow X2 after switching to the state “1” by the arrow X1 using the ferroelectric memory of the sample number 2.
  • FIG. 13 shows the result when an impact is applied at the timing of the arrow Y2 after switching to the state of “0” at the timing of the arrow Y1.
  • the impact could not be detected and recorded.
  • Sample No. 2 a large voltage of about ⁇ 2 V is required in any case to switch the ferroelectric memory 3 to the “0” or “1” state. Therefore, with the output of a small piezoelectric element that can be mounted on a cellular phone or the like, the electronic polarization cannot be reversed in the ferroelectric memory of Comparative Example 2. Thus, it can be seen that a large piezoelectric element must be used.

Abstract

Provided is an impact detection and recording device requiring no power supply and capable of detecting one-time impact and recording and holding the one-time impact. The impact detection and recording device comprises: a piezoelectric element (2) for converting impact energy into electric energy and outputting the electric energy; and a ferroelectric memory (3) having a ferroelectric material (4) connected to the piezoelectric element (2) and having one principal surface and the other principal surface opposing to the one principal surface, a first electrode (5) formed on the side of the one principal surface of the ferroelectric material (4), and a second electrode (8) formed on the side of the other principal surface of the ferroelectric material (4). The ferroelectric memory (3) can record at least one of the first and second states derived from electron polarization of the ferroelectric material (4). The capacitance-voltage characteristics of the ferroelectric memory (3) have a hysteresis. In the hysteresis curve of the capacitance-voltage characteristics, when the voltage value at which the largest difference in capacitance occurs between the curve when the voltage is increased and the curve when the voltage is decreased is defined as a threshold voltage (Vth), the threshold voltage (Vth) becomes greater than or less than zero.

Description

衝撃検知・記録装置Impact detection / recording device
　本発明は、外部からの衝撃を検知し、記録することを可能とする衝撃検知・記録装置に関し、より詳細には、圧電素子と強誘電体メモリとを備えた衝撃検知・記録装置に関する。 The present invention relates to an impact detection / recording apparatus capable of detecting and recording an external impact, and more particularly to an impact detection / recording apparatus including a piezoelectric element and a ferroelectric memory.
　従来、電子機器や車両などにおいて、衝撃を検知し、記録するために様々なセンサが提案されている。下記の特許文献１には、振動エネルギーを電気エネルギーに変換する電荷発生用圧電体と、発生した電荷により分極反転を繰り返す強誘電体メモリとを備える圧電振動エネルギーセンサが開示されている。衝撃等の振動が加わると、圧電体が電荷を発生する。この電荷により強誘電体メモリが分極反転する。多数の振動が繰り返し与えられた場合、分極反転が繰り返され、疲労により残留分極が低下する。残留分極の低下度合いにより、加えられた振動の回数を求めることができる。上記圧電体と強誘電体メモリとを備えるものであるため、無電源で加えられた振動の回数を測定することができる。 Conventionally, various sensors have been proposed for detecting and recording impacts in electronic devices and vehicles. Patent Document 1 below discloses a piezoelectric vibration energy sensor including a charge generating piezoelectric body that converts vibration energy into electric energy and a ferroelectric memory that repeats polarization inversion by the generated charge. When vibration such as impact is applied, the piezoelectric body generates electric charges. This charge reverses the polarization of the ferroelectric memory. When a large number of vibrations are repeatedly applied, the polarization inversion is repeated, and the residual polarization decreases due to fatigue. The number of applied vibrations can be determined from the degree of decrease in remanent polarization. Since the piezoelectric body and the ferroelectric memory are provided, the number of vibrations applied without a power source can be measured.
特開２００４－６１３４７JP 2004-61347 A
　特許文献１に記載の圧電振動エネルギーセンサでは、無電源で、加えられた振動の回数を測定することができる。分極反転による疲労、すなわち残留分極の低下により振動の回数を長期間にわたり測定している。従って、特許文献１では、大きな衝撃が１回加わったとしても、該１回の衝撃を検知し、記録することはできない。 The piezoelectric vibration energy sensor described in Patent Document 1 can measure the number of applied vibrations without a power source. The number of vibrations is measured over a long period of time due to fatigue due to polarization reversal, ie, a decrease in residual polarization. Therefore, in Patent Document 1, even if a large impact is applied once, the single impact cannot be detected and recorded.
　また、残留分極を利用しているため、非常に大きな振動エネルギーを電気的エネルギーに変換する大きな圧電素子が必要である。従って、小型化が困難である。 Also, since residual polarization is used, a large piezoelectric element that converts very large vibrational energy into electrical energy is required. Therefore, downsizing is difficult.
　本発明の目的は、電源が不要な衝撃検知・記録装置であって、１回の衝撃を検出し、該１回の衝撃を記録し、保持し得る衝撃検知・記録装置を提供することにある。 An object of the present invention is to provide an impact detection / recording device that does not require a power source, and can detect and record a single impact and hold it. .
　本発明に係る衝撃検知・記録装置は、衝撃のエネルギーを電気エネルギーに変換し、出力する圧電素子と、前記圧電素子に接続されており、一方主面及び前記一方主面に対向する他方主面を有する強誘電体と、前記強誘電体の一方主面側に形成された第１の電極と、前記強誘電体の他方主面側に形成された第２の電極とを有する強誘電体メモリとを備える。本発明では、前記強誘電体メモリが、強誘電体の電子分極に由来する少なくとも第１及び第２の状態のいずれかを記録し得るものである。強誘電体メモリの静電容量－電圧特性はヒステリシスを有する。この静電容量－電圧特性のヒステリシス曲線において、電圧上昇時の曲線と、電圧降下時の曲線との間で容量の差が最も大きい電圧値を閾値電圧Ｖｔｈとしたとき、Ｖｔｈ＞０またはＶｔｈ＜０とされている。 An impact detection / recording apparatus according to the present invention converts an impact energy into electrical energy and outputs the piezoelectric element, and is connected to the piezoelectric element and has one main surface and the other main surface facing the one main surface. A ferroelectric memory, a first electrode formed on one main surface side of the ferroelectric, and a second electrode formed on the other main surface side of the ferroelectric With. In the present invention, the ferroelectric memory can record at least one of the first and second states derived from the electronic polarization of the ferroelectric. The capacitance-voltage characteristic of the ferroelectric memory has hysteresis. In this hysteresis curve of capacitance-voltage characteristics, when the voltage value having the largest capacitance difference between the curve at the time of voltage rise and the curve at the time of voltage drop is defined as the threshold voltage Vth, Vth> 0 or Vth < 0.
　第１，第２の電極がそれぞれ強誘電体の一方主面側、他方主面側に形成されているとは、各電極が強誘電体上に直接形成されていることに限定されるものではなく、実施形態のように半導体やバッファ層を介していてもよい。 The fact that the first and second electrodes are respectively formed on the one main surface side and the other main surface side of the ferroelectric is not limited to that each electrode is formed directly on the ferroelectric. Instead, it may be via a semiconductor or a buffer layer as in the embodiment.
　本発明に係る衝撃検知・記録装置のある特定の局面では、前記強誘電体メモリを第１の状態から第２の状態に反転させるのに必要な反転電圧をＶ０、第２の状態から第１の状態に反転させるための反転電圧をＶ１としたときに、Ｖ０＜０＜Ｖ１またはＶ０＞０＞Ｖ１である。この場合には、時間とともに分極状態が反転して記録され、情報が消えるおそれがない。 In a specific aspect of the impact detection / recording apparatus according to the present invention, an inversion voltage required to invert the ferroelectric memory from the first state to the second state is V 0 , and the second state is the second state. the inversion voltage for inverting the first state when the V 1, V 0 <0 < V 1 or V 0>0> is V 1. In this case, the polarization state is reversed and recorded with time, and there is no possibility that information is lost.
　本発明に係る衝撃検知・記録装置の他の特定の局面では、前記強誘電体メモリの閾値電圧Ｖｔｈの絶対値が、０．５Ｖ～３Ｖの範囲にある。この範囲内であれば、閾値電圧を０Ｖから容易にシフトさせて衝撃を検知・記録することができるとともに、圧電素子で発生する電荷により衝撃をより確実に記録することができる。 In another specific aspect of the impact detection / recording apparatus according to the present invention, the absolute value of the threshold voltage Vth of the ferroelectric memory is in a range of 0.5V to 3V. Within this range, the threshold voltage can be easily shifted from 0V to detect and record the impact, and the impact can be more reliably recorded by the charge generated by the piezoelectric element.
　本発明に係る衝撃検知・記録装置にさらに他の特定の局面では、前記強誘電体メモリが、前記強誘電体とを第２の電極との間に積層された半導体層をさらに有する。この場合には、強誘電体と半導体層との接合によりダイオード構造が形成される。従って、上記ダイオード構造を構成している材料の選択により、閾値電圧Ｖｔｈを０から容易にシフトさせることができる。 In still another specific aspect of the impact detection / recording apparatus according to the present invention, the ferroelectric memory further includes a semiconductor layer in which the ferroelectric is stacked between a second electrode. In this case, a diode structure is formed by joining the ferroelectric and the semiconductor layer. Therefore, the threshold voltage Vth can be easily shifted from 0 by selecting the material constituting the diode structure.
　本発明に係る衝撃検知・記録装置のさらに別の特定の局面では、前記半導体層と前記強誘電体との間にバッファ層が設けられている。この場合には、バッファ層の材料及び厚み等を選択することにより閾値電圧Ｖｔｈの値を容易に制御することができる。 In yet another specific aspect of the impact detection / recording apparatus according to the present invention, a buffer layer is provided between the semiconductor layer and the ferroelectric. In this case, the value of the threshold voltage Vth can be easily controlled by selecting the material and thickness of the buffer layer.
　本発明に係る衝撃検知・記録装置によれば、強誘電体メモリにおける上記閾値電圧Ｖｔｈが０Ｖからシフトしているため、第１の状態から第２の状態に反転させるのに必要な反転電圧Ｖ０と、第２の状態から第１の状態に反転させるのに必要な反転電圧Ｖ１の絶対値が異なることとなる。そのため、Ｖ０＞Ｖ１またはＶ１＞Ｖ０である場合に、初期状態を第１の状態または第２の状態とし、衝撃が加わったときに第２の状態または第１の状態にスイッチングさせることにより、１回の衝撃を確実に記録し保持することができる。 According to the impact detection / recording apparatus of the present invention, since the threshold voltage Vth in the ferroelectric memory is shifted from 0V, the inversion voltage V necessary for inversion from the first state to the second state. The absolute value of the inversion voltage V 1 necessary for inversion from 0 to the first state is different from 0. Therefore, when V 0 > V 1 or V 1 > V 0 , the initial state is set to the first state or the second state, and when an impact is applied, the state is switched to the second state or the first state. Thus, a single impact can be reliably recorded and held.
　よって、本発明によれば、無電源で１回の衝撃を検出し、かつ確実に強誘電体メモリにおいて記録し保持することができる。 Therefore, according to the present invention, a single impact can be detected with no power source, and can be reliably recorded and held in the ferroelectric memory.
図１は、本発明の第１の実施形態に係る衝撃検知・記録装置に用いられる強誘電体メモリを示す正面図である。FIG. 1 is a front view showing a ferroelectric memory used in the impact detection / recording apparatus according to the first embodiment of the present invention. 図２は、本発明の第１の実施形態に係る衝撃検知・記録装置の回路図である。FIG. 2 is a circuit diagram of the impact detection / recording apparatus according to the first embodiment of the present invention. 図３は、本発明の第１の実施形態で用いられる強誘電体メモリの静電容量－電圧特性を示す図である。FIG. 3 is a diagram showing the capacitance-voltage characteristics of the ferroelectric memory used in the first embodiment of the present invention. 図４は、本発明の第１の実施形態で作製した強誘電体枠のＸ線回折プロファィルを示す図である。FIG. 4 is a diagram showing an X-ray diffraction profile of the ferroelectric frame manufactured in the first embodiment of the present invention. 図５は、本発明の第１の実施形態の衝撃検知・記録装置で用いられる強誘電体メモリのメモリ動作を説明するための図である。FIG. 5 is a diagram for explaining the memory operation of the ferroelectric memory used in the impact detection / recording apparatus according to the first embodiment of the present invention. 図６は、本発明の第１の実施形態に係る衝撃検知・記録装置における閾値電圧Ｖｔｈ及び第１，第２の反転電圧を説明するための図である。FIG. 6 is a diagram for explaining the threshold voltage Vth and the first and second inversion voltages in the impact detection / recording apparatus according to the first embodiment of the present invention. 図７は、閾値電圧Ｖが０Ｖに位置している比較例の強誘電体メモリの静電容量－電圧特性を示す図である。FIG. 7 is a diagram showing the capacitance-voltage characteristics of the ferroelectric memory of the comparative example in which the threshold voltage V is 0V. 図８は、本発明の第１の実施形態の衝撃検知・記録装置を評価するための回路構成を示す模式図である。FIG. 8 is a schematic diagram showing a circuit configuration for evaluating the impact detection / recording apparatus according to the first embodiment of the present invention. 図９は、本発明の第１の実施形態の衝撃検知・記録装置の降下を測定するための衝撃生成治具を説明するための模式図である。FIG. 9 is a schematic diagram for explaining an impact generation jig for measuring the descent of the impact detection / recording apparatus according to the first embodiment of the present invention. 図１０は、本発明の第１の実施形態の衝撃検知・記録装置の実験例における衝撃記録結果を示す図である。FIG. 10 is a diagram showing impact recording results in an experimental example of the impact detection / recording apparatus according to the first embodiment of the present invention. 図１１は、本発明の第１の比較例の衝撃検知・記録装置の実験例における衝撃記録結果を示す図である。FIG. 11 is a diagram showing an impact recording result in an experimental example of the impact detection / recording apparatus of the first comparative example of the present invention. 図１２は、比較例としての試料番号２の強誘電体メモリを用いた場合の衝撃記録特性を示す図である。FIG. 12 is a diagram showing impact recording characteristics when a ferroelectric memory of sample number 2 as a comparative example is used. 図１３は、比較例としての試料番号２の強誘電体メモリを用いた場合の衝撃記録特性を示す図である。FIG. 13 is a diagram showing impact recording characteristics when a ferroelectric memory of Sample No. 2 as a comparative example is used.
　以下、図面を参照しつつ、本発明の具体的な実施形態を説明することにより、本発明を明らかにする。 Hereinafter, the present invention will be clarified by describing specific embodiments of the present invention with reference to the drawings.
　図２は、本発明の第１の実施形態に係る衝撃検知・記録装置の概略構成図である。衝撃検知・記録装置１は、圧電素子２と強誘電体メモリ３とを備える。圧電素子２は、加えられた衝撃のエネルギーを電気エネルギーに変換し、出力する。このような圧電素子としては、従来より周知の衝撃センサとして用いられている様々な圧電素子が挙げられる。例えば、バイモルフ型圧電素子や、ユニモルフ型圧電素子等を挙げることができる。 FIG. 2 is a schematic configuration diagram of an impact detection / recording apparatus according to the first embodiment of the present invention. The impact detection / recording apparatus 1 includes a piezoelectric element 2 and a ferroelectric memory 3. The piezoelectric element 2 converts the applied impact energy into electrical energy and outputs it. Examples of such piezoelectric elements include various piezoelectric elements that have been used as well-known impact sensors. For example, a bimorph type piezoelectric element, a unimorph type piezoelectric element, etc. can be mentioned.
　本実施形態の衝撃検知・記録装置１は、圧電素子２に並列に接続されている強誘電体メモリ３を備える。強誘電体メモリ３は、圧電素子２から与えられる電気エネルギーに基づき、１回の衝撃を記録し、保持する。この強誘電体メモリ３の構造を図１を参照して説明する。 The impact detection / recording apparatus 1 of the present embodiment includes a ferroelectric memory 3 connected in parallel to the piezoelectric element 2. The ferroelectric memory 3 records and holds a single impact based on the electric energy applied from the piezoelectric element 2. The structure of the ferroelectric memory 3 will be described with reference to FIG.
　図１は、本実施形態で用いられている強誘電体メモリ３の正面図である。強誘電体メモリ３は、強誘電体層として強誘電体薄膜４を有する。強誘電体薄膜４を構成する強誘電体材料は特に限定されない。例えばＳｒＢｉ２Ｔａ２Ｏ９、Ｐｂ（Ｚｒ，Ｔｉ）Ｏ３、（Ｂｉ，Ｌａ）４Ｔｉ３Ｏ１２、ＢｉＦｅＯ３などを挙げることができる。本実施形態では、強誘電体薄膜４は、ＳｒＢｉ２Ｔａ２Ｏ９からなる。 FIG. 1 is a front view of a ferroelectric memory 3 used in this embodiment. The ferroelectric memory 3 has a ferroelectric thin film 4 as a ferroelectric layer. The ferroelectric material constituting the ferroelectric thin film 4 is not particularly limited. For example, SrBi 2 Ta 2 O 9 , Pb (Zr, Ti) O 3 , (Bi, La) 4 Ti 3 O 12 , BiFeO 3 and the like can be mentioned. In the present embodiment, the ferroelectric thin film 4 is made of SrBi 2 Ta 2 O 9 .
　強誘電体薄膜４の一方主面上に第１の電極５が形成されている。また、強誘電体薄膜４の他方主面は、半導体基板６の上面にバッファ層７を介して積層されている。半導体基板６は強誘電体薄膜４とダイオード接合を果し得る適宜の半導体からなる。本実施形態では、半導体基板６は、Ｓｉからなる。 A first electrode 5 is formed on one main surface of the ferroelectric thin film 4. The other main surface of the ferroelectric thin film 4 is laminated on the upper surface of the semiconductor substrate 6 with a buffer layer 7 interposed therebetween. The semiconductor substrate 6 is made of an appropriate semiconductor that can form a diode junction with the ferroelectric thin film 4. In the present embodiment, the semiconductor substrate 6 is made of Si.
　バッファ層７は、強誘電体薄膜４と半導体基板６との間の相互拡散による劣化を抑制するために設けられている。バッファ層７を構成する材料は、特に限定されず、ＨｆＯｘ、Ａｌ２Ｏ３、ＺｒＯ２、ＣｅＯ２、ＬａＡｌＯ３またはＬａ２Ｏ３などがあげられる。本実施形態では、バッファ層７は、ＨｆＯｘ（ただしｘは約２）からなる。バッファ層７を構成する材料については、強誘電体薄膜４を構成する強誘電体材料、半導体基板６を構成する半導体材料等に応じて適宜選択すればよい。また、バッファ層７の材料を選択することにより、後述の閾値電圧を制御することも可能である。 The buffer layer 7 is provided in order to suppress deterioration due to mutual diffusion between the ferroelectric thin film 4 and the semiconductor substrate 6. The material constituting the buffer layer 7 is not particularly limited, HfO x, Al 2 O 3 , etc. ZrO 2, CeO 2, LaAlO 3, or La 2 O 3 and the like. In the present embodiment, the buffer layer 7 is made of HfO x (where x is about 2). What is necessary is just to select suitably the material which comprises the buffer layer 7 according to the ferroelectric material which comprises the ferroelectric thin film 4, the semiconductor material which comprises the semiconductor substrate 6, etc. FIG. In addition, the threshold voltage described later can be controlled by selecting the material of the buffer layer 7.
　複数の材料からなるバッファ層を積層したり、複数の材料の固溶体を使用したりして、それによって閾値電圧Ｖｔｈを適切な値としてもよい。 The buffer layer made of a plurality of materials may be laminated, or a solid solution of a plurality of materials may be used, thereby making the threshold voltage Vth an appropriate value.
　半導体基板６の下面すなわち強誘電体薄膜４の他方主面側には、第２の電極８が形成されている。従って、強誘電体薄膜４は、第１の電極５と第２の電極８とに挟まれている。 A second electrode 8 is formed on the lower surface of the semiconductor substrate 6, that is, on the other main surface side of the ferroelectric thin film 4. Therefore, the ferroelectric thin film 4 is sandwiched between the first electrode 5 and the second electrode 8.
　本実施形態では、第１の電極５及び第２の電極８は、強誘電体薄膜４を介して対向する位置に形成されているが、強誘電体薄膜４の一方主面と他方主面との間に電圧を印加できるのであれば、互いに対向させる位置に形成する必要は必ずしもない。 In the present embodiment, the first electrode 5 and the second electrode 8 are formed at positions facing each other with the ferroelectric thin film 4 therebetween, but one main surface and the other main surface of the ferroelectric thin film 4 If a voltage can be applied between them, it is not always necessary to form them at positions facing each other.
　第１の電極５と第２の電極８とは適宜の金属材料により形成することができる。本実施形態では、第１の電極５及び第２の電極８は、Ｐｔからなる。もっとも、Ｐｔ以外に、Ａｕ、Ａｇ、Ａｌ、Ｐｄ、Ｉｒ、Ｃｕなどの適宜の金属もしくは合金、またはＳｒＲｕＯ３、ＰｔＯｘ（ただしｘは１～３の整数）、ＩｒＯ２、ＰｄＯなどの酸化物を用いることができる。 The first electrode 5 and the second electrode 8 can be formed of an appropriate metal material. In the present embodiment, the first electrode 5 and the second electrode 8 are made of Pt. However, in addition to Pt, an appropriate metal or alloy such as Au, Ag, Al, Pd, Ir, or Cu, or an oxide such as SrRuO 3 , PtO x (where x is an integer of 1 to 3), IrO 2 , or PdO. Can be used.
　なお、第１，第２の電極５，８の材料を調整することによって、後述の閾値電圧Ｖｔｈを調整することも可能である。また、本実施形態では、第１の電極５と第２の電極８とは強誘電体薄膜４、バッファ層７及び半導体基板６を介して対向するように配置されているが、第１，第２の電極５，８の強誘電体薄膜４介して対向する形態はこれに限定されるものではない。 It should be noted that the threshold voltage Vth described later can be adjusted by adjusting the materials of the first and second electrodes 5 and 8. In the present embodiment, the first electrode 5 and the second electrode 8 are disposed so as to face each other with the ferroelectric thin film 4, the buffer layer 7 and the semiconductor substrate 6 therebetween. The form of the two electrodes 5 and 8 facing each other via the ferroelectric thin film 4 is not limited to this.
　もっとも、本実施形態の衝撃検知・記録装置１では、強誘電体メモリ３が圧電素子２から与えられる電気エネルギーに基づき、衝撃を記録し、保持する必要がある。従って、以下に述べるように、閾値電圧Ｖｔｈが０Ｖからシフトされている。すなわちＶｔｈ＞０またはＶｔｈ＜０であり、それによって１回の衝撃を記録し、保持することができる。よって、上記強誘電体薄膜４は、バッファ層７を介して半導体基板６に接合されていたり、強誘電体薄膜４が直接半導体基板６に積層されたりして、上記ダイオード接合を有していることが望ましい。それによって、閾値電圧Ｖｔｈを０Ｖから容易にシフトさせることができる。 However, in the impact detection / recording apparatus 1 of the present embodiment, it is necessary for the ferroelectric memory 3 to record and hold the impact based on the electrical energy given from the piezoelectric element 2. Therefore, as described below, the threshold voltage Vth is shifted from 0V. That is, Vth> 0 or Vth <0, whereby a single impact can be recorded and held. Therefore, the ferroelectric thin film 4 is bonded to the semiconductor substrate 6 via the buffer layer 7, or the ferroelectric thin film 4 is directly stacked on the semiconductor substrate 6 to have the diode junction. It is desirable. Thereby, the threshold voltage Vth can be easily shifted from 0V.
　次に、上記強誘電体メモリ３の動作を図３、図５及び図６を参照して説明する。 Next, the operation of the ferroelectric memory 3 will be described with reference to FIG. 3, FIG. 5 and FIG.
　図３は、上記強誘電体メモリ３の静電容量－電圧特性を示す図である。図示のように、静電容量－電圧特性曲線はヒステリシスを有する。すなわち電圧上昇時の曲線と、電圧降下時の曲線とが一致しておらず、ずれている。 FIG. 3 is a diagram showing the capacitance-voltage characteristics of the ferroelectric memory 3. As illustrated, the capacitance-voltage characteristic curve has hysteresis. That is, the curve at the time of voltage rise and the curve at the time of voltage drop are not coincident and are shifted.
　本実施形態では、図６に示すように、閾値電圧Ｖｔｈが約１．２ＶでありＶｔｈ＞０Ｖとされている。ここで閾値電圧Ｖｔｈとは、静電容量－電圧特性のヒステリシスにおいて、電圧上昇時の曲線と、電圧降下時の曲線との間で、容量の差が最も大きくなる電圧値をいうものとする。 In this embodiment, as shown in FIG. 6, the threshold voltage Vth is about 1.2V, and Vth> 0V. Here, the threshold voltage Vth refers to a voltage value at which the difference in capacitance is the largest between the curve at the time of voltage rise and the curve at the time of voltage drop in the hysteresis of the capacitance-voltage characteristic.
　また、電圧上昇時の曲線と、電圧降下時の曲線との間で同じ静電容量値で印加電圧の差がもっとも大きい部分での該印加電圧をメモリウィンドとする。図６では、このメモリウィンドの大きさは０．６Ｖである。 Also, the applied voltage at the portion where the difference in applied voltage is the same with the same capacitance value between the curve at the time of voltage rise and the curve at the time of voltage drop is defined as a memory window. In FIG. 6, the size of this memory window is 0.6V.
　図３及び図６に示したように、上記強誘電体メモリ３の静電容量－電圧特性において、印加電圧が－３Ｖ～－４Ｖ付近で静電容量が１５０ｐＦ程度と高くなり、印加電圧が＋２Ｖ～４Ｖ程度となった場合、静電容量は１４ｐＦ程度と低くなっていることがわかる。この静電容量－電圧特性を利用して、第１の状態すなわち「０」の状態と、第２の状態「１」の状態とを区別することができる。「０」の状態は、強誘電体薄膜４の電子分極が第１の電極側に向いている場合であり、「１」の状態は、電子分極方向が半導体基板６側に向いている状態に対応している。なお、使用する半導体基板の極性によって、上記向きは変化しないが、静電容量－電圧特性の極性は逆転する。強誘電体メモリ３では、電圧を印加することにより分極反転を引き起こさせることができる。すなわち、電圧を印加することにより第１の状態である「０」の状態または第２の状態すなわち「１」の状態や、強誘電体の電子分極が完全に「０」、「１」の状態にならず、大部分が「０」、「１」の状態になっている中間の状態とすることができる。第１の状態すなわち「０」の状態にするための電圧を反転電圧Ｖ０とし、「１」の状態にスイッチングさせるための電圧を反転電圧Ｖ１とする。強誘電体メモリでは、一般に、前述したヒステリシスを有する場合、Ｖ０とＶ１とは、閾値電圧Ｖｔｈに対して対称な位置に存在する。 As shown in FIGS. 3 and 6, in the capacitance-voltage characteristics of the ferroelectric memory 3, the capacitance increases to about 150 pF when the applied voltage is around -3V to -4V, and the applied voltage is + 2V. When it is about 4V, it can be seen that the capacitance is as low as about 14 pF. Using this capacitance-voltage characteristic, it is possible to distinguish between the first state, that is, the “0” state, and the second state “1”. The “0” state is a case where the electronic polarization of the ferroelectric thin film 4 is directed to the first electrode side, and the “1” state is a state where the electronic polarization direction is directed to the semiconductor substrate 6 side. It corresponds. The direction does not change depending on the polarity of the semiconductor substrate to be used, but the polarity of the capacitance-voltage characteristic is reversed. In the ferroelectric memory 3, polarization inversion can be caused by applying a voltage. That is, when a voltage is applied, the first state is “0” or the second state, ie, “1”, or the electronic polarization of the ferroelectric is completely “0” or “1”. In other words, an intermediate state in which most of the states are “0” and “1” can be obtained. The voltage for switching to the first state, that is, the state of “0” is the inverted voltage V 0, and the voltage for switching to the “1” state is the inverted voltage V 1 . In a ferroelectric memory, generally, when having the above-described hysteresis, V 0 and V 1 exist at positions symmetrical with respect to the threshold voltage Vth.
　他方、本実施形態の強誘電体メモリ３では、閾値電圧Ｖｔｈが０Ｖではなく、１．２Ｖにシフトしている。従って、Ｖ０が－１Ｖであり、Ｖ１は＋４Ｖ程度とされている。すなわち、反転電圧Ｖ０と反転電圧Ｖ１の絶対値が異なっている。 On the other hand, in the ferroelectric memory 3 of the present embodiment, the threshold voltage Vth is shifted to 1.2V instead of 0V. Therefore, V 0 is −1V and V 1 is about + 4V. That is, the absolute values of the inversion voltage V 0 and the inversion voltage V 1 are different.
　よって、本実施形態の強誘電体メモリ３では、反転電圧Ｖ０及び反転電圧Ｖ１のうちその絶対値が高い「１」の状態を初期状態とするようにリセットしておく。「１」の状態のまま放置されても、メモリー特性を有するため、その状態は維持される。 Therefore, in the ferroelectric memory 3 of the present embodiment, the reset voltage V 0 and the inverted voltage V 1 are reset so that the state of “1” having a high absolute value is set as the initial state. Even if it is left in the “1” state, it has a memory characteristic, so that state is maintained.
　前述した圧電素子２に１回の衝撃が加わった場合には、衝撃によりエネルギーが電気エネルギーに変換される。そして、圧電素子２において電荷が発生し、該電荷に基づく出力が強誘電体メモリ３に印加される。この整流されていない電気エネルギーが、ダイオード接合構造を有する強誘電体メモリ３に入力されると、すなわち反転電圧Ｖ０または反転電圧Ｖ０に近い電圧が印加されると、強誘電体メモリ３が「１」の状態から「０」の状態または両状態の中間の状態に移行されることになる。この変化を、ダイオードの容量値、もしくは、ソース・ドレイン電極を追加してソース・ドレイン電流を検出することにより、上記衝撃の記録を確認することができる。 When a single impact is applied to the piezoelectric element 2 described above, energy is converted into electrical energy by the impact. Then, electric charges are generated in the piezoelectric element 2 and an output based on the electric charges is applied to the ferroelectric memory 3. When this non-rectified electrical energy is input to the ferroelectric memory 3 having a diode junction structure, that is, when the reverse voltage V 0 or a voltage close to the reverse voltage V 0 is applied, the ferroelectric memory 3 The state is shifted from the “1” state to the “0” state or an intermediate state between the two states. This change can be confirmed by detecting the source / drain current by adding the capacitance value of the diode or the source / drain electrodes.
　加えて、本実施形態の強誘電体メモリ３では、２回目以降の衝撃が加わったとしても、１回目の衝撃の記録は確実に保持される。すなわち、前述したように静電容量－電圧特性のヒステリシスにおいて、閾値電圧Ｖｔｈが０から１．２Ｖにシフトされている。従って、「０」の状態と、「１」の状態の安定性が異なっている。より具体的には、「０」の状態にするには、絶対値の小さい電圧を印加すればよく、「１」の状態にするには、「０」にするよりも大きな電圧が必要である。言い換えれば、「１」の状態に戻すには、より大きな電圧が必要となる。 In addition, in the ferroelectric memory 3 of the present embodiment, even if the second and subsequent impacts are applied, the first impact record is reliably maintained. That is, as described above, the threshold voltage Vth is shifted from 0 to 1.2 V in the hysteresis of the capacitance-voltage characteristics. Therefore, the stability of the “0” state and the “1” state are different. More specifically, a voltage having a small absolute value may be applied to make the state “0”, and a voltage larger than “0” is needed to make the state “1”. . In other words, a larger voltage is required to return to the “1” state.
　他方、圧電素子で圧電効果により取り出し得る電圧は、この種の衝撃センサに用いられる圧電素子では、通常、約３Ｖ以下である。従って、「１」の状態にリセットされた後に、前述したように大きな衝撃が１回加わって、「０」の状態または両状態の中間状態にリセットされたとしても、圧電素子２からの電気エネルギーでは、「１」の状態にリセットできない大きな電圧が必要となる。よって、状態の大きな１回の衝撃が強誘電体メモリ３で記録された後に、複数の衝撃が複数回圧電素子２に加わったとしても、上述した１回の衝撃による記録が消去されない。 On the other hand, the voltage that can be extracted by the piezoelectric effect by the piezoelectric element is usually about 3 V or less in the piezoelectric element used in this type of impact sensor. Therefore, even after a large impact is applied once as described above after being reset to the “1” state, the electric energy from the piezoelectric element 2 is reset even if the state is reset to the “0” state or an intermediate state between the two states. Then, a large voltage that cannot be reset to the “1” state is required. Therefore, even if a large impact is recorded in the ferroelectric memory 3 and then a plurality of impacts are applied to the piezoelectric element 2 a plurality of times, the recording due to the one impact described above is not erased.
　よって、本実施形態によれば、無電源で１回の衝撃を検知し、しかもその衝撃を記録し、保持することができる。また、多数の衝撃が後で加わったとしてもリセットされず、外部からリセット電圧を印加することなく、強誘電体メモリ３はリセットされない。よって、本実施形態によれば、例えば本実施形態の衝撃検知・記録装置が搭載されている電子機器などに故障を引き起こすような大きな衝撃か加わったことを記録し、保持させることができる。それによって、通常で考えられないような使用や事故による大きな衝撃が加わったことを確実に検出し、記録することができる。 Therefore, according to this embodiment, it is possible to detect a single impact with no power source, and to record and hold the impact. Further, even if a large number of impacts are applied later, it is not reset, and the ferroelectric memory 3 is not reset without applying a reset voltage from the outside. Therefore, according to the present embodiment, it is possible to record and hold that a large impact that causes a failure is applied to, for example, an electronic device in which the impact detection / recording apparatus of the present embodiment is mounted. As a result, it is possible to reliably detect and record the occurrence of a large impact caused by use or an accident that would normally not be considered.
　なお、一般的な強誘電体メモリでは、「０」または「１」の状態、すなわち２値を利用しているのに対し、本実施形態では、「０」の状態と「１」の状態との中間の状態も利用することができる。 Note that a general ferroelectric memory uses a “0” or “1” state, that is, a binary value, whereas in this embodiment, a “0” state and a “1” state Intermediate states can also be used.
　また、「０」の状態にするのに必要な反転電圧Ｖ０が－１Ｖ、「１」の状態とするための反転電圧Ｖ１の大きさが＋４Ｖ程度である旨を示したが、これは、上述したように閾値電圧Ｖｔｈと、対称に反転電圧Ｖ０及び反転電圧Ｖ１が表われることから、図５の静電容量－電圧極性から読み取り得る値である。－１Ｖと４Ｖとする必要は必ずしもない。 Also, it was shown that the inversion voltage V 0 required for the state of “0” is −1V, and the magnitude of the inversion voltage V 1 for the state of “1” is about + 4V. Since the threshold voltage Vth and the inverted voltage V 0 and the inverted voltage V 1 appear symmetrically as described above, the values can be read from the capacitance-voltage polarity in FIG. -1V and 4V are not necessarily required.
　本実施形態では、Ｖｔｈが１．２Ｖ程度と正の電圧とされていたが、Ｖｔｈは負の電圧すなわちＶｔｈ＜０であってもよい。その場合においても、反転電圧Ｖ０と反転電圧Ｖ１の絶対値が異なることになるため、上記実施形態と同様に、大きな衝撃１回加わったことを検出し、記録することができる。 In this embodiment, Vth is a positive voltage of about 1.2 V, but Vth may be a negative voltage, that is, Vth <0. Even in that case, since the absolute values of the inversion voltage V 0 and the inversion voltage V 1 are different, it is possible to detect and record that a large impact has been applied once as in the above embodiment.
　上記のように、本実施形態の衝撃検知・記録装置の特徴は、強誘電体メモリ３の閾値電圧Ｖｔｈを０Ｖからシフトさせたことにある。このように閾値電圧Ｖｔｈを０Ｖからシフトさせるには、前述したように、強誘電体メモリ３を構成する各材料の種類や各材料層の厚み等を選択することにより行い得る。具体的実施例を以下に挙げることにより、これをより詳細に説明する。 As described above, the characteristic of the impact detection / recording apparatus of this embodiment is that the threshold voltage Vth of the ferroelectric memory 3 is shifted from 0V. As described above, the threshold voltage Vth can be shifted from 0 V by selecting the type of each material constituting the ferroelectric memory 3 and the thickness of each material layer. This will be explained in more detail by giving specific examples below.
　以下の実験例では、代表的な強誘電体材料として知られているＳＢＴ（ＳｒＢｉ２Ｔａ２Ｏ９）からなる強誘電体薄膜４を用い強誘電体メモリ３を作製した。炭酸ストロンチウム（ＳｒＣＯ３）、酸化タンタル（Ｔａ２Ｏ５）、酸化ビスマス（Ｂｉ２Ｏ３）をＳｒＢｉ２．２Ｔａ２Ｏ９の組成となるように秤量した。秤量されたこれらの材料をＰＳＺボールを用い湿式粉砕し、混合した。なお、Ｂｉ２Ｏ３を過剰に添加したのは、Ｂｉ２Ｏ３が成膜中に気化するおそれがあるからである。 In the following experimental example, a ferroelectric memory 3 was manufactured using a ferroelectric thin film 4 made of SBT (SrBi 2 Ta 2 O 9 ), which is known as a representative ferroelectric material. Strontium carbonate (SrCO 3 ), tantalum oxide (Ta 2 O 5 ), and bismuth oxide (Bi 2 O 3 ) were weighed so as to have a composition of SrBi 2.2 Ta 2 O 9 . These weighed materials were wet-ground using PSZ balls and mixed. Note that Bi 2 O 3 was added excessively because Bi 2 O 3 might vaporize during film formation.
　上記のように据えられた混合粉末を乾燥し、９００℃の温度で大気中で２時間仮焼した。仮焼された材料をＰＳＺボールを用い粉砕し、仮焼粉末とした。該仮焼粉末を水及びポリビニルアルコールと混合し、乾燥し、プレス原料を得た。 The mixed powder placed as described above was dried and calcined in the atmosphere at a temperature of 900 ° C. for 2 hours. The calcined material was pulverized using PSZ balls to obtain a calcined powder. The calcined powder was mixed with water and polyvinyl alcohol and dried to obtain a press raw material.
　プレス装置により、上記プレス原料を直径２０ｍｍ及び厚み５ｍｍの円盤に成形した。この成形された円盤状成形体を大気中かつ４００℃で加熱し、脱バインダー処理した。しかる後、密閉された匣内で１１５０℃で４時間大気中にて焼成し、焼結体ターゲットを得た。 The press raw material was formed into a disk having a diameter of 20 mm and a thickness of 5 mm by a pressing device. The formed disk-shaped molded body was heated in the atmosphere at 400 ° C. to remove the binder. Thereafter, it was fired in the air at 1150 ° C. for 4 hours in a sealed cage to obtain a sintered compact target.
　半導体基板６として、ｐ型のＳｉ半導体基板を用意した。この半導体基板６上に、ＨｆＯｘをスパッタリングにより成膜し、バッファ層７を形成した。バッファ層７の形成に際しては、Ｒｆ電力＝１００Ｗ、基板温度＝４００℃、ガス流量：２５ｓｃｃｍ（Ａｌ：Ｏ２＝２４：１）及び圧力０．２５Ｐａの条件で成膜した。しかる後、１×１０－４Ｐａの真空中で８００℃に昇温し、しかる後１０分間アニールし、４００℃まで冷却した。４００℃で３０分間、０．２５Ｐａの酸素雰囲気中でアニールを行い、バッファ層７を形成した。 A p-type Si semiconductor substrate was prepared as the semiconductor substrate 6. On this semiconductor substrate 6, HfO x was deposited by sputtering to form a buffer layer 7. The buffer layer 7 was formed under the conditions of Rf power = 100 W, substrate temperature = 400 ° C., gas flow rate: 25 sccm (Al: O 2 = 24: 1), and pressure 0.25 Pa. Thereafter, the temperature was raised to 800 ° C. in a vacuum of 1 × 10 −4 Pa, and then annealed for 10 minutes and cooled to 400 ° C. Annealing was performed in an oxygen atmosphere of 0.25 Pa at 400 ° C. for 30 minutes, and the buffer layer 7 was formed.
　このバッファ層７が形成された半導体基板６のバッファ層７上に、パルスレーザー堆積法により上記焼結体ターゲットを用い強誘電体薄膜４を成膜した。レーザーとしてＫｒＦエキシマレーザーを用いた。基板温度は７５０℃とし、酸素分圧は３３Ｐａとし、レーザーエネルギー１２０ｍＡとして、強誘電体薄膜４の成膜を行った。 The ferroelectric thin film 4 was formed on the buffer layer 7 of the semiconductor substrate 6 on which the buffer layer 7 was formed, using the sintered body target by a pulse laser deposition method. A KrF excimer laser was used as the laser. The ferroelectric thin film 4 was formed at a substrate temperature of 750 ° C., an oxygen partial pressure of 33 Pa, and a laser energy of 120 mA.
　成膜された強誘電体薄膜４を粉砕して得られた粉末をＸ線回折測定により評価した。結果を図４に示す。 The powder obtained by pulverizing the formed ferroelectric thin film 4 was evaluated by X-ray diffraction measurement. The results are shown in FIG.
　図４から明らかなように、Ｘ線回折の２θから、ＳｒＢｉ２Ｔａ２Ｏ９膜が成膜されていることがわかる。 As is apparent from FIG. 4, it can be seen that the SrBi 2 Ta 2 O 9 film is formed from 2θ of X-ray diffraction.
　成膜時間を変えて上記強誘電体薄膜４を形成した後、Ｐｔからなる第1の電極及び第２の電極を２０ｎｍの厚みとなるように成膜した。 After changing the film formation time to form the ferroelectric thin film 4, the first electrode and the second electrode made of Pt were formed to a thickness of 20 nm.
　上記強誘電体薄膜４の膜厚を、１３０、２５０、４００または６００ｍｍとして下記の表１に示す強誘電体メモリ素子１１～１４を得た。 The ferroelectric memory elements 11 to 14 shown in Table 1 below were obtained by setting the film thickness of the ferroelectric thin film 4 to 130, 250, 400 or 600 mm.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　代表例として上記強誘電体メモリ素子１２の静電容量－電圧特性を、ＬＣＲメーター（ヒューレットパッカード社製、品番：ＨＰ４２８４）を用い測定した。測定に際しては、Ｗプローブを利用したプローバで、第１の電極と第２の電極との間に、周波数１ＭＨｚ、５０ｍＶの振幅で－３Ｖ→＋３Ｖ→－３Ｖまで０．１Ｖステップで電圧を印加した。この場合の静電容量を測定し、静電容量の電圧依存性を評価した。なお、第２の電極をグラウンド電位に接続して上記測定を行った。 As a representative example, the capacitance-voltage characteristics of the ferroelectric memory element 12 were measured using an LCR meter (manufactured by Hewlett-Packard Company, product number: HP4284). In the measurement, a probe using a W probe was used to apply a voltage between the first electrode and the second electrode in steps of 0.1 V from −3 V to +3 V to −3 V with a frequency of 1 MHz and an amplitude of 50 mV. . The capacitance in this case was measured, and the voltage dependency of the capacitance was evaluated. The measurement was performed with the second electrode connected to the ground potential.
　上記のようにして得られた静電容量－電圧特性が前述した図３、図５及び図６に示した特性である。 The capacitance-voltage characteristics obtained as described above are the characteristics shown in FIGS. 3, 5 and 6 described above.
　前述したように、ヒステリシスが現れており、正の電圧を印加することにより容量が急激に低下している。 As described above, hysteresis appears, and the capacity is rapidly reduced by applying a positive voltage.
　比較のために、図７に、閾値電圧Ｖｔｈがシフトしていない強誘電体メモリの静電容量－電圧曲線を示す。図７では、ヒステリシスは現れているが、閾値電圧Ｖｔｈは０Ｖである。 For comparison, FIG. 7 shows a capacitance-voltage curve of a ferroelectric memory in which the threshold voltage Vth is not shifted. In FIG. 7, hysteresis appears, but the threshold voltage Vth is 0V.
　前述したように、本実施形態の衝撃検知・記録装置は、強誘電体メモリ３におけるＣＶ特性上のヒステリシスを利用したものである。従って、上記ヒステリシスが現れない強誘電体メモリでは、本発明に用いることができない。例えば、測定時に－１Ｖ→１Ｖ→－１Ｖのように、非常に小さな電圧範囲で電圧をスイープした場合には、ヒステリシスは現れない。これは、強誘電体の電子分極が反転しないことによる。従って、強誘電体メモリ３を用いて上記のように衝撃の検知及び記録を行うには、上記ヒステリシスが現れるように、強誘電体薄膜に抗電界以上の電圧を印加することが必要である。 As described above, the impact detection / recording apparatus of the present embodiment uses the hysteresis on the CV characteristic in the ferroelectric memory 3. Therefore, the ferroelectric memory in which the hysteresis does not appear cannot be used in the present invention. For example, when the voltage is swept in a very small voltage range such as -1V → 1V → -1V during measurement, no hysteresis appears. This is because the electronic polarization of the ferroelectric does not reverse. Therefore, in order to detect and record an impact as described above using the ferroelectric memory 3, it is necessary to apply a voltage higher than the coercive electric field to the ferroelectric thin film so that the hysteresis appears.
　なお、通常の強誘電体メモリでは、閾値電圧Ｖｔｈは０Ｖに位置している。これに対して、本実施形態で用いられている強誘電体メモリは、上記ダイオード接合を有し、ＭＦＩＳ構造を有するため、印加された電圧はすべて強誘電体薄膜４に印加されない。従って、上記ヒステリシスが現れ、かつメモリウィンドがもっとも大きくなるところにおいて、メモリウィンド０．３Ｖ以上になる電圧を上記反転電圧Ｖ０及びＶ１と定義した。 In the normal ferroelectric memory, the threshold voltage Vth is located at 0V. On the other hand, since the ferroelectric memory used in this embodiment has the diode junction and the MFIS structure, all applied voltages are not applied to the ferroelectric thin film 4. Therefore, when the hysteresis appears and the memory window becomes the largest, the voltage at which the memory window becomes 0.3 V or more is defined as the inverted voltages V 0 and V 1 .
　なお、上記のように、強誘電体メモリ３の閾値電圧Ｖｔｈは、材料選択によりそのシフト量を調節することができる。このような強誘電体メモリにおける閾値電圧の変化については、例えば、（Ｊｐｎ．　Ｊ．　Ａｐｐｌ．　Ｐｈｙｓ．　Ｖｏｌ．　４２（２００３）ｐｐ．２０５５－２０５８：Ａ　Ｓｉｇｎｉｆｉｃａｎｔ　Ｉｍｐｒｏｖｅｍｅｎｔ　ｉｎ　ｍｅｍｏｒｙ　Ｒｅｔｅｎｔｉｏｎ　ｏｆ　Ｍｅｔａｌ－Ｆｅｒｒｏｅｌｅｃｔｒｉｃ－Ｉｎｓｕｌａｔｏｒ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｓｔｒｕｃｔｕｒｅ　ｆｏｒ　Ｏｎｅ　Ｔｒａｎｓｉｓｔｏｒ－Ｔｙｐｅ　Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　Ｍｅｍｏｒｙ　ｂｙ　Ｒａｐｉｄ　Ｔｈｅｒｍａｌ　Ａｎｎｅａｌｉｎｇ）においても記載されているように、従来より公知である。すなわち、従来より強誘電体薄膜を用いたＭＦＩＳ構造では、熱処理条件を変えることにより、閾値電圧Ｖｔｈが変化することが知られていた。従って、強誘電体メモリ３における閾値電圧Ｖｔｈをシフトさせる条件等については従来より公知の技術に従って知ることができる。もっとも、このような閾値電圧Ｖｔｈをシフトさせることを積極的に利用した技術については上記文献には示されていない。 As described above, the threshold voltage Vth of the ferroelectric memory 3 can be adjusted in the amount of shift by selecting the material. Regarding the change in threshold voltage in such a ferroelectric memory, for example, (Jpn. -Conventionally known as described in Semiconductor Structure for One Transistor-Type Ferroelectric Memory by Rapid Thermal Annealing). That is, it has been conventionally known that the threshold voltage Vth changes in the MFIS structure using the ferroelectric thin film by changing the heat treatment condition. Therefore, the conditions for shifting the threshold voltage Vth in the ferroelectric memory 3 can be known in accordance with a conventionally known technique. However, the technique that actively uses such a shift of the threshold voltage Vth is not described in the above-mentioned document.
　次に、上記実施形態の効果を実際の衝撃を加えて評価した。すなわち、図８に示すように、強誘電体メモリ３に、スイッチ２１を介してＬＣＲメーター２２及び圧電素子２を接続した。また、図９に示す衝撃生成治具３１を用意した。衝撃生成治具３１では、鉄板３２上にポスト３３が立設されている。ポスト３３に沿って上下方向にスライドし得るガイド３４が設けられている。ガイド３４に圧電素子２を固定し、ガイド３４を高さ２５ｃｍ、８０ｃｍまたは１２０ｃｍの位置から鉄板３２上に落下させた。この落下による衝撃を、上記圧電素子２及び強誘電体メモリ３を含む図８の回路により検出し、記録した。 Next, the effect of the above embodiment was evaluated by applying an actual impact. That is, as shown in FIG. 8, the LCR meter 22 and the piezoelectric element 2 were connected to the ferroelectric memory 3 via the switch 21. Further, an impact generating jig 31 shown in FIG. 9 was prepared. In the impact generating jig 31, a post 33 is erected on an iron plate 32. A guide 34 that can slide up and down along the post 33 is provided. The piezoelectric element 2 was fixed to the guide 34, and the guide 34 was dropped onto the iron plate 32 from a position having a height of 25 cm, 80 cm, or 120 cm. The impact due to the drop was detected and recorded by the circuit of FIG. 8 including the piezoelectric element 2 and the ferroelectric memory 3.
　まず、ＬＣＲメーター２２に強誘電体メモリ３を接続し、リセット状態となるよう電圧を印加した。そのときの静電容量を読みとった。次に、スイッチ２１により強誘電体メモリ３からＬＣＲメーター２２を切り離し、圧電素子２に接続した。この圧電素子２を強誘電体メモリ３とを配線等により接続した状態でガイド３４に固定されている圧電素子２に前述のような落下による衝撃を加えた。そして衝撃による電気エネルギーを、強誘電体メモリ３に書き込んだ。しかる後、スイッチ２１を切り換え、強誘電体メモリ３をＬＣＲメーター２２に再度接続し、静電容量を読みとった。それによって、衝撃を記録することができるか否かを評価した。 First, the ferroelectric memory 3 was connected to the LCR meter 22 and a voltage was applied so as to be in a reset state. The capacitance at that time was read. Next, the LCR meter 22 was disconnected from the ferroelectric memory 3 by the switch 21 and connected to the piezoelectric element 2. The piezoelectric element 2 was fixed to the guide 34 in a state where the piezoelectric element 2 was connected to the ferroelectric memory 3 by wiring or the like, and the impact due to the dropping as described above was applied. Then, electric energy generated by the impact was written in the ferroelectric memory 3. Thereafter, the switch 21 was switched, and the ferroelectric memory 3 was reconnected to the LCR meter 22 to read the capacitance. Thereby, it was evaluated whether or not the impact could be recorded.
　上記圧電素子２としては、加速度検出感度が０．３５ｐＣ／Ｇ、静電容量７４０ｐＦの第１の圧電素子と、加速度検出感度が０．８４ｐＣ／Ｇ、静電容量が７７０ｐＦの第２の圧電素子とを用意した。加速度検出感度が大きいほど、同じ大きさの衝撃でより大きな電荷を発生させる。結果を下記の表２に示す。 The piezoelectric element 2 includes a first piezoelectric element having an acceleration detection sensitivity of 0.35 pC / G and a capacitance of 740 pF, and a second piezoelectric element having an acceleration detection sensitivity of 0.84 pC / G and a capacitance of 770 pF. And prepared. The greater the acceleration detection sensitivity, the greater the charge generated by the same magnitude of impact. The results are shown in Table 2 below.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　表２の試料番号１，２は比較例に相当し、いずれかの高さから落下させた場合においても、衝撃を記録することができなかった。これに対して、試料番号３～１０では、少なくともいずれかの高さ位置から落下した場合に衝撃を検知し、記録することができた。 Sample numbers 1 and 2 in Table 2 correspond to comparative examples, and even when dropped from any height, no impact could be recorded. In contrast, Sample Nos. 3 to 10 were able to detect and record an impact when dropped from at least one of the height positions.
　例えば試料番号７では、２５ｃｍの高さから落下した場合に衝撃を記録することはできなかった。同様に試料番号９では、２５ｃｍ及び８０ｃｍの高さから落下させた場合には衝撃を記録することができなかった。しかしながら、試料番号７及び９においても８０ｃｍの高さや、１２０ｃｍの高さから落下させた場合には衝撃を記録することができる。従って、記録したい衝撃の大きさに応じて、閾値電圧及び反転電圧を調整すれば、本発明に従って１回の衝撃を検出し、記録し得ることがわかる。 For example, sample No. 7 could not record an impact when dropped from a height of 25 cm. Similarly, in sample No. 9, the impact could not be recorded when dropped from a height of 25 cm and 80 cm. However, in the case of sample numbers 7 and 9, the impact can be recorded when dropped from a height of 80 cm or 120 cm. Therefore, it can be seen that one impact can be detected and recorded according to the present invention by adjusting the threshold voltage and the reverse voltage according to the magnitude of the impact to be recorded.
　なお、図１０及び図１１は、上記試料番号５を８０ｃｍから落下させた場合の結果を示す。３～４Ｖの電圧を５秒印加し、リセット処理した段階で、強誘電体メモリの静電容量は１１７ｐＦであり、この状態が「１」の状態に対応する。次に、図１０の矢印Ａ１で示す部分において上記落下試験に従って８０ｃｍの高さから落下させた。その結果、ＬＣＲメーター２２により図示のように１３８ｐＦと大きくなった。なお、上記衝撃を記録した後、再度衝撃を加えても、静電容量は変化しなかった。他方、図１１に示すように－１Ｖの電圧を５秒印加した後、上記強誘電体メモリの静電容量を測定すると１３８．８ｐＦであった。これは、「０」の状態である。再度、上記スイッチ２１により接続を切り換え、矢印Ｂ１及び矢印Ｂ２のタイミングで圧電素子２を８０ｃｍの高さから落下させ、しかる後スイッチ２１を切り換え、ＬＣＲメーター２２により強誘電体メモリの静電容量を読み取った。その結果、図１１に示すように、静電容量は１３９．３ｐＦとほとんど変化せず、記録することができなかった。 In addition, FIG.10 and FIG.11 shows the result at the time of dropping the said sample number 5 from 80 cm. At a stage where a voltage of 3 to 4 V is applied for 5 seconds and the reset process is performed, the capacitance of the ferroelectric memory is 117 pF, and this state corresponds to a state of “1”. Next, it was dropped from a height of 80 cm according to the drop test at the portion indicated by arrow A1 in FIG. As a result, it increased to 138 pF by the LCR meter 22 as shown in the figure. Note that the electrostatic capacity did not change even when the impact was applied again after recording the impact. On the other hand, as shown in FIG. 11, after applying a voltage of −1 V for 5 seconds, the capacitance of the ferroelectric memory was measured to be 138.8 pF. This is a state of “0”. The connection is switched again by the switch 21, and the piezoelectric element 2 is dropped from the height of 80 cm at the timing of the arrows B1 and B2. I read it. As a result, as shown in FIG. 11, the electrostatic capacitance hardly changed to 139.3 pF, and recording could not be performed.
　上記のとおり、試料番号５の強誘電体メモリと上記圧電素子との組み合わせでは、「１」の状態にリセットしておけば、圧電素子からの電気的エネルギーにより衝撃を記録し、保持し得ることがわかる。また、上記のように１回の衝撃を検知し、記録することができる。加えて非常に高感度であるため、１回の衝撃を記録し得るだけでなく、３×３×０．５ｍｍタイプの小さな圧電素子をセンサとして用いることができる。よって、小型携帯端末などに搭載可能な衝撃検知・記録装置を構成し得ることがわかる。 As described above, in the combination of the ferroelectric memory of sample number 5 and the piezoelectric element, if the state is reset to “1”, the impact can be recorded and held by the electric energy from the piezoelectric element. I understand. Further, it is possible to detect and record a single impact as described above. In addition, since the sensitivity is very high, not only can one impact be recorded, but a small piezoelectric element of 3 × 3 × 0.5 mm type can be used as a sensor. Therefore, it can be seen that an impact detection / recording apparatus that can be mounted on a small portable terminal or the like can be configured.
　なお、比較のために試料番号２の強誘電体メモリを用い、上記と同様に圧電素子８０ｃｍから落下させたときの結果を図１２及び図１３に示す。 For comparison, FIGS. 12 and 13 show the results when a ferroelectric memory of sample number 2 was used and dropped from a piezoelectric element of 80 cm in the same manner as described above.
　図１２は、試料番号２の強誘電体メモリを用い、「１」の状態に矢印Ｘ１でスイッチングさせた後、矢印Ｘ２のタイミングで衝撃を加えた場合の結果を示す。図１３では、矢印Ｙ１のタイミングで「０」の状態にスイッチングにした後、矢印Ｙ２のタイミングで衝撃を加えた場合の結果を示す。何れの場合においても衝撃を検知し、かつ記録することができなかった。これは、試料番号２では強誘電体メモリ３を、「０」または「１」の状態にスイッチングさせるにはいずれの場合にも±２Ｖ程度の大きな電圧が必要であることによる。従って、携帯電話機などに実装可能なような小さな圧電素子の出力では、比較例２の強誘電体メモリでは電子分極を反転させることができない。よって、大きな圧電素子を用いなければならないことがわかる。 FIG. 12 shows the result when the impact is applied at the timing of the arrow X2 after switching to the state “1” by the arrow X1 using the ferroelectric memory of the sample number 2. FIG. 13 shows the result when an impact is applied at the timing of the arrow Y2 after switching to the state of “0” at the timing of the arrow Y1. In either case, the impact could not be detected and recorded. This is because, in Sample No. 2, a large voltage of about ± 2 V is required in any case to switch the ferroelectric memory 3 to the “0” or “1” state. Therefore, with the output of a small piezoelectric element that can be mounted on a cellular phone or the like, the electronic polarization cannot be reversed in the ferroelectric memory of Comparative Example 2. Thus, it can be seen that a large piezoelectric element must be used.
１…衝撃検知・記録装置
２…圧電素子
３…強誘電体メモリ
４…強誘電体薄膜
５…第１の電極
６…半導体基板
７…バッファ層
８…第２の電極
２１…スイッチ
２２…ＬＣＲメーター
３１…衝撃生成器具
３２…鉄板
３３…ポスト
３４…ガイド DESCRIPTION OF SYMBOLS 1 ... Impact detection and recording apparatus 2 ... Piezoelectric element 3 ... Ferroelectric memory 4 ... Ferroelectric thin film 5 ... 1st electrode 6 ... Semiconductor substrate 7 ... Buffer layer 8 ... 2nd electrode 21 ... Switch 22 ... LCR meter 31 ... Impact generating device 32 ... Iron plate 33 ... Post 34 ... Guide

Claims (5)

  1. 　衝撃のエネルギーを電気エネルギーに変換し、出力する圧電素子と、
    　前記圧電素子に接続されており、一方主面及び前記一方主面に対向する他方主面を有する強誘電体と、前記強誘電体の一方主面側に形成された第１の電極と、前記強誘電体の他方主面側に形成された第２の電極とを有する強誘電体メモリとを備え、
    　前記強誘電体メモリが、強誘電体の電子分極に由来する少なくとも第１及び第２の状態のいずれかを記録し得るものであり、強誘電体メモリの静電容量－電圧特性がヒステリシスを有し、静電容量－電圧特性のヒステリシス曲線において、電圧上昇時の曲線と、電圧降下時の曲線との間で容量の差が最も大きい電圧値を閾値電圧Ｖｔｈとしたとき、Ｖｔｈ＞０またはＶｔｈ＜０である、衝撃検知・記録装置。     A piezoelectric element that converts impact energy into electrical energy and outputs it;
    A ferroelectric material connected to the piezoelectric element and having one main surface and the other main surface facing the one main surface; a first electrode formed on one main surface side of the ferroelectric; and A ferroelectric memory having a second electrode formed on the other main surface side of the ferroelectric,
    The ferroelectric memory can record at least one of the first and second states derived from the electronic polarization of the ferroelectric, and the capacitance-voltage characteristic of the ferroelectric memory has hysteresis. In the hysteresis curve of capacitance-voltage characteristics, Vth> 0 or Vth, where the threshold voltage Vth is the voltage value having the largest capacitance difference between the curve at the time of voltage rise and the curve at the time of voltage drop. <0, impact detection / recording device.
  2. 　前記強誘電体メモリを第１の状態から第２の状態に反転させるのに必要な反転電圧をＶ０、第２の状態から第１の状態に反転させるための反転電圧をＶ１としたときに、Ｖ０＜０＜Ｖ１またはＶ０＞０＞Ｖ１である、請求項１に記載の衝撃検知・記録装置。 When an inversion voltage necessary to invert the ferroelectric memory from the first state to the second state is V 0 and an inversion voltage for inversion from the second state to the first state is V 1 2. The impact detection / recording apparatus according to claim 1 , wherein V 0 <0 <V 1 or V 0 >0> V 1 is satisfied.
  3. 　前記強誘電体メモリの閾値電圧Ｖｔｈの絶対値が、０．５Ｖ～３Ｖの範囲にある請求項１または２に記載の衝撃検知・記録装置。 3. The impact detection / recording apparatus according to claim 1, wherein an absolute value of the threshold voltage Vth of the ferroelectric memory is in a range of 0.5V to 3V.
  4. 　前記強誘電体メモリが、前記強誘電体と第２の電極との間に積層された半導体層をさらに有する、請求項１～３のいずれか１項に記載の衝撃検知・記録装置。 The impact detection / recording device according to any one of claims 1 to 3, wherein the ferroelectric memory further includes a semiconductor layer stacked between the ferroelectric and the second electrode.
  5. 　前記半導体層と前記強誘電体との間にバッファ層が設けられている、請求項４に記載の衝撃検知・記録装置。 The impact detection / recording apparatus according to claim 4, wherein a buffer layer is provided between the semiconductor layer and the ferroelectric substance.
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