WO2013057465A3 - Method of placing solder balls on a substrate using a stencil with spacing means and reversely tapered apertures and corresponding apparatus - Google Patents

Method of placing solder balls on a substrate using a stencil with spacing means and reversely tapered apertures and corresponding apparatus Download PDF

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Publication number
WO2013057465A3
WO2013057465A3 PCT/GB2012/000795 GB2012000795W WO2013057465A3 WO 2013057465 A3 WO2013057465 A3 WO 2013057465A3 GB 2012000795 W GB2012000795 W GB 2012000795W WO 2013057465 A3 WO2013057465 A3 WO 2013057465A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
stencil
ball placement
spacing means
balls
Prior art date
Application number
PCT/GB2012/000795
Other languages
French (fr)
Other versions
WO2013057465A2 (en
Inventor
Hans Korsse
Leo MERTENS
Theo Van MECHELEN
Original Assignee
Alpha Fry Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha Fry Limited filed Critical Alpha Fry Limited
Publication of WO2013057465A2 publication Critical patent/WO2013057465A2/en
Publication of WO2013057465A3 publication Critical patent/WO2013057465A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/742—Apparatus for manufacturing bump connectors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/06—Solder feeding devices; Solder melting pans
    • B23K3/0607—Solder feeding devices
    • B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41N—PRINTING PLATES OR FOILS; MATERIALS FOR SURFACES USED IN PRINTING MACHINES FOR PRINTING, INKING, DAMPING, OR THE LIKE; PREPARING SUCH SURFACES FOR USE AND CONSERVING THEM
    • B41N1/00—Printing plates or foils; Materials therefor
    • B41N1/24—Stencils; Stencil materials; Carriers therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03005—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for aligning the bonding area, e.g. marks, spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/03828—Applying flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11005—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for aligning the bump connector, e.g. marks, spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER

Abstract

The present invention relates to a method of placing solder balls (400) on a substrate (500) containing a plurality of semiconductor devices having input/output terminals (510) using a ball placement stencil (100) and to a corresponding ball placement stencil (100), the method comprising: - providing a substrate (500); - providing a plurality of balls (400) comprising solder; - providing a ball placement stencil (100) having an upper side (110) and a lower side (120), the ball placement stencil (100) comprising a plurality of apertures (105) for receiving the balls (400) and positioning the balls (400) on the substrate (500), and having attached thereto a plurality of discrete spacing means (200) (e.g. pillars) on the lower side (120); - positioning the ball placement stencil (100) adjacent the substrate (500) so that the ball placement stencil (100) is spaced from the substrate (500) by the spacing means (200); and - depositing the balls (400) onto the substrate (500) via the apertures (105) of the stencil (100), wherein the apertures (105) reduce in width from the upper side (110) towards the lower side (120). The reverse taper of the ball placement stencil (100) provides an upper opening (115) that readily accepts a solder ball (400), whilst providing a lower opening (125) that allows accurate positioning of the solder balls (400) on the substrate (500). The discrete spacing means (200) are arranged on the lower side (120) of the ball placement stencil (100) such that there is a clearance (210) between the edge of the discrete spacing means (200) and the lower opening (125) of each aperture (105). The cleareance (210) allows the discrete spacing means (200) to be located away from flux deposit (300) helping to retain the solder balls (400) in position on the substrate (500), thereby reducing the risk that flux (300) would adhere to the ball placement assembly and increase the need for intensive cleaning. Moreover, a plurality of markers may be located on the lower (120) and/or upper side (110) of the ball placement stencil (100) for alignment of the stencil (100) while positioning it on the substrate (500).
PCT/GB2012/000795 2011-10-20 2012-10-18 Solder ball placement method and apparatus WO2013057465A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1118160.9 2011-10-20
GB1118160.9A GB2495761A (en) 2011-10-20 2011-10-20 Solder Ball Placement Method and Apparatus

Publications (2)

Publication Number Publication Date
WO2013057465A2 WO2013057465A2 (en) 2013-04-25
WO2013057465A3 true WO2013057465A3 (en) 2013-06-13

Family

ID=45220032

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2012/000795 WO2013057465A2 (en) 2011-10-20 2012-10-18 Solder ball placement method and apparatus

Country Status (3)

Country Link
GB (1) GB2495761A (en)
TW (1) TW201322395A (en)
WO (1) WO2013057465A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6213386B1 (en) * 1998-05-29 2001-04-10 Hitachi, Ltd. Method of forming bumps
JP2006324618A (en) * 2005-04-20 2006-11-30 Kyushu Hitachi Maxell Ltd Mask for conductive ball arrangement and its manufacturing method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5918792A (en) * 1997-04-04 1999-07-06 Rvsi Vanguard, Inc. Apparatus and method for filling a ball grid array
US6089151A (en) * 1998-02-24 2000-07-18 Micron Technology, Inc. Method and stencil for extruding material on a substrate
US6191022B1 (en) * 1999-04-18 2001-02-20 Cts Corporation Fine pitch solder sphere placement
US6845901B2 (en) * 2002-08-22 2005-01-25 Micron Technology, Inc. Apparatus and method for depositing and reflowing solder paste on a microelectronic workpiece
US20050139643A1 (en) * 2003-12-30 2005-06-30 Texas Instruments Incorporated Method and system for applying solder
SG178011A1 (en) 2009-08-27 2012-03-29 Alpha Fry Ltd Stencil printing frame

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6213386B1 (en) * 1998-05-29 2001-04-10 Hitachi, Ltd. Method of forming bumps
JP2006324618A (en) * 2005-04-20 2006-11-30 Kyushu Hitachi Maxell Ltd Mask for conductive ball arrangement and its manufacturing method

Also Published As

Publication number Publication date
WO2013057465A2 (en) 2013-04-25
GB201118160D0 (en) 2011-11-30
TW201322395A (en) 2013-06-01
GB2495761A (en) 2013-04-24

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