WO2013054389A9 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2013054389A9 WO2013054389A9 PCT/JP2011/073310 JP2011073310W WO2013054389A9 WO 2013054389 A9 WO2013054389 A9 WO 2013054389A9 JP 2011073310 W JP2011073310 W JP 2011073310W WO 2013054389 A9 WO2013054389 A9 WO 2013054389A9
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
Definitions
- the present invention relates to a non-volatile semiconductor memory, and further to a semiconductor device such as a microcomputer in which a non-volatile semiconductor memory is mounted together with a central processing unit (CPU), and in particular, a voltage generated inside the non-volatile semiconductor memory.
- a semiconductor device such as a microcomputer in which a non-volatile semiconductor memory is mounted together with a central processing unit (CPU), and in particular, a voltage generated inside the non-volatile semiconductor memory.
- CPU central processing unit
- the present invention relates to a semiconductor device that operates by using it.
- the microcomputer In order to detect a decrease or interruption of the power supply of the microcomputer, the microcomputer is provided with a power-on reset circuit and an LVD (Low Voltage Detection) circuit.
- LVD Low Voltage Detection
- the state of the power supply inside the nonvolatile semiconductor memory included in the microcomputer is detected by the power-on reset circuit and the LVD circuit due to various factors such as the use of different power supplies, differences in sensitivity to noise, layout and wiring. There are cases where it is not possible.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2010-2328478 describes a method of discharging as follows as a method of discharging electric charge remaining after the power supply is shut off.
- the discharge circuit includes a plurality of discharge NMOS transistors, a potential compensation NMOS transistor, and a DMOS transistor that lowers the potential of the wiring by a coupling capacitor.
- the potential of the wiring is lowered to a negative potential by the DMOS transistor and the potential compensating NMOS transistor, and a plurality of NMOS transistors for discharge operate to lower the residual charge of the wiring and discharge.
- Patent Document 1 it may be difficult to detect the instantaneous power failure depending on the state of the instantaneous power failure, for example, the amount of voltage change or the width, and a circuit with high accuracy and a large area is required as a countermeasure. There is. In addition, it is difficult to apply to the discharge of voltage wiring having a large load capacity, and there is a possibility that a high voltage remains.
- an object of the present invention is to provide a semiconductor device that can reliably discharge a charge remaining due to a power supply abnormality.
- a control logic unit that generates a control signal that is activated when a power supply is operating normally, and a voltage control line that is supplied with a voltage generated by a voltage generation circuit are provided.
- a charge circuit connected to a certain first node for charging a capacitor element; a first discharge circuit connected to a charge storage node of the charge circuit for discharging the stored charge when the control signal is activated;
- a second discharge circuit is provided for discharging the first node when the charge storage node exceeds a predetermined potential.
- FIG. 3 is a cross-sectional view showing a configuration of a memory cell MC included in a nonvolatile semiconductor memory.
- FIG. It is a figure which shows the electrical equivalent circuit of the memory cell MC. It is a figure which shows the structure of memory block MB, and the structure of its peripheral circuit. It is a figure showing the structure of a power supply instantaneous power failure detection and high voltage discharge circuit, and a reset request circuit. It is a normal timing chart without the instantaneous power failure of an internal power supply at the time of writing in the first embodiment.
- 6 is a timing chart when an instantaneous power failure of the internal power supply occurs during writing in the first embodiment. It is a normal timing chart without the instantaneous power failure of an internal power supply at the time of conventional writing. It is a timing chart when the instantaneous power failure of an internal power supply generate
- FIG. 1 is a configuration diagram of a microcomputer equipped with a nonvolatile semiconductor memory according to an embodiment of the present invention.
- the microcomputer 51 controls the peripheral circuit 52, the oscillation circuit 53 that generates the reference clock clk0, the frequency dividing circuit 54 that divides the reference clock clk0 generated by the oscillation circuit 53, and the transmission of the signal that flows through the bus 72.
- a bus controller 56 controls the RAM (Random Access Memory) 57, a CPU 58, and a system controller 71 that controls the overall operation of the microcomputer 51.
- the microcomputer 51 includes a nonvolatile semiconductor memory 55, a nonvolatile semiconductor memory controller 59 that controls writing to the nonvolatile semiconductor memory in accordance with an instruction from the CPU 58, an input for outputting a signal to the outside and receiving a signal from the outside. And an output port 60.
- the nonvolatile semiconductor memory 55 outputs an activated control signal voltdown to the system controller 71 when it detects an instantaneous power interruption in the nonvolatile semiconductor memory 55.
- the system controller 71 receives the activated control signal voltdown from the nonvolatile semiconductor memory 55, the system controller 71 sends a reset signal RST to each component of the microcomputer 51 to perform initialization processing.
- FIG. 2 is a circuit block diagram of the nonvolatile semiconductor memory.
- the nonvolatile semiconductor memory 55 includes a memory mat 10 in which a plurality of memory cells MC are arranged, an address buffer 12 that generates an address specifying the memory cell MC of the memory mat 10, and an address buffer 12.
- X decoder 14 and Y decoder 16 for selecting the addressed memory cell of memory mat 10 in accordance with the internal address of the memory mat 10.
- the memory mat 10 is divided into a plurality of memory blocks MB, and each memory block MB includes a plurality of memory cells MC.
- Memory cell MC included in memory block MB has the configuration shown in FIGS.
- control gate line CG and memory gate line MG are arranged corresponding to each memory cell row
- source line SL is arranged corresponding to each memory cell row.
- a common bit line BL is arranged corresponding to each memory cell column.
- a global bit line GBL common to a plurality of memory blocks MB is arranged corresponding to each memory cell column. The voltage level in the selected state of each signal line varies depending on the operation mode.
- the address buffer 12 generates an internal address in accordance with a given address AD when accessing the nonvolatile semiconductor memory 55 (when erasing, writing and reading).
- X decoder 14 drives the memory cell row of memory mat 10 to the selected state in accordance with the internal address signal from address buffer 12.
- the nonvolatile semiconductor memory 55 further includes a Y gate 18 for selecting a memory cell column (global bit line GBL) of the memory mat 10.
- Y gate 18 selects global bit line GBL corresponding to the addressed column of memory mat 10 in accordance with a column selection signal from Y decoder 16. In the erase operation mode, Y gate 18 is maintained in a non-conductive state.
- the nonvolatile semiconductor memory 55 further includes a control logic unit 20 that controls internal operations, a write driver 22 that generates internal write data Dm during a write operation, and memory cell data (bit line current) Qm during a read operation.
- Sense amplifier 24 for generating internal read data QI and I / O buffer 26 for inputting / outputting data to / from the outside.
- the control logic unit 20 is composed of, for example, a sequence controller, and performs internal operation control necessary for execution of the designated operation mode in accordance with a command CMD that designates an operation mode from the outside of the nonvolatile semiconductor memory 55. For example, the control logic unit 20 initializes each component in the nonvolatile semiconductor memory 55 when a reset signal RST which is a kind of command CMD is input. In addition, the control logic unit 20 receives the reference clock clk0 from the outside of the nonvolatile semiconductor memory 55 and generates the internal clock clk.
- control logic unit 20 includes a reset request circuit 41.
- the reset request circuit 41 outputs a control signal “voltdown” requesting resetting of the entire microcomputer 51 to the system controller 71 when an instantaneous power failure of the internal power supply is detected.
- the control logic unit 20 further includes a discharge control unit 44.
- the discharge control unit 44 generates a control signal live_pulse for controlling discharge according to the internal clock clk, and supplies the control signal live_pulse to the power supply instantaneous power failure detection / high voltage discharge circuit 40.
- the write driver 22 generates write data Dm for the memory cell MC according to the internal write data WDI from the control logic unit 20.
- Write data Dm from write driver 22 is applied to bit line BL of the selected column via Y gate 18.
- bit line BL of the selected column is set to the ground voltage level, for example, and data “0” is written. Is included.
- the bit line BL for the memory cell MC maintained in the erased state is set to a voltage level comparable to that of the selected memory gate line MG.
- the sense amplifier 24 detects a current (cell data) Qm flowing through the memory cell column (bit line BL) selected via the Y gate 18 in accordance with the sense control signal ⁇ S from the control logic unit 20, and performs internal reading according to the detection result.
- Data QI is generated.
- I / O buffer 26 generates external read data DQ according to internal read data QI from sense amplifier 24 during a read operation, and internal write data DI according to external write data DQ during a write operation. It is generated and given to the control logic unit 20.
- the nonvolatile semiconductor memory 55 further includes an internal voltage generation circuit 30 that generates an internal voltage required according to each operation mode, and a voltage level detection that detects the level of the internal voltage generated by the internal voltage generation circuit 30. Circuit 32.
- the internal voltage generation circuit 30 includes a VDD generation circuit 91, a Vmg generation circuit 92, a Vsl generation circuit 93, a Vbl generation circuit 94, and a Vcg generation circuit 95.
- the internal voltage generation circuit 30 includes an internal reference voltage VDD, a bit line voltage Vbl transmitted to the bit line BL, a control gate voltage Vcg applied to the control gate line CG, and a memory from the power supply voltage VCC outside the nonvolatile semiconductor memory 55 Internal voltages used in the nonvolatile semiconductor memory 55 such as the memory gate voltage Vmg applied to the gate line MG and the source line voltage Vsl applied to the source line SL are generated. When the power supplied to the nonvolatile semiconductor memory 55 is momentarily interrupted, the reference voltage VDD, the bit line voltage Vbl, the control gate voltage Vcg, the memory gate voltage Vmg, and the source line voltage Vsl are indefinite.
- the reference voltage VDD is used as a so-called power source in various circuits in the nonvolatile semiconductor memory 55, particularly in the control logic circuit 20. For this reason, when the reference voltage VDD becomes indefinite, the signal generated by each component in the nonvolatile semiconductor memory 55 operating at the reference voltage VDD and the clock clk become undefined.
- the internal voltage generation circuit 30 generates an internal voltage according to the control signal CTL from the control logic unit 20.
- the control signal vmg_on which is a kind of the control signal CTL
- the memory gate voltage Vmg is boosted.
- the memory gate voltage Vmg is boosted to a high voltage (for example, 10 V or more) at the time of writing.
- the memory gate voltage Vmg is supplied to the X decoder 14 by the voltage control line MMG.
- the power supply interruption detection / high voltage discharge circuit 40 plays such a role. The configuration and operation of the instantaneous power failure detection / high voltage discharge circuit 40 will be described later.
- the voltage level detection circuit 32 adjusts the internal voltage level generated by the internal voltage generation circuit 30 according to the voltage level designation signal LV from the control logic unit 20 according to each operation mode. That is, the voltage level detection circuit 32 sets the detection voltage level according to the voltage level designation signal LV, detects whether the voltage level of the internal voltage generated by the internal voltage generation circuit 30 is at the designated voltage level, and The internal voltage generation operation of the internal voltage generation circuit 30 is controlled according to the detection result.
- FIG. 3 is a cross-sectional view showing the configuration of the memory cell MC included in the nonvolatile semiconductor memory.
- the memory cell MC stores data according to the level change of the threshold voltage.
- the memory cell MC includes a gate insulating film 4 on the surface of the semiconductor substrate region 1 so as to overlap with impurity regions 2 and 3 formed on the semiconductor substrate region 1 and a part of the impurity region 2.
- Impurity regions 2 and 3 are coupled to bit line BL and source line SL, respectively.
- Control gate 5 and memory gate 6 are coupled to control gate line CG and memory gate line MG, respectively.
- the memory gate 6 is formed using the same method as the side wall spacer of the control gate 5. That is, for example, a polysilicon film is deposited on the control gate 5, and this polysilicon film is patterned by etching. The memory gate length can be adjusted by the thickness of the polysilicon film. Therefore, even in the configuration in which two gates of the control gate 5 and the memory gate 6 are provided, the memory gate 6 can be made sufficiently shorter than the control gate 5, and an increase in the memory cell size is sufficiently suppressed.
- the insulating film 7 has a laminated structure of a bottom oxide film (O film) 7a, a nitride film (N film) 7b, and a top oxide film (O film) 7c. Electric charges are accumulated in the nitride film 7b, and data (information) is stored according to the accumulated electric charge amount.
- a select transistor ST is formed by the control gate 5, the impurity region 2 and the semiconductor substrate region 1, and a memory transistor MT is formed by the memory gate 6, the impurity region 3 and the semiconductor substrate region 1.
- FIG. 4 is a diagram showing an electrical equivalent circuit of the memory cell MC.
- a select transistor ST and a memory transistor MT are connected in series between a bit line BL and a source line SL.
- Writing (programming), erasing, reading and holding of data in the memory cell MC are performed as follows.
- a positive voltage is applied to the impurity region 3 via the source line SL, and a memory gate voltage Vmg higher than the voltage of the source line SL is applied to the memory gate 6 via the memory gate line MG.
- a voltage slightly higher than the threshold voltage of the selection transistor ST is applied to the control gate 5 via the control gate line CG.
- the same bit line write voltage as that of semiconductor substrate region 1 is applied to bit line BL.
- This write (program) state is a state in which the threshold voltage of the memory transistor MT is high, and is generally associated with a state in which data “0” is stored.
- a negative voltage is applied to the memory gate 6 via the memory gate line MG.
- a positive voltage is applied to impurity region 3 through source line SL.
- the control gate line CG, the bit line BL, and the semiconductor substrate region 1 are set to the same voltage, and the selection transistor ST is in an off state. In this state, strong inversion occurs in the region where the end of the impurity region 3 connected to the source line SL of the memory gate 6 and the memory gate 6 overlap, causing an interband tunneling phenomenon and generating holes.
- the generated holes (hot holes) are accelerated by the negative bias of the memory gate 6 and injected into the insulating film 7 (nitride film 7b) below the memory gate 6.
- This erase state is a state in which the threshold voltage of the memory transistor MT is low, and is generally associated with a state in which data “1” is stored.
- a positive voltage is applied to the control gate 5 through the control gate line CG, and a channel is formed on the surface of the semiconductor substrate region 1 immediately below the control gate 5.
- a positive voltage between the threshold voltages of the erase state and the write state is applied to the memory gate 6 via the memory gate line MG.
- a channel is selectively formed on the surface of the semiconductor substrate region 1 below the memory gate 6 in accordance with the amount of charge accumulated in the insulating film 7.
- the data is held as charges (electrons or holes) injected into the insulating film 7 below the memory gate 6.
- the movement of charges in the insulating film (nitride film 7b) is small or slow.
- electric charge is held in the insulating film 7, that is, the nitride film 7b.
- FIG. 5 is a diagram showing the configuration of the memory block MB and the configuration of its peripheral circuits. Although the memory block MB actually includes a large number of memory cells MC, FIG. 5 shows eight memory cells MC in two rows and four columns for the sake of simplicity.
- the memory cell MC is configured by a serial body of a selection transistor ST and a memory transistor MT.
- a control gate line CG is commonly provided for the select transistors ST of the four memory cells MC aligned in the X direction, and a memory gate is commonly provided for the memory transistors MT of the four memory cells MC aligned in the X direction.
- a line MG is provided.
- a bit line BL is provided in common for the two memory cells MC aligned in the Y direction.
- Bit line BL is connected to select transistor ST of memory cell MC in the corresponding column via bit line contact BCT.
- Each bit line BL is connected to the global bit line GBL in the corresponding column.
- a source line SL is provided in common for the eight memory cells MC arranged in two rows.
- a control gate drive circuit CGD is provided for each control gate line CG, a source line drive circuit SLD is provided for the source line SL, and a memory gate drive circuit MGD is provided for each memory gate line MG.
- the control gate drive circuit CGD sets the voltage level of the corresponding control gate line CG.
- the source line drive circuit SLD sets the voltage level of the corresponding source line SL.
- Memory gate drive circuit MGD is connected to voltage control line MMG, and supplies the voltage of voltage control line MMG to a corresponding memory gate line MG selected by an address signal (not shown) to set the voltage level.
- Control gate drive circuit CGD, source line drive circuit SLD, and memory gate drive circuit MGD are included in X decoder 14 shown in FIG.
- a bit line peripheral circuit 34 is provided for the four bit lines BL. Bit line peripheral circuit 34 rewrites and reads data via bit line BL. Bit line peripheral circuit 34 includes global bit line BL, Y decoder 16, Y gate 18, sense amplifier 24, and write driver 22.
- FIG. 6 is a diagram illustrating the configuration of the power supply instantaneous power failure detection / high voltage discharge circuit and the reset request circuit.
- the instantaneous power failure detection / high voltage discharge circuit 40 includes a charge circuit 83, a first discharge circuit 82, and a second discharge circuit 84.
- the charge circuit 83 is connected to the node ND1 of the voltage control line MMG through which the memory gate voltage Vmg is transmitted.
- the charge circuit 83 includes a node ND2, an NMOS transistor N3 functioning as a load provided between the nodes ND1 and ND2, and a capacitive element CP provided between the node ND2 and the ground.
- the NMOS transistor N3 is diode-connected.
- the charge circuit 83 can store charges with a time constant of R ⁇ C.
- C is the capacitance element CP
- R is the load resistance value of the N-channel MOS transistor N3.
- the voltage stored by the capacitive element CP that is, the voltage vmg_charge of the node ND2 can be discharged by activating the first discharge circuit 82. Since the resistance of the NMOS transistor N3 is high, the voltage at the node ND1 does not decrease due to the discharge by the first discharge circuit 82.
- the first discharge circuit 82 includes an NMOS transistor N1 provided between the node ND2 and the ground.
- a control signal live_pulse is input to the gate of the NMOS transistor N1.
- the control signal live_pulse is activated to the “H” level, the NMOS transistor N1 is turned on.
- the node ND2 and the ground are connected, and the voltage vmg_charge of the node ND2 is discharged.
- the second discharge circuit 84 includes an NMOS transistor N2 provided between the node ND1 and the ground.
- the gate of the NMOS transistor N2 is connected to the node ND2 and the reset request circuit 41.
- the NMOS transistor N2 is turned on when the voltage vmg_charge at the node ND2 exceeds a threshold voltage TH (about 1 V).
- a threshold voltage TH about 1 V.
- C of the capacitor CP is about 5 ⁇ F
- L of the transistor N1 is about 1 ⁇ m
- W is about 10 ⁇
- L of the transistor N2 is about 1 ⁇ m
- W is about 20 ⁇
- L is about 200 ⁇ m
- W is about 1 ⁇ m.
- C is the capacitance of the capacitor
- L is the gate length of the transistor
- W is the gate width of the transistor.
- the reset request circuit 41 included in the control logic unit 20 includes a front-stage inverter IV1 composed of a PMOS transistor P4 and an NMOS transistor N4, and a rear-stage inverter IV2 composed of a PMOS transistor P5 and an NMOS transistor N5.
- the input of inverter IV1 is connected to node ND2.
- the inverter IV2 outputs a control signal voltdown requesting resetting of the entire microcomputer 51.
- the threshold voltages of the inverters IV1 and IV2 are the same as the threshold voltage TH of the NMOS transistor N2.
- the reset request circuit 41 activates the control signal voltdown to “H” level when the voltage of the node ND2 exceeds the threshold voltage TH.
- FIG. 7 is a normal timing chart in which there is no instantaneous power failure of the internal power supply at the time of writing in the first embodiment.
- control logic unit 20 activates control signal vmg_on to “H” level in synchronization with clock clk, and internal voltage generation circuit 30 sets memory gate voltage.
- Vmg is boosted.
- the voltages of the voltage control line MMG (not shown) and the selected memory gate line MG also increase.
- the memory gate voltage Vmg increases, charges are accumulated in the capacitive element CP of the charge circuit 83, and the voltage vmg_charge of the node ND2 increases at a lower speed than the rate at which the memory gate voltage Vmg increases.
- the discharge control unit 44 of the control logic unit 20 sets the control signal live_pulse to the “H” level with a cycle of dividing the internal clock clk by two. Activate with.
- the NMOS transistor N1 of the first discharge circuit 82 When the control signal live_pulse becomes “H” level, the NMOS transistor N1 of the first discharge circuit 82 is turned on to discharge the voltage vmg_charge of the node ND2. Thereafter, when the control signal live_pulse returns to the “L” level, the NMOS transistor N1 of the first discharge circuit 82 is turned off, the voltage vmg_charge of the node ND2 increases again, and then the control signal live_pulse becomes “H”. Sometimes the increased voltage vmg_charge of the node ND2 is discharged again.
- the control logic unit 20 deactivates the control signal vmg_on to “L” level in synchronization with the clock clk, and the internal voltage generation circuit 30 reduces the memory gate voltage Vmg. Is done. As a result, the voltages of the voltage control line MMG and the selected memory gate line MG are also reduced.
- the memory gate voltage Vmg reaches the ground level, no charge is accumulated in the capacitive element CP of the charge circuit 83, and the voltage vmg_charge of the node ND2 also decreases to the ground level.
- the second discharging is performed.
- the circuit 84 does not operate, and the memory gate voltage Vmg is applied to the selected memory gate line MG via the voltage control line MMG and used for normal rewriting.
- FIG. 8 is a timing chart when an internal power failure occurs during writing in the first embodiment.
- the reference voltage VDD the clock clk
- the control signal vmg_on the memory gate voltage Vmg
- the voltage of the voltage control line MMG not shown
- the voltage of the selected memory gate line MG the control The signal voltdown is indefinite.
- the control signal live_pulse is not periodically activated with a one-shot pulse. Therefore, the voltage vmg_charge at the node ND2 is not discharged by the first discharge circuit 82 and continues to rise.
- the NMOS transistor N2 of the second discharge circuit 84 When the voltage vmg_charge of the node ND2 exceeds the threshold voltage TH, the NMOS transistor N2 of the second discharge circuit 84 is turned on, and the memory gate voltage Vmg is discharged to the ground level. As a result, the voltages of the voltage control line MMG and the selected memory gate line MG are also reduced to the ground level.
- FIG. 9 is a normal timing chart in which there is no instantaneous power failure of the internal power supply during conventional writing.
- the memory gate voltage Vmg is increased or decreased by activation or inactivation of the control signal vmg_on, so that the memory gate voltage Vmg is not maintained at a high voltage.
- FIG. 10 is a timing chart in the case where a momentary power failure of the internal power supply occurs at the time of conventional writing.
- the reference voltage VDD, the clock clk, and the control signal vmg_on are undefined.
- the memory gate voltage Vmg and the voltage of the selected memory gate line MG also become unstable and may be maintained at a high voltage.
- the discharge by the second discharge circuit 84 is substantially performed by the memory gate voltage Vmg itself that is desired to be discharged. Therefore, there is no problem even if the other power supply voltage is lowered.
- the memory gate voltage Vmg can be reduced. Therefore, adverse effects on the reliability of the transistor due to erroneous rewriting of the memory cell or application of a high voltage for a long time can be prevented.
- the system controller 71 controls the entire microcomputer, the system controller notifies the instantaneous power failure of the internal power source. It becomes possible to reset the entire computer, and it is possible to prevent the influence of the instantaneous power interruption in the nonvolatile semiconductor memory from adversely affecting other components in the microcomputer.
- control logic unit 20 activates the control signal live_pulse to the “H” level with a one-shot pulse in a cycle obtained by dividing the internal clock clk by 2, but the present invention is not limited to this.
- a periodic activation is performed from a sequencer in the system controller that controls the entire semiconductor device.
- the control signal live_pulse to be converted may be received.
- the charge circuit 83 does not include the NMOS transistor N3, but the charge circuit 85 may include the resistance element R as shown in FIG.
- a periodic one-shot shot pulse is used as the control signal live_pulse.
- the control signal live_pulse supplied to the first discharge circuit 82 is at the “H” level unless an instantaneous power failure of the internal power supply occurs. Any signal may be used as long as the signal is activated and is deactivated to the “L” level when an internal power failure occurs.
- the control signal live_pulse whose level changes in this way will be described.
- FIG. 12 is a diagram illustrating the configuration of the discharge control unit 44 according to the second embodiment.
- the discharge control unit 44 includes a plurality of flip-flops 61_1 to 61_N and an AND circuit 62 that outputs a logical product of the outputs of the plurality of flip-flops 61_1 to 61_N.
- the size (gate length and gate width) of the MOS transistor that constitutes at least one of the flip-flops 61_1 to 61_N is different from the size of the MOS transistors that constitute the other flip-flops.
- each flip-flop may be configured with a different size MOS transistor.
- the power supply of the plurality of flip-flops is the reference voltage VDD.
- the control signal live_pulse is set to the “H” level by controlling the datah signal and the set signal which are the inputs of the flip-flops 61_1 to 61_N to store and output the “H” level.
- the control signal live_pulse is at the “H” level.
- control signal live_pulse is set to the “L” level by controlling the datah signal and the set signal which are the inputs of the flip-flops 61_1 to 61_N to store and output the “L” level in the flip-flops 61_1 to 61_N. To do.
- the outputs of the plurality of flip-flops 61_1 to 61_N maintain the “H” level, and the control signal live_pulse maintains the “H” level. While the control signal live_pulse is at “H” level, the voltage vmg_charge of the node ND2 is maintained at the ground level.
- the sizes of the plurality of flip-flops 61_1 to 61_N are not uniform, and therefore, some of the plurality of flip-flops 61_1 to 61_N have the “H” level. Output, and the rest outputs “L” level. As a result, the control signal live_pulse becomes “L” level. When live_pulse becomes “L” level, the voltage of the node ND2 gradually increases. When the voltage vmg_charge of the node ND2 exceeds the threshold voltage TH, the memory gate voltage Vmg, which is a high voltage of the node ND1, is directly discharged by the second discharge circuit as in the first embodiment.
- FIG. 13 is a timing chart when an internal power failure occurs during writing in the second embodiment.
- control logic unit 20 activates control signal vmg_on to “H” level in synchronization with clock clk, and internal voltage generation circuit 30 activates the memory gate voltage.
- Vmg increases.
- the voltage of the selected memory gate line MG also increases.
- the discharge control unit 44 of the control logic unit 20 outputs the “H” level live_pulse in synchronization with the clock clk, and thereafter continues to output while maintaining the “H” level.
- the NMOS transistor N1 of the first discharge circuit 82 is turned on, so that no charge is accumulated in the capacitive element CP of the charge circuit 83, and the voltage vmg_charge of the node ND2 does not increase.
- the control signal live_pulse output from the discharge control unit 44 of the control logic unit 20 is not indefinite and changes to the “L” level.
- the NMOS transistor N1 of the first discharge circuit 82 is turned off, charge is accumulated in the capacitive element CP of the charge circuit 83, and the voltage vmg_charge of the node ND2 continues to rise.
- the NMOS transistor N2 of the second discharge circuit 84 When the voltage vmg_charge of the node ND2 exceeds the threshold voltage TH, the NMOS transistor N2 of the second discharge circuit 84 is turned on, and the memory gate voltage Vmg is discharged to the ground level. As a result, the voltage of the selected memory gate line MG is also reduced to the ground level.
- the discharge by the second discharge circuit is performed by the memory gate voltage Vmg itself, so even if the other power supply voltage is lowered.
- the memory gate voltage Vmg can be reduced without any problem.
- the system controller can be connected to the power supply in the nonvolatile semiconductor memory. Since the instantaneous power failure is notified, the entire microcomputer can be reset on the system controller side.
- an inverter is provided in a part of the plurality of flip-flops of the discharge control circuit, and the datah signal and the set signal are controlled to “L” in some of the flip-flops before rewriting.
- the remaining flip-flops are set to the level, and the datah signal and the set signal are controlled and set to the “H” level before rewriting, whereby the detection accuracy of the instantaneous power failure of the internal power supply can be further increased.
- the memory gate voltage Vmg is discharged by an instantaneous power interruption of the internal power supply.
- the present invention is not limited to this.
- the bit line voltage Vbl, the control gate voltage Vcg, and the source line voltage Vsl, which are other voltages generated by the internal voltage generation circuit 30, may be discharged.
- the reference voltage VDD that is generated in the internal voltage generation circuit 30 by receiving the power supply VCC is used as the power supply for the control logic unit 20 (including the discharge control unit 44).
- the control logic unit 20 is inevitably used.
- the power supply VCC is also used as the power supply (including the discharge control unit 44). Even in such a case, the control logic unit 20 detects the abnormality of the VCC that is the power supply, and transmits it to the power supply instantaneous power failure detection / high voltage discharge circuit 40 by the control signal to perform the discharge operation.
- the power supply of the plurality of flip-flops has been described as being the reference voltage VDD, but may be VCC.
- the control logic unit 20 composed of a sequence controller that performs internal operation control necessary for executing the operation mode of the nonvolatile semiconductor memory 55 is provided in the nonvolatile semiconductor memory 55.
- the present invention is also applicable to the case where it is arranged in the nonvolatile semiconductor memory controller 59.
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Abstract
Description
マイクロコンピュータの電源の低下、遮断を検出するために、マイクロコンピュータには、パワーオンリセット回路やLVD(Low Voltage Detection)回路が設けられている。しかし、マイクロコンピュータに含まれている不揮発性半導体メモリ内部の電源の状態は、異なる電源の使用、ノイズに対する感度の違い、配置や配線など様々な要因によって、このパワーオンリセット回路やLVD回路では検出できない場合がある。
[第1の実施形態]
(マイクロコンピュータ)
図1は、本発明の実施形態の不揮発性半導体メモリを搭載したマイクロコンピュータの構成図である。
不揮発性半導体メモリ55は、不揮発性半導体メモリ55内の電源の瞬停を検出したときには、活性化された制御信号voltdownをシステムコントローラ71へ出力する。システムコントローラ71は、不揮発性半導体メモリ55から活性化された制御信号voltdownを受けたときには、リセット信号RSTをマイクロコンピュータ51の各構成要素に送って、初期化処理をさせる。
図2は、不揮発性半導体メモリの回路ブロック図である。
図3は、不揮発性半導体メモリに含まれるメモリセルMCの構成を示す断面図である。このメモリセルMCは、しきい値電圧のレベル変化によってデータを記憶する。
図4は、メモリセルMCの電気的等価回路を示す図である。
図5は、メモリブロックMBの構成およびその周辺回路の構成を示す図である。メモリブロックMBは実際には多数のメモリセルMCを含むが、図5では図面の簡単化のため、2行4列の8個のメモリセルMCが示されている。
図6は、電源瞬停検出・高電圧放電回路およびリセット要求回路の構成を表わす図である。
図7は、第1の実施形態での書込み時に内部電源の瞬停がない通常のタイミングチャートである。
図8は、第1の実施形態での書込み中に内部の電源の瞬停が起こった場合のタイミングチャートである。
また、ノードND2の電圧vmg_chargeが閾値電圧THを越えると、リセット要求回路41によって、制御信号voltdownが「H」レベルに活性化される。「H」レベルの制御信号voltdownを受取ったシステムコントローラ71は、マイクロコンピュータ51の全体をリセットする。
次に、電源瞬停検出・高電圧放電回路40を有しない従来例の動作を説明する。
第1の実施形態では、制御信号live_pulseとして周期的なワンショショットパルスを使用していたが、第1放電回路82に与える制御信号live_pulseは、内部の電源の瞬停が起こらなければ「H」レベルに活性化され、内部の電源の瞬停が起こったときに「L」レベルに非活性化されるような信号であれば、どのようなものでもよい。本実施の形態では、このようにレベルが変化する制御信号live_pulseの別の例を説明する。
図12は、第2の実施形態の放電制御部44の構成を表わす図である。
書換え前に、フリップフロップ61_1~61_Nの入力であるdatah信号とset信号を制御して、「H」レベルを記憶、出力させることによって、制御信号live_pulseを「H」レベルにする。複数のフリップフロップ61_1~61_Nの出力がすべて「H」レベルの場合には、制御信号live_pulseは「H」レベルとなる。
図13は、第2の実施形態での書込み時に内部の電源の瞬停が発生した場合のタイミングチャートである。
また、ノードND2の電圧vmg_chargeが閾値電圧THを越えると、リセット要求回路41によって、制御信号voltdownが「H」レベルに活性化される。「H」レベルの制御信号voltdownが入力されると、システムコントローラ71は、マイクロコンピュータ51の全体をリセットする。
第1および第2の実施の形態では、この不揮発性半導体メモリ55の動作モードの実行に必要な内部動作制御を行なうシーケンスコントローラで構成されている制御論理部20が、不揮発性半導体メモリ55内部に配置されるものとして説明しているが、不揮発性半導体メモリコントローラ59内に配置される場合にも適用可能である。
1 半導体基板領域、2,3 不純物領域、4 ゲート絶縁膜、5 制御ゲート、7 絶縁膜、7a ボトム酸化膜、7b 窒化膜、7c トップ酸化膜、10 メモリマット、12 アドレスバッファ、14 Xデコーダ、16 Yデコーダ、18 Yゲート、20 制御論理部、22 ライトドライバ、24 センスアンプ、26 I/Oバッファ、30 内部電圧発生回路、32 電圧レベル検知回路、34 ビット線周辺回路、40 電源瞬停検出・高電圧放電回路、41 リセット要求回路、44 放電制御回路、51 マイクロコンピュータ、52 周辺回路、53 発振回路、54 分周回路、55 不揮発性半導体メモリ、56 バスコントローラ、57 RAM、58 CPU、59 不揮発性半導体メモリコントーラ、60 入出力ポート、61_1~61_N フリップフロップ、62 論理積回路、71 システムコントローラ、72 バス、82 第1放電回路、83,85 チャージ回路、84 第2放電回路、BCT ビット線コンタクト、BL ビット線、CG 制御ゲート線、CGD 制御ゲートドライブ回路、MB メモリブロック、MC メモリセル、MG メモリゲート線、MMG 電圧制御線、MGD メモリゲートドライブ回路、MT メモリトランジスタ、GBL グローバルビット線、SL ソース線、SLD ソース線ドライブ回路、ST 選択トランジスタ、IV1,IV2 インバータ、N1,N2,N3,N4,N5 NMOSトランジスタ、P4,P5 PMOSトランジスタ、CP 容量素子、R 抵抗素子。
Claims (10)
- 各々がしきい値電圧のレベル変化によってデータを記憶する複数のメモリセルと、
前記メモリセルに与える電圧を発生する電圧発生回路と、
電源が正常に供給されている場合に、活性化される制御信号を生成する制御論理部と、
前記電圧発生回路で発生した電圧が供給される電圧制御線上にある第1のノードと接続されるチャージ回路と、前記チャージ回路は、第2のノードと、前記第2のノードと接続される容量素子とを含み、
前記第2のノードと接続され、前記制御信号が活性化されたときに、前記第2のノードとグランドとを接続する第1放電回路と、
前記第2のノードの電圧が閾値を越えたときに、前記第1のノードと前記グランドとを接続する第2放電回路とを備えた、半導体装置。 - 前記制御論理部は、電源供給の正常を周期的に活性化されることによって示す前記制御信号を生成する、請求項1記載の半導体装置。
- 前記制御論理部は、電源供給の正常を活性化状態の維持によって示す前記制御信号を生成する、請求項1記載の半導体装置。
- 前記制御論理部は、
複数個のフリップフロップと、
前記複数個のフリップフロップの出力の論理積を前記制御信号として出力する論理回路とを備え、
前記複数個のフリップフロップの少なくとも1つのフリップフロップを構成するトランジスタのサイズは、他のフリップフロップを構成するトランジスタのサイズと同一ではない、請求項3記載の半導体装置。 - 前記第1放電回路は、前記第2のノードとグランドとの間に設けられて、制御電極に前記制御信号が入力されるトランジスタを含む、請求項1記載の半導体装置。
- 前記第2放電回路は、前記第1のノードとグランドとの間に設けられて、制御電極が前記第2のノードと接続されるトランジスタを含む、請求項1記載の半導体装置。
- 前記チャージ回路は、前記第1のノードと前記第2のノードの間に設けられる負荷素子と、前記第2のノードとグランドの間に設けられる前記容量素子とを含む、請求項1記載の半導体装置。
- [規則91に基づく訂正 29.03.2013]
前記半導体装置は、システムコントローラを更に備えたマイクロコンピュータであり、
前記第2のノードの電圧が前記閾値を越えたときに、前記システムコントローラに不揮発性半導体メモリが含まれるマイクロコンピュータのリセットを要求するための通知信号を活性化するリセット要求回路をさらに備える、請求項1記載の半導体装置。 - 前記電圧発生回路で発生されて前記電圧制御線に供給される電圧は、前記メモリセルのメモリゲートに与えられるメモリゲート電圧である、請求項1記載の半導体装置。
- 各々がしきい値電圧のレベル変化によってデータを記憶する複数のメモリセルと、
前記メモリセルに与える電圧を発生する電圧発生回路と、
定期的に活性化されることによって電源の正常供給を示す制御信号を生成する制御論理部と、
前記制御信号を受け、前記制御信号が定期的に活性化されないことによって前記電源の瞬停を検知して、前記電圧発生回路で発生した電圧が供給される電圧制御線上にある第1のノードの電圧を放電する回路とを備えた半導体装置。
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PCT/JP2011/073310 WO2013054389A1 (ja) | 2011-10-11 | 2011-10-11 | 半導体装置 |
US14/350,775 US9143118B2 (en) | 2011-10-11 | 2011-10-11 | Semiconductor memory device with power interruption detection and reset circuit |
CN201180074100.3A CN103858349B (zh) | 2011-10-11 | 2011-10-11 | 半导体装置 |
JP2013538350A JP5820888B2 (ja) | 2011-10-11 | 2011-10-11 | 半導体装置 |
TW101134696A TWI540416B (zh) | 2011-10-11 | 2012-09-21 | Semiconductor device |
US14/826,117 US20150348641A1 (en) | 2011-10-11 | 2015-08-13 | Semiconductor memory device with power interruption detection and reset circuit |
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PCT/JP2011/073310 WO2013054389A1 (ja) | 2011-10-11 | 2011-10-11 | 半導体装置 |
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US14/826,117 Continuation US20150348641A1 (en) | 2011-10-11 | 2015-08-13 | Semiconductor memory device with power interruption detection and reset circuit |
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CN104467767A (zh) * | 2014-12-18 | 2015-03-25 | 中国电子科技集团公司第五十四研究所 | 一种可多次连续复位的复位电路 |
JP6187454B2 (ja) * | 2014-12-29 | 2017-08-30 | コニカミノルタ株式会社 | 画像処理装置 |
JP6170596B1 (ja) * | 2016-06-15 | 2017-07-26 | ウィンボンド エレクトロニクス コーポレーション | 半導体装置 |
US10832765B2 (en) * | 2018-06-29 | 2020-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Variation tolerant read assist circuit for SRAM |
JP7332493B2 (ja) * | 2020-01-30 | 2023-08-23 | キオクシア株式会社 | メモリシステムおよび半導体記憶装置 |
KR20210155224A (ko) | 2020-06-15 | 2021-12-22 | 삼성전자주식회사 | 고전압 스위칭 회로를 포함하는 비휘발성 메모리 장치 및 이의 동작 방법 |
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JPS6278646A (ja) | 1985-10-02 | 1987-04-10 | Mitsubishi Electric Corp | 不揮発性半導体メモリのメモリ誤動作保護回路 |
US5109163A (en) * | 1991-02-15 | 1992-04-28 | Zilog, Inc. | Integrated power-on reset circuit |
KR100481841B1 (ko) | 1997-11-25 | 2005-08-25 | 삼성전자주식회사 | 음의고전압을방전시키기위한회로를구비한플래시메모리장치 |
JP2000148309A (ja) * | 1998-11-11 | 2000-05-26 | Miyagi Oki Denki Kk | マイクロプロセッサのリセット回路 |
US7135898B2 (en) * | 2003-06-27 | 2006-11-14 | Macronix International Co., Ltd. | Power-on reset circuit with supply voltage and temperature immunity, ultra-low DC leakage current, and fast power crash reaction |
JP2007018584A (ja) * | 2005-07-06 | 2007-01-25 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
JP5238943B2 (ja) | 2006-11-14 | 2013-07-17 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 高電圧回路のリセット回路 |
JP5183087B2 (ja) * | 2007-03-30 | 2013-04-17 | ルネサスエレクトロニクス株式会社 | 不揮発性半導体記憶装置 |
JP5217848B2 (ja) * | 2008-09-29 | 2013-06-19 | ルネサスエレクトロニクス株式会社 | 不揮発性半導体記憶装置 |
JP2010232848A (ja) | 2009-03-26 | 2010-10-14 | Oki Semiconductor Co Ltd | 半導体メモリの内部電源のスタートアップ回路 |
JP5225946B2 (ja) * | 2009-07-28 | 2013-07-03 | 株式会社三共 | 遊技機 |
US8754679B2 (en) * | 2009-09-29 | 2014-06-17 | Texas Instruments Incorporated | Low current power-on reset circuit and method |
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- 2011-10-11 CN CN201180074100.3A patent/CN103858349B/zh active Active
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- 2011-10-11 WO PCT/JP2011/073310 patent/WO2013054389A1/ja active Application Filing
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2012
- 2012-09-21 TW TW101134696A patent/TWI540416B/zh not_active IP Right Cessation
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JPWO2013054389A1 (ja) | 2015-03-30 |
CN103858349B (zh) | 2016-11-09 |
TW201337519A (zh) | 2013-09-16 |
JP5820888B2 (ja) | 2015-11-24 |
WO2013054389A1 (ja) | 2013-04-18 |
CN103858349A (zh) | 2014-06-11 |
US20140233328A1 (en) | 2014-08-21 |
US9143118B2 (en) | 2015-09-22 |
US20150348641A1 (en) | 2015-12-03 |
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