WO2013053236A1 - 多径对齐累加方法及装置 - Google Patents

多径对齐累加方法及装置 Download PDF

Info

Publication number
WO2013053236A1
WO2013053236A1 PCT/CN2012/076180 CN2012076180W WO2013053236A1 WO 2013053236 A1 WO2013053236 A1 WO 2013053236A1 CN 2012076180 W CN2012076180 W CN 2012076180W WO 2013053236 A1 WO2013053236 A1 WO 2013053236A1
Authority
WO
WIPO (PCT)
Prior art keywords
user
data
multipath
alignment
accumulation
Prior art date
Application number
PCT/CN2012/076180
Other languages
English (en)
French (fr)
Inventor
张林生
冯立国
洪思华
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to EP12840104.9A priority Critical patent/EP2768152B1/en
Priority to IN3576CHN2014 priority patent/IN2014CN03576A/en
Publication of WO2013053236A1 publication Critical patent/WO2013053236A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/711—Interference-related aspects the interference being multi-path interference
    • H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/7103—Interference-related aspects the interference being multiple access interference

Definitions

  • the present invention relates to the field of communication technologies, and in particular, to a multipath alignment accumulation method and apparatus in an interference cancellation processing process of a Wideband Code Division Multiple Access (WCDMA) system.
  • WCDMA Wideband Code Division Multiple Access
  • WCDMA is one of the third generation mobile communication air interface standards.
  • WCDM A belongs to spread spectrum communication, which adopts bidirectional closed loop power control, transmit and receive diversity, RAKE receive anti-multipath fading, convolutional code and Turbo code channel codec.
  • the mobile communication channel is very different from the fixed communication channel.
  • the WCDMA baseband receiver moves, the electromagnetic wave received by the antenna of the receiver can be directly transmitted by the transmitter antenna, or can be transmitted at the transmitter antenna. After that, multiple paths, such as reflection and diffraction, are delayed to propagate and arrive. Therefore, the received signal of the receiver has many multi-factor delays, and these multipath results interfere with each other to form multipath fading of the wireless channel.
  • the correlation of the pilot PN code is used to track and receive the resolvable multipath components in the received signal, and the baseband signals are output and path merged.
  • This method of receiving signals is called RAKE correlation.
  • RAKE-related reception performs correlation demodulation on each multipath.
  • These correlation demodulators are also called RAKE fingers.
  • the outputs of these multipath receivers are combined and sent to the channel decoder for RAKE fingers.
  • RAKE-related reception utilizes multipath components, which equivalently increases the received transmit power and achieves the goal of resisting multipath fading.
  • the multipath offset information obtained by RAKE reception and the demodulated and correctly decoded user symbols are combined with the channel estimation values to reconstruct and recover these multipath data.
  • the reconstructed multipath data is then aligned to the system timing of the original antenna data for accumulation, and finally subtracted from the original antenna data, thereby canceling out the known user multipath pairs unknown (undemodulated and decoded correctly) users
  • the effect of adding demodulation to the remaining unknown users is decoded correctly and without rate. This is called interference cancellation.
  • FIG. 1 is a schematic diagram of an offset between four user multipath data and system timing (which may also be referred to as an offset between user timing and system timing), wherein configurable correlation length is used as ip.
  • ipO to ip7 8 ip is 256chip, this article uses 256chip as an example
  • a multipath accumulating length, the length can also be configured, and each multipath serial accumulation respectively represents a certain multipath, and when the transmitter sends a signal, the actual relative system timing offset, that is, more than four The ipO of the path is issued at the time of the system timing ipO.
  • multipaths are aligned to the system timing for accumulation, and need to be performed in order: First, the stored data corresponding to the multipath offset position is read out, then accumulated, and finally stored back to the corresponding multipath offset position. These multipath data are aligned to the system timing for accumulation, and it is necessary to solve the problem of alignment efficiency and accumulation conflict.
  • one clock can only be aligned to accumulate a minimum unit, such as lchip or 4chip, and its alignment accumulation efficiency is low, and does not involve pipeline design, anteroposter to accumulate random access memory (RAM, Random Access Memory) )
  • RAM Random Access Memory
  • the main object of the present invention is to provide a multipath alignment accumulating method and apparatus, which aims to improve the multipath alignment accumulating efficiency of a WCDMA system and solve the problem of read and write conflicts of the anteroposter to the accumulated RAM.
  • the present invention provides a multipath alignment and accumulation method, the method comprising: receiving reconstructed user multipath data;
  • the multipath data of the user is paired by means of user timing and system timing being aligned with each other.
  • the alignment and accumulation process of the user multipath data is performed in a pipeline operation manner.
  • the step of performing an alignment and accumulation process on the user multipath data in a manner that the user timing and the system timing are aligned with each other includes:
  • the corresponding multipath offset is less than one ip filled with 0, and the aligned user multipath data is constructed;
  • the accumulated user multipath data is written back to the storage location corresponding to the system timing.
  • the method further comprises:
  • the user multipath data is aligned and accumulated anti-collision processing by means of high-level control scheduling.
  • the step of performing an alignment and accumulation process on the user multipath data in a manner that the user timing and the system timing are aligned with each other includes:
  • the storage space of the system timing is configured as an even ip storage unit and an odd ip storage unit, and the even ip storage unit and the odd ip storage unit respectively comprise a plurality of storage locations, each storage location corresponding to a system timing clock;
  • the step of performing an alignment and accumulation process on the multipath data of the user in a manner that the user timing and the system timing are mutually aligned further includes:
  • the corresponding accumulation result is obtained from the storage location corresponding to the even ip storage unit, the odd ip storage unit, the accumulation pipeline stage, or the write reflow stage, and the corresponding result is obtained.
  • the accumulated result is aligned with the current user multipath data.
  • the type of the multipath offset of the user multipath data relative to the system timing comprises: the multipath offset of the user multipath data relative to the system timing is within [2n, 2n+l) ips, or the user The multipath offset of the multipath data relative to the system timing is within [2 ⁇ +1, 2n+2) ips, where n is an integer.
  • the invention also provides a multipath alignment accumulating device, comprising: a data receiving module and an alignment accumulating module, wherein:
  • a data receiving module configured to receive the reconstructed user multipath data
  • the alignment accumulating module is configured to perform an alignment and accumulation process on the multipath data of the user by means of user timing and system timing being aligned with each other.
  • the alignment and accumulation module is further configured to perform an alignment and accumulation process on the user multipath data in a pipeline operation manner.
  • the alignment accumulating module comprises: an obtaining unit, a constructing unit, a reading unit, an accumulating unit and a writing back unit, wherein:
  • An acquiring unit configured to obtain a multipath offset of the user multipath data relative to the system timing; and a constructing unit, configured to: at both ends of the multipath data of the user, the corresponding multipath offset is less than a correlation length, and the structure is aligned. User multipath data afterwards;
  • a reading unit configured to read, according to the aligned user multipath data, storage data of a storage location corresponding to the system timing
  • An accumulating unit configured to store data of a storage location corresponding to the read timing of the system The aligned user multipath data is accumulated;
  • a write back unit configured to write the accumulated user multipath data back to the storage location corresponding to the system timing.
  • the alignment and accumulation module is further configured to perform alignment and accumulation anti-collision processing on the multi-path data of the user by means of high-level control scheduling.
  • the constructing unit is further configured to configure the system timing storage space as an even ip storage unit and an odd ip storage unit, where the even ip storage unit and the odd ip storage unit respectively comprise a plurality of storage locations, each The storage location corresponds to a system timing clock;
  • the reading unit is further configured to separately read the storage data of the storage location corresponding to the even-numbered ip storage unit and the odd-numbered ip storage unit according to the type of the multipath offset of the user multipath data relative to the system timing ;
  • the accumulating unit is further configured to align and store the storage data of the storage location corresponding to the even ip storage unit and the odd ip storage unit with the user multipath data;
  • the write back unit is further configured to write the accumulated result of the storage location corresponding to the even ip storage unit or the odd ip storage unit after the accumulation is completed to the storage location corresponding to the system timing.
  • the alignment accumulating module is further configured to: when the read/write conflict occurs between the two user multipath data, the storage location corresponding to the even ip storage unit, the odd ip storage unit, the accumulation pipeline stage, or the write back water The phase acquires the corresponding accumulated result, and aligns the corresponding accumulated result with the current user multipath data.
  • the multipath alignment and accumulation method and device provided by the present invention align and accumulate user multipath data by means of user timing and system timing alignment, and a system clock can be aligned to accumulate a user length multipath data of a relevant length, and The correlation length can be configured to finally align the user timing to the system timing, improve the multipath alignment accumulation efficiency of the WCDMA system, solve the problem of multi-path alignment accumulating RAM read and write conflicts before and after, and greatly improve the processing of the WCDMA system interference cancellation system. ability.
  • FIG. 1 is a schematic diagram of the offset of the current four-user multipath data with respect to system timing;
  • FIG. 2 is a schematic flowchart of an embodiment of the multipath alignment and accumulation method of the present invention
  • FIG. 3 is a schematic flowchart of a first embodiment of performing alignment and accumulation processing on user multipath data by means of user timing and system timing being aligned with each other in an embodiment of the multipath alignment and accumulation method of the present invention
  • FIG. 4 is a timing diagram showing the alignment of a user multipath data in the first embodiment shown in FIG. 3;
  • FIG. 5 is a schematic flowchart of a second implementation manner of performing alignment and accumulation processing on user multipath data in a manner in which user timing and system timing are mutually aligned in an embodiment of the multipath alignment and accumulation method of the present invention
  • FIG. 6 is a schematic diagram showing alignment and accumulation timing of a single user multipath data with a multipath offset of 0.5 i relative to system timing in the first embodiment shown in FIG. 5;
  • FIG. 7 is a schematic diagram showing the alignment and accumulation timing of a single user multipath data with a multipath offset of 1.5 i relative to the system timing in the first embodiment shown in FIG. 5;
  • FIG. 8 is a schematic diagram of a general alignment accumulating timing in which a multi-path offset of a single user multipath data is within [2n, 2n+l] ips according to an embodiment of the multipath alignment accumulating method of the present invention
  • the multi-path alignment accumulating method is a general alignment accumulating timing diagram in which the multi-path offset of the single user multipath data is within [2 ⁇ +1, 2n+2) ips;
  • Figure 11 is a block diagram showing the structure of an alignment accumulation module in an embodiment of the multipath alignment accumulating device of the present invention. detailed description
  • the solution of the embodiment of the present invention is mainly: aligning and accumulating user multipath data by means of user timing and system timing being aligned with each other, and one system clock can be aligned to accumulate one phase.
  • the length of the user multipath data, and the correlation length can be configured, and finally realizes the user timing alignment to the system timing, so as to improve the multipath alignment accumulation efficiency of the WCDMA system, and solve the problem of multi-path alignment accumulating RAM read and write conflicts before and after.
  • an embodiment of the present invention provides a multipath alignment accumulation method, which includes the following steps:
  • Step S101 Receive reconstructed user multipath data.
  • the method operation environment of the embodiment involves the offset accumulation processing of the signal after the reconstruction processing is performed in the cancellation interference processing of the WCDMA system, and the apparatus for running the multipath alignment accumulation method of the embodiment first receives the reconstructed user multipath data,
  • the user multipath data has different path delays according to reflection and diffraction, and the multipath offset is different from the system timing.
  • Step S102 Align and accumulate the user multipath data by means of user timing and system timing being aligned with each other.
  • the alignment and accumulation process of the user multipath data is completed in a pipeline operation manner, and one ip can be aligned at a time, that is, equivalent to aligning a configurable correlation length within one clock cycle (cycle), and its final purpose It is to realize the alignment between user timing and system timing, and improve the efficiency of alignment accumulation processing of user multipath data, and solve the conflict problem of system alignment accumulation.
  • the foregoing step S102 includes: Step S1021: Acquire a multipath offset of user multipath data with respect to system timing;
  • Step S1022 At both ends of the user multipath data, the corresponding multipath offset is less than a correlation length and is filled with 0, and the aligned user multipath data is constructed;
  • Step S1023 Read the stored data of the storage location corresponding to the system timing according to the aligned user multipath data
  • Step S1024 storing the stored data of the storage location corresponding to the read system timing and the aligned User multipath data is accumulated;
  • Step S1025 Write the accumulated user multipath data back to the storage location corresponding to the system timing.
  • one user multipath data may be aligned and processed, and multiple user multipath data may be processed in an aligned manner.
  • the pipeline operation is completed, and the alignment may be performed at one time.
  • An ip. First, the user multipath data is aligned to the system timing, and the aligned user multipath data is obtained. Then, the aligned user multipath data is used, and the stored data of the corresponding position of the system timing is read, and the accumulation is performed, and finally the accumulated result is stored. Returns the corresponding position of the system timing.
  • an alignment accumulation process of a user multipath data (fingerO) shown in FIG. 4 is taken as an example:
  • the fingerO includes 8 ip data from ipO to ip7, and the relevant length of each ip can be configured.
  • sipO to sip8 aligned user multipath data, read the stored data of the corresponding location of the system timing, accumulate, and then save back.
  • This embodiment can accumulate a configurable correlation length by one clock alignment, and the alignment accumulation efficiency of the system user multipath data is improved compared with the prior art.
  • the user multipath data is aligned and accumulated by the method of high-level control scheduling, thereby avoiding the alignment accumulation conflict of the multi-path data of the two users before and after. That is, the multi-path data of the two users before and after the multi-path data is arranged by the high-level software to be demodulated by different antennas, if it must be If the same antenna data is used, the high-level software configuration shields the path from re-configuration, that is, it does not cause an accumulation conflict between the two paths.
  • this embodiment requires an additional clock C y C l e to expand the data of 8 ips into 9 ips (before and after insertion 0), which loses the reconstruction accumulation capability of the system 1/9, if a multipath If the accumulated length is L ips, the reconstruction accumulation capacity of 1/L is lost.
  • this embodiment proposes a second embodiment.
  • the second embodiment is the same as the first embodiment described above in that the alignment and accumulation processing of the plurality of user multipath data is also performed in a pipeline operation manner, and one ip can be aligned at a time.
  • the difference is that the second implementation method can solve the problem of alignment and accumulation conflict of two user multipath data before and after the high-level control scheduling.
  • the foregoing step S102 includes:
  • Step S1026 the system timing storage space is configured as an even ip storage unit and an odd ip storage unit, and the even ip storage unit and the odd ip storage unit respectively comprise a plurality of storage locations, and each storage location corresponds to a system timing clock;
  • Step S1027 Read the storage data of the storage location corresponding to the even ip storage unit and the odd ip storage unit according to the type of the multipath offset of the user multipath data relative to the system timing;
  • the types of multipath offsets of the user multipath data relative to the system timing include: the multipath offset of the user multipath data relative to the system timing is within [2n, 2n+l) ips, or the user multipath data relative system The timing multipath offset is within [2n+l, 2n+2) ips, where n is an integer.
  • Step S1028 aligning the storage data of the storage location corresponding to the even ip storage unit and the odd ip storage unit with the user multipath data;
  • Step S1029 Write the accumulated result of the storage location corresponding to the even ip storage unit or the odd ip storage unit after the accumulation is completed back to the storage location corresponding to the system timing.
  • the accumulated RAM aligned to the system timing is divided into an even ip storage unit ( Even ip RAM ) and an odd ip storage unit ( Odd ip RAM ), and the even ip storage unit and the odd ip storage unit respectively include several storages. Position, each storage location corresponds to a system-timed clock.
  • the accumulated RAM of the system timing is empty, and the corresponding even ip storage unit and odd ip storage unit are also empty.
  • an Even ip and an Odd ip are read out from the accumulated RAM of the system timing to align an ip of the user timing, and then, according to the multipath offset type of the user multipath data relative to the system timing, Read an Even i or an Odd ip from an even ip storage unit or an odd ip storage unit, and combine the accumulated result of the last odd i storage unit or even i storage unit to align an ip of the user timing, thereby increasing Alignment efficiency.
  • Fig. 6 is a schematic diagram of the alignment and accumulation timing of a single user multipath data with a multipath offset of 0.5 ip relative to the system timing.
  • fO is a shorthand for the user multipath data fingerO, and the multipath offset of fO relative to the system timing is 0.5 ip.
  • system-timed accumulated RAM is divided into two blocks of Even i and Odd i, and then the following steps are used to perform the alignment accumulation:
  • fO RE ( n ) is used to denote fO Read Even ip RAM address ( n )
  • fO ACC E ( n ) is the storage portion of the data of the aligned accumulated fO ipO and the corresponding system timing Even ip address (n )
  • the thin line box indicates Wait for the next alignment accumulation after one alignment and accumulate.
  • the thick line box indicates the data that is accumulated after one or two alignments are completed, ready to be written back
  • fO WE (n) represents the system timing corresponding to the write-back address of Even i (n) 0
  • the 0th clock (clock cycle 0) needs to read the stored data from the address n of the Even ip RAM and the Odd ip RAM address n respectively; the output of the second clock (clock cycle 2) is recorded as E ( n ) and 0 ( n ); Accumulate and register the fO ACC E ( n ) of the thick line frame and the fO ACC O ( n ) of the thin line frame in the third clock, respectively, and the front part and the back part of the ipO of fO, where the thick line
  • the frame fO ACC E( n ) has completed the alignment accumulation with fO, and the thin line frame fO ACC O ( n ) also needs to be aligned and accumulated in the next 4th clock with the previous part of fO ipl ; therefore, At the 4th clock, fO ACC E ( n ) can be written back to the address n of the Even ip RAM, and at the 5th clock,
  • the first clock reads the stored data from the address n+1 of the Even ip RAM; the third clock gets E ( n+1 ), the fourth clock thin line frame fO ACC O ( n ) and E ( n+1 ) is respectively accumulated and registered with the previous part and the latter part of the i1 of fO to obtain a thick line frame fO ACC 0 ( n ) and a thin line frame fO ACC E ( n+1 ), and the fifth clock will be fO ACC O ( n ) Write back the address n of the Odd ip RAM. And fO ACC E ( n+1 ) will be aligned and accumulated on the 5th clock and ip2, and the 6th clock will be written back to the Even ip RAM address n+1.
  • ip7 directly obtains the thick line frame fO ACC E ( n+4 ) and the thick line frame fO ACC O ( n+3 ) after the alignment accumulation of the 10th clock. ), at the 11th clock, write both of them back to the Even ip RAM address n+4 and 0 (1 (11 1 ⁇ ) ⁇ address 11+3.
  • a general alignment accumulating timing in which a single-path multipath offset relative to the system timing is within [2n+l, 2n+2) ip can be obtained, where n is an arbitrary integer, as shown in the figure.
  • n is an arbitrary integer, as shown in the figure.
  • the alignment accumulation operation for ip0 ⁇ ip7 and fO and system timing offset are at [2n, 2n+l).
  • the difference is only: the address of the Even ip RAM or Odd ip RAM is different at the same clock time, and the sequence of completing the write back to Even ip RAM or Odd ip RAM is different.
  • the optimized single-path alignment and accumulation scheme uses 8 cycles to align and accumulate 8 ips of data, without losing the system's reconstruction cancellation capability, and improving the alignment accumulation of multi-path data of system users. effectiveness.
  • the ipO may need to read the data of the 5 addresses (for example, the fl multipath offset is equal to (2n+4) ip, then the ipO needs to go in the 8th clock. Read E ( n+2 ) and 0 ( n+2 ) ).
  • the accumulated RAM operation conflicts when the two paths are aligned and accumulated (including: reading and writing the same address at the same time; or the accumulated result of the previous path) An address has not been written back, and the next path has to read the address).
  • the accumulation and write back operations of the previous path are still performed according to the established rules.
  • the data read from Even ip RAM or Odd ip RAM is discarded, and the accumulation of the previous path is selected. Write back to the operation pipeline to obtain the corresponding data at different stages, and as a result of the actual accumulation, align and accumulate with ipO.
  • the ipO needs to read the address of the Even ip RAM (n+2) and the address of the Odd ip RAM (n+2) on the 8th clock. ), and expect to get E ( n+2 ) and 0 ( n+2 ) on the 10th clock, and fO is going to write back E ( n+2 ) on the 8th clock, and 0 ( n+2 ) will The 9th clock can be written back.
  • ip0 ⁇ ip3 may have read and write accumulate RAM conflicts with it, and the conflict processing is as above.
  • the processing that is, when a conflict occurs, the corresponding data is taken from the aligned accumulation pipeline stage of the previous path (may need to add different delays), and is regarded as the result read out from Even ip RAM or Odd ip RAM to participate in the connection. Align, accumulate, write back and other operations.
  • multipath offsets of user multipath data relative to system timing there are two types of multipath offsets of user multipath data relative to system timing.
  • One is that the multipath offset of the user multipath data relative to the system timing is within [2n, 2n+l) ips.
  • the other is that the multipath offset of the user multipath data relative to the system timing is within [2n+l, 2n+2) ips, where n is an arbitrary integer.
  • the four combinations include:
  • the offset relationship between the multipath data of the previous user is first determined, and then the conflict is accumulated according to the conflict situation.
  • the conflict condition is determined, the multipath of the two paths is first determined.
  • the offset belongs to which of the above four types of combinations, and then specifically analyzes which conflict situation.
  • data is taken from different stages of the pipeline for alignment accumulation, for example, from an even ip storage unit, an odd ip storage unit corresponding storage location, an accumulation pipeline stage, or a write reflow phase to obtain a corresponding accumulation result, and
  • the corresponding accumulated result is aligned with the current user multipath data, thereby effectively solving the problem that the two users multi-path data alignment accumulates before and after the read and write accumulate RAM conflicts.
  • the user multi-path data is aligned and accumulated by the user timing and the system timing are aligned with each other, and a system clock can be aligned to accumulate a user length multipath data of a relevant length, and the correlation length is configurable, and finally the user is implemented. Timing alignment to system timing, improved
  • the multipath alignment accumulating efficiency of the WCDMA system solves the problem of multi-path alignment accumulating RAM read and write conflicts before and after, and greatly improves the processing capability of the WCDMA system interference cancellation system.
  • an embodiment of the present invention provides a multipath alignment accumulating device.
  • the device is generally disposed at a WCDMA baseband receiver, and includes: a data receiving module 201 and an alignment accumulating module 202, where:
  • the data receiving module 201 is configured to receive the reconstructed user multipath data
  • the alignment accumulating module 202 is configured to perform alignment and accumulation processing on the user multipath data by means of user timing and system timing being aligned with each other.
  • the multipath alignment and accumulating device first receives the reconstructed user multipath data through the data receiving module 201, and the plurality of user multipath data have different path delays according to reflection and diffraction, and the multipath offset is different from the system timing, and then The alignment accumulating module 202 performs an alignment and accumulation process on the user multipath data in a manner in which the user timing and the system timing are aligned with each other.
  • the alignment and accumulation process of the user multipath data is completed in a pipeline operation manner, and one ip can be aligned at a time, which is equivalent to aligning a configurable correlation length within one clock cycle, and the final purpose is to achieve User timing is aligned with system timing, and the efficiency of alignment and accumulation processing of user multipath data is improved, and the conflict of system alignment accumulation is solved.
  • the following is a detailed description of the process of aligning and accumulating user multipath data by the alignment accumulating module 202 in the embodiment in which the user timing and the system timing are aligned with each other in two specific embodiments.
  • the foregoing alignment and accumulation module 202 includes: an obtaining unit 2021, a constructing unit 2022, a reading unit 2023, an accumulating unit 2024, and a writing back unit 2025, where:
  • the obtaining unit 2021 is configured to obtain a multipath offset of the user multipath data relative to the system timing.
  • the constructing unit 2022 is configured to fill the corresponding multipath offset at the two ends of the user multipath data by less than one correlation length, and construct the alignment.
  • the reading unit 2023 is configured to read, according to the aligned user multipath data, the storage data of the storage location corresponding to the system timing;
  • the accumulating unit 2024 is configured to accumulate the stored data of the storage location corresponding to the read system timing and the aligned user multipath data;
  • the write back unit 2025 is configured to write the accumulated user multipath data back to the storage location corresponding to the system timing.
  • the alignment and accumulation module 202 is further configured to perform alignment and accumulation anti-collision processing on the user multipath data by means of high-level control scheduling.
  • one user multipath data may be aligned and processed, and multiple user multipath data may be processed in an aligned manner.
  • the pipeline operation is completed, and the alignment may be performed at one time.
  • An ip. First, the user multipath data is aligned to the system timing, and the aligned user multipath data is obtained. Then, the aligned user multipath data is used, and the stored data of the corresponding position of the system timing is read, and the accumulation is performed, and finally the accumulated result is stored. Returns the corresponding position of the system timing.
  • an alignment accumulation process of a user multipath data (fingerO) shown in FIG. 4 is taken as an example:
  • the fingerO includes 8 ip data from ipO to ip7, and the relevant length of each ip can be configured.
  • sipO to sip8 aligned user multipath data, read the stored data of the corresponding location of the system timing, accumulate, and then save back.
  • This embodiment can accumulate a configurable correlation length by one clock alignment, and the alignment accumulation efficiency of the system user multipath data is improved compared with the prior art.
  • the latter user multipath data has started to read the system timing accumulation.
  • RAM at this time, it may happen that the previous user multipath data has not been written back to the accumulated result, and the latter user multipath data has started to read the data of the corresponding position, which is an accumulation conflict.
  • the multi-path data is aligned and accumulated by the high-level control scheduling method, thereby avoiding the alignment accumulation conflict of the multi-path data of the two users before and after. That is, the multi-path data of the two users before and after the multi-path data is arranged by the high-level software to be demodulated for different antennas. If it is the same antenna data, the high-level software configuration shields the path from re-reconstruction, that is, the two paths are not guaranteed. An accumulation conflict will occur.
  • this embodiment requires an additional clock C y C l e to expand the data of 8 ips into 9 ips (before and after insertion 0), which loses the reconstruction accumulation capacity of the system 1/9 (if a multipath If the accumulated length is L ips, the reconstruction accumulation capacity of 1/L is lost).
  • this embodiment proposes a second embodiment.
  • the second embodiment is the same as the first embodiment described above in that the alignment and accumulation processing of the plurality of user multipath data is also performed in a pipeline operation manner, and one ip can be aligned at a time.
  • the difference is that the second implementation method can solve the problem of alignment and accumulation conflict of two user multipath data before and after the high-level control scheduling.
  • the constructing unit 2022 is further configured to configure the system timing storage space into an even ip storage unit and an odd ip storage unit, the even ip storage unit and the odd ip storage unit respectively comprise a plurality of storage locations, each storage location corresponding to a system timing Clock
  • the reading unit 2023 is further configured to separately read the storage data of the storage location corresponding to the even ip storage unit and the odd ip storage unit according to the type of the multipath offset of the user multipath data relative to the system timing;
  • the accumulating unit 2024 is further configured to store the corresponding ip storage unit and the odd ip storage unit The storage data of the storage location is aligned with the user multipath data;
  • the write back unit 2025 is further configured to write the accumulated result of the storage location corresponding to the even ip storage unit or the odd ip storage unit after the accumulation is completed back to the storage location corresponding to the system timing.
  • the alignment accumulating module 202 is further configured to: when the read and write conflicts of the multi-path data of the two users are current, obtain corresponding correspondences from the storage locations corresponding to the even-numbered ip storage units, the odd-numbered ip storage units, the accumulation pipeline stage, or the write-back water phase Accumulate the result, and align the corresponding accumulated result with the current user multipath data.
  • the types of multipath offsets of the user multipath data relative to the system timing include: the multipath offset of the user multipath data relative to the system timing is within [2n, 2n+l) ips, or the user multipath data relative system The timing multipath offset is within [2n+l, 2n+2) ips, where n is an integer.
  • the accumulated RAM aligned to the system timing is divided into an even-numbered i-storage unit ( Even ip RAM) and an odd-numbered ip-storage unit (Odd ip RAM), and the even-numbered ip-storage unit and the odd-numbered ip-storage unit are respectively It includes several storage locations, each of which corresponds to a system-timed clock.
  • the accumulated RAM of the system timing is empty, and the corresponding even ip storage unit and odd ip storage unit are also empty.
  • an Even ip and an Odd ip are read out from the accumulated RAM of the system timing to align an ip of the user timing, and then, according to the multipath offset type of the user multipath data relative to the system timing, Read an Even i or an Odd ip from an even ip storage unit or an odd ip storage unit, and combine the accumulated result of the last odd i storage unit or even i storage unit to align an ip of the user timing, thereby increasing Alignment efficiency.
  • f0 is a shorthand for the user multipath data fingerO, and the multipath offset of f0 relative to the system timing is 0.5 ip.
  • system-timed accumulated RAM is divided into two blocks of Even i and Odd i, and then the following steps are used to perform the alignment accumulation:
  • the storage part of the corresponding system timing Even i and the storage part of Odd i are simultaneously read.
  • the address 0 of the Even ip RAM and the address 0 of the Odd ip RAM are respectively aligned, and the data of the f0 ipO is accumulated, and then The accumulated result of Even ip RAM address 0 is stored back, and the accumulated result of Odd ip RAM address 0 continues to wait for the alignment accumulation of f0 ip 1;
  • fO RE ( n ) is used to denote fO Read Even ip RAM address ( n )
  • fO ACC E ( n ) is the storage portion of the data of the aligned accumulated fO ipO and the corresponding system timing Even ip address (n )
  • the thin line box indicates Wait for the next alignment accumulation after one alignment and accumulation
  • the thick line box indicates the data that is accumulated and completed after one or two alignments
  • fO WE ( n ) indicates that the address of the corresponding system timing Even i is written back ( n ) 0
  • the optimized single-path alignment and accumulation scheme uses 8 cycles to align and accumulate 8 ips of data, without losing the system's reconstruction cancellation capability, and improving the alignment accumulation of multi-path data of system users. effectiveness.
  • multipath offsets of user multipath data relative to system timing there are two types of multipath offsets of user multipath data relative to system timing.
  • One is that the multipath offset of the user multipath data relative to the system timing is within [2n, 2n+l) ips.
  • the other is that the multipath offset of the user multipath data relative to the system timing is within [2n+l, 2n+2) ips, where n is an integer.
  • the four combinations include:
  • the offset relationship between the multipath data of the previous user is first determined, and then the conflict is accumulated according to the conflict situation.
  • the conflict condition is determined, the multipath of the two paths is first determined.
  • the offset belongs to which of the above four types of combinations, and then specifically analyzes which conflict situation.
  • data is taken from different stages of the pipeline for alignment accumulation, for example, from an even ip storage unit, an odd ip storage unit corresponding storage location, an accumulation pipeline stage, or a write reflow phase to obtain a corresponding accumulation result, and
  • the corresponding accumulated result is aligned with the current user multipath data, thereby effectively solving the problem that the two users multi-path data alignment accumulates before and after the read and write accumulate RAM conflicts.
  • the user multi-path data is aligned and accumulated by the user timing and the system timing are aligned with each other, and a system clock can be aligned to accumulate a user length multipath data of a relevant length, and the correlation length is configurable, and finally the user is implemented. Timing alignment to system timing, improved
  • the multipath alignment accumulating efficiency of the WCDMA system solves the problem of multi-path alignment accumulating RAM read and write conflicts before and after, and greatly improves the processing capability of the WCDMA system interference cancellation system.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Electric Clocks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

本发明涉及一种多径对齐累加方法及装置，其方法包括：接收重构后的用户多径数据；通过用户定时与系统定时相互对齐的方式对用户多径数据进行对齐累加处理。本发明通过用户定时与系统定时相互对齐的方式对用户多径数据进行对齐累加处理，一个系统时钟可对齐累加一个相关长度的用户多径数据，且该相关长度可配置，最终实现了将用户定时对齐到系统定时，提高了WCDMA系统的多径对齐累加效率，解决前后多径对齐累加RAM读写冲突的问题，大大提升WCDMA系统干扰抵消系统的处理能力。

Description

多径对齐累加方法及装置 技术领域
本发明涉及通信技术领域， 尤其涉及宽带码分多址 （WCDMA , Wideband Code Division Multiple Access )系统干扰抵消处理过程中一种多径 对齐累加方法及装置。 背景技术
WCDMA是第三代移动通信空中接口标准之一。 WCDM A属于扩频通 信， 其采用双向闭环功控、 发射和接收分集、 RAKE接收抗多径衰落、 卷 积码和 Turbo码信道编解码等技术。
在 WCDMA系统中， 移动通信信道与固定通信信道具有很大的区别， 当 WCDMA基带接收机移动时， 接收机的天线收到的电磁波可由发射机天 线发射后直线到达， 也可以在发射机天线发射后， 经过反射、 衍射等多条 路径延迟传播后到达， 因此， 接收机的接收信号具有很多的多径（finger ) 时延， 这些多径结果互相干扰， 形成无线信道的多径衰落。
在 WCDMA基带接收机端， 利用导频 PN码的相关性， 对接收信号中 可分辨的多径分量分别进行跟踪、 接收， 输出基带信号并进行路径合并， 这种接收信号的方式称为 RAKE相关接收。 RAKE相关接收对各多径分别 进行相关解调， 这些相关解调器也被称为多径接收器（RAKE fingers ), 然 后， 将这些多径接收器的输出进行合并， 送入信道解码器进行后续处理。 RAKE相关接收利用多径分量， 等效的增加了接收到的发射功率， 达到抗 多径衰落的目的。
WCDMA接收系统中， 利用 RAKE接收得到的多径偏移信息和解调解 码正确后的用户符号， 结合信道估计值， 对这些多径数据进行重构， 恢复 出其在无线信道中传播后、 到达接收机端时的幅度和相位信息。 然后将这 些重构后的多径数据对齐到原始天线数据的系统定时进行累加， 最终与原 始天线数据进行相减， 从而抵消掉这些已知的用户多径对未知 （未解调解 码正确） 用户的影响， 增加对剩余的未知用户解调解码正确的和无率。 此即 被称为干扰抵消。
如图 1所示， 图 1为四条用户多径数据相对系统定时之间的偏移 （也 可称为用户定时相对系统定时之间的偏移）示意图， 其中， 将可配置的相 关长度用 ip来表示， 1个 ip等于 32个码片 （ chip )的相关长度 (本文皆以 32chi 为例， 而该相关长度可配置）， ipO到 ip7 ( 8个 ip是 256chip, 本文 皆以 256chip为例表示一条多径累加长度， 该长度也可配置， 各条多径串行 累加）分别表示对应某条多径， 在发射机端发出信号时， 实际相对系统定 时之间的偏移， 即 4条多径的 ipO都是在系统定时 ipO时刻发出的。 将这些 多径对齐到系统定时进行累加， 需要按顺序进行： 首先将对应多径偏移位 置的存储数据读出， 再累加， 最后存回对应多径偏移位置。 这些多径数据 对齐到系统定时进行累加， 需要解决对齐效率及累加沖突的问题。
现有的多径对齐累加方案中， 一个时钟只能对齐累加一个最小单位， 如 lchip或 4chip, 其对齐累加效率低， 且没有涉及流水线设计中， 前后径 对累加随机存储器（ RAM , Random Access Memory )读写沖突的处理方式。 发明内容
本发明的主要目的在于提供一种多径对齐累加方法及装置， 旨在提高 WCDMA系统的多径对齐累加效率， 解决前后径对累加 RAM的读写沖突 问题。
为了达到上述目的， 本发明提出一种多径对齐累加方法， 该方法包括： 接收重构后的用户多径数据；
通过用户定时与系统定时相互对齐的方式对所述用户多径数据进行对 齐累加处理。
优选地， 所述用户多径数据的对齐累加处理过程以流水线操作方式完 成。
优选地， 所述通过用户定时与系统定时相互对齐的方式对所述用户多 径数据进行对齐累加处理的步驟包括：
获取用户多径数据相对系统定时的多径偏移；
在所述用户多径数据的两端， 对应多径偏移小于一个 ip 内填 0, 构造 对齐后的用户多径数据；
根据所述对齐后的用户多径数据， 读出所述系统定时对应的存储位置 的存储数据；
将读出的存储数据与所述对齐后的用户多径数据进行累加；
将累加后的用户多径数据写回至所述系统定时对应的存储位置。
优选地， 该方法还包括：
通过高层控制调度的方式对所述用户多径数据进行对齐累加防沖突处 理。
优选地， 所述通过用户定时与系统定时相互对齐的方式对所述用户多 径数据进行对齐累加处理的步驟包括：
将所述系统定时的存储空间构造为偶数 ip存储单元和奇数 ip存储单 元， 所述偶数 ip存储单元和奇数 ip存储单元分别包括若干存储位置， 每个 存储位置对应一个系统定时的时钟；
根据所述用户多径数据相对所述系统定时的多径偏移的类型， 分别读 出所述偶数 ip存储单元和奇数 ip存储单元对应的存储位置的存储数据； 将读出的存储数据与所述用户多径数据进行对齐累加；
将累加完成后的所述偶数 ip存储单元或奇数 ip存储单元对应的存储位 置的累加结果写回所述系统定时对应的存储位置。 优选地， 所述通过用户定时与系统定时相互对齐的方式对所述用户多 径数据进行对齐累加处理的步驟还包括：
当前后两条用户多径数据发生读写沖突时， 从所述偶数 ip存储单元、 奇数 ip存储单元对应的存储位置、 累加流水线阶段或写回流水阶段获取对 应的累加结果， 并将所述对应的累加结果与当前用户多径数据进行对齐累 加。
优选地， 所述用户多径数据相对所述系统定时的多径偏移的类型包括： 用户多径数据相对系统定时的多径偏移处于 [2n, 2n+l )个 ip之内， 或者用 户多径数据相对系统定时的多径偏移处于 [2η+1 , 2n+2 )个 ip之内， 其中 n 为整数。
本发明还提出一种多径对齐累加装置， 包括： 数据接收模块以及对齐 累加模块， 其中：
数据接收模块， 用于接收重构后的用户多径数据；
对齐累加模块， 用于通过用户定时与系统定时相互对齐的方式对所述 用户多径数据进行对齐累加处理。
优选地， 所述对齐累加模块还用于以流水线操作方式对所述用户多径 数据进行对齐累加处理。
优选地， 所述对齐累加模块包括： 获取单元、 构造单元、 读取单元、 累加单元以及写回单元， 其中：
获取单元， 用于获取用户多径数据相对系统定时的多径偏移； 构造单元， 用于在所述用户多径数据的两端， 对应多径偏移小于一个 相关长度内填 0, 构造对齐后的用户多径数据；
读取单元， 用于根据所述对齐后的用户多径数据， 读出所述系统定时 对应的存储位置的存储数据；
累加单元， 用于将读出的所述系统定时对应的存储位置的存储数据与 所述对齐后的用户多径数据进行累加；
写回单元， 用于将累加后的用户多径数据写回至所述系统定时对应的 存储位置。
优选地， 所述对齐累加模块还用于通过高层控制调度的方式对所述用 户多径数据进行对齐累加防沖突处理。
优选地， 所述构造单元， 还用于将所述系统定时的存储空间构造为偶 数 ip存储单元和奇数 ip存储单元， 所述偶数 ip存储单元和奇数 ip存储单 元分别包括若干存储位置， 每个存储位置对应一个系统定时的时钟；
所述读取单元， 还用于根据所述用户多径数据相对所述系统定时的多 径偏移的类型， 分别读出所述偶数 ip存储单元和奇数 ip存储单元对应的存 储位置的存储数据；
所述累加单元， 还用于将所述偶数 ip存储单元和奇数 ip存储单元对应 的存储位置的存储数据与所述用户多径数据进行对齐累加；
所述写回单元， 还用于将累加完成后的所述偶数 ip存储单元或奇数 ip 存储单元对应的存储位置的累加结果写回所述系统定时对应的存储位置。
优选地， 所述对齐累加模块还用于： 当前后两条用户多径数据发生读 写沖突时， 从所述偶数 ip存储单元、 奇数 ip存储单元对应的存储位置、 累 加流水线阶段或写回流水阶段获取对应的累加结果， 并将该对应的累加结 果与当前用户多径数据进行对齐累加。
本发明提出的一种多径对齐累加方法及装置， 通过用户定时与系统定 时相互对齐的方式对用户多径数据进行对齐累加处理， 一个系统时钟可对 齐累加一个相关长度的用户多径数据， 且该相关长度可配置， 最终实现了 将用户定时对齐到系统定时， 提高了 WCDMA系统的多径对齐累加效率， 解决前后多径对齐累加 RAM读写沖突的问题， 大大提升 WCDMA系统干 扰抵消系统的处理能力。 附图说明
图 1是现有的四条用户多径数据相对系统定时的偏移示意图； 图 2是本发明多径对齐累加方法一实施例的流程示意图；
图 3是本发明多径对齐累加方法一实施例中通过用户定时与系统定时 相互对齐的方式对用户多径数据进行对齐累加处理的第一种实施方式的流 程示意图；
图 4是图 3所示的第一种实施方式中一条用户多径数据对齐累加的时 序示意图；
图 5是本发明多径对齐累加方法一实施例中通过用户定时与系统定时 相互对齐的方式对用户多径数据进行对齐累加处理的第二种实施方式的流 程示意图；
图 6是图 5所示的第一种实施方式中相对系统定时的多径偏移为 0.5个 i 的单条用户多径数据的对齐累加时序示意图；
图 7是图 5所示的第一种实施方式中相对系统定时的多径偏移为 1.5个 i 的单条用户多径数据的对齐累加时序示意图；
图 8是本发明多径对齐累加方法一实施例中单条用户多径数据相对系 统定时的多径偏移处于 [2n, 2n+l )个 ip之内的通用对齐累加时序示意图； 图 9是本发明多径对齐累加方法一实施例中单条用户多径数据相对系 统定时的多径偏移处于 [2η+1 , 2n+2 )个 ip之内的通用对齐累加时序示意图； 图 10是本发明多径对齐累加装置一实施例的结构示意图；
图 11是本发明多径对齐累加装置一实施例中对齐累加模块的结构示意 图。 具体实施方式
本发明实施例解决方案主要是： 通过用户定时与系统定时相互对齐的 方式对用户多径数据进行对齐累加处理， 一个系统时钟可对齐累加一个相 关长度的用户多径数据， 且该相关长度可配置， 最终实现了将用户定时对 齐到系统定时， 以提高 WCDMA系统的多径对齐累加效率， 解决前后多径 对齐累加 RAM读写沖突的问题。
如图 2所示， 本发明一实施例提出一种多径对齐累加方法， 该方法包 括以下几个步驟：
步驟 S101 , 接收重构后的用户多径数据；
本实施例方法运行环境涉及 WCDMA系统的抵消干扰处理中， 重构处 理恢复后的信号的对齐累加处理， 运行本实施例多径对齐累加方法的装置 首先接收重构后的用户多径数据， 多条用户多径数据根据反射、 衍射的路 径延迟不同， 相对系统定时的多径偏移不同。
步驟 S102, 通过用户定时与系统定时相互对齐的方式对用户多径数据 进行对齐累加处理。
在本实施例中， 用户多径数据的对齐累加处理过程均以流水线操作方 式完成， 并且一次可以对齐一个 ip, 即相当于一个时钟周期 （cycle ) 内对 齐一个可配置的相关长度， 其最终目的是实现用户定时与系统定时的对齐， 并提高用户多径数据的对齐累加处理效率， 解决系统对齐累加的沖突问题。 定时相互对齐的方式对用户多径数据进行对齐累加处理的过程。
如图 3所示， 作为本实施例的第一种实施方式， 上述步驟 S102包括： 步驟 S1021 , 获取用户多径数据相对系统定时的多径偏移；
步驟 S1022,在用户多径数据的两端，对应多径偏移小于一个相关长度 内填 0, 构造对齐后的用户多径数据；
步驟 S1023 ,根据对齐后的用户多径数据 ,读出系统定时对应的存储位 置的存储数据；
步驟 S1024,将读出的系统定时对应的存储位置的存储数据与对齐后的 用户多径数据进行累加；
步驟 S1025 , 将累加后的用户多径数据写回至系统定时对应的存储位 置。
本实施方式中， 可以对齐累加处理一条用户多径数据， 也可以对齐累 加处理多条用户多径数据， 对于多条用户多径数据的对齐累加， 均是以流 水线操作方式完成， 并且一次可以对齐一个 ip。 首先将用户多径数据对齐 到系统定时， 得到对齐后的用户多径数据， 然后， 利用对齐后的用户多径 数据， 再读取系统定时对应位置的存储数据， 进行累加， 最后将累加结果 存回系统定时的对应位置。
具体地， 以图 4所示的一条用户多径数据 ( fingerO )的对齐累加处理为 例：
该 fingerO包括 ipO到 ip7共 8个 ip的数据，每个 ip的相关长度可配置。 首先， 将 fingerO对齐到系统定时， 即在 fingerO的两端， 对应偏移小于 一个 ip以内填 0, 得到一个从 sipO到 sip8的对齐的用户多径数据。
再利用 sipO到 sip8对齐的用户多径数据， 读出系统定时对应位置的存 储数据， 进行累加， 然后存回。
该实施方式可以通过一个时钟对齐累加一个可配置的相关长度， 相比 现有技术， 系统用户多径数据的对齐累加效率得到提高。
关于用户多径数据的累加沖突， 即前一条用户多径数据仍在对齐累加 的流水线操作过程中时， 后一条用户多径数据已经开始读取系统定时累加
RAM, 此时， 可能出现前一条用户多径数据仍未写回累加结果， 后一条用 户多径数据已经开始读取相应位置的数据， 此即累加沖突。
在本实施方式中， 通过高层控制调度的方式对用户多径数据进行对齐 累加处理， 避免了前后两条用户多径数据的对齐累加沖突。 即前后两条用 户多径数据由高层软件安排为不同天线解调出来的多径数据， 如果一定是 相同天线数据， 则高层软件配置屏蔽该条径不进行重构， 即保证前后两条 径不会发生累加沖突。
然而， 该方案对于软件操作有约束， 且对于实际少天线场景， 必然会 损失重构抵消性能。
此外，本实施方式需要额外增加一个时钟 CyCle来将 8个 ip的数据扩展 为 9个 ip (前后插 0 ), 损失了系统 1/9的重构累加能力， 如果一条多径的 累加长度为 L个 ip, 则损失 1/L的重构累加能力。
基于上述特点， 本实施例提出第二种实施方式。 该第二种实施方式与 上述第一种实施方式的相同之处在于， 同样是以流水线操作方式完成对多 条用户多径数据的对齐累加处理， 并且一次可以对齐一个 ip。 其不同之处 在于， 该第二种实施方式不需通过高层控制调度即可解决前后两条用户多 径数据的对齐累加沖突问题。
具体地，如图 5所示，作为本实施例的第二种实施方式，上述步驟 S102 包括：
步驟 S1026, 将系统定时的存储空间构造为偶数 ip存储单元和奇数 ip 存储单元， 偶数 ip存储单元和奇数 ip存储单元分别包括多个存储位置， 每 个存储位置对应一个系统定时的时钟；
步驟 S1027,根据用户多径数据相对系统定时的多径偏移的类型，分别 读出偶数 ip存储单元和奇数 ip存储单元对应的存储位置的存储数据；
其中， 用户多径数据相对系统定时的多径偏移的类型包括： 用户多径 数据相对系统定时的多径偏移处于 [2n, 2n+l )个 ip之内， 或者用户多径数 据相对系统定时的多径偏移处于 [2n+l , 2n+2 )个 ip之内， 其中 n为整数。
对于多条用户多径数据， 当前后连续两条用户多径数据串行进行对齐 累加时， 根据前后两条用户多径数据相对系统定时的多径偏移， 存在 4种 组合情况， 都可能会发生读写累加 RAM沖突。 步驟 S1028, 将偶数 ip存储单元和奇数 ip存储单元对应的存储位置的 存储数据与用户多径数据进行对齐累加；
步驟 S1029, 将累加完成后的偶数 ip存储单元或奇数 ip存储单元对应 的存储位置的累加结果写回系统定时对应的存储位置。
在本实施方式中， 将对齐到系统定时的累加 RAM切分为偶数 ip存储 单元（ Even ip RAM )和奇数 ip存储单元（ Odd ip RAM ), 偶数 ip存储单 元和奇数 ip存储单元分别包括若干存储位置， 每个存储位置对应一个系统 定时的时钟。
在初始对齐时， 系统定时的累加 RAM为空， 对应的偶数 ip存储单元 和奇数 ip存储单元也为空。
在对齐累加时，首先，从系统定时的累加 RAM中一次读出一个 Even ip 和一个 Odd ip来对齐用户定时的一个 ip, 之后， 根据用户多径数据相对系 统定时的多径偏移类型，依次从偶数 ip存储单元或奇数 ip存储单元读读出 一个 Even i 或一个 Odd ip, 结合上一次的奇数 i 存储单元或偶数 i 存储 单元的累加结果， 来对齐用户定时的一个 ip, 以此提高多径对齐效率。
下面以具体实例对本实施方式进行详细说明：
如图 6所示， 图 6为相对系统定时的多径偏移为 0.5个 ip的单条用户 多径数据的对齐累加时序示意图。
在图 6中， fO是用户多径数据 fingerO的简写， fO相对系统定时的多径 偏移为 0.5个 ip。
在本实例中， 将系统定时的累加 RAM切分为 Even i 和 Odd i 两块 RAM, 然后按照以下步驟进行对齐累加：
对于 fO的 ipO, 同时读出对应系统定时 Even i 的存储部分和 Odd i 的 存储部分， 图 6中分别为 Even ip RAM的地址 0和 Odd ip RAM的地址 0, 对齐累加 fO ipO的数据， 然后将 Even ip RAM地址 0的累加结果存回， 而 Odd ip RAM地址 0的累加结果继续等待 fO ipl的对齐累加；
对于 fO的 ipl ,读出对应系统定时 Even i 的存储部分，结合 Odd ip RAM 地址 0的累加结果，对应图 6中分别为 Even ip RAM的地址 1和 Odd ip RAM 的地址 0, 对齐累加 fO i l的数据， 然后将 Odd ip RAM地址 0的累加结果 存回， 而 Even ip RAM地址 1的累加结果继续等待 fO ip2的对齐累加； fO的 ip2到 ip6均类似于 ipO和 ipl的对齐累加， 至 ip6对齐累加操作 完毕之后， 0(1(11 1^^1地址3的累加结果继续等待《) 1 7的对齐累加； 对于 fO的 ip7 ,读出对应系统定时 Even i 的存储部分，结合 Odd ip RAM 地址 3的累加结果，对应图 6中分别为 Even ip RAM的地址 4和 Odd ip RAM 的地址 3, 对齐累加 f0 ip7, 然后将 Even ip RAM地址 4和 Odd ip RAM地 址 3的累加结果同时存回。
如果 fO的多径偏移为 1.5个 ip, 与图 6中 fO多径偏移为 0.5个 ip的对 齐累加过程的不同之处在于，首先需要同时读出 Even ip RAM地址 1和 Odd ip RAM地址 0, 最后将 Even ip RAM地址 4和 Odd ip RAM地址 4一起写 回， 如图 7所示， 图 7为相对系统定时的多径偏移为 1.5个 ip的单条用户 多径数据的对齐累加时序示意图。
对应上述图 6所示的对齐累加原理， 可以得到单条用户多径数据相对 系统定时的多径偏移处于 [2n, 2n+l )个 ip之内的通用对齐累加时序， 其中 n为整数， 如图 8所示。
其中， 假设读取系统定时的累加 RAM使能之后 2个时钟 cycle得到
RAM输出数据， 将累加结果寄存需要 lcycle, 最后生成的写 RAM数据和 地址再延迟 lcycle,这些延迟均可变。此外，用 fO R E( n )表示 fO Read Even ip RAM地址（ n ), fO ACC E ( n )表示对齐累加 fO ipO的数据与对应系统定 时 Even ip地址（n ) 的存储部分， 细线框表示一次对齐累加之后等待下一 次的对齐累加， 粗线框表示一次或两次对齐累加完毕、 准备写回的数据， fO W E ( n )表示写回对应系统定时 Even i 的地址（ n )0
具体地， 如图 8所示， fO与系统定时偏移处于 [2n, 2n+l )个 ip之内时 ( n为任意整数）， 对于其 ipO的对齐累加操作描述如下：
第 0个时钟（ clock cycle 0 )需要从 Even ip RAM的地址 n和 Odd ip RAM 地址 n分别读取存储的数据； 第 2个时钟（ clock cycle 2 )得到输出结果分 别记为 E ( n )和 0 ( n ); 在第 3个时钟分别与 fO的 ipO前一部分、 后一部 分对齐累加并寄存得到粗线框的 fO ACC E ( n )和细线框的 fO ACC O ( n ), 其中粗线框的 fO ACC E( n )已经完成了与 fO的对齐累加，而细线框的 fO ACC O ( n )还需要在接下来的第 4个时钟与 fO ipl的前一部分进行对齐累加； 因此， 在第 4个时钟可以将 fO ACC E ( n )写回 Even ip RAM的地址 n, 而 在第 5个时钟再将 fO ACC O ( n ) 写回 Odd ip RAM的地址 n。
对于 fO ipl , 第 1个时钟从 Even ip RAM的地址 n+1读取存储的数据； 第 3个时钟得到 E ( n+1 ), 第 4个时钟细线框 fO ACC O ( n )与 E ( n+1 ) 分别与 fO的 ipl前一部分、 后一部分对齐累加并寄存得到粗线框 fO ACC 0 ( n )和细线框 fO ACC E ( n+1 ), 第 5个时钟将 fO ACC O ( n )写回 Odd ip RAM的地址 n。 而 fO ACC E ( n+1 )将在第 5个时钟与 ip2进行对齐累加， 第 6个时钟写回 Even ip RAM地址 n+1。
对于 f0 ip2~ip7, 与 ipl操作均类似， 唯一不同在于 ip7在第 10个时钟 的对齐累加寄存后直接得到粗线框 fO ACC E ( n+4 )和粗线框 fO ACC O ( n+3 ), 在第 11个时钟将其两者同时分别写回 Even ip RAM地址 n+4和 0(1(11 1八]^地址11+3。
对应上述图 7所示的对齐累加原理， 可以得到单条径多径偏移相对系 统定时处于 [2n+l , 2n+2 )个 ip之内的通用对齐累加时序， 其中 n为任意整 数， 如图 9所示， fO与系统定时偏移处于 [2n+l, 2n+2 )个 ip之内时， 对于 其 ip0~ip7的对齐累加操作与 fO与系统定时偏移处于 [2n, 2n+l )个 ip之内 时类似， 不同之处仅在于： 同一时钟时刻读取 Even ip RAM或 Odd ip RAM 的地址不同，以及完成累加写回 Even ip RAM或 Odd ip RAM的先后顺序不 同。
由上述第二种实施方式可知， 优化后的单径对齐累加方案采用 8 个 cycle来对齐累加 8个 ip的数据， 不会损失系统的重构抵消能力， 提高了系 统用户多径数据的对齐累加效率。
以下详细描述前后两条用户多径数据的对齐累加及沖突解决的时序： 如图 8所示， fO之后的第 8个时钟后一条多径数据 fl的 ipO到达， 需 要读取 Even ip RAM或 Odd ip RAM的某个地址，而此时（ clock cycle 8 ) fO ACC E ( n+2 )、 fO ACC O ( n+2 )、 fO ACC E ( n+3 )、 fO ACC O ( n+3 )、 fO ACC E ( n+4 ) 尚未写回 Even ip RAM或 Odd ip RAM。 如果后一条多径 fl相对 系统定时的偏移与 fO相对系统定时的偏移差别很大， 则一切正常按照图 8 或图 9的规则进行对齐累加的流水操作； 而当后一条多径 fl相对系统定时 的偏移处于一定范围之内时， 则 ipO可能需要去读取这 5个地址的数据（如 fl多径偏移等于 （ 2n+4 )个 ip, 则 ipO在第 8个时钟需要去读取 E ( n+2 ) 和 0 ( n+2 ) )， 此时， 就发生前后两条径对齐累加时对累加 RAM操作沖突 (包括： 同时读写同一地址； 或者前一条径的累加结果尚未写回某地址， 而后一条径已经要读取该地址）。 对于这种沖突情况， 前一条径的累加、 写 回操作仍按照既定的规则进行， 后一条径在累加时则放弃从 Even ip RAM 或 Odd ip RAM读出的数据， 而选择从前一条径的累加、 写回操作流水线不 同阶段上获取相应的数据， 作为真正待累加的结果与 ipO进行对齐累加。
举例说明， 如 fl多径偏移等于 （ 2n+4 )个 ip, 则其 ipO在第 8个时钟 需要去读取 Even ip RAM的地址（ n+2 )和 Odd ip RAM的地址（ n+2 ), 并 预计在第 10个时钟得到 E ( n+2 )和 0 ( n+2 ), 而 fO在第 8个时钟正要写 回 E ( n+2 ), 而 0 ( n+2 )将在第 9个时钟才能写回。 针对该沖突， 可以将 第 8个时钟正要写回的 E ( n+2 ) ( f0 W E ( n+2 ) )延迟 2个时钟， 在第 10 个时钟将其看作是从 Even ip RAM地址（ n+2 )读出的结果； 将第 9个时钟 正要写回的 0 ( n+2 ) ( f0 W 0 ( n+2 ) )延迟 1个时钟， 在第 10个时钟将其 看作是从 Odd ip RAM地址（n+2 )读出结果。 由于 f0的流水线操作仅在第 8-11个时钟（取决于实际流水线级数）有未完成的步驟，因此 fl仅有 ip0~ip3 可能会与之发生读写累加 RAM沖突， 沖突处理均如上所述处理， 即当发生 沖突时， 从前一条径的对齐累加流水线阶段上取相应的数据 （可能需要添 加不同的延迟 ) , 看作从 Even ip RAM或 Odd ip RAM中读出的结果， 来参 与接下来的对齐、 累加、 写回等操作。
图 9中 fl与系统定时的偏移处于一定范围之内时，其 ip0~ip3读取 Even ip RAM或 Odd ip RAM时如果与 fO的流水线操作发生对累加 RAM操作沖 突， 则与上面的描述完全类似地， 从 f0的流水线不同阶段上取相应的数据 (可能需要添加不同的延迟）， 看作从 RAM中读出的结果， 来参与接下来 的对齐、 累加、 写回等操作。
如上所述， 用户多径数据相对系统定时的多径偏移的类型有两种， 一 种是用户多径数据相对系统定时的多径偏移处于 [2n, 2n+l )个 ip之内， 另 一种是用户多径数据相对系统定时的多径偏移处于 [2n+l , 2n+2 )个 ip之内 , 其中 n为任意整数。
当前后连续两条用户多径数据串行进行对齐累加时， 根据前后两条用 户多径数据相对系统定时的多径偏移， 具有 4种组合情况， 都可能会发生 读写累加 RAM沖突。
该 4种组合情况包括：
( 1 ) ( f 0 offset 6 [2n, 2n+l ) ip ) && ( fl offset 6 [2X, 2X+1 ) ip ); ( 2 ) ( f 0 offset [2n, 2n+l ) ip ) && ( fl offset 6 [2X+1 , 2X+2 ) ip ); ( 3 ) ( f 0 offset [2n+l , 2n+2 ) ip ) && ( f 1 offset 6 [2X, 2X+1 ) ip ); ( 4 ) ( f 0 offset [2n+l , 2n+2 ) ip ) && ( fl offset 6 [2X+1 , 2X+2 ) ip )0 其中， n、 X均为整数。
4叚设在后一条径 fl到来的前 a个 cycle, 前一条径 f0由于流水线操作 仍有 b个 ip的累加结果仍未写回 Even ip RAM或 Odd ip RAM。 如果 fO与 fl前后两条径之间的偏移比较大，则 fl不会使用 /读出这些尚未写回的累加 结果， 则 fl如 fO—样， 正常按照如前所述的对齐累加过程进行对齐累加操 作； 如果 fO与 fl前后两条径之间的偏移满足一定的关系， 则 fl会使用 /读 出 fO这些尚未写回的累加结果， 由此发生读写沖突， 此时， 后一条径 fl的 对齐累加操作则需要对这些沖突情况进行检测并分别处理。
当前待累加的用户多径数据输入后， 首先判断与前一条用户多径数据 之间的偏移关系， 再根据沖突情况进行沖突累加解决， 判断沖突情况时， 首先判断前后两条径的多径偏移属于上述 4类组合情况中哪一种， 再具体 分析是哪种沖突情况。
根据不同的沖突情况， 从流水线上的不同阶段取数据进行对齐累加， 比如从偶数 ip存储单元、 奇数 ip存储单元对应的存储位置、 累加流水线阶 段或写回流水阶段获取对应的累加结果， 并将该对应的累加结果与当前用 户多径数据进行对齐累加， 从而有效的解决前后两条用户多径数据对齐累 加发生读写累加 RAM沖突的问题，
此外， 对于更多条用户多径数据的对齐累加， 比如 N条用户多径数据 串行的对齐累加， 在操作每一条径时仅仅涉及： 当前条径与其前一条径、 当前条径与其后一条径之间的相关沖突关系， 并采用上述方案解决沖突累 加问题， 以提高干扰抵消系统的处理能力。
本实施例通过用户定时与系统定时相互对齐的方式对用户多径数据进 行对齐累加处理， 一个系统时钟可对齐累加一个相关长度的用户多径数据， 且该相关长度可配置， 最终实现了将用户定时对齐到系统定时， 提高了 WCDMA系统的多径对齐累加效率， 解决前后多径对齐累加 RAM读写沖 突的问题， 大大提升 WCDMA系统干扰抵消系统的处理能力。
如图 10所示， 本发明一实施例提出一种多径对齐累加装置， 该装置一 般设置在 WCDMA基带接收机端， 包括： 数据接收模块 201以及对齐累加 模块 202, 其中：
数据接收模块 201 , 用于接收重构后的用户多径数据；
对齐累加模块 202,用于通过用户定时与系统定时相互对齐的方式对用 户多径数据进行对齐累加处理。
本实施例多径对齐累加装置首先通过数据接收模块 201接收重构后的 用户多径数据， 多条用户多径数据根据反射、 衍射的路径延迟不同， 相对 系统定时的多径偏移不同， 然后， 由对齐累加模块 202通过用户定时与系 统定时相互对齐的方式对用户多径数据进行对齐累加处理。
在本实施例中， 用户多径数据的对齐累加处理过程均以流水线操作方 式完成， 并且一次可以对齐一个 ip, 即相当于一个时钟 cycle内对齐一个可 配置的相关长度， 其最终目的是将实现用户定时与系统定时的对齐， 并提 高用户多径数据的对齐累加处理效率， 解决系统对齐累加的沖突问题。
下面以两种具体的实施方式详细说明本实施例中对齐累加模块 202通 过用户定时与系统定时相互对齐的方式对用户多径数据进行对齐累加处理 的过程。
如图 11所示，作为本实施例的第一种实施方式，上述对齐累加模块 202 包括： 获取单元 2021、 构造单元 2022、 读取单元 2023、 累加单元 2024以 及写回单元 2025, 其中：
获取单元 2021 , 用于获取用户多径数据相对系统定时的多径偏移； 构造单元 2022, 用于在用户多径数据的两端对应多径偏移小于一个相 关长度内填 0, 构造对齐后的用户多径数据； 读取单元 2023 , 用于根据对齐后的用户多径数据， 读出系统定时对应 的存储位置的存储数据；
累加单元 2024, 用于将读出的系统定时对应的存储位置的存储数据与 对齐后的用户多径数据进行累加；
写回单元 2025 , 用于将累加后的用户多径数据写回至系统定时对应的 存储位置。
对齐累加模块 202还用于通过高层控制调度的方式对用户多径数据进 行对齐累加防沖突处理。
本实施方式中， 可以对齐累加处理一条用户多径数据， 也可以对齐累 加处理多条用户多径数据， 对于多条用户多径数据的对齐累加， 均是以流 水线操作方式完成， 并且一次可以对齐一个 ip。 首先将用户多径数据对齐 到系统定时， 得到对齐后的用户多径数据， 然后， 利用对齐后的用户多径 数据， 再读取系统定时对应位置的存储数据， 进行累加， 最后将累加结果 存回系统定时的对应位置。
具体地， 以图 4所示的一条用户多径数据 ( fingerO )的对齐累加处理为 例：
该 fingerO包括 ipO到 ip7共 8个 ip的数据，每个 ip的相关长度可配置。 首先， 将 fingerO对齐到系统定时， 即在 fingerO的两端， 对应偏移小于 一个 ip以内填 0, 得到一个从 sipO到 sip8的对齐的用户多径数据。
再利用 sipO到 sip8对齐的用户多径数据， 读出系统定时对应位置的存 储数据， 进行累加， 然后存回。
该实施方式可以通过一个时钟对齐累加一个可配置的相关长度， 相比 现有技术， 系统用户多径数据的对齐累加效率得到提高。
关于用户多径数据的累加沖突， 即前一条用户多径数据仍在对齐累加 的流水线操作过程中时， 后一条用户多径数据已经开始读取系统定时累加 RAM, 此时， 可能出现前一条用户多径数据仍未写回累加结果， 后一条用 户多径数据已经开始读取相应位置的数据， 此即累加沖突。
在本实施方式中， 通过高层控制调度的方式对用户多径数据进行对齐 累加处理， 避免了前后两条用户多径数据的对齐累加沖突。 即前后两条用 户多径数据由高层软件安排为不同天线解调出来的多径数据， 如果一定是 相同天线数据， 则高层软件配置屏蔽该条径不进行重构， 即保证前后两条 径不会发生累加沖突。
然而， 该方案对于软件操作有约束， 且对于实际少天线场景， 必然会 损失重构抵消性能。
此外，本实施方式需要额外增加一个时钟 CyCle来将 8个 ip的数据扩展 为 9个 ip (前后插 0 ), 损失了系统 1/9的重构累加能力 （如果一条多径的 累加长度为 L个 ip, 则损失 1/L的重构累加能力）。
基于上述特点， 本实施例提出第二种实施方式。 该第二种实施方式与 上述第一种实施方式的相同之处在于， 同样是以流水线操作方式完成对多 条用户多径数据的对齐累加处理， 并且一次可以对齐一个 ip。 其不同之处 在于， 该第二种实施方式不需通过高层控制调度即可解决前后两条用户多 径数据的对齐累加沖突问题。
具体地， 在第二种实施方式中：
上述构造单元 2022, 还用于将系统定时的存储空间构造为偶数 ip存储 单元和奇数 ip存储单元，偶数 ip存储单元和奇数 ip存储单元分别包括若干 存储位置， 每个存储位置对应一个系统定时的时钟；
读取单元 2023, 还用于根据用户多径数据相对系统定时的多径偏移的 类型， 分别读出偶数 ip存储单元和奇数 ip存储单元对应的存储位置的存储 数据；
累加单元 2024,还用于将偶数 ip存储单元和奇数 ip存储单元对应的存 储位置的存储数据与用户多径数据进行对齐累加；
写回单元 2025,还用于将累加完成后的偶数 ip存储单元或奇数 ip存储 单元对应的存储位置的累加结果写回系统定时对应的存储位置。
同时， 对齐累加模块 202还用于： 当前后两条用户多径数据发生读写 沖突时， 从偶数 ip存储单元、 奇数 ip存储单元对应的存储位置、 累加流水 线阶段或写回流水阶段获取对应的累加结果， 并将该对应的累加结果与当 前用户多径数据进行对齐累加。
其中， 用户多径数据相对系统定时的多径偏移的类型包括： 用户多径 数据相对系统定时的多径偏移处于 [2n, 2n+l )个 ip之内， 或者用户多径数 据相对系统定时的多径偏移处于 [2n+l , 2n+2 )个 ip之内， 其中 n为整数。
对于多条用户多径数据， 当前后连续两条用户多径数据串行进行对齐 累加时， 根据前后两条用户多径数据相对系统定时的多径偏移， 存在 4种 组合情况， 都可能会发生读写累加 RAM沖突。
具体地，在本实施方式中，将对齐到系统定时的累加 RAM切分为偶数 i 存储单元（ Even ip RAM )和奇数 ip存储单元（ Odd ip RAM ), 偶数 ip 存储单元和奇数 ip存储单元分别包括若干存储位置， 每个存储位置对应一 个系统定时的时钟。
在初始对齐时， 系统定时的累加 RAM为空， 对应的偶数 ip存储单元 和奇数 ip存储单元也为空。
在对齐累加时，首先，从系统定时的累加 RAM中一次读出一个 Even ip 和一个 Odd ip来对齐用户定时的一个 ip, 之后， 根据用户多径数据相对系 统定时的多径偏移类型，依次从偶数 ip存储单元或奇数 ip存储单元读读出 一个 Even i 或一个 Odd ip, 结合上一次的奇数 i 存储单元或偶数 i 存储 单元的累加结果， 来对齐用户定时的一个 ip, 以此提高多径对齐效率。
下面以具体实例对本实施方式进行详细说明： 如图 6所示， f0是用户多径数据 fingerO的简写， f0相对系统定时的多 径偏移为 0.5个 ip。
在本实例中， 将系统定时的累加 RAM切分为 Even i 和 Odd i 两块 RAM, 然后按照以下步驟进行对齐累加：
对于 f0的 ipO, 同时读出对应系统定时 Even i 的存储部分和 Odd i 的 存储部分， 图 6中分别为 Even ip RAM的地址 0和 Odd ip RAM的地址 0, 对齐累加 f0 ipO的数据， 然后将 Even ip RAM地址 0的累加结果存回， 而 Odd ip RAM地址 0的累加结果继续等待 f0 ip 1的对齐累加；
对于 f0的 ipl ,读出对应系统定时 Even i 的存储部分，结合 Odd ip RAM 地址 0的累加结果，对应图 6中分别为 Even ip RAM的地址 1和 Odd ip RAM 的地址 0, 对齐累加 f0 i l的数据， 然后将 Odd ip RAM地址 0的累加结果 存回， 而 Even ip RAM地址 1的累加结果继续等待 f0 ip2的对齐累加； f0的 ip2到 ip6均类似于 ipO和 ipl的对齐累加， 至 ip6对齐累加操作 完毕之后， 0(1(11 1^^1地址3的累加结果继续等待《) 1 7的对齐累加； 对于 f0的 ip7 ,读出对应系统定时 Even i 的存储部分，结合 Odd ip RAM 地址 3的累加结果，对应图 6中分别为 Even ip RAM的地址 4和 Odd ip RAM 的地址 3 , 对齐累加 f0 ip7 , 然后将 Even ip RAM地址 4和 Odd ip RAM地 址 3的累加结果同时存回。
如果 f0的多径偏移为 1.5个 ip, 与图 6中 f0多径偏移为 0.5个 ip的对 齐累加过程的不同之处在于，首先需要同时读出 Even ip RAM地址 1和 Odd ip RAM地址 0, 最后将 Even ip RAM地址 4和 Odd ip RAM地址 4一起写 回， 如图 7所示， 图 7为相对系统定时的多径偏移为 1.5个 ip的单条用户 多径数据的对齐累加时序示意图。
对应上述图 6所示的对齐累加原理， 可以得到单条用户多径数据相对 系统定时的多径偏移处于 [2n, 2n+l )个 ip之内的通用对齐累加时序， 其中 n为整数， 如图 8所示。
其中， 假设读取系统定时的累加 RAM使能之后 2个时钟 cycle得到 RAM输出数据， 将累加结果寄存到 lcycle, 最后生成的写 RAM数据和地 址再延迟 lcycle, 这些延迟均可变。 此外， 用 fO R E ( n )表示 fO Read Even ip RAM地址（ n ), fO ACC E ( n )表示对齐累加 fO ipO的数据与对应系统定 时 Even ip地址（n ) 的存储部分， 细线框表示一次对齐累加之后等待下一 次的对齐累加， 粗线框表示一次或两次对齐累加完毕、 准备写回的数据， fO W E ( n )表示写回对应系统定时 Even i 的地址（ n )0
对应上述图 7所示的对齐累加原理， 可以得到单条径多径偏移相对系 统定时处于 [2n+l , 2n+2 )个 ip之内的通用对齐累加时序， 其中 n为整数， 如图 9所示。
由上述第二种实施方式可知， 优化后的单径对齐累加方案采用 8 个 cycle来对齐累加 8个 ip的数据， 不会损失系统的重构抵消能力， 提高了系 统用户多径数据的对齐累加效率。
如上所述， 用户多径数据相对系统定时的多径偏移的类型有两种， 一 种是用户多径数据相对系统定时的多径偏移处于 [2n, 2n+l )个 ip之内， 另 一种是用户多径数据相对系统定时的多径偏移处于 [2n+l , 2n+2 )个 ip之内 , 其中 n为整数。
当前后连续两条用户多径数据串行进行对齐累加时， 根据前后两条用 户多径数据相对系统定时的多径偏移， 具有 4种组合情况， 都可能会发生 读写累加 RAM沖突。
该 4种组合情况包括：
( 1 ) ( f 0 offset 6 [2n, 2n+l ) ip ) && ( fl offset 6 [2X, 2X+1 ) ip ); ( 2 ) ( f 0 offset [2n, 2n+l ) ip ) && ( fl offset 6 [2X+1 , 2X+2 ) ip ); ( 3 ) ( f 0 offset [2n+l , 2n+2 ) ip ) && ( f 1 offset 6 [2X, 2X+1 ) ip ); ( 4 ) ( f 0 offset [2n+l , 2n+2 ) ip ) && ( fl offset 6 [2X+1 , 2X+2 ) ip )0 其中， n、 X均为整数。
4叚设在后一条径 fl到来的前 a个 cycle, 前一条径 f0由于流水线操作 仍有 b个 ip的累加结果仍未写回 Even ip RAM或 Odd ip RAM。 如果 fO与 fl前后两条径之间的偏移比较大，则 fl不会使用 /读出这些尚未写回的累加 结果， 则 fl如 fO—样， 正常按照如前所述的对齐累加过程进行对齐累加操 作； 如果 fO与 fl前后两条径之间的偏移满足一定的关系， 则 fl会使用 /读 出 fO这些尚未写回的累加结果， 由此发生读写沖突， 此时， 后一条径 fl的 对齐累加操作则需要对这些沖突情况进行检测并分别处理。
当前待累加的用户多径数据输入后， 首先判断与前一条用户多径数据 之间的偏移关系， 再根据沖突情况进行沖突累加解决， 判断沖突情况时， 首先判断前后两条径的多径偏移属于上述 4类组合情况中哪一种， 再具体 分析是哪种沖突情况。
根据不同的沖突情况， 从流水线上的不同阶段取数据进行对齐累加， 比如从偶数 ip存储单元、 奇数 ip存储单元对应的存储位置、 累加流水线阶 段或写回流水阶段获取对应的累加结果， 并将该对应的累加结果与当前用 户多径数据进行对齐累加， 从而有效的解决前后两条用户多径数据对齐累 加发生读写累加 RAM沖突的问题，
此外， 对于更多条用户多径数据的对齐累加， 比如 N条用户多径数据 串行的对齐累加， 在操作每一条径时仅仅涉及： 当前条径与其前一条径、 当前条径与其后一条径之间的相关沖突关系， 并采用上述方案解决沖突累 加问题， 以提高干扰抵消系统的处理能力。
本实施例通过用户定时与系统定时相互对齐的方式对用户多径数据进 行对齐累加处理， 一个系统时钟可对齐累加一个相关长度的用户多径数据， 且该相关长度可配置， 最终实现了将用户定时对齐到系统定时， 提高了 WCDMA系统的多径对齐累加效率， 解决前后多径对齐累加 RAM读写沖 突的问题， 大大提升 WCDMA系统干扰抵消系统的处理能力。
以上所述仅为本发明的优选实施例， 并非因此限制本发明的专利范围 , 凡是利用本发明说明书及附图内容所作的等效结构或流程变换， 或直接或 间接运用在其它相关的技术领域， 均同理包括在本发明的专利保护范围内。

Claims

权利要求书
1、 一种多径对齐累加方法， 其特征在于， 该方法包括：
接收重构后的用户多径数据；
通过用户定时与系统定时相互对齐的方式对所述用户多径数据进行对 齐累加处理。
2、 根据权利要求 1所述的方法， 其特征在于， 所述用户多径数据的对 齐累加处理过程以流水线操作方式完成。
3、 根据权利要求 1所述的方法， 其特征在于， 所述通过用户定时与系 统定时相互对齐的方式对所述用户多径数据进行对齐累加处理的步驟包 括：
获取用户多径数据相对系统定时的多径偏移；
在所述用户多径数据的两端， 对应多径偏移小于一个可配置的相关长 度 ip内填 0, 构造对齐后的用户多径数据；
根据所述对齐后的用户多径数据， 读出所述系统定时对应的存储位置 的存储数据；
将读出的存储数据与所述对齐后的用户多径数据进行累加；
将累加后的用户多径数据写回至所述系统定时对应的存储位置。
4、 根据权利要求 3所述的方法， 其特征在于， 该方法还包括： 通过高层控制调度的方式对所述用户多径数据进行对齐累加防沖突处 理。
5、 根据权利要求 1所述的方法， 其特征在于， 所述通过用户定时与系 统定时相互对齐的方式对所述用户多径数据进行对齐累加处理的步驟包 括：
将所述系统定时的存储空间构造为偶数 ip存储单元和奇数 ip存储单 元， 所述偶数 ip存储单元和奇数 ip存储单元分别包括若干存储位置， 每个 存储位置对应一个系统定时的时钟；
根据所述用户多径数据相对所述系统定时的多径偏移的类型， 分别读 出所述偶数 ip存储单元和奇数 ip存储单元对应的存储位置的存储数据； 将读出的存储数据与所述用户多径数据进行对齐累加；
将累加完成后的所述偶数 ip存储单元或奇数 ip存储单元对应的存储位 置的累加结果写回所述系统定时对应的存储位置。
6、 根据权利要求 5所述的方法， 其特征在于， 所述通过用户定时与系 统定时相互对齐的方式对所述用户多径数据进行对齐累加处理的步驟还包 括：
当前后两条用户多径数据发生读写沖突时， 从所述偶数 ip存储单元、 奇数 ip存储单元对应的存储位置、 累加流水线阶段或写回流水阶段获取对 应的累加结果， 并将所述对应的累加结果与当前用户多径数据进行对齐累 加。
7、 根据权利要求 5或 6所述的方法， 其特征在于， 所述用户多径数据 相对所述系统定时的多径偏移的类型包括： 用户多径数据相对系统定时的 多径偏移处于 [2n, 2n+l )个 ip之内， 或者用户多径数据相对系统定时的多 径偏移处于 [2n+l , 2n+2 )个 ip之内， 其中 n为整数。
8、 一种多径对齐累加装置， 其特征在于， 该装置包括： 数据接收模块 以及对齐累加模块， 其中：
数据接收模块， 用于接收重构后的用户多径数据；
对齐累加模块， 用于通过用户定时与系统定时相互对齐的方式对所述 用户多径数据进行对齐累加处理。
9、 根据权利要求 8所述的装置， 其特征在于， 所述对齐累加模块还用 于以流水线操作方式对所述用户多径数据进行对齐累加处理。
10、 根据权利要求 8所述的装置， 其特征在于， 所述对齐累加模块包 括： 获取单元、 构造单元、 读取单元、 累加单元以及写回单元， 其中： 获取单元， 用于获取用户多径数据相对系统定时的多径偏移； 构造单元， 用于在所述用户多径数据的两端， 对应多径偏移小于一个 相关长度内填 0, 构造对齐后的用户多径数据；
读取单元， 用于根据所述对齐后的用户多径数据， 读出所述系统定时 对应的存储位置的存储数据；
累加单元， 用于将读出的所述系统定时对应的存储位置的存储数据与 所述对齐后的用户多径数据进行累加；
写回单元， 用于将累加后的用户多径数据写回至所述系统定时对应的 存储位置。
11、 根据权利要求 10所述的装置， 其特征在于， 所述对齐累加模块还 用于通过高层控制调度的方式对所述用户多径数据进行对齐累加防沖突处 理。
12、 根据权利要求 10所述的装置， 其特征在于，
所述构造单元， 还用于将所述系统定时的存储空间构造为偶数 ip存储 单元和奇数 ip存储单元，所述偶数 ip存储单元和奇数 ip存储单元分别包括 若干存储位置， 每个存储位置对应一个系统定时的时钟；
所述读取单元， 还用于根据所述用户多径数据相对所述系统定时的多 径偏移的类型， 分别读出所述偶数 ip存储单元和奇数 ip存储单元对应的存 储位置的存储数据；
所述累加单元， 还用于将所述偶数 ip存储单元和奇数 ip存储单元对应 的存储位置的存储数据与所述用户多径数据进行对齐累加；
所述写回单元， 还用于将累加完成后的所述偶数 ip存储单元或奇数 ip 存储单元对应的存储位置的累加结果写回所述系统定时对应的存储位置。
13、 根据权利要求 12所述的装置， 其特征在于， 所述对齐累加模块还 用于： 当前后两条用户多径数据发生读写沖突时，从所述偶数 ip存储单元、 奇数 ip存储单元对应的存储位置、 累加流水线阶段或写回流水阶段获取对 应的累加结果， 并将该对应的累加结果与当前用户多径数据进行对齐累加。
PCT/CN2012/076180 2011-10-13 2012-05-28 多径对齐累加方法及装置 WO2013053236A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP12840104.9A EP2768152B1 (en) 2011-10-13 2012-05-28 Finger aligned accumulation method and device
IN3576CHN2014 IN2014CN03576A (zh) 2011-10-13 2012-05-28

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110309616.3 2011-10-13
CN201110309616.3A CN103051357B (zh) 2011-10-13 2011-10-13 多径对齐累加方法及装置

Publications (1)

Publication Number Publication Date
WO2013053236A1 true WO2013053236A1 (zh) 2013-04-18

Family

ID=48063872

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/076180 WO2013053236A1 (zh) 2011-10-13 2012-05-28 多径对齐累加方法及装置

Country Status (4)

Country Link
EP (1) EP2768152B1 (zh)
CN (1) CN103051357B (zh)
IN (1) IN2014CN03576A (zh)
WO (1) WO2013053236A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1347216A (zh) * 2001-10-22 2002-05-01 信息产业部电信传输研究所 可配置w－cdma多径对齐方法及装置
CN1459939A (zh) * 2002-05-20 2003-12-03 上海贝尔有限公司 一种wcdma扩频系统多径对齐的方法和装置
US20110182330A1 (en) * 2001-09-28 2011-07-28 Rambus Inc. Serial cancellation receiver design for a coded signal processing engine

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY120873A (en) * 1994-09-30 2005-12-30 Qualcomm Inc Multipath search processor for a spread spectrum multiple access communication system
US20050013350A1 (en) * 2001-06-06 2005-01-20 Coralli Alessandro Vanelli Method and apparatus for canceling pilot interference in a wireless communication system
US8064494B2 (en) * 2003-05-28 2011-11-22 Qualcomm Incorporated Last finger polling for rake receivers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110182330A1 (en) * 2001-09-28 2011-07-28 Rambus Inc. Serial cancellation receiver design for a coded signal processing engine
CN1347216A (zh) * 2001-10-22 2002-05-01 信息产业部电信传输研究所 可配置w－cdma多径对齐方法及装置
CN1459939A (zh) * 2002-05-20 2003-12-03 上海贝尔有限公司 一种wcdma扩频系统多径对齐的方法和装置

Also Published As

Publication number Publication date
CN103051357B (zh) 2017-03-29
EP2768152B1 (en) 2019-01-02
IN2014CN03576A (zh) 2015-10-09
CN103051357A (zh) 2013-04-17
EP2768152A4 (en) 2015-03-11
EP2768152A1 (en) 2014-08-20

Similar Documents

Publication Publication Date Title
CN101203846B (zh) 具有可编程网络的数字信号处理器
CN106464324B (zh) 大规模mimo架构
US20140013179A1 (en) Transmission delay difference correction method, communication device, and communication system
WO2015089719A1 (zh) 降低互调干扰的方法和设备
KR20150046689A (ko) 신호를 수신하는 방법 및 전자 장치
US8526548B2 (en) Matched filter circuit apparatus in the base band process system of the terminal device and method thereof
WO2005076493A1 (en) Post despreading interpolation in cdma systems
WO2008122152A1 (fr) Procédé et récepteur pour la détection multi-voie dans un système à accès multiple par répartition en code
US20060251155A1 (en) Rake receiver with time-shared fingers
WO2017070849A1 (zh) 一种同频干扰的消除方法及装置
WO2013053236A1 (zh) 多径对齐累加方法及装置
Wu et al. System architecture for 3GPP-LTE modem using a programmable baseband processor
US8027375B2 (en) Shared filter design for pilot symbol averaging in rake fingers in WCDMA systems
JP2001223611A (ja) 受信装置
CN102723977B (zh) 一种基于cpci总线的短波八通道自适应阵列信号处理器
US10887145B2 (en) Data processing device and method
CN101369823A (zh) 耙式接收器、路径搜寻器及结合装置与行动通讯装置
CN102684740B (zh) 高速低复杂度rake接收机及其实现方法
JP4509133B2 (ja) デジタル放送復調装置
WO2011072525A1 (zh) 用于多径搜索的码片相关实现方法和装置
JP4859989B2 (ja) デジタル放送復調装置
US8824271B2 (en) ODFM receiver
CN102752017B (zh) 信号接收方法和装置
Platov et al. System design approach for RSFQ multiuser detector
WO2014015836A1 (zh) 一种基带板间干扰消除的方法和装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12840104

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2012840104

Country of ref document: EP