WO2013045191A1 - Image sensor achieving electron multiplication via vertical gates - Google Patents

Image sensor achieving electron multiplication via vertical gates Download PDF

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Publication number
WO2013045191A1
WO2013045191A1 PCT/EP2012/066705 EP2012066705W WO2013045191A1 WO 2013045191 A1 WO2013045191 A1 WO 2013045191A1 EP 2012066705 W EP2012066705 W EP 2012066705W WO 2013045191 A1 WO2013045191 A1 WO 2013045191A1
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Prior art keywords
photodiode
grids
region
potential
image sensor
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PCT/EP2012/066705
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French (fr)
Inventor
Pierre Fereyre
Frédéric Mayer
Thierry Ligozat
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E2V Semiconductors
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Publication of WO2013045191A1 publication Critical patent/WO2013045191A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14638—Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

Definitions

  • the invention relates to image sensors, and more particularly those that are intended to collect images at low luminance level.
  • the pixels of a matrix image sensor collect few electrons; we have to increase the integration time a lot to obtain an image, but it is to the detriment of the signal-to-noise ratio.
  • CCD Charge-Coupled Devices
  • the invention proposes an image sensor which uses active pixels and which nevertheless allows a multiplication of electrons for the purpose of provide satisfactory images even in the presence of very low light level.
  • an active pixel image sensor comprising, on the surface of a semiconductor active layer, a photodiode region adjacent to a transfer gate itself adjacent to a storage region of charges, the transfer gate allowing, when it receives a transfer pulse, the transfer of charges from the photodiode region to the storage region,
  • this sensor being characterized in that the photodiode region is adjacent to at least two gates electron multiplying unit (GA, GB) extending vertically in depth in the active layer in a plane perpendicular to the surface of the sensor between two adjacent pixels, the multiplication gates being isolated from the photodiode region by a vertical planar layer insulating, and in that the sensor comprises switching means arranged to apply to the two multiplication grids, during a preceding integration phase the transfer pulse, a series of alternations of different potentials said high and low, in phase opposition, inducing opposite electric fields, alternately in one direction and the other, between the gates and the photodiode.
  • G gate electron multiplying unit
  • the multiplication of electrons takes place during the integration of charges; it occurs in the photodiode itself, in the sense that the electrons (photogenerated or already resulting from carrier impacts with the atoms) are accelerated in turn in a direction tending to bring them closer to the multiplication grids and in a sense tending to remove them, and this in phase opposition for the two grids so that the electrons also tend to go from one gate to the other and back in the opposite direction.
  • the impacts with the atoms of the semiconductor layer of the photodiode region cause other electrons of the valence band to pass into the conduction band. They lose energy during these impacts but they are accelerated again by the electric field present.
  • the number of alternations of the potentials applied to the multiplication grids and the value of the potentials used are the factors which determine the overall multiplication coefficient obtained at the end of a duration. integration T, that is to say between two successive transfer pulses of the photodiode to the charge storage region.
  • the two grids may be aligned along the same edge of the photodiode or may be placed on different edges, including opposite edges of the photodiode.
  • Each grid is preferably adjacent to the two photodiodes of two adjacent pixels, that is to say that the same grids perform a multiplication of electrons simultaneously in the two adjacent pixels.
  • the photodiode is a "pinned" type photodiode, that is to say having a doped surface region maintained at a zero reference potential; this region induces in the photodiode region a fixed base potential or internal potential in the absence of photogenerated charges, which depends on the doping of the photodiode; the alternation of potentials applied to the acceleration gates comprises a high potential greater than the reference potential, which induces in the photodiode close to the gate a higher potential than the base potential of the photodiode, and a low potential lower than the reference potential, which induces below the gate a surface potential lower than the base potential of the photodiode.
  • a third gate is interposed between the first two gates and is maintained at a fixed potential intermediate between the high potential and the low potential.
  • the three grids can be for example aligned along the same edge of the photodiode or be distributed over several edges, for example placed on three consecutive edges.
  • the first grid can be subdivided into several first grids separated from each other and receiving the same alternation of potentials; and the same with respect to the second grid and the third grid.
  • a set of three grids may be provided along a first edge, a second set of three grids along a second edge, and a third set of three grids along a third edge.
  • FIG. 1 shows in vertical section the general structure of an active pixel image sensor
  • FIG. 2 represents in vertical section the structure of a modified pixel according to the invention
  • FIG. 3 represents a horizontal view of the pixel, showing three vertical grids separating two adjacent pixels
  • FIG. 1 shows the main elements of an active pixel of conventional CMOS technology.
  • the pixel is formed in a substrate 10 which preferably comprises a P-doped semiconductor active layer 12 (the P-symbol is used to designate this weak doping) formed on the surface of a more doped layer (P +).
  • the pixel is isolated from neighboring pixels by an insulating barrier 13 which completely surrounds it. This barrier may be a superficial insulating trench over a more doped P-type well than the active layer.
  • the pixel comprises a photodiode region PHD which is delimited by the contours of an N-type semiconductor region 14 implanted in a part of the depth of the active layer 12.
  • This implanted region is surmounted by a more doped surface region 16 of type P +, which is maintained at a zero reference potential.
  • the zero reference potential is that which is applied to the active layer P-. In the simplest case, it is the potential of the P + type substrate situated under the active layer and applying its own potential to the active layer; the maintenance of the surface region 16 at this zero potential is achieved for example by the fact that the region 16 touches in some places (not visible in the figure) a deep diffusion of P + type which joins the substrate 10. An electrical contact can also be expected on this deep diffusion to apply by this contact a zero potential to the region 16.
  • a charge storage region 18 is provided outside the PHD photodiode region; it is separated by an insulated gate TR which allows to allow or prohibit a transfer of charges stored in the photodiode to the storage region.
  • the storage area of loads 18 is a N-type diffusion in the active layer 12.
  • a contact is formed on the storage region, to enable the potential of this region to be applied to the gate of a not shown follower transistor, in order to transform into a voltage level. the amount of charge contained in the storage region.
  • Another gate RS allows to empty the charges of the storage region to a drain drain 20 which is an N + type region connected to a positive reset potential Vref.
  • the transfer or reset grids, and more generally the transistor gates of the pixels and the control circuits of the pixel matrix are generally polycrystalline silicon. They are isolated from the active layer 12 by a very thin insulating layer, preferably of silicon oxide.
  • the electrons (with the conductivity types and potentials considered here, but these could be the holes if all the conductivity types were reversed and the signs of the potential differences applied) are stored in the N-region 14 of the photodiode.
  • the potential of the storage region is reset to Vref by the reset gate RS.
  • a transfer pulse is applied to the gate TR and the charges stored in the photodiode are poured into the storage region. They are then read by the not shown follower transistor, while a new integration time begins.
  • means are provided for imparting, during the integration phase itself, a strong and alternating acceleration to the electrons which accumulate in the photodiode during this phase.
  • These means comprise vertical buried multiplication grids which are electrodes extending in the depth of the active layer, preferably in all the depth of the N regions and even in the entire depth of the active layer, and means for switching the potential of these grids so as to create an alternation of electric fields in the region where the electrons accumulate.
  • the multiplication grids are arranged between the photodiodes of two adjacent pixels and act on the electrons of the photodiodes of these two pixels.
  • FIG. 2 represents the corresponding modification of the pixel of FIG. 1.
  • one or more buried grids have been placed (only one is visible and designated by GC in FIG. 2).
  • the grids are fully insulated from the active layer by an insulating layer 22 which surrounds each grid also covering the lower part thereof to ensure complete isolation. This layer also isolates the grids from each other to allow them to apply different potentials.
  • This insulating layer 22 is preferably made of silicon oxide.
  • the grids are preferably polycrystalline silicon (but they could be metal); they are flush with the surface of the active layer or near this surface and electrical contacts (not shown) are provided on the surface to apply the desired potentials.
  • the grids are as narrow as the manufacturing technology allows.
  • the insulating layer 22 may be formed by oxidation of the silicon substrate in an open trench in the active layer, which is then trenched and filled with polycrystalline silicon.
  • the thickness of the insulating layer 22 may be chosen independently of the insulation thickness of the horizontal grids TR and RS of the pixel because it is not formed by the same oxidation step.
  • the thickness of the layer 22 is preferably much greater than the thickness of the insulation of the transfer gate or the reset gate. This greater thickness makes it possible to apply to the multiplier gates voltages much higher than those which can be applied without degradation to the transfer and reset gates. These higher voltages promote the desired electron multiplication. It should be noted that it would be impossible to apply to the multiplier gates voltages greater than the acceptable voltages for the transfer gates if the multiplication gates were formed by the same technical and in the same step as the transfer and reset grids.
  • FIG. 3 shows a top view of a possible arrangement of the different elements of the pixel; to simplify, we have not represented elements that can be conventionally present in the pixel and in particular a follower transistor for copying the potential of the storage region 18, and a line selection transistor, in the case of a matrix of several lines of pixels, to allow the connection of the source of the follower transistor to a column conductor of the matrix. These elements are in any case located outside the isolation region 13 which surrounds the photodiode.
  • Two main multiplication gates GA, GB are shown and an intermediate (optional) gate GC is placed between the two gates.
  • the section of Figure 2 is taken along the line AA of Figure 3 and passes through the GC grid which, if present, is constituted in the same manner and at the same time as the other two.
  • the set of grids separates the photodiodes from the adjacent pixels. If the grids did not completely occupy the boundary between the two photodiodes, this boundary would be completed by a conventional insulating structure such as 13.
  • the grids are aligned in the same general vertical plane as shown in FIG.
  • Potential switching means are provided for directly applying to the main multiplication gates GA and GB a series of alternations with a high potential and a low potential, in phase opposition for the two gates, and one level. able to cause a multiplication of electrons. These switching means are not shown because they are not located in the pixel. If the sensor comprises a matrix of pixels, these switching means are common to the entire matrix and the multiplication gates GA and GB of all the pixels can be connected together to these switching means, by conductive lines in punctual contact with each other. the upper part of the grids. Alternatively, the multiplication grids of the same pixel line can be controlled independently of those of the other grids.
  • the series of alternations is applied during all or part of the integration time T which separates two successive transfers of charges (by the gate transfer circuit TR) between the photodiode region PHD and the storage region 18.
  • the photodiode is a "pinned" type photodiode, that is to say having a doped surface region maintained at a zero reference potential; this region induces in the photodiode region a fixed base potential (in the absence of accumulated charges) which depends on the doping of the photodiode; the alternation of potentials applied to the multiplication gates comprises a high potential which induces in the photodiode close to the gate a higher potential than the base potential of the photodiode and a low potential which induces a greater surface potential under the gate; lower than the basic potential of the photodiode.
  • a third gate GC When a third gate GC is present, it is preferably brought to an intermediate potential between the high potential and the low potential.
  • the GA and GB multiplication grids (as well as GC) occupy a minimum surface which hinders very little the production of electrons by the light.
  • the electrons are attracted with an electric field all the stronger as the potentials are stronger towards the grid with the highest potential; in the next phase of the alternation they are attracted to the other grid.
  • the speed they acquire creates the impacts that cause the progressive multiplication of electrons.
  • the electrons do not pass from one photodiode to the adjacent photodiode because of the depth of the gate which extends below the depth of the N regions of the photodiode and which preferably extends through the entire depth of the photodiode. the active layer P.
  • all the multiplication grids are represented on one side of the photodiode, more precisely a side that separates two adjacent pixels from the same line.
  • the grids could be on one side that separates two adjacent pixels from the same column, or spread over two or more sides of the pixel.
  • a group of two or three grids GA, GB, GC would be placed on one side and another group of two or three grids on an opposite side.
  • both multiplication grids are on two opposite edges of the photodiode, the third gate being on a third edge joining the two opposite edges.
  • the operating chronogram of this pixel is conventional, except that it adds an alternation of potentials on the GA and GB multiplication gates during all or part of the charge integration time in the photodiode.
  • the timing diagram of an integration period starts with a reset pulse of the potential of the photodiode at a reference level; the end of this pulse defines the beginning of the integration of charges in the photodiode under the effect of the light illuminating the pixel.
  • the end of the integration period is defined by the end of a transfer pulse applied to the transfer electrode TR of all the pixels of the matrix; the charges of the photodiode are transferred to the storage node 18 of each pixel.
  • the potential of the storage node 18 resulting from this charge transfer is then read line by line: for a given line it is carried over to a column conductor and collected by a sampler at the bottom of the column. After each read of a line, the potential of the storage node is reset to a reference value by the application of a reset pulse on the RS gate; the reset potential is collected by the bottom-of-column sampler and a differential measurement is made between the read potential and the reset potential. Then this double reading is repeated for the next line, and so on.
  • the chronogram could also be a chronogram in so-called rolling shutter mode in which the integration durations of the different lines are identical but not simultaneous, with the failure to create the image dragging but with the benefit of reducing the reset noise.
  • the transfer of charges by the transfer electrode TR is then done line by line and it is possible to reset the storage node and read the reset potential just before the transfer of charges in the storage node and the reading of the potential. resulting.
  • the grids are as narrow as possible so as not to reduce the area occupied by the photodiode in the pixel. It suffices that they comprise at their upper part an area wide enough to place an electrical contact, to bring the alternative potential necessary for their operation.
  • the depth of the buried vertical grids GA, GB, GC may be about 1.5 to 2 microns, their width 0.3 microns, their length 1.5 to 3 microns, for pixels about 25 square micrometers.
  • They are polycrystalline silicon and the insulating layer separating them from the active layer can have a thickness of 10 to 50 nanometers. This thickness is chosen to withstand voltages of 7 to 8 volts or more between the active layer and the grids. This thickness is greater than the thickness of insulating layer between the transfer gate TR and the active layer, the latter thickness to be minimized (of the order of 5 to 10 nanometers for example) to ensure good charge transfer.
  • the manufacture of the buried grids is preferably done using, in particular, the following steps:
  • the grids are made of doped polycrystalline silicon. They could however also be metal.
  • an alternation of potentials is triggered only in case of very low illumination. For example, depending on the level of illumination detected, one triggers or does not trigger the series of alternations of potentials. If it is not triggered, the acceleration grids are left at a low level. And if it is triggered, we can predict that the number of alternations is variable depending on the level of illumination detected.
  • the invention can be used with an image sensor illuminated by the front face, or with a thin-film silicon image sensor illuminated by the rear face.

Abstract

The invention relates to image sensors, and more particularly to sensors that are intended to detect images at low light levels. An active-pixel image sensor is provided, each pixel comprising, on the surface of an active semiconductor layer (12), a photodiode region (PHD) adjacent to a transfer gate (TR) itself adjacent to a charge storage region (18), the transfer gate permitting, when it receives a transfer pulse, the transfer of charge from the photodiode region to the storage region. The photodiode is adjacent to two multiplication gates (GA, GB) that extend vertically depthwise in the active layer between two adjacent pixels. The multiplication gates are isolated from the photodiode by a planar vertical insulating layer (22). They receive, during an integration phase preceding the transfer pulse, a series of high and low potential alternations in phase opposition, inducing opposed electric fields alternately, in one direction and then the other, between the gates and the photodiode.

Description

CAPTEUR D'IMAGE A MULTIPLICATION D'ELECTRONS  ELECTRON MULTIPLICATION IMAGE SENSOR
PAR GRILLES VERTICALES  BY VERTICAL GRIDS
L'invention concerne les capteurs d'image, et plus particulièrement ceux qui sont destinés à recueillir des images à bas niveau de luminance. The invention relates to image sensors, and more particularly those that are intended to collect images at low luminance level.
Lorsque le niveau de lumière est faible, les pixels d'un capteur d'image matriciel recueillent peu d'électrons ; on est obligé d'augmenter beaucoup la durée d'intégration pour obtenir une image, mais c'est au détriment du rapport signal sur bruit.  When the light level is low, the pixels of a matrix image sensor collect few electrons; we have to increase the integration time a lot to obtain an image, but it is to the detriment of the signal-to-noise ratio.
En technologie CCD (Charge-Coupled Devices) on a déjà proposé d'incorporer au capteur des systèmes de multiplication d'électrons qui créent des électrons supplémentaires à partir des électrons générés naturellement par la lumière. Le signal électrique qui est recueilli ensuite est donc multiplié par un coefficient. Le bruit augmente aussi mais dans un rapport plus faible que le signal.  In Charge-Coupled Devices (CCD) technology, it has already been proposed to incorporate electron multiplication systems into the sensor that create additional electrons from the electrons naturally generated by the light. The electrical signal which is then collected is multiplied by a coefficient. The noise also increases but in a lower ratio than the signal.
Ces principes de multiplication d'électrons en technologie CCD consistent à augmenter les différences de potentiel présentes entre les grilles de transfert de charges, ce qui accélère les électrons en cours de transfert ; l'énergie qui leur est conférée est suffisante pour que les impacts avec les atomes du matériau semiconducteur fassent passer des électrons de ces atomes de la bande de valence à la bande de conduction. Ces électrons arrachés aux atomes sont eux-mêmes accélérés et peuvent donner lieu à d'autres impacts. Il en résulte un phénomène de multiplication d'électrons.  These principles of electron multiplication in CCD technology consist in increasing the potential differences present between the charge transfer gates, which accelerates the electrons being transferred; the energy conferred on them is sufficient for the impacts with the atoms of the semiconductor material to pass electrons from these atoms of the valence band to the conduction band. These electrons torn from the atoms are themselves accelerated and can give rise to other impacts. This results in a phenomenon of multiplication of electrons.
Dans les capteurs CCD on peut le faire car les électrons sont transférés de grille en grille et c'est l'augmentation de la tension sur certaines grilles qui permet d'accélérer fortement les électrons pour provoquer cette multiplication.  In CCD sensors this can be done because the electrons are transferred from grid to grid and it is the increase of the voltage on some gates which allows to accelerate strongly the electrons to cause this multiplication.
Mais dans les capteurs à pixels actifs, comprenant au sein de chaque pixel un circuit (quelques transistors) de conversion charge-tension, ce n'est pas possible car les paquets d'électrons sont convertis en tension immédiatement après chaque période d'intégration. Ils ne sont pas transférés de grille en grille.  But in active pixel sensors, comprising within each pixel a circuit (some transistors) charge-voltage conversion, this is not possible because the electron packets are converted into voltage immediately after each integration period. They are not transferred from grid to grid.
L'invention propose un capteur d'image qui utilise des pixels actifs et qui permet quand même une multiplication d'électrons dans le but de fournir des images satisfaisantes même en présence de très bas niveau de lumière. The invention proposes an image sensor which uses active pixels and which nevertheless allows a multiplication of electrons for the purpose of provide satisfactory images even in the presence of very low light level.
Selon l'invention, on propose un capteur d'image à pixels actifs, chaque pixel comprenant, à la surface d'une couche active semiconductrice, une région de photodiode adjacente à une grille de transfert elle-même adjacente à une région de stockage de charges, la grille de transfert autorisant, lorsqu'elle reçoit une impulsion de transfert, le transfert de charges de la région de photodiode vers la région de stockage, ce capteur étant caractérisé en ce que la région de photodiode est adjacente à au moins deux grilles de multiplication d'électrons (GA, GB) s'étendant verticalement en profondeur dans la couche active dans un plan perpendiculaire à la surface du capteur entre deux pixels adjacents, les grilles de multiplication étant isolées de la région de photodiode par une couche plane verticale isolante, et en ce que le capteur comprend des moyens de commutation agencés pour appliquer aux deux grilles de multiplication, pendant une phase d'intégration précédant l'impulsion de transfert, une série d'alternances de potentiels différents dits haut et bas, en opposition de phase, induisant des champs électriques opposés, alternativement dans un sens et dans l'autre, entre les grilles et la photodiode.  According to the invention, an active pixel image sensor is provided, each pixel comprising, on the surface of a semiconductor active layer, a photodiode region adjacent to a transfer gate itself adjacent to a storage region of charges, the transfer gate allowing, when it receives a transfer pulse, the transfer of charges from the photodiode region to the storage region, this sensor being characterized in that the photodiode region is adjacent to at least two gates electron multiplying unit (GA, GB) extending vertically in depth in the active layer in a plane perpendicular to the surface of the sensor between two adjacent pixels, the multiplication gates being isolated from the photodiode region by a vertical planar layer insulating, and in that the sensor comprises switching means arranged to apply to the two multiplication grids, during a preceding integration phase the transfer pulse, a series of alternations of different potentials said high and low, in phase opposition, inducing opposite electric fields, alternately in one direction and the other, between the gates and the photodiode.
La multiplication d'électrons a lieu pendant l'intégration de charges ; elle se produit dans la photodiode elle-même, en ce sens que les électrons (photogénérés ou résultant déjà d'impacts de porteurs avec les atomes) sont accélérés tour à tour dans un sens tendant à les rapprocher des grilles de multiplication et dans un sens tendant à les éloigner, et ceci en opposition de phase pour les deux grilles de sorte que les électrons tendent aussi à aller d'une grille vers l'autre et à revenir en sens inverse. Au cours de ces multiples trajets, les impacts avec les atomes de la couche semiconductrice de la région de photodiode font passer d'autres électrons de la bande de valence dans la bande de conduction. Ils perdent de l'énergie lors de ces impacts mais ils sont à nouveau accélérés par le champ électrique présent.  The multiplication of electrons takes place during the integration of charges; it occurs in the photodiode itself, in the sense that the electrons (photogenerated or already resulting from carrier impacts with the atoms) are accelerated in turn in a direction tending to bring them closer to the multiplication grids and in a sense tending to remove them, and this in phase opposition for the two grids so that the electrons also tend to go from one gate to the other and back in the opposite direction. During these multiple paths, the impacts with the atoms of the semiconductor layer of the photodiode region cause other electrons of the valence band to pass into the conduction band. They lose energy during these impacts but they are accelerated again by the electric field present.
Le nombre d'alternances des potentiels appliqués aux grilles de multiplication et la valeur des potentiels utilisés sont les facteurs qui déterminent le coefficient de multiplication global obtenu à la fin d'une durée d'intégration T, c'est-à-dire entre deux impulsions de transfert successives de la photodiode vers la région de stockage de charges. The number of alternations of the potentials applied to the multiplication grids and the value of the potentials used are the factors which determine the overall multiplication coefficient obtained at the end of a duration. integration T, that is to say between two successive transfer pulses of the photodiode to the charge storage region.
Les deux grilles peuvent être alignées le long d'un même bord de la photodiode ou être placées sur des bords différents, y compris des bords opposés de la photodiode. Chaque grille est de préférence adjacente aux deux photodiodes de deux pixels adjacents, c'est-à-dire que les mêmes grilles réalisent une multiplication d'électrons simultanément dans les deux pixels adjacents.  The two grids may be aligned along the same edge of the photodiode or may be placed on different edges, including opposite edges of the photodiode. Each grid is preferably adjacent to the two photodiodes of two adjacent pixels, that is to say that the same grids perform a multiplication of electrons simultaneously in the two adjacent pixels.
La photodiode est une photodiode de type "pinned", c'est-à-dire dotée d'une région superficielle dopée maintenue à un potentiel de référence zéro ; cette région induit dans la région de photodiode un potentiel de base fixe ou potentiel interne en l'absence de charges photogénérées, qui dépend des dopages de la photodiode ; l'alternance de potentiels appliqués aux grilles d'accélération comprend un potentiel haut supérieur au potentiel de référence, qui induit dans la photodiode à proximité de la grille un potentiel plus élevé que le potentiel de base de la photodiode, et un potentiel bas inférieur au potentiel de référence, qui induit sous la grille un potentiel de surface plus bas que le potentiel de base de la photodiode.  The photodiode is a "pinned" type photodiode, that is to say having a doped surface region maintained at a zero reference potential; this region induces in the photodiode region a fixed base potential or internal potential in the absence of photogenerated charges, which depends on the doping of the photodiode; the alternation of potentials applied to the acceleration gates comprises a high potential greater than the reference potential, which induces in the photodiode close to the gate a higher potential than the base potential of the photodiode, and a low potential lower than the reference potential, which induces below the gate a surface potential lower than the base potential of the photodiode.
De préférence une troisième grille est interposée entre les deux premières grilles et est maintenue à un potentiel fixe intermédiaire entre le potentiel haut et le potentiel bas. Dans ce cas, les trois grilles peuvent être par exemple alignées le long d'un même bord de la photodiode ou être réparties sur plusieurs bords, par exemple placées sur trois bords consécutifs.  Preferably a third gate is interposed between the first two gates and is maintained at a fixed potential intermediate between the high potential and the low potential. In this case, the three grids can be for example aligned along the same edge of the photodiode or be distributed over several edges, for example placed on three consecutive edges.
Plus généralement, la première grille peut être subdivisée en plusieurs premières grilles séparées les unes des autres et recevant la même alternance de potentiels ; et de même en ce qui concerne la deuxième grille et la troisième grille. Par exemple, un ensemble de trois grilles (deux grilles recevant des potentiels opposés et une troisième placée entre elles et recevant un potentiel fixe intermédiaire) peut être prévu le long d'un premier bord, un deuxième ensemble de trois grilles le long d'un deuxième bord, et un troisième ensemble de trois grilles le long d'un troisième bord. D'autres caractéristiques et avantages de l'invention apparaîtront à la lecture de la description détaillée qui suit et qui est faite en référence aux dessins annexés dans lesquels : More generally, the first grid can be subdivided into several first grids separated from each other and receiving the same alternation of potentials; and the same with respect to the second grid and the third grid. For example, a set of three grids (two grids receiving opposite potentials and a third grids placed between them and receiving an intermediate fixed potential) may be provided along a first edge, a second set of three grids along a second edge, and a third set of three grids along a third edge. Other features and advantages of the invention will appear on reading the detailed description which follows and which is given with reference to the appended drawings in which:
- la figure 1 représente en coupe verticale la structure générale d'un capteur d'image à pixels actifs ;  - Figure 1 shows in vertical section the general structure of an active pixel image sensor;
- la figure 2 représente en coupe verticale la structure d'un pixel modifié selon l'invention ;  FIG. 2 represents in vertical section the structure of a modified pixel according to the invention;
- la figure 3 représente une vue horizontale du pixel, montrant trois grilles verticales séparant deux pixels adjacents ;  FIG. 3 represents a horizontal view of the pixel, showing three vertical grids separating two adjacent pixels;
Sur la figure 1 on a représenté les éléments principaux d'un pixel actif de technologie CMOS classique. Le pixel est formé dans un substrat 10 qui comprend de préférence une couche active semiconductrice 12 de type P peu dopée (le symbole P- est utilisé pour désigner ce faible dopage) formée à la surface d'une couche plus dopée (P+). Le pixel est isolé des pixels voisins par une barrière isolante 13 qui l'entoure complètement. Cette barrière peut être une tranchée isolante superficielle au-dessus d'un caisson de type P plus dopé que la couche active. FIG. 1 shows the main elements of an active pixel of conventional CMOS technology. The pixel is formed in a substrate 10 which preferably comprises a P-doped semiconductor active layer 12 (the P-symbol is used to designate this weak doping) formed on the surface of a more doped layer (P +). The pixel is isolated from neighboring pixels by an insulating barrier 13 which completely surrounds it. This barrier may be a superficial insulating trench over a more doped P-type well than the active layer.
Le pixel comprend une région de photodiode PHD qui est délimitée par les contours d'une région semiconductrice 14 de type N implantée dans une partie de la profondeur de la couche active 12. Cette région implantée est surmontée par une région superficielle 16 plus dopée de type P+, qui est maintenue à un potentiel de référence zéro. Le potentiel de référence zéro est celui qui est appliqué à la couche active P-. Dans le cas le plus simple, c'est le potentiel du substrat de type P+ situé sous la couche active et appliquant son propre potentiel à la couche active ; le maintien de la région superficielle 16 à ce potentiel zéro est réalisé par exemple par le fait que la région 16 touche à certains endroits (non visibles sur la figure) une diffusion profonde de type P+ qui rejoint le substrat 10. Un contact électrique peut aussi être prévu sur cette diffusion profonde pour appliquer par ce contact un potentiel zéro à la région 16.  The pixel comprises a photodiode region PHD which is delimited by the contours of an N-type semiconductor region 14 implanted in a part of the depth of the active layer 12. This implanted region is surmounted by a more doped surface region 16 of type P +, which is maintained at a zero reference potential. The zero reference potential is that which is applied to the active layer P-. In the simplest case, it is the potential of the P + type substrate situated under the active layer and applying its own potential to the active layer; the maintenance of the surface region 16 at this zero potential is achieved for example by the fact that the region 16 touches in some places (not visible in the figure) a deep diffusion of P + type which joins the substrate 10. An electrical contact can also be expected on this deep diffusion to apply by this contact a zero potential to the region 16.
Une région de stockage de charges 18 est prévue en dehors de la région de photodiode PHD ; elle en est séparée par une grille isolée TR qui permet d'autoriser ou d'interdire un transfert des charges stockées dans la photodiode vers la région de stockage. La région de stockage de charges 18 est une diffusion de type N dans la couche active 12. Un contact est formé sur la région de stockage, pour permettre d'appliquer le potentiel de cette région sur la grille d'un transistor suiveur non représenté, afin de transformer en niveau de tension électrique la quantité de charges contenue dans la région de stockage. A charge storage region 18 is provided outside the PHD photodiode region; it is separated by an insulated gate TR which allows to allow or prohibit a transfer of charges stored in the photodiode to the storage region. The storage area of loads 18 is a N-type diffusion in the active layer 12. A contact is formed on the storage region, to enable the potential of this region to be applied to the gate of a not shown follower transistor, in order to transform into a voltage level. the amount of charge contained in the storage region.
Une autre grille RS, appelée grille de réinitialisation, permet de vider les charges de la région de stockage vers un drain d'évacuation 20 qui est une région de type N+ reliée à un potentiel de réinitialisation positif Vref.  Another gate RS, called reset gate, allows to empty the charges of the storage region to a drain drain 20 which is an N + type region connected to a positive reset potential Vref.
Les grilles de transfert ou de réinitialisation, et plus généralement les grilles de transistors des pixels et des circuits de commande de la matrice de pixels sont en général en silicium polycristallin. Elles sont isolées de la couche active 12 par une couche isolante très fine, de préférence en oxyde de silicium.  The transfer or reset grids, and more generally the transistor gates of the pixels and the control circuits of the pixel matrix are generally polycrystalline silicon. They are isolated from the active layer 12 by a very thin insulating layer, preferably of silicon oxide.
Dans la configuration représentée, on a supposé que deux pixels adjacents étaient placés dos-à-dos, orientés en sens inverse l'un de l'autre, et c'est pourquoi on voit sur la figure 1 deux photodiodes PHD, appartenant à deux pixels différents adjacents, qui sont séparées seulement par une barrière isolante 13.  In the configuration shown, it was assumed that two adjacent pixels were placed back-to-back, oriented in opposite directions from each other, and this is why we see in Figure 1 two PHD photodiodes belonging to two adjacent different pixels, which are separated only by an insulating barrier 13.
Le pixel fonctionne en général de la manière suivante : l'éclairement de la région de photodiode PHD pendant une durée d'intégration T génère des paires électrons-trous. Les électrons (avec les types de conductivité et potentiels considérés ici, mais ce pourraient être les trous si on inversait tous les types de conductivité et les signes des différences de potentiel appliquées) sont stockées dans la région N 14 de la photodiode. Avant la fin de la durée T, le potentiel de la région de stockage est réinitialisé à Vref par la grille de réinitialisation RS. A la fin de la durée T, une impulsion de transfert est appliquée à la grille TR et les charges stockées dans la photodiode viennent se déverser dans la région de stockage. Elles sont ensuite lues par le transistor suiveur non représenté, pendant qu'une nouvelle durée d'intégration commence.  The pixel functions in general as follows: the illumination of the photodiode region PHD during an integration period T generates electron-hole pairs. The electrons (with the conductivity types and potentials considered here, but these could be the holes if all the conductivity types were reversed and the signs of the potential differences applied) are stored in the N-region 14 of the photodiode. Before the end of the duration T, the potential of the storage region is reset to Vref by the reset gate RS. At the end of the duration T, a transfer pulse is applied to the gate TR and the charges stored in the photodiode are poured into the storage region. They are then read by the not shown follower transistor, while a new integration time begins.
Selon l'invention, on prévoit des moyens pour conférer, pendant la phase d'intégration elle-même, une accélération forte et alternée aux électrons qui s'accumulent dans la photodiode pendant cette phase. Ces moyens comprennent des grilles de multiplication enterrées verticales qui sont des électrodes s'étendant dans la profondeur de la couche active, de préférence dans toute la profondeur des régions N et même dans toute la profondeur de la couche active, et des moyens pour commuter le potentiel de ces grilles de manière à créer une alternance de champs électriques dans la région où s'accumulent les électrons. De préférence, les grilles de multiplication sont disposées entre les photodiodes de deux pixels adjacents et agissent sur les électrons des photodiodes de ces deux pixels. According to the invention, means are provided for imparting, during the integration phase itself, a strong and alternating acceleration to the electrons which accumulate in the photodiode during this phase. These means comprise vertical buried multiplication grids which are electrodes extending in the depth of the active layer, preferably in all the depth of the N regions and even in the entire depth of the active layer, and means for switching the potential of these grids so as to create an alternation of electric fields in the region where the electrons accumulate. Preferably, the multiplication grids are arranged between the photodiodes of two adjacent pixels and act on the electrons of the photodiodes of these two pixels.
La figure 2 représente la modification correspondante du pixel de la figure 1 . A la place de la région 13 qui sépare les deux photodiodes PHD, on a placé une ou plusieurs grilles enterrées (une seule est visible et désignée par GC sur la figure 2). Les grilles sont entièrement isolées de la couche active par une couche isolante 22 qui entoure chaque grille en couvrant aussi la partie inférieure de celle-ci pour en assurer l'isolation complète. Cette couche isole également les grilles les unes des autres pour permettre de leur appliquer des potentiels différents. Cette couche isolante 22 est de préférence en oxyde de silicium.  FIG. 2 represents the corresponding modification of the pixel of FIG. 1. Instead of the region 13 which separates the two photodiodes PHD, one or more buried grids have been placed (only one is visible and designated by GC in FIG. 2). The grids are fully insulated from the active layer by an insulating layer 22 which surrounds each grid also covering the lower part thereof to ensure complete isolation. This layer also isolates the grids from each other to allow them to apply different potentials. This insulating layer 22 is preferably made of silicon oxide.
Les grilles sont de préférence en silicium polycristallin (mais elles pourraient être en métal) ; elles affleurent à la surface de la couche active ou à proximité de cette surface et des contacts électriques (non représentés) sont prévus en surface pour leur appliquer les potentiels désirés. Les grilles sont aussi étroites que la technologie de fabrication le permet. La couche isolante 22 peut être formée par oxydation du substrat de silicium dans une tranchée ouverte dans la couche active, tranchée que l'on vient ensuite combler par du silicium polycristallin.  The grids are preferably polycrystalline silicon (but they could be metal); they are flush with the surface of the active layer or near this surface and electrical contacts (not shown) are provided on the surface to apply the desired potentials. The grids are as narrow as the manufacturing technology allows. The insulating layer 22 may be formed by oxidation of the silicon substrate in an open trench in the active layer, which is then trenched and filled with polycrystalline silicon.
L'épaisseur de la couche isolante 22 peut être choisie de manière indépendante de l'épaisseur d'isolant des grilles horizontales TR et RS du pixel car elle n'est pas formée par la même étape d'oxydation. L'épaisseur de la couche 22 est de préférence bien supérieure à l'épaisseur de l'isolant de la grille de transfert ou de la grille de réinitialisation. Cette épaisseur supérieure permet d'appliquer aux grilles de multiplication des tensions bien supérieures à celles qu'on peut appliquer sans dégradation aux grilles de transfert et de réinitialisation. Ces tensions supérieures favorisent la multiplication d'électrons souhaitée. On notera qu'on ne pourrait pas appliquer aux grilles de multiplication des tensions supérieures aux tensions acceptables pour les grilles de transfert si les grilles de multiplication étaient formées par la même technique et dans la même étape que les grilles de transfert et de réinitialisation. The thickness of the insulating layer 22 may be chosen independently of the insulation thickness of the horizontal grids TR and RS of the pixel because it is not formed by the same oxidation step. The thickness of the layer 22 is preferably much greater than the thickness of the insulation of the transfer gate or the reset gate. This greater thickness makes it possible to apply to the multiplier gates voltages much higher than those which can be applied without degradation to the transfer and reset gates. These higher voltages promote the desired electron multiplication. It should be noted that it would be impossible to apply to the multiplier gates voltages greater than the acceptable voltages for the transfer gates if the multiplication gates were formed by the same technical and in the same step as the transfer and reset grids.
La figure 3 représente en vue de dessus une disposition possible des différents éléments du pixel ; pour simplifier on n'a pas représenté des éléments qui peuvent être classiquement présents dans le pixel et notamment un transistor suiveur pour recopier le potentiel de la région de stockage 18, et un transistor de sélection de ligne, dans le cas d'une matrice de plusieurs lignes de pixels, pour autoriser la connexion de la source du transistor suiveur à un conducteur de colonne de la matrice. Ces éléments sont de toutes façons situés en dehors de la région d'isolation 13 qui entoure la photodiode.  3 shows a top view of a possible arrangement of the different elements of the pixel; to simplify, we have not represented elements that can be conventionally present in the pixel and in particular a follower transistor for copying the potential of the storage region 18, and a line selection transistor, in the case of a matrix of several lines of pixels, to allow the connection of the source of the follower transistor to a column conductor of the matrix. These elements are in any case located outside the isolation region 13 which surrounds the photodiode.
Deux grilles de multiplication principales GA, GB sont représentées et une grille intermédiaire (facultative) GC est placée entre les deux grilles. La coupe de la figure 2 est faite selon la ligne AA de la figure 3 et passe ici à travers la grille GC qui, si elle est présente, est constituée de la même manière et en même temps que les deux autres. L'ensemble des grilles sépare les photodiodes des pixels adjacents. Si les grilles n'occupaient pas complètement la frontière entre les deux photodiodes, cette frontière serait complétée par une structure isolante classique telle que 13.  Two main multiplication gates GA, GB are shown and an intermediate (optional) gate GC is placed between the two gates. The section of Figure 2 is taken along the line AA of Figure 3 and passes through the GC grid which, if present, is constituted in the same manner and at the same time as the other two. The set of grids separates the photodiodes from the adjacent pixels. If the grids did not completely occupy the boundary between the two photodiodes, this boundary would be completed by a conventional insulating structure such as 13.
Dans la solution préférée, les grilles sont alignées dans un même plan vertical général comme le montre la figure 3.  In the preferred solution, the grids are aligned in the same general vertical plane as shown in FIG.
Des moyens de commutation de potentiel sont prévus pour appliquer directement aux grilles de multiplication principales GA et GB une série d'alternances d'un potentiel haut et d'un potentiel bas, en opposition de phase pour les deux grilles, et d'un niveau propre à provoquer une multiplication d'électrons. Ces moyens de commutation ne sont pas représentés car ils ne sont pas situés dans le pixel. Si le capteur comporte une matrice de pixels, ces moyens de commutation sont communs à toute la matrice et les grilles de multiplication GA et GB de tous les pixels peuvent être reliées toutes ensemble à ces moyens de commutation, par des lignes conductrices en contact ponctuellement avec la partie supérieure des grilles. Alternativement, les grilles de multiplication d'une même ligne de pixels peuvent être commandées indépendamment de celles des autres grilles. La série d'alternances est appliquée pendant tout ou partie de la durée d'intégration T qui sépare deux transferts successifs de charges (par la grille de transfert TR) entre la région de photodiode PHD et la région de stockage 18. Potential switching means are provided for directly applying to the main multiplication gates GA and GB a series of alternations with a high potential and a low potential, in phase opposition for the two gates, and one level. able to cause a multiplication of electrons. These switching means are not shown because they are not located in the pixel. If the sensor comprises a matrix of pixels, these switching means are common to the entire matrix and the multiplication gates GA and GB of all the pixels can be connected together to these switching means, by conductive lines in punctual contact with each other. the upper part of the grids. Alternatively, the multiplication grids of the same pixel line can be controlled independently of those of the other grids. The series of alternations is applied during all or part of the integration time T which separates two successive transfers of charges (by the gate transfer circuit TR) between the photodiode region PHD and the storage region 18.
La photodiode est une photodiode de type "pinned", c'est-à-dire dotée d'une région superficielle dopée maintenue à un potentiel de référence zéro ; cette région induit dans la région de photodiode un potentiel de base fixe (en l'absence de charges accumulées) qui dépend des dopages de la photodiode ; l'alternance de potentiels appliqués aux grilles de multiplication comprend un potentiel haut qui induit dans la photodiode à proximité de la grille un potentiel plus élevé que le potentiel de base de la photodiode et un potentiel bas qui induit sous la grille un potentiel de surface plus bas que le potentiel de base de la photodiode.  The photodiode is a "pinned" type photodiode, that is to say having a doped surface region maintained at a zero reference potential; this region induces in the photodiode region a fixed base potential (in the absence of accumulated charges) which depends on the doping of the photodiode; the alternation of potentials applied to the multiplication gates comprises a high potential which induces in the photodiode close to the gate a higher potential than the base potential of the photodiode and a low potential which induces a greater surface potential under the gate; lower than the basic potential of the photodiode.
Lorsqu'une troisième grille GC est présente, elle est de préférence portée à un potentiel intermédiaire entre le potentiel haut et le potentiel bas.  When a third gate GC is present, it is preferably brought to an intermediate potential between the high potential and the low potential.
Grâce à leur configuration verticale, leur très faible épaisseur, et leur position entre deux photodiodes adjacentes, les grilles de multiplication GA et GB (ainsi que GC) occupent une surface minimale qui gêne très peu la production d'électrons par la lumière.  Due to their vertical configuration, their very small thickness, and their position between two adjacent photodiodes, the GA and GB multiplication grids (as well as GC) occupy a minimum surface which hinders very little the production of electrons by the light.
Lorsque l'alternance de potentiels est appliquée, les électrons sont attirés avec un champ électrique d'autant plus fort que les potentiels sont plus forts vers la grille au potentiel le plus haut ; lors de la phase suivante de l'alternance ils sont attirés vers l'autre grille. La vitesse qu'ils acquièrent crée les impacts qui engendrent la multiplication progressive d'électrons.  When the alternation of potentials is applied, the electrons are attracted with an electric field all the stronger as the potentials are stronger towards the grid with the highest potential; in the next phase of the alternation they are attracted to the other grid. The speed they acquire creates the impacts that cause the progressive multiplication of electrons.
Les électrons ne passent pas d'une photodiode à la photodiode adjacente du fait de la profondeur de la grille qui s'étend au-dessous de la profondeur des régions N de la photodiode et qui s'étend de préférence à travers toute la profondeur de la couche active P.  The electrons do not pass from one photodiode to the adjacent photodiode because of the depth of the gate which extends below the depth of the N regions of the photodiode and which preferably extends through the entire depth of the photodiode. the active layer P.
Sur la figure 3, on a représenté toutes les grilles de multiplication sur un seul côté de la photodiode, plus précisément un côté qui sépare deux pixels adjacents d'une même ligne. Les grilles pourraient être sur un côté qui sépare deux pixels adjacents d'une même colonne, ou réparties sur deux ou plusieurs côtés du pixel. Par exemple, un groupe de deux ou trois grilles GA, GB, GC seraient placées d'un côté et un autre groupe de deux ou trois grilles sur un côté opposé. On peut à titre d'exemple prévoir aussi que les deux grilles de multiplication sont sur deux bords opposés de la photodiode, la troisième grille étant sur un troisième bord joignant les deux bords opposés. In FIG. 3, all the multiplication grids are represented on one side of the photodiode, more precisely a side that separates two adjacent pixels from the same line. The grids could be on one side that separates two adjacent pixels from the same column, or spread over two or more sides of the pixel. For example, a group of two or three grids GA, GB, GC would be placed on one side and another group of two or three grids on an opposite side. For example, we can also predict that both multiplication grids are on two opposite edges of the photodiode, the third gate being on a third edge joining the two opposite edges.
Le chronogramme de fonctionnement de ce pixel est classique, à l'exception du fait qu'on y rajoute une alternance de potentiels sur les grilles de multiplication GA et GB pendant tout ou partie de la durée d'intégration de charges dans la photodiode. The operating chronogram of this pixel is conventional, except that it adds an alternation of potentials on the GA and GB multiplication gates during all or part of the charge integration time in the photodiode.
Typiquement, on suppose qu'il y a une électrode de réinitialisation du potentiel de la photodiode (non représentée sur les figures mais classique dans les capteurs d'image à pixels actifs à cinq transistors). On fonctionne alors en mode dit « global shutter » dans laquelle les durées d'intégration sont réglables et simultanées pour toutes les lignes.  Typically, it is assumed that there is a potential reset electrode of the photodiode (not shown in the figures but conventional in active pixel image sensors with five transistors). We then operate in so-called "global shutter" mode in which the integration times are adjustable and simultaneous for all lines.
Le chronogramme d'une période d'intégration commence par une impulsion de réinitialisation du potentiel de la photodiode à un niveau de référence ; la fin de cette impulsion définit le début de l'intégration de charges dans la photodiode sous l'effet de la lumière éclairant le pixel.  The timing diagram of an integration period starts with a reset pulse of the potential of the photodiode at a reference level; the end of this pulse defines the beginning of the integration of charges in the photodiode under the effect of the light illuminating the pixel.
Puis, pendant tout ou partie de la durée d'intégration on applique des potentiels alternés aux grilles GA et GB pour effectuer une multiplication d'électrons.  Then, during all or part of the integration time alternating potentials are applied to the gates GA and GB to perform an electron multiplication.
La fin de la période d'intégration est définie par la fin d'une impulsion de transfert appliquée à l'électrode de transfert TR de tous les pixels de la matrice ; les charges de la photodiode sont transférées dans le nœud de stockage 18 de chaque pixel.  The end of the integration period is defined by the end of a transfer pulse applied to the transfer electrode TR of all the pixels of the matrix; the charges of the photodiode are transferred to the storage node 18 of each pixel.
Le potentiel du nœud de stockage 18 résultant de ce transfert de charges est ensuite lu ligne par ligne : pour une ligne donnée il est reporté sur un conducteur de colonne et recueilli par un échantillonneur en pied de colonne. Après chaque lecture d'une ligne, le potentiel du nœud de stockage est réinitialisé à une valeur de référence par l'application d'une impulsion de réinitialisation sur la grille RS ; le potentiel de réinitialisation est recueilli par l'échantillonneur bloqueur en pied de colonne et une mesure différentielle est établie entre le potentiel lu et le potentiel de réinitialisation. Puis cette double lecture est répétée pour la ligne suivante, et ainsi de suite.  The potential of the storage node 18 resulting from this charge transfer is then read line by line: for a given line it is carried over to a column conductor and collected by a sampler at the bottom of the column. After each read of a line, the potential of the storage node is reset to a reference value by the application of a reset pulse on the RS gate; the reset potential is collected by the bottom-of-column sampler and a differential measurement is made between the read potential and the reset potential. Then this double reading is repeated for the next line, and so on.
Le chronogramme pourrait aussi être un chronogramme en mode dit « rolling shutter » dans lequel les durées d'intégration des différentes lignes sont identiques mais non simultanées, avec le défaut de créer du traînage d'image mais avec l'avantage de réduire le bruit de réinitialisation. Le transfert de charges par l'électrode de transfert TR se fait alors ligne par ligne et on peut faire une réinitialisation du nœud de stockage et une lecture du potentiel de réinitialisation juste avant le transfert de charges dans le nœud de stockage et la lecture du potentiel qui en résulte. The chronogram could also be a chronogram in so-called rolling shutter mode in which the integration durations of the different lines are identical but not simultaneous, with the failure to create the image dragging but with the benefit of reducing the reset noise. The transfer of charges by the transfer electrode TR is then done line by line and it is possible to reset the storage node and read the reset potential just before the transfer of charges in the storage node and the reading of the potential. resulting.
Les grilles sont aussi étroites que possible pour ne pas réduire la surface occupée par la photodiode dans le pixel. Il suffit qu'elles comportent à leur partie supérieure une zone assez large pour y placer un contact électrique, pour amener le potentiel alternatif nécessaire à leur fonctionnement. The grids are as narrow as possible so as not to reduce the area occupied by the photodiode in the pixel. It suffices that they comprise at their upper part an area wide enough to place an electrical contact, to bring the alternative potential necessary for their operation.
A titre d'exemple, la profondeur des grilles verticales enterrées GA, GB, GC peut être d'environ 1 ,5 à 2 micromètres, leur largeur de 0,3 micromètre, leur longueur de 1 ,5 à 3 micromètres, pour des pixels d'environ 25 micromètres carrés. Elles sont en silicium polycristallin et la couche isolante qui les sépare de la couche active peut avoir une épaisseur de 10 à 50 nanomètres. Cette épaisseur est choisie pour supporter des tensions de 7 à 8 volts, voire plus entre la couche active et les grilles. Cette épaisseur est supérieure à l'épaisseur de couche isolante entre la grille de transfert TR et la couche active, cette dernière épaisseur devant être minimisée (de l'ordre de 5 à 10 nanomètres par exemple) pour assurer un bon transfert de charges.  For example, the depth of the buried vertical grids GA, GB, GC may be about 1.5 to 2 microns, their width 0.3 microns, their length 1.5 to 3 microns, for pixels about 25 square micrometers. They are polycrystalline silicon and the insulating layer separating them from the active layer can have a thickness of 10 to 50 nanometers. This thickness is chosen to withstand voltages of 7 to 8 volts or more between the active layer and the grids. This thickness is greater than the thickness of insulating layer between the transfer gate TR and the active layer, the latter thickness to be minimized (of the order of 5 to 10 nanometers for example) to ensure good charge transfer.
La fabrication des grilles enterrées se fait de préférence en utilisant notamment les étapes suivantes : The manufacture of the buried grids is preferably done using, in particular, the following steps:
- photolithographie d'une résine déposée sur la couche active en silicium monocristallin pour définir des ouvertures ayant un peu plus que la largeur et la longueur souhaitées pour chacune des grilles ;  photolithography of a resin deposited on the active monocrystalline silicon layer to define openings having a little more than the desired width and length for each of the grids;
- gravure directionnelle verticale de la couche active sur la profondeur désirée pour définir des tranchées correspondant au volume de chaque grille ;  vertical directional etching of the active layer over the desired depth to define trenches corresponding to the volume of each grid;
- oxydation thermique du silicium dans les tranchées pour former la couche isolante 22 qui séparera la grille de la couche active ; - remplissage des tranchées avec du silicium polycristallin dopé qui forme les grilles ; thermal oxidation of the silicon in the trenches to form the insulating layer 22 which will separate the gate from the active layer; - Trench filling with doped polycrystalline silicon which forms the grids;
- gravure du silicium polycristallin pour délimiter sa surface supérieure ;  etching of the polycrystalline silicon to delimit its upper surface;
- formation d'un contact entre une ligne conductrice et la surface supérieure de la grille pour permettre d'amener un potentiel alterné par cette ligne.  - Formation of a contact between a conductive line and the upper surface of the gate to allow to bring an alternating potential by this line.
Dans la réalisation qui précède, les grilles sont en silicium polycristallin dopé. Elles pourraient cependant aussi être en métal. In the preceding embodiment, the grids are made of doped polycrystalline silicon. They could however also be metal.
On peut prévoir que l'utilisation d'une alternance de potentiels est déclenchée seulement en cas de très faible éclairement. Par exemple, en fonction du niveau d'éclairement détecté, on déclenche ou on ne déclenche pas la série d'alternances de potentiels. Si on ne la déclenche pas, on laisse les grilles d'accélération à un niveau bas. Et si on la déclenche, on peut prévoir que le nombre d'alternances est variable en fonction du niveau d'éclairement détecté.  It can be expected that the use of an alternation of potentials is triggered only in case of very low illumination. For example, depending on the level of illumination detected, one triggers or does not trigger the series of alternations of potentials. If it is not triggered, the acceleration grids are left at a low level. And if it is triggered, we can predict that the number of alternations is variable depending on the level of illumination detected.
L'invention peut être utilisée avec un capteur d'image éclairé par la face avant, ou avec un capteur d'image sur substrat de silicium aminci éclairé par la face arrière.  The invention can be used with an image sensor illuminated by the front face, or with a thin-film silicon image sensor illuminated by the rear face.

Claims

REVENDICATIONS
1 . Capteur d'image à pixels actifs, chaque pixel comprenant, à la surface d'une couche active semiconductrice (12), une région de photodiode (PHD) adjacente à une grille de transfert (TR) elle-même adjacente à une région de stockage de charges (18), la grille de transfert autorisant, lorsqu'elle reçoit une impulsion de transfert, le transfert de charges de la région de photodiode vers la région de stockage, ce capteur étant caractérisé en ce que la région de photodiode est adjacente à au moins deux grilles de multiplication d'électrons (GA, GB) s'étendant verticalement en profondeur dans la couche active dans un plan perpendiculaire à la surface du capteur entre deux pixels adjacents, les grilles de multiplication étant isolées de la région de photodiode par une couche plane verticale isolante (22), et en ce que le capteur comprend des moyens de commutation agencés pour appliquer aux deux grilles de multiplication, pendant une phase d'intégration précédant l'impulsion de transfert, une série d'alternances de potentiels différents dits haut et bas, en opposition de phase, induisant des champs électriques opposés, alternativement dans un sens et dans l'autre, entre les grilles et la photodiode. 1. An active pixel image sensor, each pixel comprising, on the surface of a semiconductor active layer (12), a photodiode region (PHD) adjacent to a transfer gate (TR) itself adjacent to a storage region of charges (18), the transfer gate allowing, when it receives a transfer pulse, the transfer of charges from the photodiode region to the storage region, this sensor being characterized in that the photodiode region is adjacent to at least two electron multiplication grids (GA, GB) extending vertically in depth in the active layer in a plane perpendicular to the sensor surface between two adjacent pixels, the multiplication gates being isolated from the photodiode region by an insulating vertical plane layer (22), and in that the sensor comprises switching means arranged to apply to the two multiplication grids, during an integration phase preceding the impulse transfer voltage, a series of alternations of different potentials called up and down, in phase opposition, inducing opposite electric fields, alternately in one direction and the other, between the gates and the photodiode.
2. Capteur d'image selon la revendication 1 , caractérisé en ce que la région de photodiode comprend une région (14) d'un premier type de conductivité (N) recouverte par une région superficielle (16) du type opposé reliée à un potentiel de référence zéro, et en ce que le potentiel haut de l'alternance est plus élevé que le potentiel de référence zéro et le potentiel bas est inférieur ou égal au potentiel de référence zéro. 2. An image sensor according to claim 1, characterized in that the photodiode region comprises a region (14) of a first type of conductivity (N) covered by a surface region (16) of the opposite type connected to a potential. reference zero, and that the high potential of the alternation is higher than the zero reference potential and the low potential is less than or equal to the zero reference potential.
3. Capteur d'image selon l'une des revendications 1 et 2, caractérisé en ce qu'une même grille de multiplication est adjacente aux deux photodiodes de pixels adjacents. 3. Image sensor according to one of claims 1 and 2, characterized in that a same multiplication grid is adjacent to the two photodiodes of adjacent pixels.
4. Capteur d'image selon l'une des revendications 1 à 3, caractérisé en ce que les deux grilles sont alignées le long d'un même bord de la photodiode. 4. Image sensor according to one of claims 1 to 3, characterized in that the two grids are aligned along the same edge of the photodiode.
5. Capteur d'image selon l'une des revendications 1 à 4, caractérisé en ce qu'il comporte une troisième grille (GC) interposée entre les deux premières grilles et maintenue à un potentiel fixe intermédiaire entre le potentiel haut et le potentiel bas. 5. An image sensor according to one of claims 1 to 4, characterized in that it comprises a third gate (GC) interposed between the first two grids and maintained at a fixed potential intermediate between the high potential and the low potential. .
6. Capteur d'image selon la revendication 5 , caractérisé en ce que les trois grilles sont alignées le long d'un même bord de la photodiode. 6. Image sensor according to claim 5, characterized in that the three grids are aligned along the same edge of the photodiode.
7. Capteur d'image selon la revendication 5, caractérisé que les trois grilles sont réparties sur plusieurs bords de la photodiode. 7. An image sensor according to claim 5, characterized in that the three grids are distributed over several edges of the photodiode.
PCT/EP2012/066705 2011-09-28 2012-08-28 Image sensor achieving electron multiplication via vertical gates WO2013045191A1 (en)

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FR3105581A1 (en) * 2019-12-19 2021-06-25 Stmicroelectronics (Crolles 2) Sas Photodiode comprising a memory area
FR3105582A1 (en) * 2019-12-19 2021-06-25 Stmicroelectronics (Crolles 2) Sas Photodiode comprising a memory area
US11923465B2 (en) 2019-12-19 2024-03-05 Stmicroelectronics (Crolles 2) Sas Photodiode comprising a memory area

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060043437A1 (en) * 2004-08-24 2006-03-02 Chandra Mouli Transparent metal shielded isolation for image sensors
US20070052056A1 (en) * 2005-09-05 2007-03-08 Kabushiki Kaisha Toshiba Solid-state imaging device and method of manufacturing same
US20090057724A1 (en) * 2007-08-28 2009-03-05 Sanyo Electric Co., Ltd. Image sensor and sensor unit
US20090266973A1 (en) * 2008-04-24 2009-10-29 Stmicroelectronics Crolles 2 Sas Very small image sensor
EP2216817A1 (en) * 2009-02-05 2010-08-11 STMicroelectronics (Crolles 2) SAS Back side illuminated image sensor
EP2315251A1 (en) * 2009-10-22 2011-04-27 STMicroelectronics (Crolles 2) SAS Imager with vertical transfer gate and its method of fabrication

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060043437A1 (en) * 2004-08-24 2006-03-02 Chandra Mouli Transparent metal shielded isolation for image sensors
US20070052056A1 (en) * 2005-09-05 2007-03-08 Kabushiki Kaisha Toshiba Solid-state imaging device and method of manufacturing same
US20090057724A1 (en) * 2007-08-28 2009-03-05 Sanyo Electric Co., Ltd. Image sensor and sensor unit
US20090266973A1 (en) * 2008-04-24 2009-10-29 Stmicroelectronics Crolles 2 Sas Very small image sensor
EP2216817A1 (en) * 2009-02-05 2010-08-11 STMicroelectronics (Crolles 2) SAS Back side illuminated image sensor
EP2315251A1 (en) * 2009-10-22 2011-04-27 STMicroelectronics (Crolles 2) SAS Imager with vertical transfer gate and its method of fabrication

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