WO2013032169A3 - 3차원 멀티코어 프로세서의 분기예측기 배치방법 및 3차원 멀티코어 프로세서 - Google Patents

3차원 멀티코어 프로세서의 분기예측기 배치방법 및 3차원 멀티코어 프로세서 Download PDF

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Publication number
WO2013032169A3
WO2013032169A3 PCT/KR2012/006693 KR2012006693W WO2013032169A3 WO 2013032169 A3 WO2013032169 A3 WO 2013032169A3 KR 2012006693 W KR2012006693 W KR 2012006693W WO 2013032169 A3 WO2013032169 A3 WO 2013032169A3
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WO
WIPO (PCT)
Prior art keywords
core processors
dimensional multi
branch predictors
arranging
predictors
Prior art date
Application number
PCT/KR2012/006693
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English (en)
French (fr)
Other versions
WO2013032169A2 (ko
Inventor
손동오
안진우
김철홍
Original Assignee
전남대학교산학협력단
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Application filed by 전남대학교산학협력단 filed Critical 전남대학교산학협력단
Publication of WO2013032169A2 publication Critical patent/WO2013032169A2/ko
Publication of WO2013032169A3 publication Critical patent/WO2013032169A3/ko

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3848—Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)

Abstract

본 발명은 3차원 멀티코어 프로세서의 분기예측기 배치방법 및 3차원 멀티코어 프로세서에 관한 것으로, 보다 구체적으로는 분기예측기를 복잡도 별로 구분하여 높은 동작온도를 갖는 프로세서 코어에는 복잡도가 낮은 분기예측기를 배치하고, 낮은 동작온도를 갖는 프로세서 코어에는 복잡도가 높은 분기예측기를 배치함으로써 분기 예측기의 정확도 하락은 최소화하면서도 저 온도로 분기예측기를 동작하게 할 수 있는 3차원 멀티코어 프로세서의 분기예측기 배치방법 및 3차원 멀티코어 프로세서에 관한 것이다.
PCT/KR2012/006693 2011-08-31 2012-08-23 3차원 멀티코어 프로세서의 분기예측기 배치방법 및 3차원 멀티코어 프로세서 WO2013032169A2 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020110087625A KR101294629B1 (ko) 2011-08-31 2011-08-31 3차원 멀티코어 프로세서의 분기예측기 배치방법 및 3차원 멀티코어 프로세서
KR10-2011-0087625 2011-08-31

Publications (2)

Publication Number Publication Date
WO2013032169A2 WO2013032169A2 (ko) 2013-03-07
WO2013032169A3 true WO2013032169A3 (ko) 2013-04-25

Family

ID=47757021

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2012/006693 WO2013032169A2 (ko) 2011-08-31 2012-08-23 3차원 멀티코어 프로세서의 분기예측기 배치방법 및 3차원 멀티코어 프로세서

Country Status (2)

Country Link
KR (1) KR101294629B1 (ko)
WO (1) WO2013032169A2 (ko)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080054409A (ko) * 2005-10-26 2008-06-17 인텔 코오퍼레이션 변화를 탐지하는 클러스터 아키텍처
US20100146249A1 (en) * 2008-12-05 2010-06-10 Intellectual Ventures Management, Llc Control-Flow Prediction Using Multiple Independent Predictors
KR20110075638A (ko) * 2009-12-28 2011-07-06 전남대학교산학협력단 저 전력 트레이스 캐쉬 및 명령어 세트 예측기를 구비한 프로세서 시스템

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080054409A (ko) * 2005-10-26 2008-06-17 인텔 코오퍼레이션 변화를 탐지하는 클러스터 아키텍처
US20100146249A1 (en) * 2008-12-05 2010-06-10 Intellectual Ventures Management, Llc Control-Flow Prediction Using Multiple Independent Predictors
KR20110075638A (ko) * 2009-12-28 2011-07-06 전남대학교산학협력단 저 전력 트레이스 캐쉬 및 명령어 세트 예측기를 구비한 프로세서 시스템

Also Published As

Publication number Publication date
KR20130024279A (ko) 2013-03-08
KR101294629B1 (ko) 2013-08-08
WO2013032169A2 (ko) 2013-03-07

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