WO2013020269A1 - Circuit en pont complet à déphasage et son procédé de commande - Google Patents

Circuit en pont complet à déphasage et son procédé de commande Download PDF

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Publication number
WO2013020269A1
WO2013020269A1 PCT/CN2011/078150 CN2011078150W WO2013020269A1 WO 2013020269 A1 WO2013020269 A1 WO 2013020269A1 CN 2011078150 W CN2011078150 W CN 2011078150W WO 2013020269 A1 WO2013020269 A1 WO 2013020269A1
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Prior art keywords
mos transistor
mos
transformer
phase
drain
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PCT/CN2011/078150
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English (en)
Chinese (zh)
Inventor
付登萌
韩卫军
孙辉
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联合汽车电子有限公司
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Priority to PCT/CN2011/078150 priority Critical patent/WO2013020269A1/fr
Publication of WO2013020269A1 publication Critical patent/WO2013020269A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/337—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
    • H02M3/3372—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration of the parallel type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a DC/DC (DC-DC converter), and more particularly to a soft switching Phase shift full bridge circuit.
  • the vehicle DC/DC In electric vehicles and hybrid vehicles, the vehicle DC/DC is used to convert the voltage of the high-voltage battery into a low voltage, thereby supplying power to the low-voltage load while charging the low-voltage battery.
  • soft switching technology In order to improve the efficiency of DC/DC, reduce the volume, and reduce the cost, soft switching technology is widely used. Automotive DC/DC usually uses a phase-shifted full-bridge circuit to achieve soft switching.
  • FIG. 1 is an existing phase shift full bridge circuit, including:
  • a leading bridge arm which is composed of MOS tubes Q1 and Q2 connected in series;
  • a lag bridge arm which is composed of MOS tubes Q3 and Q4 connected in series, and the connection node D of the two MOS tubes is connected to one end of the primary side of the transformer TX;
  • the two clamp diodes D1 and D2 are connected in reverse between the connection node A of the MOS transistors Q1 and Q3 and the connection node B of the MOS transistors Q2 and Q4.
  • the connection nodes E and the transformer of the two clamp diodes D1 and D2 are connected.
  • the other end of the TX primary side is connected;
  • a resonant inductor L1 is connected in series between the connection node C of the two MOS transistors Q1 and Q2 and the connection node E;
  • An output circuit is mainly composed of two rectifying MOS tubes Q5, Q6, an output inductor L2 and an output capacitor C; one end of the secondary side of the transformer TX is connected to the rectifying MOS tube Q5 and grounded; the other end of the secondary side of the transformer TX is connected to the rectifying MOS tube Grounding after Q6; the middle tap of the secondary side of the transformer TX (dividing the secondary side of the transformer TX into two coils) is connected in series with the output inductor L2 and the output capacitor C.
  • the input DC voltage Vin is applied between the connection node A and the connection node B, and the output DC voltage Vo is the two ends of the output capacitor C, that is, the load not shown is Parallel to the output capacitor C.
  • phase-shifted full-bridge circuit shown in FIG. 1 The control method of the phase-shifted full-bridge circuit shown in FIG. 1 is as shown in FIG. 2, wherein OA, OB, OC, OD, OE, and OF are the applied gate voltages of the MOS transistors Q1 to Q6, respectively, and V_TX is the transformer TX once. Voltage (primary voltage), I_TX is the primary current of the transformer TX (primary current).
  • the entire phase shift control can be divided into the following stages in one work cycle:
  • Phase 1 OA, OD, and OF are high level, OB, OC, and OE are low level, MOS transistors Q1, Q4, and Q6 are turned on, V_TX is positive, and I_TX is increased;
  • Phase 2 OD goes low, MOS transistor Q4 turns off, the parasitic capacitance between the resonant inductor L1 and the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate.
  • the drain and source of the MOS transistor Q4 The voltage between the two starts to rise, that is, the voltage between the drain and the source of the MOS transistor Q3 starts to drop.
  • V_TX drops and I_TX continues to increase.
  • Phase 3 OC becomes a high level.
  • the MOS transistors Q1 and Q3 are turned on, and the full bridge structure composed of the MOS transistors Q1 to Q4 enters the freewheel mode, and V_TX is zero, and I_TX is decreased.
  • OE becomes a high level, that is, MOS tubes Q5 and Q6 are simultaneously turned on.
  • the time interval between the turn-off of the MOS transistor Q4 and the turn-on of the MOS transistor Q3 is the dead time of the MOS transistors Q3, Q4 (lag bridge arm), which should be carefully selected to make the MOS transistor When Q3 is turned on, its drain-source voltage is zero, thereby achieving zero-voltage turn-on of MOS transistor Q3.
  • This process can be described by the equivalent circuit of phase 2 shown in FIG.
  • capacitors C3 and C4 represent the parasitic capacitance between the drain and source of MOS transistors Q3 and Q4, respectively.
  • the initial values are Vin and 0, respectively;
  • IL1 is the current of resonant inductor L1, and its initial value is greater than zero. Since the input power source Vin will supply energy during the resonance process, the drain-source voltage of the MOS transistor Q4 can reach the input voltage (ie, the drain-source voltage of the MOS transistor Q3 is zero), so the zero voltage of the MOS transistor Q3 is turned on. Always feasible.
  • Phase 4 OA goes low, MOS transistor Q1 turns off, the parasitic capacitance between the resonant inductor L1 and the drain and source of the MOS transistor Q1, and the parasitic capacitance between the drain and source of the Q2 resonate.
  • the drain and source of the MOS transistor Q1 The voltage between the two starts to rise, that is, the voltage between the drain and the source of the MOS transistor Q2 starts to drop.
  • V_TX rises in the opposite direction, and I_TX decreases and reverses.
  • Phase 5 OB goes high. At this time, MOS transistors Q2 and Q3 are turned on, V_TX is negative, and I_TX is increased in reverse. At the same time, OF becomes a low level, and MOS transistor Q6 is turned off.
  • the time interval between the turn-off of the MOS transistor Q1 and the turn-on of the MOS transistor Q2 is the dead time of the MOS transistors Q1, Q2 (leading bridge arm), which should be carefully selected to make the MOS transistor When Q2 is turned on, its drain-source voltage is zero, thereby achieving zero voltage turn-on of MOS transistor Q2.
  • This process can be described by the equivalent circuit of stage 4 shown in FIG.
  • capacitors C1 and C2 represent the parasitic capacitance between the drain and source of MOS transistors Q1 and Q2, respectively.
  • the initial values are 0 and Vin respectively;
  • IL1 is the current of resonant inductor L1, and its initial value is greater than zero.
  • the input power source Vin will absorb energy, so in order to make the drain-source voltage of the MOS transistor Q2 reach zero, the following conditions must be satisfied: L1*(I 0 ) 2 >2*Vin*Q c .
  • Phase 6 OC goes low, MOS transistor Q3 turns off, the parasitic capacitance between the resonant inductor L1 and the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate.
  • the drain and source of the MOS transistor Q3 The voltage between the two starts to rise, that is, the voltage between the drain and the source of the MOS transistor Q4 starts to drop.
  • V_TX drops and I_TX continues to increase. This phase is similar to Phase 2, and the analysis process is no longer exhaustive.
  • Phase 7 OD becomes high level. At this time, MOS transistors Q2 and Q4 are turned on, and the full bridge structure composed of MOS transistors Q1 to Q4 enters the freewheel mode, V_TX is zero, and I_TX is decreased. At the same time, OF becomes a high level, that is, MOS tubes Q5 and Q6 are simultaneously turned on. This phase is similar to Phase 3, and the analysis process is no longer exhaustive.
  • Stage 8 OB becomes low level, MOS transistor Q2 is turned off, the parasitic capacitance between the resonant inductor L1 and the drain and source of the MOS transistor Q1, and the parasitic capacitance between the drain and source of the Q2 resonate, and the drain and source of the MOS transistor Q2
  • the voltage between the two starts to rise, that is, the voltage between the drain and the source of the MOS transistor Q1 starts to drop.
  • V_TX rises in the opposite direction, and I_TX decreases and reverses. This phase is similar to Phase 4, and the analysis process is no longer exhaustive.
  • the resonant inductor L1 in order to make the drain-source voltage zero before the MOS transistors Q1 and Q2 are turned on, the resonant inductor L1 must store sufficient energy before the resonance occurs. This can be achieved by increasing the inductance of the resonant inductor L1 or by increasing the current flowing through the resonant inductor L1.
  • the current flowing through the resonant inductor L1 is determined by the load, which determines that the commonly used phase-shifted full-bridge circuit cannot achieve soft switching within the full load range, that is, phase shifting under light load (small load) conditions.
  • the bridge circuit cannot implement soft switching.
  • the technical problem to be solved by the present invention is to provide a phase shift full bridge circuit control method, which can be Soft switching under light load conditions.
  • the present invention also provides a phase shift full bridge circuit to which the control method is applicable, which can improve the efficiency of the system.
  • the control method of the phase shift full bridge circuit of the present invention divides a duty cycle of the phase shift full bridge circuit into the following 10 stages; Wherein OA, OB, OC, OD, OE, and OF are the applied gate voltages of the MOS transistors Q1 to Q6, respectively, V_TX is the primary voltage of the transformer TX, and I_TX is the primary current of the transformer TX;
  • Phase 1 OA, OD, and OF are high level, OB, OC, and OE are low level, MOS transistors Q1, Q4, and Q6 are turned on, V_TX is positive, and I_TX is increased;
  • Phase 2 OD becomes low level, MOS transistor Q4 is turned off, the leakage inductance between the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate, the MOS transistor Q4
  • the voltage between the drain and the source begins to rise, that is, the voltage between the drain and the source of the MOS transistor Q3 begins to decrease;
  • V_TX decreases, and I_TX continues to increase;
  • Stage 3 OE becomes high level, and MOS tubes Q5 and Q6 are turned on at the same time; at this time, the secondary side (secondary side) of the transformer TX is short-circuited, and I_TX rises rapidly;
  • Phase 4 OC becomes high level. At this time, the MOS transistors Q1 and Q3 are turned on, and the full bridge structure composed of the MOS transistors Q1 to Q4 enters the freewheel mode, V_TX is zero, and I_TX is slowly decreased;
  • Phase 5 OA becomes low level, MOS transistor Q1 is turned off, the leakage inductance of the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q1 and the parasitic capacitance between the drain and source of the Q2 resonate, the MOS transistor
  • the voltage between the drain and source of Q1 begins to rise, that is, the voltage between the drain and source of MOS transistor Q2 begins to decrease;
  • V_TX rises in the reverse direction, and I_TX decreases and reverses;
  • Stage 6 OB becomes high level. At this time, MOS transistors Q2 and Q3 are turned on, V_T is negative, and I_TX is increased in reverse; at the same time OF becomes low level, and MOS transistor Q6 is turned off;
  • Phase 7 OC goes low, MOS transistor Q3 turns off, the leakage inductance between the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate.
  • MOS transistor Q3 The voltage between the drain and the source begins to rise, that is, the voltage between the drain and the source of the MOS transistor Q4 begins to decrease; V_TX decreases, and I_TX continues to increase;
  • Stage 8 OF becomes high level, and MOS tubes Q5 and Q6 are turned on at the same time; at this time, the secondary side of the transformer TX is short-circuited, and I_TX rises rapidly;
  • Stage 9 OD becomes high level. At this time, MOS tubes Q2 and Q4 are turned on, and the full bridge structure composed of MOS tubes Q1 to Q4 enters the freewheel mode, V_TX is zero, and I_TX is slowly decreased;
  • Stage 10 OB becomes low level, MOS transistor Q2 is turned off, the leakage inductance of the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q1 and the parasitic capacitance between the drain and source of the Q2 resonate, the MOS transistor
  • the voltage between the drain and source of Q2 begins to rise, that is, the voltage between the drain and source of MOS transistor Q1 begins to decrease; V_TX rises in the reverse direction, and I_TX decreases and reverses.
  • the MOS transistor may be replaced in whole or in part with an insulated gate bipolar transistor.
  • phase-shifted full-bridge circuit to which the above-described phase-shifting full-bridge circuit control method is applied must satisfy the following two conditions: First, the primary side of the transformer is a full-bridge structure, and the full-bridge structure is composed of 4n MOS tubes, where n For the natural number; second, the secondary side of the transformer is a synchronous rectification structure, that is, both ends of the secondary winding of the transformer are grounded through a MOS tube.
  • the MOS transistor in the circuit may be replaced in whole or in part by an insulated gate bipolar transistor.
  • the control method of the phase shift full bridge circuit of the invention can realize soft switching under light load conditions, and the applicable phase shift full bridge circuit can omit the resonant inductor L1 of the primary side of the transformer TX and the two clamp diodes D1 and D2, thereby reducing System cost, reducing system size.
  • the removed device is also a loss, and can be deleted after deletion. Further improve the efficiency of the system.
  • FIG. 2 is a timing chart of a control method of a conventional phase shift full bridge circuit
  • Figure 3 is an equivalent circuit diagram of stage 2 in Figure 2;
  • Figure 4 is an equivalent circuit diagram of stage 4 of Figure 2;
  • Figure 5 is a phase shift full bridge circuit in which the method of the present invention is particularly applicable
  • FIG. 6 is a timing chart of a phase shift full bridge circuit control method of the present invention.
  • Figure 7 is an equivalent circuit diagram of stage 3 in Figure 6;
  • Figure 8 is an equivalent circuit diagram of stage 5 in Figure 6;
  • FIG. 9 is a schematic diagram showing an implementation environment of a method for controlling a phase-shifted full-bridge circuit of the present invention.
  • Figure 10 is a waveform of the control method of the phase shift full bridge circuit of the present invention in a test environment.
  • Q1 ⁇ Q4 are MOS tubes; Q5 and Q6 are rectifier MOS tubes; L1 is resonant inductors; D1 and D2 are clamp diodes; TX is transformers; L2 is output inductors; C is output capacitors; Vin is DC input voltage; Vo DC output voltage; OA, OB, OC, OD, OE, OF are the applied gate voltages of MOS transistors Q1 ⁇ Q6 respectively; V_TX is the transformer primary voltage; I_TX is the transformer primary current; C1 ⁇ C4 are MOS tube Q1 ⁇ The parasitic capacitance between the source and the drain of Q4; Vc1 to Vc4 are the voltages across the parasitic capacitances C1 to C4; IL1 is the current flowing through the resonant inductor L1; Llk is the leakage inductance of the primary side of the transformer TX; IL is the leakage current The current of Llk is sensed.
  • the control method of the phase-shifted full-bridge circuit provided by the present invention is as shown in FIG. 6.
  • the control method divides one duty cycle of the phase-shifted full-bridge circuit into the following ten stages.
  • OA, OB, OC, OD, OE, and OF are the applied gate voltages of the MOS transistors Q1 to Q6, respectively,
  • V_TX is the primary voltage of the transformer TX, and
  • I_TX is the primary current of the transformer TX.
  • Phase 1 OA, OD, and OF are high level, OB, OC, and OE are low level, MOS transistors Q1, Q4, and Q6 are turned on, V_TX is positive, and I_TX is increased.
  • Phase 2 OD becomes low level, MOS transistor Q4 is turned off, the leakage inductance between the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate, the MOS transistor Q4
  • the voltage between the drain and the source starts to rise, that is, the voltage between the drain and the source of the MOS transistor Q3 starts to drop.
  • V_TX drops and I_TX continues to increase.
  • Phase 3 OE goes high, and MOS transistors Q5 and Q6 are turned on at the same time. This process can be described by the equivalent circuit of stage 3 shown in FIG.
  • capacitors C3 and C4 represent the parasitic capacitance between the drain and source of MOS transistors Q3 and Q4, respectively; Llk represents the leakage inductance of the primary side (primary side) of transformer TX. At this time, the voltage across the capacitor C4 is greater than zero and less than the input voltage Vin, and the secondary side (secondary side) of the transformer TX is short-circuited by the MOS transistors Q5 and Q6, so the leakage current flowing through the primary side of the transformer increases sharply, and at the same time, the capacitor C4 The voltage at the terminal rises rapidly.
  • Phase 4 OC becomes a high level. At this time, the MOS transistors Q1 and Q3 are turned on, and the full bridge structure composed of the MOS transistors Q1 to Q4 enters the freewheel mode, V_TX is zero, and I_TX is slowly decreased.
  • the time interval between the turn-off of the transistor Q4 and the turn-on of the MOS transistor Q3 is the dead time of the MOS transistors Q3, Q4 (lag bridge arm), and the dead time should be carefully
  • the MOS transistor Q3 is turned on, its source-drain voltage is zero, thereby achieving zero voltage turn-on of the MOS transistor Q3.
  • the selection method of the dead time is prior art and will not be described again.
  • Phase 5 OA becomes low level, MOS transistor Q1 is turned off, the leakage inductance of the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q1 and the parasitic capacitance between the drain and source of the Q2 resonate, the MOS transistor
  • the voltage between the drain and source of Q1 begins to rise, that is, the voltage between the drain and source of MOS transistor Q2 begins to decrease.
  • V_TX rises in the opposite direction, and I_TX decreases and reverses.
  • Phase 6 OB becomes high. At this time, MOS transistors Q2 and Q3 are turned on, V_T is negative, and I_TX is inversely increased. At the same time, OF becomes a low level, and MOS transistor Q6 is turned off.
  • the time interval between the turn-off of MOS transistor Q1 and the turn-on of MOS transistor Q2 is the dead time of MOS transistors Q1, Q2 (leading bridge arm), which should be carefully selected to make MOS
  • MOS transistors Q1, Q2 leading bridge arm
  • capacitors C1 and C2 represent the parasitic capacitance of the drain and source of MOS transistors Q1 and Q2, respectively;
  • Llk represents the leakage inductance of the primary side of transformer TX.
  • E lk is the energy stored in the primary leakage inductance Llk of the transformer TX
  • Vin is the input supply voltage
  • Q C is the initial charge of the parasitic capacitance C2 between the drain and source of the MOS transistor Q2.
  • Phase 7 OC goes low, MOS transistor Q3 turns off, the leakage inductance between the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate.
  • MOS transistor Q3 The voltage between the drain and the source begins to rise, that is, the voltage between the drain and the source of the MOS transistor Q4 begins to drop.
  • V_TX drops and I_TX continues to increase. This phase is similar to Phase 2, and the analysis process is no longer exhaustive.
  • Stage 8 OF becomes high level, and MOS transistors Q5 and Q6 are turned on at the same time. This phase is similar to Phase 3, and the analysis process is no longer exhaustive.
  • Stage 9 OD becomes high level. At this time, MOS transistors Q2 and Q4 are turned on, and the full bridge structure composed of MOS tubes Q1 to Q4 enters the freewheel mode, V_TX is zero, and I_TX is slowly decreased. This phase is similar to Phase 4, and the analysis process is no longer exhaustive.
  • Stage 10 OB becomes low level, MOS transistor Q2 is turned off, the leakage inductance of the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q1 and the parasitic capacitance between the drain and source of the Q2 resonate, the MOS transistor The voltage between the drain and source of Q2 begins to rise, that is, the voltage between the drain and source of MOS transistor Q1 begins to decrease. V_TX rises in the opposite direction, and I_TX decreases and reverses. This phase is similar to Phase 5, and the analysis process is no longer exhaustive.
  • the control method of the phase-shifted full-bridge circuit of the present invention switches the secondary side of the transformer TX through the synchronous rectification control during the process of switching from the energy transfer phase to the freewheeling phase, so that the primary side leakage inductance of the transformer TX is stored.
  • the energy is used to solve the problem that the traditional phase-shifted full-bridge circuit control method cannot realize zero voltage switching due to insufficient resonance energy at light load.
  • phase 2 and phase 3 corresponds to phase 2 of the prior art method shown in FIG. 2; the sum of phase 7 and phase 8 corresponds to FIG. Stage 6 of the existing method shown.
  • the control method of the present invention can be applied to all phase-shifted full-bridge circuits that simultaneously satisfy the following two conditions: First, the primary side of the transformer TX is a full-bridge structure, and the full-bridge structure is composed of 4n MOS tubes, where n is Natural number; (when n ⁇ 2, n MOS transistors are connected in parallel to one primary MOS tube in Fig. 1) Second, the secondary side of the transformer TX is a synchronous rectification structure, that is, both ends of the secondary side winding of the transformer TX Grounded through a MOS tube.
  • phase shift full bridge circuit shown in FIG. 5
  • the most simplified phase-shifted full-bridge circuit corresponding to the control method of the present invention is as shown in FIG. 5, and includes:
  • a lead bridge arm which is composed of a MOS tube Q1 and Q2 connected in series, and a connection node C of the two MOS tubes Q1 and Q2 is connected to one end of the primary side of the transformer TX;
  • a hysteresis bridge arm which is composed of MOS tubes Q3 and Q4 connected in series, and the connection node D of the two MOS tubes Q3 and Q4 is connected to the other end of the primary side of the transformer TX;
  • the input DC voltage Vin is applied between the connection node A of the MOS transistors Q1 and Q3 and the connection node B of the MOS transistors Q2 and Q4;
  • An output circuit is mainly composed of two rectifying MOS tubes Q5, Q6, an output inductor L2 and an output capacitor C; one end of the secondary side of the transformer TX is connected to the rectifying MOS tube Q5 and grounded; the other end of the secondary side of the transformer TX is connected to the rectifying MOS tube Grounding after Q6; the middle tap of the secondary side of the transformer TX (dividing the secondary side of the transformer TX into two coils equally) is connected to the series connected output inductor L2 and the output capacitor C and grounded;
  • the MOS transistors Q1 to Q6 can also be changed to other Switching device, such as IGBT (Insulated Gate Bipolar Transistor), the emitter of the IGBT is equivalent to the source of the MOS transistor, and the collector of the IGBT is equivalent to the drain of the MOS transistor .
  • IGBT Insulated Gate Bipolar Transistor
  • the MOS transistors Q1 to Q6 are both NMOS as an example.
  • the source of the MOS transistor Q1 is connected to the drain of the MOS transistor Q2 as a connection node C.
  • the source of the MOS transistor Q3 is connected to the drain of the MOS transistor Q4 as a connection node D.
  • the drain of the MOS transistor Q1 is connected to the drain of the MOS transistor Q3 as the connection node A.
  • the source of the MOS transistor Q2 is connected to the source of the MOS transistor Q4, and is connected to the node B and grounded.
  • the positive pole of the input DC voltage Vin is connected to the connection node A, and the negative pole is connected to the connection node B.
  • the transformer TX has only one winding on the primary side, and the secondary side of the transformer TX has an intermediate tap that evenly distributes the secondary winding.
  • One end of the secondary side of the transformer TX is connected to the drain of the rectifying MOS transistor Q5, and the other end of the secondary side of the transformer TX is connected to the drain of the rectifying MOS transistor Q6, and the sources of the rectifying MOS transistors Q5 and Q6 are grounded.
  • the tap of the secondary side of the transformer TX is connected to the series output inductor L2 and the output capacitor C and grounded. A load not shown is applied across the output capacitor C, that is, the load is connected in parallel with the output capacitor C.
  • FIG. 9 shows a specific implementation environment of the control method of the present invention, wherein the phase shift control circuit and FIG. 5 It's exactly the same, no longer telling.
  • AUIRS2191 is the driving chip of the primary MOSFET, and provides the external gate voltage for the MOS transistors Q1 ⁇ Q4, thereby controlling the turn-on or turn-off of these MOS transistors
  • UCC27322 is the driving chip of the secondary MOSFET, which is the MOS transistor Q5, Q6 provides an additional gate voltage to control the turn-on or turn-off of these MOS transistors
  • ISO7240 is an isolation chip for isolation of the primary and secondary sides of the transformer
  • UCC28950 is the control chip.
  • Figure 10 is a signal output waveform of the phase shift full bridge circuit of the present invention in the test environment shown in Figure 9.
  • Test conditions DC input voltage is 420V; DC output voltage is 10V; output current is 10A.
  • CH1 represents the primary voltage of the transformer and CH4 represents the primary current of the transformer.
  • CH1 obtained by the test is consistent with the V_TX obtained by the theoretical analysis in Fig. 6.
  • the CH4 obtained by the test is also consistent with the I_TX obtained by the theoretical analysis in Fig. 6.
  • the control method of the phase-shifted full-bridge circuit of the present invention controls the transformer TX through synchronous rectification (ie, both ends of the secondary winding of the transformer are grounded through a MOS tube or IGBT) during the process of switching from the energy transfer phase to the freewheeling phase.
  • the secondary side is short-circuited, so that the transformer TX has a certain amount of energy stored on the primary side leakage, which is used to solve the problem that the zero-voltage switching cannot be realized due to insufficient resonance energy at the light load in the control method of the conventional phase-shifted full-bridge circuit.
  • phase-shifted full-bridge circuit can omit the resonant inductor L1 on the primary side of the transformer TX and the two clamp diodes D1 and D2, thereby reducing system cost and reducing system volume.
  • the removed device is also inherently lossy, so the phase-shifted full-bridge circuit of the present invention can Improve the efficiency of the system.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

L'invention porte sur un circuit en pont complet à déphasage et sur son procédé de commande. Le procédé divise un rapport cyclique d'un circuit en pont complet à déphasage en 10 stades. OA, OB, OC, OD, OE et OF sont les tensions de grille externe des tubes MOS I à IV (Q1 - Q6) respectivement. Le procédé change simultanément l'augmentation de OE et OC à des première et seconde augmentations, et change simultanément l'augmentation de OF et OD à des première et seconde augmentations, amenant ainsi le circuit en pont complet à déphasage à réaliser une commutation douce dans des conditions de sous-charge. Dans un circuit en pont complet à déphasage appliquant le procédé, le côté primaire du transformateur est d'une structure en pont complet et le côté secondaire du transformateur est d'une structure de redressement synchrone. Le circuit omet l'inducteur de résonance et la diode de calage au côté primaire du transformateur, réduisant ainsi les coûts de système, réduisant le volume du système et améliorant l'efficacité du système.
PCT/CN2011/078150 2011-08-09 2011-08-09 Circuit en pont complet à déphasage et son procédé de commande WO2013020269A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104811081A (zh) * 2015-04-14 2015-07-29 汪水仿 恒定移相全桥软开关技术

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001339945A (ja) * 2000-05-26 2001-12-07 Sanken Electric Co Ltd 電力変換器
US20020172061A1 (en) * 2001-05-18 2002-11-21 Phadke Vijay Gangadhar Simple control circuit for synchronous rectifiers used in zvs phase shifted full bridge converter
CN1504014A (zh) * 2000-11-06 2004-06-09 艾利森公司 在同步整流变换器电路中减小反向电流的方法和电路
US20100054008A1 (en) * 2008-09-04 2010-03-04 Astec International Limited Inductorless Isolated Power Converters With Zero Voltage and Zero Current Switching
US20100232180A1 (en) * 2009-03-10 2010-09-16 Hitachi, Ltd. Power supply unit, hard disk drive and method of switching the power supply unit
CN102291002A (zh) * 2011-08-09 2011-12-21 联合汽车电子有限公司 移相全桥电路及其控制方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001339945A (ja) * 2000-05-26 2001-12-07 Sanken Electric Co Ltd 電力変換器
CN1504014A (zh) * 2000-11-06 2004-06-09 艾利森公司 在同步整流变换器电路中减小反向电流的方法和电路
US20020172061A1 (en) * 2001-05-18 2002-11-21 Phadke Vijay Gangadhar Simple control circuit for synchronous rectifiers used in zvs phase shifted full bridge converter
US20100054008A1 (en) * 2008-09-04 2010-03-04 Astec International Limited Inductorless Isolated Power Converters With Zero Voltage and Zero Current Switching
US20100232180A1 (en) * 2009-03-10 2010-09-16 Hitachi, Ltd. Power supply unit, hard disk drive and method of switching the power supply unit
CN102291002A (zh) * 2011-08-09 2011-12-21 联合汽车电子有限公司 移相全桥电路及其控制方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104811081A (zh) * 2015-04-14 2015-07-29 汪水仿 恒定移相全桥软开关技术

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