WO2013013956A3 - Schichtverbund aus einer schichtanordnung und einer elektrischen oder elektronischen komponente - Google Patents

Schichtverbund aus einer schichtanordnung und einer elektrischen oder elektronischen komponente Download PDF

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Publication number
WO2013013956A3
WO2013013956A3 PCT/EP2012/063224 EP2012063224W WO2013013956A3 WO 2013013956 A3 WO2013013956 A3 WO 2013013956A3 EP 2012063224 W EP2012063224 W EP 2012063224W WO 2013013956 A3 WO2013013956 A3 WO 2013013956A3
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WIPO (PCT)
Prior art keywords
layer
noble metal
arrangement
electrical
electronic component
Prior art date
Application number
PCT/EP2012/063224
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English (en)
French (fr)
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WO2013013956A2 (de
Inventor
Daniel Wolde-Giorgis
Andrea Feiock
Manfred Boehm
Thomas Kalich
Original Assignee
Robert Bosch Gmbh
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Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO2013013956A2 publication Critical patent/WO2013013956A2/de
Publication of WO2013013956A3 publication Critical patent/WO2013013956A3/de

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    • H—ELECTRICITY
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    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H01B1/02—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of metals or alloys
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131—Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1157—Using means for chemical reduction
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/12—Using specific substances
    • H05K2203/121—Metallo-organic compounds
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Laminated Bodies (AREA)
  • Powder Metallurgy (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

Die Erfindung betrifft einen Schichtverbund, wobei der Schichtverbund mindestens eine elektrische oder elektronische Komponente und eine Schichtanordnung aus mehreren Schichten umfasst. Die Schichtanordnung ist aus zumindest einer ersten Schicht gebildet, welche zumindest eine organische Metallverbindung und/oder ein Edelmetalloxid enthält, wobei die organische Metallverbindung und/oder das Edelmetalloxid bei einer Temperaturbehandlung des Schichtverbundes oder der Schichtanordnung in das zugrunde liegende elementare Metall und/oder Edelmetall umgewandelt werden. Ferner weist die Schichtanordnung zumindest eine an die erste Schicht angrenzende zweite Schicht auf. Kennzeichnend für die Erfindung ist, dass die zumindest zweite Schicht ein Reduktionsmittel enthält, mittels welchem die Reduktion der organischen Metallverbindung und/oder des Edelmetalloxids zu dem elementaren Metall und/oder Edelmetall bei einer Temperatur unterhalb der Sintertemperatur des elementaren Metalls und/oder Edelmetalls erfolgt. Insgesamt ist nach Abschluss der Temperaturbehandlung innerhalb des Schichtverbundes eine Sinterverbindung ausgebildet.
PCT/EP2012/063224 2011-07-22 2012-07-06 Schichtverbund aus einer schichtanordnung und einer elektrischen oder elektronischen komponente WO2013013956A2 (de)

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DE102011079660.6 2011-07-22
DE102011079660.6A DE102011079660B4 (de) 2011-07-22 2011-07-22 Schichtverbund aus einer Schichtanordnung und einer elektrischen oder elektronischen Komponente, eine Schaltungsanordnung diesen Schichtverbund enthaltend und Verfahren zu dessen Ausbildung

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US10002821B1 (en) 2017-09-29 2018-06-19 Infineon Technologies Ag Semiconductor chip package comprising semiconductor chip and leadframe disposed between two substrates

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US20080156398A1 (en) * 2006-12-28 2008-07-03 Yusuke Yasuda Bonding method and bonding material using metal particle
JP2008311371A (ja) * 2007-06-13 2008-12-25 Denso Corp 接合方法及び接合体

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EP1460644B1 (de) 2001-12-27 2007-07-25 Fujikura Ltd. Elektroleitfähige zusammensetzung, elektroleitfähige beschichtung und verfahren zur bildung einer elektroleitfähigen beschichtung
DE102007046901A1 (de) 2007-09-28 2009-04-09 W.C. Heraeus Gmbh Verfahren und Paste zur Kontaktierung von Metallflächen
DK2042260T3 (en) * 2007-09-28 2014-03-17 Heraeus Materials Tech Gmbh METHOD AND FIT FOR ESTABLISHING CONTACT BETWEEN METAL SURFACES
US20090142482A1 (en) * 2007-11-30 2009-06-04 Xerox Corporation Methods of Printing Conductive Silver Features
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US20080156398A1 (en) * 2006-12-28 2008-07-03 Yusuke Yasuda Bonding method and bonding material using metal particle
JP2008311371A (ja) * 2007-06-13 2008-12-25 Denso Corp 接合方法及び接合体

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