WO2013006026A1

WO2013006026A1 - A method for converting analog signal to digital signal using a successive approximation register analog to digital converter

Info

Publication number: WO2013006026A1
Application number: PCT/MY2012/000132
Authority: WO
Inventors: Tan Kong YEW; Ng Mei YEE
Original assignee: Mimos Berhad
Priority date: 2011-07-07
Filing date: 2012-06-22
Publication date: 2013-01-10
Also published as: MY158579A

Abstract

The present invention relates to a method for converting analog signal to digital signal using a successive approximation register analog to digital converter. The method allows the SAR-ADC (100) to go through a first iteration of bit cycling and then stores the most significant bits and monitor bits in a register of the SAR- ADC (100). The most significant bits are fixed for the subsequent iteration of bit cycling until a change has been detected to the monitor bits.

Description

A METHOD FOR CONVERTING ANALOG SIGNAL TO DIGITAL SIGNAL USING A SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER

FIELD OF INVENTION

The present invention relates to a method for converting analog signal to digital signal using a successive approximation register analog^' to digital converter (SAR-ADC).

BACKGROUND OF THE INVENTION

A successive approximation register analog to digital converter (SAR-ADC) converts an analog signal to a digital signal by applying a binary search algorithm to find the closest digital code that matches the analog signal. Initially, the most significant bit is set to,a logic high or , while the remaining bits are all set to a logic low or '0 The digital code is fed to a digital analog converter (DAC). Thereon, the DAC supplies an analog voltage equivalent of the digital code to an analog comparator for comparison with an analog input voltage sampled by a sample and hold circuit. If the analog voltage equivalent exceeds the analog input voltage, the analog comparator causes the successive approximation register to reset the most significant bit to 'Ο'; otherwise, the bit is left at . Thereon, the next bit down is set to Ί ' and the same test is done, continuing this binary search all the way down to a least significant bit. Once this is done, the resulting code is the digital approximation of the sampled input voltage and is finally output by the successive approximation register. During the process of setting and resetting of each bit, a significant amount of power is used and wasted due to the charging and discharging of the capacitors that make up the DAC. The power wastage is made worse when the charging and discharging of the large capacitors are done every time a sample is read. This power wastage is particularly significant in the bit cycling of the most significant bit whereby a significant amount of power is wasted as the most significant bit corresponds to the largest capacitor in the array of capacitors of the DAC. Setting a SAR bit to Ί ' means that the capacitor will be charged to a reference voltage. However, if the output of the analog comparator dictates that the bit should be reset to 'Ο', then the charged capacitor will have to be discharged, wasting the initial charge that was used. In addition to that, the charging and discharging of capacitors also lead to higher Differential Non Linearity (DNL) error that would degrade the performance of the SAR-ADC. Therefore, there is a need to provide a method of analog to digital conversion of a successive approximation register analog to digital converter (SAR-ADC) that reduces power wastage and minimizes DNL error during charging and discharging of DAC's capacitors. SUMMARY OF INVENTION

The present invention provides a method for converting an analog signal to a digital signal using a successive approximation register analog to digital converter (100). The method comprises the steps of (a) selecting a first set of binary weighted capacitors of a digital to analog converter as most significant bits, a second set of binary weighted capacitors of the digital to analog converter as monitor bits and a third set of binary weighted capacitors of the digital to analog converter as least significant bits; (b) sampling an analog signal to be converted to a digital signal; (c) supplying a first sampled analog input voltage (V|_N) to an analog comparator (120); (d) performing a first iteration of bit cycling operation for all digital bits (bit-0 to bit-n- 1); (e) providing the digital code from the first iteration of bit cycling operation in a SAR-ADC register as an output of the first sampled analog input voltage; (f) storing and fixing the most significant bits in the SAR-ADC register; (g) storing the monitor bits in the SAR-ADC register; (h) sampling an analog signal to be converted to a digital signal; (i) supplying a subsequent sampled analog input voltage (V|_N) to the analog comparator (120); (j) performing a subsequent iteration of bit cycling operation for the monitor bits and the least significant bits; (k) comparing the monitor bits from the subsequent iteration with the monitor bits stored in the SAR-ADC register; (I) providing the digital code from the subsequent iteration of bit cycling operation in a SAR-ADC register as an output of the subsequent sampled analog input voltage if the monitor bits from the subsequent iteration are the same as the monitor bits stored in the SAR-ADC register; and (m) repeating steps (d) to (k) if the monitor bits from the subsequent iteration differ from the monitor bits stored in the SAR-ADC register. Preferably, the most significant bits is a set of capacitors having high binary weighted values, the monitor bits is a set of capacitors having medium binary weighted values, and the least significant bits is a set of capacitors having low binary weighted values.

Preferably, the total number of capacitors selected for the most significant bits, monitor bits and least significant bits is equal to n, wherein n is number of resolution bits of the successive approximation register analog to digital converter used.

Preferably, during the subsequent iteration of bit cycling operation, the capacitors of the most significant bits remain switched to either a reference voltage (VREF) or ground based on the first iteration of the bit cycling operation. Advantageously, the present invention reduces power wastage by a SAR-

ADC during analog signal to digital signal conversion.

Advantageously, the present invention minimizes Differential Non Linearity (DNL) error of a SAR-ADC.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 shows a block diagram of a successive approximation register analog to digital converter or SAR-ADC (100).

FIG. 2 shows a schematic of a 12-bit digital to analog converter (140) of a successive approximation register analog to digital converter or SAR-ADC (100).

FIG. 3 shows a flow chart of a method of analog to digital conversion according to an embodiment of the present invention. DESCRIPTION OF THE PREFFERED EMBODIMENT

A preferred embodiment of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well known functions or constructions are not described in detail since they would obscure the description with unnecessary detail.

FIG. 1 shows a block diagram of a successive approximation register digital to analog converter or SAR-ADC (100). The SAR-ADC (100) comprises of a sample and hold circuit (110), an analog comparator (120), a successive approximation register circuit (130), and a digital to analog converter or DAC (140).

The sample and hold circuit (110) is used to sample an input voltage (V_!N) from an analog signal which is to be converted to a digital signal. The sample and hold circuit (110) is connected to an input of the analog comparator (120).

The analog comparator (120) is used to compare an output voltage from the DAC (140) with the input voltage (V,_N) from the sample and hold circuit (110). An output of the analog comparator (120) is connected to an input of the successive approximation register circuit (130) to provide the comparison result.

The successive approximation register circuit (130) is configured to provide an approximate digital code of the input voltage (V|_N) to the DAC (140). Moreover, the digital code is stored in a register of the SAR-ADC (100) as an output of the analog to digital conversion. An output of the successive approximation register circuit (130) is connected to an input of the DAC (140).

The DAC (140) is configured to provide the analog voltage comparator (120) with an analog voltage equivalent (V_DAC) of the digital code from the successive approximation register circuit (130) for comparison with the input voltage (V|_N). The DAC (140) is added or subtracted with a binary weighted voltage based on the analog comparator (120) output in each bit cycle. Hence, the DAC (140) tries to estimate the value of each analog signal through successive approximations and comparisons. The DAC (140) comprises of an array of individually switched binary-weighted capacitors connected in parallel wherein a connection of each capacitor is connected to an input of the analog comparator (120), whereas another connection of each capacitor is selectively connected to either a reference voltage (V_REF) or ground (V_ss) through a switch. The binary weighted capacitors are divided into three sets of capacitors. A first set of capacitors is defined as most significant bits or MSBs which relates to the capacitors having high binary weighted values. A second set of capacitors is defined as monitor bits which relates to the capacitors having medium binary weighted values. A third set of capacitors is defined as least significant bits or LSBs which relates to the capacitors having low binary weighted values. The total number of capacitors selected for the MSBs, monitor bits and LSBs must be equal to n, where n is number of resolution bits.

FIG. 2 shows a schematic of a 12-bit DAC (140) having three sets of capacitors defined as MSBs, monitor bits and LSBs. The LSBs comprise of binary weighted capacitors of CO to C3 wherein the capacitance of capacitor CO is C, the capacitance of capacitor C1 is 2C, the capacitance of capacitor C2 is 4C, and the capacitance of capacitor C3 is 8C. The monitor bits comprise of binary weighted capacitors of C4 to C7 wherein the capacitance of capacitor C4 is 16C, the capacitance of capacitor C5 is 32C, the capacitance of capacitor C6 is 64C, and the capacitance of capacitor C7 is 128C. The MSBs comprise of binary weighted capacitors of C8 to C11 wherein the capacitance of capacitor C8 is 256C, the capacitance of capacitor C9 is 512C, the capacitance of capacitor C10 is 1024C, and the capacitance of capacitor C11 is 2048C. The capacitors (C0-C11) are connected in parallel wherein a connection of each capacitor is connected to an input of the analog comparator (120), whereas another connection of each capacitor is selectively connected to either a reference voltage (V_REF) or ground (Vss) through a switch (S0-S11). The DAC (140) also includes a capacitor C with a capacitance of C. The capacitor C is connected in parallel with capacitors C0-C11 , wherein a connection of the capacitor C is connected to the input of the analog comparator (120) and another connection of the capacitor C is connected to ground (V_ss).

A method for a SAR-ADC (100) to convert an analog signal to a digital signal is provided herein below. The method allows the SAR-ADC (100) to go through a first iteration of bit cycling and then stores the most significant bits in a register of the SAR-ADC (100). The most significant bits are fixed for the subsequent iteration of bit cycling until a change has been detected to the monitor bits. Thus, this reduces the power consumed during the charging and discharging of the capacitors of the most significant bits. Below is an example of a calculated power saved for charging the most significant bits of four capacitors having the highest binary weighted values in a 12-bit SAR-ADC.

W = ½ x C x V², where C = capacitance, V = Voltage

= ½ x (2¹¹ + 2¹⁰ + 2⁹ + 2⁸)*C x V²

= ½ x 3840C x V²

= 1 .92 nJoule (assuming C = 1 pF, V = 1 V)

Percentage of power saved = (3840/4096)*100% = 93.75%

Referring now to FIG. 3, there is shown a flow chart of a method for converting an analog signal to a digital signal using an n-b^'A SAR-ADC (100). Initially, the most significant bits, the monitor bits and the least significant bits are selected and defined.

Thereon, as in step 301 , an analog signal to be converted to a digital signal is sampled by a sample and hold circuit (1 10). The sample and hold circuit (1 10) supplies a first sampled analog input voltage (V_!N) to the analog comparator (120) for comparison with the output voltage (VDAC) of the DAC (140) during the bit cycling operation. A first iteration of bit cycling operation is performed for all digital bits (bit-0 to bit-n-i) as in step 302. The bit cycling operation includes switching the switch of the most significant bit capacitor (G_n-i) to connect it to V_REF while the rest of the capacitors are connected to ground, and thereon, comparing the output voltage (V_DAC) of the DAC (140) with the first sampled analog input voltage V_!N. If V_DAC is equal or less than V|_N, capacitor C_n-i remains connected to V_REF which translates to setting bit- ?- ί as a logic high or . Otherwise, the switch for capacitor C_n-1 is switched to ground which translates to setting bit-n-i as a logic low or Ό'. These steps are repeated for all other bits in decreasing order until bit-0 or capacitor CO is reached. After the bit cycling operation has been performed, the digital code is stored in a SAR-ADC register which is the digital code for the first sampled analog input voltage (V|_N). Next, as in step 303, the most significant bits are stored and fixed in the SAR- ADC register for the subsequent sampled input voltage. Thus, for the subsequent sampled input voltage (V|_N), the capacitors of the most significant bits remain switched to either V_REF or ground based on the first iteration of the bit cycling operation.

In step 304, the monitor bits are stored in the SAR-ADC register for the subsequent sampled input voltage. Thereon, as in step 305, a subsequent sampled analog input voltage (V|_N) is supplied to the analog comparator (120) by the sample and hold circuit (110) for comparison with V_DAc during the bit cycling operation.

A subsequent iteration of bit cycling operation is performed for only the monitor bits and the least significant bits as in step 306. The most significant bits are fixed based on the result from the first iteration of the bit cycling operation.

After the bit cycling operation has been performed, as in step 307, the digital code of the monitor bits from the subsequent iteration are compared to the monitor bits stored in the SAR-ADC register. If the monitor bits from the subsequent iteration are the same as the monitor bits stored in the SAR-ADC register, then the monitor bits and the least significant bits are stored in the SAR-ADC register as in step 308.

However, if the monitor bits from the subsequent iteration differ from the monitor bits stored in the SAR-ADC register, steps 302 to 307 are repeated to convert the subsequent sampled analog input voltage to digital signal.

For a further understanding of this invention, a specific example is provided herein below for illustration purpose only and is not intended to be limiting unless otherwise specified.

A 12-bit SAR-ADC (100) is used as an exemplary to the method for converting an analog signal to a digital signal. The SAR-ADC (100) includes the DAC (140) of FIG. 2 wherein bit-8 to bit-11 which includes capacitors C8 to C11 are defined as the most significant bits, bit-4 to bit-7 which includes capacitors C4 to C7 are defined as the monitor bits, and bit-0 to bit-3 which includes capacitors CO to C3 are defined as the least significant bits. A reference voltage (V_REF) of 5.0V is supplied to the DAC (140). A first sampled analog input voltage (V|_N) is provided as 3.0V to the analog comparator (120). A first iteration of bit cycling operation is performed for all the digital bits (bit-0 to bit-1 1 ). The first iteration of bit cycling operation includes the steps of switching switch S11 to connect capacitor C11 to V_REF while the rest of the capacitors (C10-C0) are connected to ground, and thereon, comparing the V_DAC with the first sampled analog input voltage V|_N. If V_DAC is equal or less than V|_N, capacitor C11 remains connected to V_REF which translates to setting bit-1 1 as a logic high or . Otherwise, switch S11 is switched to V_Ss which translates to setting bit-1 1 as a logic low or Ό'. These steps are repeated for all other bits in decreasing order until bit-0 or capacitor CO is reached. As a result of the first iteration of the bit cycling operation, the SAR-ADC register outputs the digital code as Ί 001 1 001 1001 ' which represents VIM of 3.0V. The most significant bits of '1001 ' are stored and fixed for the next subsequent input voltage. The monitor bits of '1001 ' are also stored in the SAR- ADC register for the next subsequent input voltage. Thereon, a second sampled analog input voltage (V_!N) of 2.99V is provided by the sample and hold circuit (110). The DAC performs a second iteration of bit cycling operation for only bit-0 to bit-7. The most significant bits are fixed based on the result from the first iteration of the bit cycling operation. The second iteration of bit cycling operation includes the steps of switching switch S7 to connect capacitor C7 to V_REF while capacitors C6 to CO are connected to ground, and thereon, comparing the V_DAc with the second sampled analog input voltage V_!N. If V_DAC is equal or less than V|_N, capacitor C7 remains connected to V_REF which translates to setting bit-7 as a logic high or . Otherwise, switch S7 is switched to V_SS which translates to setting bit-7 as a logic low or 'Ο'. These steps are repeated for all other bits in decreasing order until bit-0 or capacitor CO is reached. As a result, the approximated digital code by the SAR-ADC (100) is Ί 001 1001 0001 '. The monitor bits from the second iteration of bit cycling are compared with the monitor bits from the first iteration of bit cycling. Since there are no changes on the monitor bits, the approximated digital code of Ί 001 1001 0001 ' is stored in the SAR-ADC register and provided as an output of the digital code converted from the analog input voltage (V|_N) of 2.99V. A third sampled analog input voltage (V|_N) of 4.0V is then provided by the sample and hold circuit (110). The DAC (140) performs a third iteration of bit cycling operation for only bit-0 to bit-7. The most significant bits are fixed based on the result from the first iteration of the bit cycling operation. The third iteration of bit cycling operation includes the steps of switching switch S7 to connect capacitor C7 to V_REF while capacitors C6 to CO are connected to ground, and thereon, comparing the V_DAC with the third sampled analog input voltage V_!N. If V_DAC is equal or less than V|_N, capacitor C7 remains connected to V_REF which translates to setting bit-7 as a logic high or . Otherwise, switch S7 is switched to V_SS which translates to setting bit-7 as a logic low or 'Ο'. These steps are repeated for all other bits in decreasing order until bit-0 or capacitor CO is reached. As a result, the approximated digital code is "1001 1 1 1 1 1 1 1 1 '. The monitor bits from the second iteration of bit cycling are compared with the stored monitor bits.-Since the monitor bits differ from the stored monitor bits, a bit cycling operation is performed again for all the digital bits (bit-1 1 to bit-0). As a result, an approximation digital code of '1 1 10 01 10 01 10' is obtained and stored in the SAR-ADC register and provided as an output of the digital code converted from the analog input voltage (V|_N) of 4.0V. The most significant bits of ' 0' are now stored and fixed for the next subsequent input voltage. The monitor bits of '01 10' are also stored in the SAR-ADC register for the next subsequent input voltage.

From the abovementioned description, it is appreciated that the method for converting an analog signal to a digital signal by using a successive approximation register digital to analog converter can be applied in biomedical and agricultural applications whereby analog signals to be converted to digital signals are changing gradually which allows the most significant bits to be fixed until a change has been detected in the monitor bits.

While embodiments of the invention have been illustrated and described, it is not intended that these embodiments illustrated and describe all possible forms of the invention. Rather, the words used in the specifications are words of description rather than limitation and various changes may be made without departing from the scope of the invention.

Claims

1. A method for converting an analog signal to a digital signal using a successive approximation register analog to digital converter (100) is characterised by the steps of:

a) selecting a first set of binary weighted capacitors of a digital to analog converter as most significant bits, a second set of binary weighted capacitors of the digital to analog converter as monitor bits and a third set of binary weighted capacitors of the digital to analog converter as least significant bits;

b) sampling an analog signal to be converted to a digital signal; c) supplying a first sampled analog input voltage (V_!N) to an analog comparator (120);

d) performing a first iteration of bit cycling operation for all digital bits (bit- 0 to bit-n-f);

e) providing the digital code from the first iteration of bit cycling operation in a SAR-ADC register as an output of the first sampled analog input voltage;

f) storing and fixing the most significant bits in the SAR-ADC register; g) storing the monitor bits in the SAR-ADC register;

h) sampling an analog signal to be converted to a digital signal; i) supplying a subsequent sampled analog input voltage (V,_N) to the analog comparator (120);

j) performing a subsequent iteration of bit cycling operation for the monitor bits and the least significant bits;

k) comparing the monitor bits from the subsequent iteration with the monitor bits stored in the SAR-ADC register;

I) providing the digital code from the subsequent iteration of bit cycling operation in a SAR-ADC register as an output of the subsequent sampled analog input voltage if the monitor bits from the subsequent iteration are the same as the monitor bits stored in the SAR-ADC register; and

m) repeating steps (d) to (k) if the monitor bits from the subsequent iteration differ from the monitor bits stored in the SAR-ADC register.

2. The method as claimed in step (a) of claim 1 , wherein the most significant bits is a set of capacitors having high binary weighted values, the monitor bits is a set of capacitors having medium binary weighted values, and the least significant bits is a set of capacitors having low binary weighted values.

3. The method as claimed in step (a) of claim 1 , wherein the total number of capacitors selected for the most significant bits, monitor bits and least significant bits is equal to n, wherein n is number of resolution bits of the successive approximation register analog to digital converter (100).

4. The method as claimed in step (j) of claim 1 , wherein the capacitors of the most significant bits remain switched to either a reference voltage (V_REF) or ground based on the first iteration of the bit cycling operation.