WO2013095085A1

WO2013095085A1 - An analog to digital converter

Info

Publication number: WO2013095085A1
Application number: PCT/MY2012/000170
Authority: WO
Inventors: Mei Yee Ng; Kong Yew Tan
Original assignee: Mimos Berhad
Priority date: 2011-12-20
Filing date: 2012-06-29
Publication date: 2013-06-27
Also published as: MY165440A

Abstract

The present invention relates to an analog to digital converter (100). The analog to digital converter (100) resolves the most significant bits by using asynchronous binary search method and the remaining bits by using charge redistribution method. The analog to digital converter (100) comprises of a sample and hold circuit (110), an analog comparator (120), a successive approximation register (130), a binary tree of comparators (140) and a digital to analog converter or DAC (150).

Description

AN ANALOG TO DIGITAL CONVERTER

FIELD OF INVENTION

The present invention relates to an analog to digital converter and more particularly, to a successive approximation register analog to digital converter (SAR- ADC).

BACKGROUND OF THE INVENTION

In a successive approximation analog to digital converter (SAR-ADC) based on charge redistribution, a binary search is performed by repeatedly charging and discharging an array of binary weighted capacitors to convert an analog signal to a digital representation signal. However, this results in large power consumption during the data conversion. Moreover, the accuracy of the conversion can be severely affected due to poor matching of the capacitors.

In another successive approximation analog to digital converter (SAR-ADC) based on asynchronous binary search as disclosed in European Patent No. 2,107,683, a binary tree of comparators is used for an analog to digital conversion. Each of the comparators has a predetermined threshold which is fed with a same input signal. However, this method relies entirely on binary search with comparators alone. At higher resolution of conversion, more comparators will be required and even more predetermined threshold voltages need to be generated, which increases the power consumption of the SAR-ADC. Therefore, there is a need to provide a successive approximation analog to digital converter (SAR-ADC) that consumes less power during conversion and provides better conversion accuracy.

SUMMARY OF INVENTION

The present invention provides an analog to digital converter (100). The analog to digital converter (100) comprises of a sample and hold circuit (110), an analog comparator (120), a successive approximation register (130) connected to the analog comparator (120), and a digital to analog converter (150) connected to the analog comparator (120) and to the successive approximation register (130). The analog to digital converter (100) is characterised in that it further includes a plurality of comparators (140) to resolve a number of most significant bits and to select a reference voltage (V_REF2) for the digital to analog converter (150), wherein each comparator (140) has a predetermined threshold voltage and an output controlling at least two other comparators (140), and wherein each comparator is connected to the sample and hold circuit (110) and to the successive approximation register (130); the digital to analog converter (150) includes an array of binary weighted capacitors to resolve the remaining bits, wherein an output of the digital to analog converter (150) is connected through a switch to the reference voltage (V_REF₂) selected by the plurality of comparators (140); and the analog comparator (120) is further connected to ground.

Preferably, the analog comparator (120) is used to compare an output voltage (VDAC) from the digital to analog converter (150) with ground (V_SS) or 0V, and wherein the output voltage (V_DAC) of the digital to analog converter (150) is based on the equation below:

where V_REF2 is the reference voltage selected by the plurality of comparators (140), V|_N is a sampled input voltage from the sample and hold circuit (110), N is a number of bits of the analog to digital converter (100), M is a number of bits assigned as the most significant bits, D_n is bit value for bit-n, and V_REF3 is a fixed reference voltage for the digital to analog converter (150).

Preferably, the number of comparators (140) is determined by 2 - 1 , wherein M is a number of bits assigned as the most significant bits.

Preferably, an output of each comparator (140) is connected to an enable input of at least two other comparators (140) to activate either one of the at least two connected comparators (140) during conversion.

Preferably, the plurality of comparators (140) selects the reference voltage (V_REF2) for the DAC (150) by selecting a multiplier, k based on the resolved most significant bits, and wherein V_REF2 is based on the equation below:

VREF∑ - k ^* VREF1 where k is a multiplier selected based on the binary search result of the most significant bits, and V_REF1 is a reference voltage supplied for the plurality of comparators (140). A method for converting an analog input voltage (V_iN) to a digital code using an A/-bit analog to digital converter (100) is also provided in the present invention. The method is characterised by the steps of performing asynchronous binary search by sequentially comparing the input voltage (V,_N) with a predetermined threshold voltage based on a first reference voltage (V_REFI) by using a plurality of comparators (140); determining the digital code for M most significant bits, wherein M is a number of bits; determining and supplying a second reference voltage (V_REF2) for a digital to analog converter (150) based on the result of M most significant bits; performing a bit cycling operation using the digital to analog converter (150) for the remaining bits (Λ/- M); determining the digital code for the remaining bits; and storing the digital code for the analog input voltage (V_!N) in the successive approximation register (130).

Preferably, the plurality of comparators (140) selects the second reference voltage (V_REF2) for the digital to analog converter (150) by selecting a multiplier, k based on the resolved most significant bits, and wherein V_REF2 is based on the equation below:

V - k * V

where k is a multiplier selected based on the binary search result of the most significant bits, and V_REF is the first reference voltage supplied for the plurality of comparators (140).

Preferably, the bit cycling operation includes the steps of: (a) connecting the second reference voltage (V_REF2) to an output of the digital to analog converter (150); (b) connecting a highest order bit capacitor (C_w-M-i) to a third reference voltage (V_REF3) and connecting the rest of the capacitors of the digital to analog converter (150) to the second reference voltage (V_REF2); (c) comparing an output voltage (V_DAC) of the digital to analog converter (150) with ground (V_SS), wherein if V_DAC is equal or less than V_ss, capacitor C_N._M-i remains connected to V_REF3 which translates to setting b^'A-(N-M-l) as a logic high or , and wherein if V_DAC is greater than V_Ss, capacitor C is connected to ground (V_Ss); and repeating steps (b) and (c) for all other bits in decreasing order until b^'it-0 or capacitor CO is reached. Advantageously, the present invention reduces power consumption by a SAR-ADC during analog signal to digital signal conversion. Advantageously, the present invention reduces silicon area of a SAR-ADC.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 shows a block diagram of a successive approximation register analog to digital converter or SAR-ADC (100) according to an embodiment of the present invention.

FIGS. 2 show a schematic diagram of a binary tree of comparators (140) of the SAR- ADC (100) of FIG. 1.

FIGS. 3 show a schematic diagram of a digital to analog converter (150) of the SAR- ADC (100) of FIG. 1.

FIG. 4 shows a flow chart of a method of analog to digital conversion using SAR- ADC (100) of FIG. 1. DESCRIPTION OF THE PREFFERED EMBODIMENT

A preferred embodiment of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well known functions or constructions are not described in detail since they would obscure the description with unnecessary detail.

FIG. 1 shows a block diagram of a successive approximation register digital to analog converter or SAR-ADC (100). The SAR-ADC (100) resolves the most significant bits by using asynchronous binary search method and the rest of the bits by using charge redistribution method. The SAR-ADC (100) comprises of a sample and hold circuit (110), an analog comparator (120), a successive approximation register (130), a binary tree of comparators (140) and a digital to analog converter or DAC (150).

The sample and hold circuit (110) is used to sample an input voltage (V,_N) from an analog signal which is to be converted to a digital signal. The sample and hold circuit (110) is connected to an input of the binary tree of comparators (140).

The analog comparator (120) is used to compare an output voltage (V_DAC) from the DAC (150) with ground (V_ss) or 0V. An output of the analog comparator (120) is connected to an input of the successive approximation register (130) to provide the comparison result.

The successive approximation register (130) receives the digital code for the most significant bits from the binary tree of comparators (140) and provides an approximate digital code for the remaining bits to the DAC (150). When the conversion has been completed, the successive approximation register (130) stores the digital code and indicates end of conversion through an output of the successive approximation register (130). The binary tree of comparators (140) is used to determine the most significant bits by using asynchronous binary search. The number of comparators (140) used is determined by 2^M - 1, wherein M is the number of bits assigned as the most significant bits. As an example, if 3 bits are assigned as the most significant bits, a binary tree of 7 comparators (140) is used. Each comparator (140) has a predetermined threshold voltage which is compared to the input voltage (V,_N) and an enable input to activate the comparator (140). The comparators (140) are connected in a binary tree structure, wherein the output of each comparator (140) is connected to the enable input of two comparators and thus, enabling either one of the two connected comparators (140) during conversion. Each hierarchical layer of the binary tree of comparators (140) defines a bit of the digital code. The result of the asynchronous binary search is used to select a second reference voltage (V_REF2) for the DAC (150).

The DAC (150) is used to determine the remaining bits by using charge redistribution, wherein the DAC (150) is configured to provide the analog voltage comparator (120) with an analog voltage equivalent (V_DAC) of the digital code for the remaining bits from the successive approximation register (130) for comparison with ground (V_Ss). The analog voltage equivalent (V_DAc) is equated based on the equation below:

where V_REF2 is the second reference voltage, V|_N is the sampled input voltage, N is the number of bits of the SAR-ADC (100), M is the number of bits assigned as the most significant bits, D_n is bit value for bit-n, and V_REF3 is a fixed reference voltage for the DAC (150) which is calculated by 2^W"M/2^w*l _REFi.

The DAC (150) comprises of an array of individually switched binary-weighted capacitors. The binary weighted capacitors are connected in parallel wherein a connection of each capacitor is connected to an input of the analog comparator (120), whereas another connection of each capacitor is selectively connected to either ground (V_Ss), a third reference voltage (V_REF3), or input voltage (V,_N) through a switch. The input of the analog comparator (120) is also connected to the second reference voltage (V_REF2) through a switch. The second reference voltage (V_REF2) is selected by the binary tree of comparators (140), wherein the V_REF2 is based on the equation below:

V - * V where k is a multiplier selected based on the binary search result of the most significant bits, and V_REFi is a first reference voltage. As an example, Table 1 shows the multiplier, k value based on the binary search result of three most significant bits (bit-9 to bit-1 1). Table 1

FIGS. 2 show an exemplary schematic diagram of a binary tree of comparators (140) to determine three most significant bits (bit-9 to bit-1 1) by using asynchronous binary search. The result of the asynchronous binary search is also used to select the second reference voltage (V_REF2) for the DAC (140). The binary tree of comparators (140) comprises of 7 dynamic comparators (COMPO to COMP6). The comparators (COMPO to COMP6) are supplied with a first reference voltage (V_REF ) for comparing with the input voltage (V|_N). Comparator COMPO compares the input voltage (V,_N) with a first reference voltage divided by 2 or V_REFI/2 and outputs a signal to enable comparator COMP1 or comparator COMP2. Comparator COMP1 compares the input voltage (V,_N) with the first reference voltage divided by 4 (V_REF1/4) and outputs a signal to enable comparator COMP3 or comparator COMP4. Comparator COMP2 compares the input voltage (V|_N) with a threshold value of 3V_REF1/4 and outputs a signal to enable comparator COMP5 or comparator COMP6. Comparator COMP3 compares the input voltage (V|_N) with a threshold value of V_REF1/8 and selects a voltage of either 0.75V_REF1 or 0.875V_REF1 as the second reference voltage (V_REF2). Comparator COMP4 compares the input voltage (V|_N) with a threshold value of 3V_REF1/8 and selects a voltage of either 0.5V_REF1 or 0.625V_REF as the second reference voltage (V_REF2). Comparator COMP5 compares the input voltage (V|_N) with a threshold value of 5V_REF /8 and selects a voltage of either 0.25V_REFi or 0.375V_REFi as the second reference voltage (V_REF2). Comparator COMP6 compares the input voltage (V_!N) with a threshold value of 7V_REFi/8 and selects a voltage of either 0 or 0.125V_REFI as the second reference voltage (V_{RE 2}). Each hierarchical layer of the binary tree of comparators defines a bit of the digital code, wherein comparator COMPO defines bit-1 1 , comparators COMP1 and COMP2 define bit-10, and comparators COMP3 to COMP6 define bit-9.

Referring now to FIG. 3, there is shown an exemplary schematic diagram of a DAC (150) to determine the remaining bits (bit-0 to bit-8) by using charge redistribution. The DAC (150) is connected to the binary tree of comparators as shown in FIG. 2. The DAC (150) comprises of 9 binary weighted capacitors (CO to C8), wherein the capacitance of capacitor CO is C, the capacitance of capacitor C1 is 2C, the capacitance of capacitor C2 is 4C, the capacitance of capacitor C3 is 8C, the capacitance of capacitor C4 is 16C, the capacitance of capacitor C5 is 32C, the capacitance of capacitor C6 is 64C, the capacitance of capacitor C7 is 128C, and the capacitance of capacitor C8 is 256C. The capacitors (C0-C8) are connected in parallel wherein a connection of each capacitor is connected to an input of the analog comparator (120), whereas another connection of each capacitor is selectively connected to either ground (V_Ss), a third reference voltage (V_REF3), or input voltage (V|_N) through a switch (S0-S8). In addition to that, a capacitor C with a capacitance of C is also connected in parallel with capacitors C0-C8, wherein a connection of the capacitor C is connected to the input of the analog comparator (120) and another connection of the capacitor C is connected to ground (V_Ss). The input of the analog comparator (120) is also connected to the second reference voltage (V_REF2) through a switch (S20). The second reference voltage (V _EF2) is selected by the binary tree of comparators (COMPO to COMP6) with a voltage of either 0, 0.125V_REFi, 0.25V_REF1 , 0.375V_REF1, 0.5V_REFi, 0.625V_REF1, 0.75V_REF1 or 0.875V_REF1.

By resolving only 9 bits out of 12 bits using charge redistribution method, this allows the largest binary weighted capacitor size to have a capacitance of 256C instead of 2048C and thereby, reducing the ratio of the capacitors. Moreover, this results in an improved capacitor matching and accuracy. The total capacitance that the reference voltage needs to supply is also much smaller which is 512C instead of 4096C and thus, reduces the power consumption of the DAC (150). Below is an example of a calculated power saved (W) by the DAC (150) of FIG. 3 with C = 1 pF. W = ½ x C x V2, where C = Capacitance, V = Voltage = ½ x (2 ¹ x 2¹⁰ x 2⁹)C x V²

= 1.8nJoule

Percentage of energy saved = (3584/4096)*100% = 87.5%

Besides saving power, it also saves silicon area since the amount of capacitors used now would be 29 pF instead of 212 pF, which translates to a total of 87.5% reduction in silicon area. Referring now to FIG. 4, there is shown a flow chart of a method for converting an analog signal to a digital signal using an A/-bit SAR-ADC (100) of FIG. 1 , wherein N is number of resolution bits. Initially, as in step 301 , an analog signal to be converted to a digital signal is sampled by a sample and hold circuit (1 10). The sampled analog input voltage (V,_N) is supplied to the binary tree of comparators (140) and the DAC (150).

Thereon, as in step 302, the M-most significant bits are resolved by asynchronous binary search using the binary tree of comparators (140). The asynchronous binary search includes activating the highest order bit comparator (COMP_N-1) to compare the input voltage V|_N with V_REF1/2 while the rest of the comparators are deactivated. If V_REFI/2 is equal or less than V,_N, comparator COMPN-I outputs to set b^'A-(N-1) as a logic high or '1 ' and thus, activating another comparator having a higher threshold voltage connected to comparator COMP_N-1. Otherwise, comparator COMP_N-i outputs to set b t-(N-1) as a logic low or '0' and thus, activating another comparator having a lower threshold voltage connected to comparator COMP_N-i . These steps are repeated for all other bits in decreasing order until bit-(/V-M). As a result, the digital code for the M-most significant bits is determined and stored in the successive approximation register (130). Thereon, the second reference voltage is selected by using the result of the binary search from the binary tree of comparators (140) as in step 303, wherein the V_REF2 is based on the equation below:

½?EF2 ⁼ k * VREF where k is a multiplier selected based on the binary search result of the most significant bits, and V_REF is a first reference voltage. In step 304, the remaining bits are resolved by performing a bit cycling operation based on charge redistribution of the binary weighted capacitors of the DAC (150). The bit cycling operation includes switching the switch to connect V_REF2 to the input of the analog comparator (120) and switching the switch of the highest order bit capacitor (C_N._M-i) to connect the capacitor (C_N._M-i) to V_REF3 while the rest of the capacitors are connected to ground, and thereon, comparing the output voltage (VDAC) of the DAC (150) with ground (V_Ss)- The analog voltage equivalent (V_DAc) is equated based on the equation below:

where V_REF2 is the second reference voltage, V_!N is the sampled input voltage, N is the number of bits of the SAR-ADC (100), M is the number of bits assigned as the most significant bits, D_n is bit value for bit-n, and V_REF3 is a fixed reference voltage for the DAC (150) which is calculated by 2^W",72^W*V_REFJ. If V_DAC is equal or less than V_ss, capacitor C_N._M-i remains connected to V_REF3 which translates to setting b^'A-(N-M-l) as a logic high or Ί '. Otherwise, the switch for capacitor C_N.M-I is switched to ground (Vss) which translates to setting bit-(N-M-l) as a logic low or Ό'. These steps are repeated for all other bits in decreasing order until bit-0 or capacitor CO is reached.

After the bit cycling operation has been completed, the digital code for the remaining bits is stored in the successive approximation register (130) which completes the digital code for the sampled analog input voltage (V|_N) as in step 305. Moreover, the successive approximation register (130) indicates end of conversion through its output.

For a further understanding of this invention, a specific example is provided herein below for illustration purpose only and is not intended to be limiting unless otherwise specified.

A 12-bit SAR-ADC (100) is used as an exemplary to the method for converting an analog signal to a digital signal. The SAR-ADC (100) includes the binary tree of comparators (140) of FIG. 2 and the DAC (150) of FIG. 3, wherein three most significant bits are resolved using asynchronous binary search and the remaining bits are resolved using charge redistribution. A first reference voltage (VREFI) of 5.0V is supplied to the binary tree of comparators (140), a third reference voltage (V_REF₃) of 0.625V is supplied to the DAC (150) and a sampled analog input voltage (V,_N) is provided as 3.0V.

The three most significant bits are resolved by asynchronous binary search using the binary tree of comparators (COMPO to COMP6). The asynchronous binary search is initiated by activating comparator COMPO to compare V|_N = 3.0V with VREFI 2 = 2.5V while the rest of the comparators (COMP1 to COMP6) are deactivated. Since V_REF1/2 is lesser than V|_N, comparator COMPO outputs to set bit- 11 as a logic high or '1 ' and thus, activating comparator COMP1 while the rest of the comparators COMP2 to COMP6 are still deactivated. Thereon, comparator COMP1 compares V,_N = 3.0V with 3V_REF /4 = 3.75V. Since 3V_REF /4 is higher than V|_N> comparator COMP1 outputs to set bit- 10 as a logic low or '0' and thus, activating comparator COMP4 while the rest of the comparators COMP2, COMP3, COMP5 and COMP6 are still deactivated. Thereon, comparator COMP4 compares V_tN = 3.0V with 5V_REF1/8 = 3.125V. Since 5V_REF1/8 is higher than V|_N, comparator COMP4 outputs to set bit-9 as a logic low or Ό'. As a result, the digital code for the 3 most significant bits is determined as '100' and the second reference voltage (V_REF2) is selected to be supplied with a voltage of 0.5V_REF1 = 2.5V, wherein the multiplier, k is selected as 0.5 as provided in Table 1.

Next, the remaining bits (bit-0 to bit-8) are resolved by performing a bit cycling operation using the binary weighted capacitors. The bit cycling operation is initiated by switching switch S20 to connect V_REF2 to the input of the analog comparator (120) and switching switch S8 to connect capacitor C8 to V_REF3 = 0.625V while the rest of the capacitors (C7-C0) are connected to ground (V_Ss)- Thereon, V_DAc is compared with ground (V_Ss) by using the analog comparator (120). If V_DAC is equal or less than Vss, capacitor C8 remains connected to V_REF3 which translates to setting bit-8 as a logic high or Ί '. Otherwise, switch S8 is switched to V_Ss which translates to setting bit-8 as a logic low or 'Ο'. These steps are repeated for all other bits in decreasing order until bit-0 or capacitor CO is reached. As a result of the bit cycling operation using the binary weighted capacitors, the digital code for the remaining bits (bit-0 to bit-8) is obtained as Ί 1001 1001 ' Therefore, the successive approximation register (130) stores the digital code of Ί 001 1001 1001' for the input voltage of 3.0V.

While embodiments of the invention have been illustrated and described, it is not intended that these embodiments illustrated and describe all possible forms of the invention. Rather, the words used in the specifications are words of description rather than limitation and various changes may be made without departing from the scope of the invention.

Claims

An analog to digital converter (100) comprising:

a sample and hold circuit (110),

an analog comparator (120),

a successive approximation register (130), wherein the successive approximation register (130) is connected to the analog comparator (120), and

a digital to analog converter (150), wherein the digital to analog converter (150) is connected to the analog comparator (120) and to the successive approximation register (130); characterised in that:

the analog to digital converter (100) further includes a plurality of comparators (140) to resolve a number of most significant bits and to select a reference voltage (V_REF₂) for the digital to analog converter (150), wherein each comparator (140) has a predetermined threshold voltage and an output controlling at least two other comparators (140), and wherein each comparator is connected to the sample and hold circuit (110) and to the successive approximation register (130); the digital to analog converter (150) includes an array of binary weighted capacitors to resolve the remaining bits, wherein an output of the digital to analog converter (150) is connected through a switch to the reference voltage (V_REF2) selected by the plurality of comparators (140); and the analog comparator (120) is further connected to ground.

2. The analog to digital converter (100) as claimed in claim 1 , wherein the analog comparator (120) is used to compare an output voltage (V_DAC) fr°^m the digital to analog converter (150) with ground (V_SS) or 0V, and wherein the output voltage (V_DAC) of the digital to analog converter (150) is based on the equation below:

The analog to digital converter (100) as claimed in claim 1 , wherein the number of comparators (140) is determined by 2^M - 1 , wherein M is a number of bits assigned as the most significant bits.

The analog to digital converter (100) as claimed in claim 1 , wherein an output of each comparator (140) is connected to an enable input of at least two other comparators (140) to activate either one of the at least two connected comparators (140) during conversion.

The analog to digital converter (100) as claimed in claim 1 , wherein the plurality of comparators (140) selects the reference voltage (V_REF2) for the DAC (150) by selecting a multiplier, k based on the resolved most significant bits, and wherein V_REF2 is based on the equation below:

V ⁼ k * V

where k is a multiplier selected based on the binary search result of the most significant bits, and V_REF1 is a reference voltage supplied for the plurality of comparators (140).

A method for converting an analog input voltage (V|_N) to a digital code using an A/-bit analog to digital converter (100) is characterised by the steps of: a) performing asynchronous binary search by sequentially comparing the input voltage (V|_N) with a predetermined threshold voltage based on a first reference voltage (V_REFi) by using a plurality of comparators (140);

b) determining the digital code for M most significant bits, wherein M is a number of bits;

c) determining and supplying a second reference voltage (V_REF2) for a digital to analog converter (150) based on the result of M most significant bits; d) performing a bit cycling operation using the digital to analog converter (150) for the remaining bits (N-M);

e) determining the digital code for the remaining bits; and

f) storing the digital code for the analog input voltage (V,_N) in the successive approximation register (130).

The method as claimed in claim 6, wherein the plurality of comparators (140) selects the second reference voltage (V_REF2) for the digital to analog converter (150) by selecting a multiplier, k based on the resolved most significant bits, and wherein V_REF2 is based on the equation below:

V ⁼ k * V

where k is a multiplier selected based on the binary search result of the most significant bits, and V_REFi is the first reference voltage supplied for the plurality of comparators (140).

The method as claimed in claim 6, wherein the bit cycling operation includes the steps of:

a) connecting the second reference voltage (V_REF2) to an output of the digital to analog converter (150);

b) connecting a highest order bit capacitor (C_N._M-i) to a third reference voltage (V_REF3) and connecting the rest of the capacitors of the digital to analog converter (150) to the second reference voltage (V_REF2); c) comparing an output voltage (V_DAC) of the digital to analog converter (150) with ground (V_Ss), wherein if V_DAc is equal or less than V_Ss- capacitor C_N._M-i remains connected to V_REF3 which translates to setting b^'A-(N-M-l) as a logic high or , and wherein if V_DAC is greater than Vss, capacitor C_N._M-i is connected to V_Ss; and

d) repeating steps (b) and (c) for all other bits in decreasing order until bit-0 or capacitor CO is reached.