WO2013004829A1 - Insulated gate bipolar transistor - Google Patents

Insulated gate bipolar transistor Download PDF

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Publication number
WO2013004829A1
WO2013004829A1 PCT/EP2012/063303 EP2012063303W WO2013004829A1 WO 2013004829 A1 WO2013004829 A1 WO 2013004829A1 EP 2012063303 W EP2012063303 W EP 2012063303W WO 2013004829 A1 WO2013004829 A1 WO 2013004829A1
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WO
WIPO (PCT)
Prior art keywords
layer
base layer
conductivity type
well
emitter
Prior art date
Application number
PCT/EP2012/063303
Other languages
French (fr)
Inventor
Maxi ANDENNA
Munaf Rahimo
Chiara Corvasce
Arnost Kopta
Original Assignee
Abb Technology Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Abb Technology Ag filed Critical Abb Technology Ag
Priority to JP2014517832A priority Critical patent/JP5985624B2/en
Priority to GB1400075.6A priority patent/GB2506075B/en
Priority to KR1020147003224A priority patent/KR101840903B1/en
Priority to DE112012002823.6T priority patent/DE112012002823B4/en
Priority to CN201280033829.0A priority patent/CN103650148B/en
Publication of WO2013004829A1 publication Critical patent/WO2013004829A1/en
Priority to US14/149,412 priority patent/US9105680B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the invention relates to the field of power semiconductor devices. It relates to a Insulated Gate Bipolar according to the preamble of claim 1 .
  • FIG. 1 shows a prior art IGBT 120 with planar gate electrodes.
  • the IGBT 120 is a device with a four-layer structure, which layers are arranged between an emitter electrode 2 on an emitter side 1 1 and a collector electrode 25 on a collector side 15, which is arranged opposite of the emitter side 1 1 .
  • An (n-) doped drift layer 8 is arranged between the emitter side 1 1 and the collector side 15.
  • a p doped base layer 4 is arranged between the drift layer 8 and the emitter electrode 2, which base layer 4 is in direct electrical contact to the emitter electrode 2.
  • An n- doped source region 7 is arranged on the emitter side 1 1 embedded into the planar base layer 4 and contacts the emitter electrode 2.
  • a planar gate electrode 31 is arranged on top of the emitter side 1 1 .
  • the planar gate electrode 31 is electrically insulated from the base layer 4, the first source region 7 and the drift layer 8 by a first insulating layer 34.
  • a collector layer 9 is arranged between the drift layer 8 and the collector electrode 25.
  • planar MOS cell design exhibits a number of disadvantages when applied to BiMOS type switch concepts.
  • the device has high on-state losses due to a plurality of effects.
  • the planar design offers a lateral MOS channel which suffers from carrier spreading (also called JFET effect) near the cell. Therefore the planar cells show low carrier enhancement.
  • the planar design suffers also from the hole drain effect (PNP effect) due to the lateral electron spreading out of the MOS channel.
  • PNP effect hole drain effect
  • the region between the cells offers strong charge enhancement for the PiN diode part.
  • This PiN effect can only show a positive impact in high voltage devices with low cell packing densities (a low number of cells within an area). In order to achieve reduced channel resistance the planar devices are made with less cell packing density, and this can only be compensated with narrow pitches (distance between two cells), thereby reducing the PiN effect.
  • planar design provides good blocking capability due to low peak fields in the cells and between the cells.
  • planar design can have a large MOS accumulation region below the gate electrode and large associated capacitance. Nevertheless, the device shows good controllability due to the application of a field oxide type layer between the cells for miller capacitance reduction. Therefore, good controllability and low switching losses can be achieved for planar design.
  • prior art IGBTs 130 having trench MOS cell designs as shown in FIG. 2 have been introduced, in which a trench gate electrode 3 is electrically insulated from a base layer 4, a first source region 7 and the drift layer 8 by a first insulating layer 34.
  • the trench gate electrode 3 is arranged in the same plane and lateral to the base layer 4 and extends deeper into the drift layer 8 than the base layer 4.
  • the on-state losses are lower, because the trench design offers a vertical MOS channel, which provides enhanced injection of electrons in the vertical direction and suffers from no drawbacks from charge spreading (so called JFET effect) near the cell. Therefore the trench cells show much improved carrier enhancement for lower losses. Due to the vertical channel design, the trench offers also less hole drain effect (PNP effect) due to the improved electron spreading out of the MOS channel. At the bottom of the trench there is an accumulation layer, which offers strong charge enhancement for the PIN diode part. Hence wide and/or deep trenches show optimum performance. The trench design offers large cell packing density for reduced channel resistance. The trench design, however, suffer from lower blocking capability near the bottom corners of the trenches due to high peak electric fields.
  • the trench design has a large MOS accumulation region and associated capacitance with difficulty to apply field oxide type layers in the trench for miller capacitance reduction. Therefore, the device results in bad controllability and high switching losses. Furthermore, the high cell densities in trench designs will result in high short circuit currents.
  • the trench gate electrodes have been made wide and deep, whereas the cells have to be made narrow, so that losses are reduced and short circuit current can be kept low.
  • such trenches are difficult to process and will still suffer from bad controllability.
  • IGBTs 140 having a pitched- trench gate electrode 300 design has been applied, in which a MOS area is inserted between the cells.
  • the two trench gate electrodes 3 are connected by a layer made of the same material as the trench gate electrodes, thereby forming an area below, in which a part of the base layer is arranged, but no source region or contact of the base layer to the emitter electrode is available in this MOS area.
  • such devices result in bad blocking properties and high switching losses due to slow field spreading from the pitched area during switching (FIG 3).
  • dummy trench cells 1 10 have been introduced into another prior art IGBT 150, in which active cells 100 and dummy cells 1 10 are arranged in an alternating manner.
  • the base layer 4 and first source regions 7 do not have a contact to the emitter electrode 2 in the dummy cell 1 10,
  • n doped enhancement layers may be introduced between the drift layer 8 and the base layer 4 in order to reduce on-state losses.
  • JP 201 1 -40586 another prior art IGBT 160 having trench gate electrodes is described.
  • the deep p base layer 4 is connected to the active trenches 3, which has a negative impact on the device turn-on behaviour in terms of controllability.
  • the problem is solved by the semiconductor device with the characteristics of claim 1 .
  • the inventive Insulated gated bipolar transistor has layers between an emitter electrode on an emitter side and a collector electrode on a collector side opposite to the emitter side, comprising:
  • collector layer of the second conductivity type different than the first conductivity type which is arranged between the drift layer and the collector electrode and which electrically contacts the collector electrode
  • a base layer of a second conductivity type which is arranged between the drift layer and the emitter electrode, which base layer is in direct electrical contact to the emitter electrode
  • first source region of the first conductivity type having a higher doping concentration than the drift layer, which first source region is arranged on the base layer towards the emitter side and contacts the emitter electrode, - a or at least two trench gate electrodes, which is arranged lateral to the base layer and extends deeper into the drift layer than the base layer and which trench gate electrode is separated from the base layer, the first source region and the drift layer by a first insulating layer, wherein a channel is formable between the emitter electrode, the first source region, the base layer and the drift layer,
  • a third insulating layer which is arranged on the emitter side on top of the trench gate electrode, the electrically conductive layer and those parts of the base layer, the enhancement layer and the drift layer lying between the trench gate electrode and the well, and which has a recess on top of the electrically conducting layer such that the electrically conducting layer electrically contacts the emitter electrode.
  • This structure combines the positive effects of the prior art devices by having the deep well between two active cells, which ensures good blocking performance, improved controllability and low switching losses. Furthermore, the deep well is separated from the base layer by the enhancement layer for better turn-on behavior.
  • the enhancement layer itself also has the advantage that the on-state losses are reduced. As the electrically conductive layer is on the potential of the emitter electrode, it does not play a negative role by adding a capacitive effect in the gate circuit and hence, improved switching is obtained with lower losses and good controllability.
  • inventive IGBT For the creation of the inventive IGBT no complicated steps like trenches having different depths are used.
  • the inventive IGBT has good electrical properties for both the static and dynamic characteristics.
  • the device is easy to manufacture, because the inventive design can be manufactured based on a self-aligned process for the base layer and the enhancement layer between the well and the gate and if present for a second source region with the potential of applying the inventive emitter sided structure also on other IGBT device types like reverse conducting designs in a number of possible combinations.
  • the inventive design is suitable for full or part stripes but can also be implemented in cellular designs.
  • the electrically conductive layer is used as a mask for the creation of the enhancement layer and the base layer (self alignment), which is advantageous, because no mask alignment is needed (as it is the case for a mask, that is only applied for the creation of these layers and removed afterwards) and the mask does not have to be removed for finalizing the device.
  • FIG. 1 shows a IGBT with a planar gate electrode according to the prior art
  • FIG. 2 shows an IGBT with a trench gate electrode according to the prior art
  • FIG. 3 shows another IGBT with a pitched trench gate electrode according to the prior art
  • FIG. 4 shows another IGBT with a dummy cell according to the prior art
  • FIG. 5 shows another IGBT with a pitched trench gate electrode according to the prior art
  • FIG. 6 shows a first exemplary embodiment of an IGBT according to the
  • FIG. 7 to 12 show other exemplary embodiments of IGBTs according to the invention.
  • FIG. 6 shows a first embodiment of an inventive power semiconductor device 1 in form of an insulated gate bipolar transistor (IGBT) with a four-layer structure (pnpn).
  • the layers are arranged between an emitter electrode 2 on an emitter side and a collector electrode 25 on a collector side 15, which is arranged oppositehe emitter side 1 1.
  • the IGBT comprises the following layers:
  • An (n-) lowly doped drift layer 8 is arranged between the emitter side 1 1 and the collector side 15. Examplarily, the drift layer has a constant, uniform low doping concentration.
  • a p doped collector layer 9 is arranged between the drift layer 8 and the collector electrode 25.
  • the collector layer is arranged adjacent to and electrically contacts the collector electrode 25.
  • a p doped base layer 4 is arranged between the drift layer 8 and the emitter electrode 2.
  • the base layer 4 is in direct electrical contact to the emitter electrode 2.
  • n doped first source region 7 is arranged on the base layer 4 towards the emitter side 1 1 and contacts the emitter electrode 2.
  • the first source region 7 has a higher doping concentration than the drift layer 8.
  • the first source region 7 is arranged on top of the base layer 4, it is meant that the first source region 7 is arranged at the surface at the emitter side 1 1.
  • the first source region 7 may be embedded in the base layer 4 such that both layer have a common surface on the emitter side 1 1 .
  • the trench gate electrodes 3 are arranged in the same plane (which plane lies parallel to the emitter side 1 1 ) and lateral to the base layer 4 and extends deeper into the drift layer 8 from the emitter side 1 1 than the base layer 4.
  • the trench gate electrode 3 is separated from the base layer 4, the first source region 7 and the drift layer 8 by a first insulating layer 34.
  • a channel is formable between the emitter electrode 2, the first source region 7, the base layer 4 and the drift layer 8.
  • the trench gate electrodes may have any design well-known to the experts like cellular design, full or part stripes.
  • a p doped well 5 is arranged in the same plane and lateral to the base layer 4 and extends deeper into the drift layer 8 than the base layer 4.
  • the p well 5 is not connected to the p base layer 4.
  • the enhancement layer 6 is shallower than the well 5.
  • an electrically conducting layer 32 is arranged on the emitter side 1 1 , which covers the well 5 (FIG. 12). Additionally the electrically conductive layer 32 may cover such part of the enhancement layer 6, which is arranged between the well 5 and the base layer 4, and extends to a region above the base layer 4. If the drift layer extends to the surface on the emitter side 1 1 , the drift layer 8 is also covered by the electrically conductive layer 32 in this embodiment.
  • the second electrically insulating layer 36 and/or the electrically conductive layer 32 can be used as a mask, therefore simplifying the manufacturing.
  • the electrically conductive layer 32 can be made of any suitable electrically conductive material, exemplarily polysilicon or metal.
  • a second electrically insulating layer 36 separates the electrically
  • This second insulating layer 36 can be chosen as thin as 50 to 150 nm, which is much thinner than the insulating layers 38 used in prior art devices like those shown in FIG. 3 and 4, which have a third insulating layer 38 in form of a silicon oxide layer with a thickness of 500 to 1500 nm.
  • a third insulating layer 38 is arranged on the emitter side 1 1 on top of the trench gate electrode 3, the electrically conductive layer 32 and those parts of the base layer 4, the enhancement layer 6 and the drift layer 8, which extend to the emitter side 1 1 between a trench gate electrode 3 and the well 5.
  • the third insulating layer 38 has a recess 39 on top of the electrically conducting layer 32, i.e. on such a side of the layer 32 which lies opposite to the second insulating layer 38, such that the electrically conducting layer 32 is in electrical contact to the emitter electrode 2.
  • “Lateral” shall mean in this description that two layers/regions are arranged in a same plane, which plane lies parallel to the emitter side. Within that plane the layers are arranged lateral (neighboured, side to side) or adjacent to each other, whereas the layers may have a distance from each other, i.e. another layer may be arranged between the two layers, but they may also be directly adjacent to each other, i.e. in touch to each other. "Lateral sides” of a layer shall be the sides of an object perpendicular to the emitter side 1 1.
  • IGBTs similar to the one shown in FIG. 6 are disclosed, but these IGBTs comprise additional features as explained below in more detail.
  • a second n doped source region 75 is arranged at the emitter side 1 1 on the base layer 4 between the trench gate electrode 3 and the well 5, wherein the second source region 75 exemplarily extends from the first electrically insulating layer 34 at least to a border of the electrically conductive layer 32.
  • the second source region 75 is exemplarily created together with the first source region 7, thus reducing the masking steps during manufacturing.
  • the second source region 75 has a higher doping concentration than the drift layer 8.
  • FIG. 8 shows another inventive IGBT comprising an n doped buffer layer 85 having a higher doping concentration than the drift layer 8, which is arranged between the drift layer 8 and the collector layer 9.
  • the inventive emitter sided design can also be applied to a reverse conducting IGBT, in which in the same plane as the collector layer 9 (i.e. on the collector side 15 and lateral to the collector layer 9), an n doped first region 95 is arranged as shown in FIG. 9.
  • the first region 95 is thus arranged alternating to the collector layer 9.
  • the first region 95 has a higher doping concentration than the drift layer 8.
  • the electrically conductive layer 32 may be made of the same material as the trench gate electrode 3. By its contact to the emitter electrode 2 the electrically conductive layer 32 is on the same potential as the emitter electrode 2. This layer is not controllable as a gate electrode. Thus, it has no negative impact on the switching performance due to an increased capacitive effect on the gate.
  • the inventive IGBT comprises a p well 5, which extends deeper into the drift layer 8 than the trench gate electrode 3. This will provide improved blocking performance and lower switching losses.
  • the enhancement layer 6 adjoins the well 5 directly.
  • the drift layer 8 may extend to the insulation layer 36 in an area between the well 5 and the enhancement layer 6.
  • the drift layer 8 extends to the surface of the wafer so that the enhancement layer 6 and the well 5 are separated from each other by the drift layer 8. On state losses may be reduced by such an arrangement.
  • the second insulating layer 36 and the electrically conductive layer 32 are used as a mask for the creation of the base layer 4 and the enhancement layer 6.
  • the inventive semiconductor devices can comprise a gate electrode design with a different numbers of trench gate electrodes 3 than electrically conductive layers 32.
  • the inventive semiconductor devices can comprise a gate electrode design with a different numbers of trench gate electrodes 3 than electrically conductive layers 32.
  • more than one p wells 5 are arranged between the active trenches, wherein the wells 5 may be arranged below a common electrically conductive layer or the wells 5 may be arranged below separate electrically conductive layers 32, wherein the layers 32 are separated by the third insulating layer 38. Between two wells 5, the structure with the base layer 4 surrounded by the enhancement layer 6 may be repeated.
  • the inventive IGBT 1 comprises a p doped bar having a higher doping concentration than the base layer 4.
  • the bar is arranged at the emitter side 1 1 in a plane perpendicular to the perspective shown in the FIG.s 6 to 12.
  • the source regions 7, 75, base layer 4 and the enhancement layer 6 terminate.
  • the bar extends to the surface of the wafer.
  • the bar extends in a plane parallel to the emitter side perpendicular to the direction, in which the first source regions 7 attach the trench gate electrodes 3.
  • the well 5 may extend to the bar 45 or, alternatively it may be terminated such that no contact to the bar 45 is achieved.
  • the enhancement layer 6 or the base layer 4 or both of these layers may be arranged between the well 5 and the bar 45.
  • the connection between the well and the bar will result in a non floating well which will increase the static losses and worsen the switching performance.
  • the conductivity types are switched, i.e. all layers of the first conductivity type are p type (e.g. the drift layer 8, the first and second source region 7, 75) and all layers of the second conductivity type are n type (e.g. base layer 4, well 5).
  • the inventive IGBT 1 is manufactured by the following method. A lowly (n-) doped wafer having an emitter side and a collector side is provided. The wafer has a uniform, constant doping concentration. The wafer may be made on a basis of a silicon or GaN or SiC wafer. Part of the wafer having unamended low doping in the finalized insulated gated bipolar transistor 1 forms a drift layer 8.
  • a mask is applied and a first p dopant is introduced for forming a well 5.
  • a trench recess is introduced on the emitter side 1 1 , which is coated with a first insulating layer 34.
  • the coated trench recess is then filled with an electrically conductive material like a heavily doped polysilicon or a metal like aluminum. By this step the trench gete electrode 3 is formed.
  • a second insulating layer 36 which covers the well 5, is formed.
  • an electrically conductive layer 32 is formed on top of this second insulating layer 36.
  • This electrically conductive layer 32 may be formed of the same material as the trench gate electrode 3, but also other electrically conductive materials ban be used.
  • the electrically conductive layer 32 covers the well 5 and may extend laterally (i.e. in a plane parallel to the emitter side 1 1 ) beyond the well 5 so that the well is covered by the electrically conductive layer 32, but insulated from it by the second insulation layer 36.
  • the electrically conductive layer 32 may exemplarily extend outside the well 5 by 1 to 10 ⁇ , in another exemplary embodiment by 1 to 5 ⁇ or by 5 to 10 ⁇ .
  • As the second insulating layer 36 insulates the electrically conductive layer 32 from the wafer, it extends laterally at least to the lateral sides of the electrically conductive layer 32 or even beyond its lateral sides.
  • an enhancement layer 6 is formed by introducing an n second dopant on the emitter side 1 1 , which is diffused into the wafer using the electrically conductive layer 32 as a mask.
  • a base layer 4 is formed by introducing a p third dopant on the emitter side 1 1 , using the electrically conductive layer 32 as a mask.
  • the p third dopant is diffused into the wafer from the emitter side 1 1 to a lower depth, than the depth, into which the second dopant has been diffused so that the base layer 5 is embedded in the enhancement layer 6.
  • the embodiments shown in the fig. 6 (enhancement layer 6 extending to the p well 5, but separating the p well 5 from the base layer 4) or in fig. 12, in which the enhancement layer 6 still separates the base layer 4 from the drift layer 8, but is separated from the p well 5 by the drift layer 8.
  • the third dopant is not laterally diffused so far as to reach the p well 5.
  • a collector layer 9 is then formed by introducing a p fourth dopant on the collector side 15, which is diffused into the wafer.
  • the collector layer 9 may also be made at another manufacturing step.
  • a buffer layer 85 is created (see fig. 8), the buffer layer 85 has to be created before the collector layer 9.
  • the buffer layer 85 is exemplarily created by introducing an n dopant on the collector side 15.
  • the buffer layer 85 always has higher doping concentration than the drift layer 8.
  • a third insulating layer 38 is applied on top of the electrically conductive layer 32, which laterally extends to the trench gate electrode 3.
  • the third insulating layer 38 is made with a recess 39 on the electrically conductive layer 32 for a contact of the electrically conductive layer 32 to the emitter electrode 2 and with a contact opening of the emitter electrode 2 to the base layer 4.
  • the recess and contact opening are exemplarily made by partial removal of the third insulating layer 38 on top of the base layer and electrically conductive layer, respectively.
  • a n fifth dopant is introduced using the third insulating layer 38 and the electrically conductive layer 32 as a mask for forming first source regions 7. Examplarily the fifth dopant is activated afterwards.
  • the electrically conductive layer 32 may be used as a mask for introducing the n fifth dopant.
  • first source regions between two trench gate electrodes 3 and second source regions 75 between a trench gate electrode 3 and a p well 5 are created.
  • the third insulating layer 38 may then be applied after the creation of the source regions 7, 75.
  • the third insulating layer 38 covers the second source region 75, the electrically conductive layer 32 besides the recess 39 and leaves open a contact opening between two trench gate elctrodes 3.
  • An etch step is exemplarily performed in order to etch through a first source region 7 for the contact of the base layer 5 to the emitter electrode 2 (not shown in the figures; by this method the contact opening of the base layer 5 to the emitter electrode 2 is arranged in a plane below the emitter side 1 1.
  • the emitter side 1 1 of the wafer shall be the most outer plane, in which layers or regions are arranged in the wafer parallel at the side, at which the emitter electrode 2 is arranged.
  • source regions are created with a mask, which covers a central area between two trench gate electrodes 3 for the contact of the base layer 5 to the emitter electrode 3. Finally an emitter electrode 2 and a collector electrode 25 are made.
  • the dopants can be introduced by any appropriate method like implantation or deposition. Diffusion steps can be made directly after the introducing of the corresponding dopant, but can also be perfomed at a later stage, e.g. for the base layer 4, the p well 5 being made with a diffusion step, their doping profile decreases from a maximum value steadily to the maximum diffusion depth of the dopant (which depends on the dopant sort and the diffusion conditions like diffusion time and temperature).
  • the term “comprising” does not exclude other elements or steps and that the indefinite article "a” or “an” does not exclude the plural. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.

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Abstract

An IGBT is provided having layers between an emitter electrode (2) on an emitter side (11) and a collector electrode (25) on a collector side (15), comprising: - a collector layer (9) on the collector side (15), - a drift layer (8), - a base layer (4) of a second conductivity type, - a first source region (7), which is arranged on the base layer (4) towards the emitter side (11), - a trench gate electrode (3), which is arranged lateral to the base layer (4) and extends deeper into the drift layer (8) than the base layer (4), - a well (5), which is arranged lateral to the base layer (4) and extends deeper into the drift layer (8) than the base layer (4), - an enhancement layer (6), which surrounds the base layer (4) such that the enhancement layer (6) completely separates the base layer (4) from the drift layer (8) and the well (5), - additionally to the emitter electrode (2) an electrically conducting layer (32), which covers the well (5), wherein the electrically conductive layer (32) is separated from the well (5) by a second electrically insulating layer (36), - a third insulating layer (38), which has a recess (39) on top of the electrically conducting layer (32) such that the electrically conducting layer (32) electrically contacts the emitter electrode (2).

Description

Insulated Gate Bipolar Transistor
Description Field of invention
The invention relates to the field of power semiconductor devices. It relates to a Insulated Gate Bipolar according to the preamble of claim 1 .
Background of the invention
FIG. 1 shows a prior art IGBT 120 with planar gate electrodes. The IGBT 120 is a device with a four-layer structure, which layers are arranged between an emitter electrode 2 on an emitter side 1 1 and a collector electrode 25 on a collector side 15, which is arranged opposite of the emitter side 1 1 . An (n-) doped drift layer 8 is arranged between the emitter side 1 1 and the collector side 15. A p doped base layer 4 is arranged between the drift layer 8 and the emitter electrode 2, which base layer 4 is in direct electrical contact to the emitter electrode 2. An n- doped source region 7 is arranged on the emitter side 1 1 embedded into the planar base layer 4 and contacts the emitter electrode 2.
A planar gate electrode 31 is arranged on top of the emitter side 1 1 . The planar gate electrode 31 is electrically insulated from the base layer 4, the first source region 7 and the drift layer 8 by a first insulating layer 34. There is a third insulating layer 38 arranged between the planar gate electrode 31 and the emitter electrode 2. On the collector side, a collector layer 9 is arranged between the drift layer 8 and the collector electrode 25.
Such a planar MOS cell design exhibits a number of disadvantages when applied to BiMOS type switch concepts. The device has high on-state losses due to a plurality of effects. The planar design offers a lateral MOS channel which suffers from carrier spreading (also called JFET effect) near the cell. Therefore the planar cells show low carrier enhancement. Furthermore, due to the lateral channel design, the planar design suffers also from the hole drain effect (PNP effect) due to the lateral electron spreading out of the MOS channel. The region between the cells offers strong charge enhancement for the PiN diode part. This PiN effect, however, can only show a positive impact in high voltage devices with low cell packing densities (a low number of cells within an area). In order to achieve reduced channel resistance the planar devices are made with less cell packing density, and this can only be compensated with narrow pitches (distance between two cells), thereby reducing the PiN effect.
The high losses have been reduced by the introduction of n doped
enhancement layers, which surround the planar base layer.
Concerning the blocking capability the planar design provides good blocking capability due to low peak fields in the cells and between the cells.
The planar design can have a large MOS accumulation region below the gate electrode and large associated capacitance. Nevertheless, the device shows good controllability due to the application of a field oxide type layer between the cells for miller capacitance reduction. Therefore, good controllability and low switching losses can be achieved for planar design.
Furthermore, the cell densities in planar designs can be easily adjusted for the required short circuit currents.
As a result taking all above mentioned effects into account prior art planar cells apply very narrow cells and wide pitches with Field Oxide layers.
Alternatively to planar designs, prior art IGBTs 130 having trench MOS cell designs as shown in FIG. 2 have been introduced, in which a trench gate electrode 3 is electrically insulated from a base layer 4, a first source region 7 and the drift layer 8 by a first insulating layer 34. The trench gate electrode 3 is arranged in the same plane and lateral to the base layer 4 and extends deeper into the drift layer 8 than the base layer 4.
With such trench gate electrode designs, the on-state losses are lower, because the trench design offers a vertical MOS channel, which provides enhanced injection of electrons in the vertical direction and suffers from no drawbacks from charge spreading (so called JFET effect) near the cell. Therefore the trench cells show much improved carrier enhancement for lower losses. Due to the vertical channel design, the trench offers also less hole drain effect (PNP effect) due to the improved electron spreading out of the MOS channel. At the bottom of the trench there is an accumulation layer, which offers strong charge enhancement for the PIN diode part. Hence wide and/or deep trenches show optimum performance. The trench design offers large cell packing density for reduced channel resistance. The trench design, however, suffer from lower blocking capability near the bottom corners of the trenches due to high peak electric fields. The trench design has a large MOS accumulation region and associated capacitance with difficulty to apply field oxide type layers in the trench for miller capacitance reduction. Therefore, the device results in bad controllability and high switching losses. Furthermore, the high cell densities in trench designs will result in high short circuit currents.
In order to reduce above mentioned effects, the trench gate electrodes have been made wide and deep, whereas the cells have to be made narrow, so that losses are reduced and short circuit current can be kept low. However, such trenches are difficult to process and will still suffer from bad controllability.
In a further prior art concept shown in FIG. 3, IGBTs 140 having a pitched- trench gate electrode 300 design has been applied, in which a MOS area is inserted between the cells. The two trench gate electrodes 3 are connected by a layer made of the same material as the trench gate electrodes, thereby forming an area below, in which a part of the base layer is arranged, but no source region or contact of the base layer to the emitter electrode is available in this MOS area. However, such devices result in bad blocking properties and high switching losses due to slow field spreading from the pitched area during switching (FIG 3).
In another approach shown in FIG. 4, dummy trench cells 1 10 have been introduced into another prior art IGBT 150, in which active cells 100 and dummy cells 1 10 are arranged in an alternating manner. The base layer 4 and first source regions 7 do not have a contact to the emitter electrode 2 in the dummy cell 1 10, However, similar problems to those mentioned for the pitched-trench design apply. For this design, n doped enhancement layers may be introduced between the drift layer 8 and the base layer 4 in order to reduce on-state losses. In JP 201 1 -40586 another prior art IGBT 160 having trench gate electrodes is described. Between two active trenches 3 shallow pitched trenches 300 with an upper lying planar layer of the same electrically conductive poly silicon material are arranged, which do not have a contact to the emitter electrode 2 similar to the prior art IGBT 140 (shown in FIG. 3). However, as one base layer 4 is applied in the active cells as well as in the pitched gate area below the shallow pitched trenches 300, this base layer 4 has to be rather deep because the pitched gate electrodes 300 are embedded in the base layer 4, whereas the active trenches 3 are deeper than the base layer 4. The manufacturing of such trenches 3, 300 with different depths and the deep p base layer 4 is very difficult, because the active trenches 3 and the pitched trenches have to be manufactured separately.
Furthermore, the deep p base layer 4 is connected to the active trenches 3, which has a negative impact on the device turn-on behaviour in terms of controllability.
Description of the invention
It is an object of the invention to provide a power semiconductor device with reduced on-state losses, improved blocking capability, low drainage of holes and good controllability, which is easier to manufacture than prior art devices.
The problem is solved by the semiconductor device with the characteristics of claim 1 .
The inventive Insulated gated bipolar transistor (IGBT) has layers between an emitter electrode on an emitter side and a collector electrode on a collector side opposite to the emitter side, comprising:
- a drift layer of a first conductivity type,
- a collector layer of the second conductivity type different than the first conductivity type ,which is arranged between the drift layer and the collector electrode and which electrically contacts the collector electrode,
- a base layer of a second conductivity type, which is arranged between the drift layer and the emitter electrode, which base layer is in direct electrical contact to the emitter electrode,
- a first source region of the first conductivity type having a higher doping concentration than the drift layer, which first source region is arranged on the base layer towards the emitter side and contacts the emitter electrode, - a or at least two trench gate electrodes, which is arranged lateral to the base layer and extends deeper into the drift layer than the base layer and which trench gate electrode is separated from the base layer, the first source region and the drift layer by a first insulating layer, wherein a channel is formable between the emitter electrode, the first source region, the base layer and the drift layer,
- a well of the second conductivity type, which is arranged lateral to the base layer and extends deeper into the drift layer than the base layer,
- an enhancement layer of the first conductivity type, which surrounds the base layer such that the enhancement layer completely separates the base layer from the drift layer and the well,
- additionally to the emitter electrode an electrically conducting layer,
which covers the well and is separated at least from the well by a second electrically insulating layer,
- a third insulating layer, which is arranged on the emitter side on top of the trench gate electrode, the electrically conductive layer and those parts of the base layer, the enhancement layer and the drift layer lying between the trench gate electrode and the well, and which has a recess on top of the electrically conducting layer such that the electrically conducting layer electrically contacts the emitter electrode.
This structure combines the positive effects of the prior art devices by having the deep well between two active cells, which ensures good blocking performance, improved controllability and low switching losses. Furthermore, the deep well is separated from the base layer by the enhancement layer for better turn-on behavior. The enhancement layer itself also has the advantage that the on-state losses are reduced. As the electrically conductive layer is on the potential of the emitter electrode, it does not play a negative role by adding a capacitive effect in the gate circuit and hence, improved switching is obtained with lower losses and good controllability.
For the creation of the inventive IGBT no complicated steps like trenches having different depths are used. The inventive IGBT has good electrical properties for both the static and dynamic characteristics.
Furthermore, the device is easy to manufacture, because the inventive design can be manufactured based on a self-aligned process for the base layer and the enhancement layer between the well and the gate and if present for a second source region with the potential of applying the inventive emitter sided structure also on other IGBT device types like reverse conducting designs in a number of possible combinations. The inventive design is suitable for full or part stripes but can also be implemented in cellular designs. The electrically conductive layer is used as a mask for the creation of the enhancement layer and the base layer (self alignment), which is advantageous, because no mask alignment is needed (as it is the case for a mask, that is only applied for the creation of these layers and removed afterwards) and the mask does not have to be removed for finalizing the device.
Further advantages according to the present invention will be apparent from the dependent claims.
Brief description of the drawings
The subject matter of the invention will be explained in more detail in the following text with reference to the attached drawings, in which:
FIG. 1 shows a IGBT with a planar gate electrode according to the prior art; FIG. 2 shows an IGBT with a trench gate electrode according to the prior art; FIG. 3 shows another IGBT with a pitched trench gate electrode according to the prior art;
FIG. 4 shows another IGBT with a dummy cell according to the prior art;
FIG. 5 shows another IGBT with a pitched trench gate electrode according to the prior art;
FIG. 6 shows a first exemplary embodiment of an IGBT according to the
invention; and
FIG. 7 to 12 show other exemplary embodiments of IGBTs according to the invention.
The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. Generally, alike or alike-functioning parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.
Detailed description of preferred embodiments
FIG. 6 shows a first embodiment of an inventive power semiconductor device 1 in form of an insulated gate bipolar transistor (IGBT) with a four-layer structure (pnpn). The layers are arranged between an emitter electrode 2 on an emitter side and a collector electrode 25 on a collector side 15, which is arranged oppositehe emitter side 1 1. The IGBT comprises the following layers:
- An (n-) lowly doped drift layer 8 is arranged between the emitter side 1 1 and the collector side 15. Examplarily, the drift layer has a constant, uniform low doping concentration.
- A p doped collector layer 9 is arranged between the drift layer 8 and the collector electrode 25. The collector layer is arranged adjacent to and electrically contacts the collector electrode 25.
- A p doped base layer 4 is arranged between the drift layer 8 and the emitter electrode 2. The base layer 4 is in direct electrical contact to the emitter electrode 2.
- An n doped first source region 7 is arranged on the base layer 4 towards the emitter side 1 1 and contacts the emitter electrode 2. The first source region 7 has a higher doping concentration than the drift layer 8. With the first source region 7 being arranged on top of the base layer 4, it is meant that the first source region 7 is arranged at the surface at the emitter side 1 1. The first source region 7 may be embedded in the base layer 4 such that both layer have a common surface on the emitter side 1 1 .
- A trench gate electrode 3 or a plurality, i.e. at least two trench gate
electrodes 3 are arranged in the same plane (which plane lies parallel to the emitter side 1 1 ) and lateral to the base layer 4 and extends deeper into the drift layer 8 from the emitter side 1 1 than the base layer 4. The trench gate electrode 3 is separated from the base layer 4, the first source region 7 and the drift layer 8 by a first insulating layer 34. A channel is formable between the emitter electrode 2, the first source region 7, the base layer 4 and the drift layer 8. The trench gate electrodes may have any design well-known to the experts like cellular design, full or part stripes.
- A p doped well 5 is arranged in the same plane and lateral to the base layer 4 and extends deeper into the drift layer 8 than the base layer 4.
The p well 5 is not connected to the p base layer 4.
- An n doped enhancement layer 6, which is higher doped than the drift layer 8, surrounds the base layer 4 such that the enhancement layer 6 completely separates the base layer 4 from the drift layer 8 and the well 5. Exemplarily, the enhancement layer 6 is shallower than the well 5. - Additionally to the emitter electrode (2) an electrically conducting layer 32 is arranged on the emitter side 1 1 , which covers the well 5 (FIG. 12). Additionally the electrically conductive layer 32 may cover such part of the enhancement layer 6, which is arranged between the well 5 and the base layer 4, and extends to a region above the base layer 4. If the drift layer extends to the surface on the emitter side 1 1 , the drift layer 8 is also covered by the electrically conductive layer 32 in this embodiment. For manufacturing such a device, the second electrically insulating layer 36 and/or the electrically conductive layer 32 can be used as a mask, therefore simplifying the manufacturing. The electrically conductive layer 32 can be made of any suitable electrically conductive material, exemplarily polysilicon or metal.
- A second electrically insulating layer 36 separates the electrically
conducting layer 32 from the well 5 and the other layers 4, 6,
respectively. This second insulating layer 36 can be chosen as thin as 50 to 150 nm, which is much thinner than the insulating layers 38 used in prior art devices like those shown in FIG. 3 and 4, which have a third insulating layer 38 in form of a silicon oxide layer with a thickness of 500 to 1500 nm. By having such a thin second insulating layer the
capacitance is positively reduced and therby, the switching capability is improved.
- A third insulating layer 38 is arranged on the emitter side 1 1 on top of the trench gate electrode 3, the electrically conductive layer 32 and those parts of the base layer 4, the enhancement layer 6 and the drift layer 8, which extend to the emitter side 1 1 between a trench gate electrode 3 and the well 5. The third insulating layer 38 has a recess 39 on top of the electrically conducting layer 32, i.e. on such a side of the layer 32 which lies opposite to the second insulating layer 38, such that the electrically conducting layer 32 is in electrical contact to the emitter electrode 2.
"Lateral" shall mean in this description that two layers/regions are arranged in a same plane, which plane lies parallel to the emitter side. Within that plane the layers are arranged lateral (neighboured, side to side) or adjacent to each other, whereas the layers may have a distance from each other, i.e. another layer may be arranged between the two layers, but they may also be directly adjacent to each other, i.e. in touch to each other. "Lateral sides" of a layer shall be the sides of an object perpendicular to the emitter side 1 1.
In the Fig. 7 to 12 IGBTs similar to the one shown in FIG. 6 are disclosed, but these IGBTs comprise additional features as explained below in more detail.
In the inventive IGBT shown in FIG. 7 a second n doped source region 75 is arranged at the emitter side 1 1 on the base layer 4 between the trench gate electrode 3 and the well 5, wherein the second source region 75 exemplarily extends from the first electrically insulating layer 34 at least to a border of the electrically conductive layer 32. The second source region 75 is exemplarily created together with the first source region 7, thus reducing the masking steps during manufacturing. The second source region 75 has a higher doping concentration than the drift layer 8.
FIG. 8 shows another inventive IGBT comprising an n doped buffer layer 85 having a higher doping concentration than the drift layer 8, which is arranged between the drift layer 8 and the collector layer 9.
The inventive emitter sided design can also be applied to a reverse conducting IGBT, in which in the same plane as the collector layer 9 (i.e. on the collector side 15 and lateral to the collector layer 9), an n doped first region 95 is arranged as shown in FIG. 9. The first region 95 is thus arranged alternating to the collector layer 9. The first region 95 has a higher doping concentration than the drift layer 8.
The electrically conductive layer 32 may be made of the same material as the trench gate electrode 3. By its contact to the emitter electrode 2 the electrically conductive layer 32 is on the same potential as the emitter electrode 2. This layer is not controllable as a gate electrode. Thus, it has no negative impact on the switching performance due to an increased capacitive effect on the gate.
In a further exemplary embodiment as shown in FIG. 10, the inventive IGBT comprises a p well 5, which extends deeper into the drift layer 8 than the trench gate electrode 3. This will provide improved blocking performance and lower switching losses.
In the FIG.s 6 to 10 and 12 the enhancement layer 6 adjoins the well 5 directly.
Alternatively, as shown in FIG. 1 1 , the drift layer 8 may extend to the insulation layer 36 in an area between the well 5 and the enhancement layer 6. In this embodiment, the drift layer 8 extends to the surface of the wafer so that the enhancement layer 6 and the well 5 are separated from each other by the drift layer 8. On state losses may be reduced by such an arrangement.
In an exemplary manufacturing method for this embodiment, the second insulating layer 36 and the electrically conductive layer 32 are used as a mask for the creation of the base layer 4 and the enhancement layer 6. In case of a wide electrically conductive layer 32 and a narrow well 5 the well 5 and the
enhancement layer 6 become disposed from each other. Exemplarily, the inventive semiconductor devices can comprise a gate electrode design with a different numbers of trench gate electrodes 3 than electrically conductive layers 32. For example, there may be less electrically conductive layers 32 than trench gate electrodes 3 arranged in the design so that the density of active cells 100 versus total area is increased. In another alternative, more than one p wells 5 are arranged between the active trenches, wherein the wells 5 may be arranged below a common electrically conductive layer or the wells 5 may be arranged below separate electrically conductive layers 32, wherein the layers 32 are separated by the third insulating layer 38. Between two wells 5, the structure with the base layer 4 surrounded by the enhancement layer 6 may be repeated.
In a further exemplary embodiment, the inventive IGBT 1 comprises a p doped bar having a higher doping concentration than the base layer 4. The bar is arranged at the emitter side 1 1 in a plane perpendicular to the perspective shown in the FIG.s 6 to 12. At the bar the source regions 7, 75, base layer 4 and the enhancement layer 6 terminate. The bar extends to the surface of the wafer. The bar extends in a plane parallel to the emitter side perpendicular to the direction, in which the first source regions 7 attach the trench gate electrodes 3.
The well 5 may extend to the bar 45 or, alternatively it may be terminated such that no contact to the bar 45 is achieved. In this case the enhancement layer 6 or the base layer 4 or both of these layers may be arranged between the well 5 and the bar 45. The connection between the well and the bar will result in a non floating well which will increase the static losses and worsen the switching performance.
In another embodiment, the conductivity types are switched, i.e. all layers of the first conductivity type are p type (e.g. the drift layer 8, the first and second source region 7, 75) and all layers of the second conductivity type are n type (e.g. base layer 4, well 5). The inventive IGBT 1 is manufactured by the following method. A lowly (n-) doped wafer having an emitter side and a collector side is provided. The wafer has a uniform, constant doping concentration. The wafer may be made on a basis of a silicon or GaN or SiC wafer. Part of the wafer having unamended low doping in the finalized insulated gated bipolar transistor 1 forms a drift layer 8.
A mask is applied and a first p dopant is introduced for forming a well 5.
A trench recess is introduced on the emitter side 1 1 , which is coated with a first insulating layer 34. The coated trench recess is then filled with an electrically conductive material like a heavily doped polysilicon or a metal like aluminum. By this step the trench gete electrode 3 is formed.
Afterwards a second insulating layer 36, which covers the well 5, is formed. On top of this second insulating layer 36 an electrically conductive layer 32 is formed. This electrically conductive layer 32 may be formed of the same material as the trench gate electrode 3, but also other electrically conductive materials ban be used. The electrically conductive layer 32 covers the well 5 and may extend laterally (i.e. in a plane parallel to the emitter side 1 1 ) beyond the well 5 so that the well is covered by the electrically conductive layer 32, but insulated from it by the second insulation layer 36. The electrically conductive layer 32 may exemplarily extend outside the well 5 by 1 to 10 μηη, in another exemplary embodiment by 1 to 5 μηη or by 5 to 10 μηη. As the second insulating layer 36 insulates the electrically conductive layer 32 from the wafer, it extends laterally at least to the lateral sides of the electrically conductive layer 32 or even beyond its lateral sides.
Then an enhancement layer 6 is formed by introducing an n second dopant on the emitter side 1 1 , which is diffused into the wafer using the electrically conductive layer 32 as a mask.
After the introduction of the n second dopant a base layer 4 is formed by introducing a p third dopant on the emitter side 1 1 , using the electrically conductive layer 32 as a mask. The p third dopant is diffused into the wafer from the emitter side 1 1 to a lower depth, than the depth, into which the second dopant has been diffused so that the base layer 5 is embedded in the enhancement layer 6. Depending on the distance, which the electrically conductive layer 32 extends beyond the p well 5 and depending on the diffusion depth/length of the second and third dopants, the embodiments shown in the fig. 6 (enhancement layer 6 extending to the p well 5, but separating the p well 5 from the base layer 4) or in fig. 12, in which the enhancement layer 6 still separates the base layer 4 from the drift layer 8, but is separated from the p well 5 by the drift layer 8. In such a device the third dopant is not laterally diffused so far as to reach the p well 5.
Examplarily, a collector layer 9 is then formed by introducing a p fourth dopant on the collector side 15, which is diffused into the wafer. The collector layer 9 may also be made at another manufacturing step.
If a buffer layer 85 is created (see fig. 8), the buffer layer 85 has to be created before the collector layer 9. The buffer layer 85 is exemplarily created by introducing an n dopant on the collector side 15. The buffer layer 85 always has higher doping concentration than the drift layer 8.
Then a third insulating layer 38 is applied on top of the electrically conductive layer 32, which laterally extends to the trench gate electrode 3. The third insulating layer 38 is made with a recess 39 on the electrically conductive layer 32 for a contact of the electrically conductive layer 32 to the emitter electrode 2 and with a contact opening of the emitter electrode 2 to the base layer 4. The recess and contact opening are exemplarily made by partial removal of the third insulating layer 38 on top of the base layer and electrically conductive layer, respectively.
In the contact opening a n fifth dopant is introduced using the third insulating layer 38 and the electrically conductive layer 32 as a mask for forming first source regions 7. Examplarily the fifth dopant is activated afterwards.
Alternatively, the electrically conductive layer 32 may be used as a mask for introducing the n fifth dopant. In this case, first source regions between two trench gate electrodes 3 and second source regions 75 between a trench gate electrode 3 and a p well 5 are created. The third insulating layer 38 may then be applied after the creation of the source regions 7, 75. The third insulating layer 38 covers the second source region 75, the electrically conductive layer 32 besides the recess 39 and leaves open a contact opening between two trench gate elctrodes 3. An etch step is exemplarily performed in order to etch through a first source region 7 for the contact of the base layer 5 to the emitter electrode 2 (not shown in the figures; by this method the contact opening of the base layer 5 to the emitter electrode 2 is arranged in a plane below the emitter side 1 1. The emitter side 1 1 of the wafer shall be the most outer plane, in which layers or regions are arranged in the wafer parallel at the side, at which the emitter electrode 2 is arranged.
Alternatively, source regions are created with a mask, which covers a central area between two trench gate electrodes 3 for the contact of the base layer 5 to the emitter electrode 3. Finally an emitter electrode 2 and a collector electrode 25 are made.
The dopants can be introduced by any appropriate method like implantation or deposition. Diffusion steps can be made directly after the introducing of the corresponding dopant, but can also be perfomed at a later stage, e.g. for the base layer 4, the p well 5 being made with a diffusion step, their doping profile decreases from a maximum value steadily to the maximum diffusion depth of the dopant (which depends on the dopant sort and the diffusion conditions like diffusion time and temperature). It should be noted that the term "comprising" does not exclude other elements or steps and that the indefinite article "a" or "an" does not exclude the plural. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.
List of reference symbols
1 IGBT
10 wafer
1 1 Emitter side
12 First side
15 Collector side
16 Second side
100 active cell
1 10 dummy cell
120, 130, 140, 150, 160 prior art IGBT
2 Emitter electrode
25 Collector electrode
3 Trench gate electrode
31 Planar gate
300 Pitched trench gate
32 Electrically conductive layer
34 First insulating layer
36 Second insulating layer
38 Third insulating layer
39 Recess
4 Base layer
5 Well
6 Enhancement layer
7 First source region
75 Second source region
8 Drift layer
85 Buffer layer
9 Collector layer
95 First region

Claims

C L A I M S
1 . Insulated gated bipolar transistor having layers between an emitter electrode (2) on an emitter side (1 1 ) and a collector electrode (25) on a collector side (15) opposite to the emitter side (1 1 ), comprising:
- a drift layer (8) of a first conductivity type,
- a collector layer (9) of the second conductivity type different than the first conductivity type, which is arranged between the drift layer (8) and the collector electrode (25) and which electrically contacts the collector electrode (25),
- a base layer (4) of a second conductivity type, which base layer (4) is arranged between the drift layer (8) and the emitter electrode (2), which base layer (4) electrically contacts the emitter electrode (2),
- a first source region (7) of the first conductivity type, which is arranged on the base layer (4) towards the emitter side (1 1 ) and electrically contacts the emitter electrode (2), which first source region (7) has a higher doping concentration than the drift layer (8),
- a trench gate electrode (3), which is arranged lateral to the base layer (4) and extends deeper into the drift layer (8) than the base layer (4) and which trench gate electrode (3) is separated from the base layer (4), the first source region (7) and the drift layer (8) by a first insulating layer (34), wherein a channel is formable between the emitter electrode (2), the first source region (7), the base layer (4) and the drift layer (8),
- a well (5) of the second conductivity type, which is arranged lateral to the base layer (4) and extends deeper into the drift layer (8) than the base layer (4),
- an enhancement layer (6) of the first conductivity type, which surrounds the base layer (4) such that the enhancement layer (6) completely separates the base layer (4) from the drift layer (8) and the well (5), - additionally to the emitter electrode (2) an electrically conducting layer
(32), which covers the well (5), wherein the electrically conductive layer (32) is separated from the well (5) by a second electrically insulating layer (36), - a third insulating layer (38), which is arranged on the emitter side (1 1 ) on top of the trench gate electrode (3), the electrically conductive layer (32) and those parts of the base layer (4), the enhancement layer (6) and the drift layer (8) lying between the trench gate electrode (3) and the well (5), and which has a recess (39) on top of the electrically conducting layer (32) such that the electrically conducting layer (32) electrically contacts the emitter electrode (2).
Insulated gated bipolar transistor (1 ) according to claim 1 , characterized in that a second source region (75) of the first conductivity type is arranged at the emitter side (1 1 ) on the base layer (4) between the trench gate electrode (3) and the well (5), wherein the second source region (75) extends from the first electrically insulating layer (34) at least to a border of the second electrically insulating layer (36), which second source region (75) has a higher doping concentration than the drift layer (8).
Insulated gated bipolar transistor (1 ) according to any of the claims 1 and 2, characterized in that the well (5) extends deeper into the drift layer (8) than the trench gate electrode (3).
Insulated gated bipolar transistor (1 ) according to any of the claims 1 to 3, characterized in that a buffer layer (85) of the first conductivity type having a higher doping concentration than the drift layer (8) is arranged between the drift layer (8) and the collector layer (9).
Insulated gated bipolar transistor (1 ) according to any of the claims 1 to 4, characterized in that the insulated gated bipolar transistor (1 ) further comprises a first region (95) of the first conductivity type, which is arranged on the collector side (15) laterally to the collector layer (9), which first region (95) has a higher doping concentration than the drift layer (8).
Insulated gated bipolar transistor (1 ) according to any of the claims 1 to 5, characterized in that the electrically conductive layer (32) is made of the same material as the trench gate electrode (3).
Insulated gated bipolar transistor (1 ) according to any of the claims 1 to 6, characterized in that the insulated gated bipolar transistor (1 ) further comprises a bar (45) of the second conductivity type having a higher doping
concentration than the base layer (4), which bar (45) is arranged at the emitter side (1 1 ) in a plane parallel to the emitter side (1 1 ) perpendicular to the direction, in which the first source regions (7) attach the trench gate electrode (3) and at which bar the first source region (7), the base layer (4) and the trench gate electrode (3) terminate.
8. Insulated gated bipolar transistor (1 ) according to claim 6, characterized in that the well (5) extends to the bar.
9. Insulated gated bipolar transistor (1 ) according to claim 6, characterized in that the well (5) is separated from the bar by at least one of the enhancement layer
(6) and the base layer (4).
10. Insulated gated bipolar transistor (1 ) according to any of the claims 1 to 8, characterized in that the electrically conducting layer (32) additionally covers such part of the enhancement layer (6), which extends to the emitter side (1 1 ) in an area between the well (5) and the first insulating layer (34), and extends to a region above the base layer (4), wherein the electrically conducting layer
(32) is separated from these layers (4, 5, 6) by the second electrically insulating layer (36).
1 1 . Insulated gated bipolar transistor (1 ) according to any of the claims 1 to 9, characterized in that the drift layer (8) extends to the second electrically insulating layer (36) in an area between the well (5) and the enhancement layer (6).
12. Insulated gated bipolar transistor (1 ) according to any of the claims 1 to 10, characterized in that the second electrically insulating layer (36) has a thickness between 50 to 150 nm.
13. Method for manufacturing an insulated gated bipolar transistor, wherein the following manufacturing steps are performed:
- providing a lowly doped wafer of a first conductivity type having an emitter side and a collector side, part of which wafer having unamended low doping in the finalized insulated gated bipolar transistor (1 ) forming a drift layer (8),
- applying a mask and introducing a first dopant of a second conductivity type, which is different than the first conductivity type, for forming a well (5),
- making a trench recess on the emitter side (1 1 ), coating the trench recess with a first insulating layer (34) and filling coated trench recess with an electrically conductive material such that a trench gate electrode (3) is formed,
- forming a second insulating layer (36), which covers the well (5), - forming an electrically conductive layer (32) on top of the second insulating layer (36),
- creating an enhancement layer (6) by introducing a second dopant of the first conductivity type and diffusing the second dopant into the wafer using the electrically conductive layer (32) as a mask,
- after introduction of the second dopant creating a base layer (4) by introducing a third dopant of the second conductivity type, using the electrically conductive layer (32) as a mask, and diffusing the third dopant into the wafer to a lower depth from the emitter side (1 1 ), into which the second dopant has been diffused,
- creating a collector layer (9) by introducing a fourth dopant of the
second conductivity type on the collector side (15), and diffusing the fourth dopant into the wafer,
- introducing a fifth dopant of the first conductivity type using at least the electrically conductive layer (32) as a mask for forming first source regions (7),
- applying a third insulating layer (38) on top of the electrically conductive layer (32), which third insulating layer (38) has a recess (39) on the electrically conductive layer (32) for a contact of the electrically conductive layer (32) to the emitter electrode (2) and a contact opening to the base layer (4),
- applying an emitter electrode (2) and a collector electrode (25).
14. Method for manufacturing an insulated gated bipolar transistor, according to claim 13, characterized in that
- first applying the third insulating layer (38) on top of the electrically conductive layer (32) such that the third insulating layer (38) laterally extends to the trench gate electrode (3), which third insulating layer (38) has a contact opening to the base layer (4),
- introducing a fifth dopant of the first conductivity type using the third insulating layer (38) and the electrically conductive layer (32) as a mask for forming first source regions (7).
PCT/EP2012/063303 2011-07-07 2012-07-06 Insulated gate bipolar transistor WO2013004829A1 (en)

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GB1400075.6A GB2506075B (en) 2011-07-07 2012-07-06 Insulated gate bipolar transistor
KR1020147003224A KR101840903B1 (en) 2011-07-07 2012-07-06 Insulated gate bipolar transistor
DE112012002823.6T DE112012002823B4 (en) 2011-07-07 2012-07-06 Insulated-gate bipolar transistor and method of making such a bipolar transistor
CN201280033829.0A CN103650148B (en) 2011-07-07 2012-07-06 Igbt
US14/149,412 US9105680B2 (en) 2011-07-07 2014-01-07 Insulated gate bipolar transistor

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