JP2015153854A - silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which has high withstand voltage and which is capable of a fast switching operation.SOLUTION: A silicon carbide semiconductor device 100 comprises: a silicon carbide substrate 10; a gate insulation film 91; and a gate electrode 92. The gate insulation film 91 contacts a bottom BT and side parts SW of a trench TR. The gate electrode 92 contacts the gate insulation film 91 inside the trench TR. A fourth impurity region 84 has a first field relaxation region 11 provided between a boundary 82a between a second impurity region 82 and a first impurity region 81 and a second principal surface 10b, a second field relaxation region 12 provided between the bottom BT of the trench TR and the second principal surface 10b, and a third field relaxation region 13 which links a part of a circumference of the first field relaxation region 11 and a part of a circumference of the second field relaxation region 12 in planar view.

Description

  The present invention relates to a silicon carbide semiconductor device, and more particularly to a silicon carbide semiconductor device having a gate insulating film.

  2. Description of the Related Art In recent years, silicon carbide has been increasingly used as a material for semiconductor devices in order to enable higher breakdown voltages, lower losses, and use in high-temperature environments for semiconductor devices such as MOSFETs (Metal Oxide Field Effect Transistors). It is being Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

  In the case of a MOSFET in which a gate insulating film is provided in a trench, the electric field tends to concentrate particularly at the bottom of the trench. For example, Japanese Unexamined Patent Application Publication No. 2009-117593 (Patent Document 1) describes a MOSFET in which a p-type RESURF region is provided at a position deeper than a trench. According to one embodiment of the MOSFET, the p-type RESURF region is provided immediately below the bottom of the trench. The p-type RESURF region alleviates electric field concentration at the bottom of the trench.

JP 2009-117593 A

  However, in a MOSFET in which a p-type RESURF region is provided immediately below the bottom of the trench, it is difficult to switch at high speed.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a silicon carbide semiconductor device having a high breakdown voltage and capable of high-speed switching operation. .

  A silicon carbide semiconductor device of the present invention includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, and separated from the first impurity region. Provided on the second impurity region, constituting a first main surface and having the first conductivity type, and separated from the second impurity region by the first impurity region, and second And a fourth impurity region having a conductivity type. A trench is provided in the first main surface of the silicon carbide substrate. The trench is formed by a side portion that penetrates through the third impurity region and the second impurity region to reach the first impurity region, and a bottom portion that is located in the first impurity region. The gate insulating film is in contact with the bottom and sides of the trench. The gate electrode is in contact with the gate insulating film inside the trench. The fourth impurity region includes a first electric field relaxation region provided between the second impurity region and the boundary between the first impurity region and the second main surface, and between the bottom of the trench and the second main surface. And a third electric field relaxation region connecting a part of the outer periphery of the first electric field relaxation region and a part of the outer periphery of the second electric field relaxation region in plan view.

  According to the present invention, a silicon carbide semiconductor device having a high breakdown voltage and capable of high-speed switching operation can be provided.

1 is a partial cross-sectional schematic diagram schematically showing a configuration of a silicon carbide semiconductor device according to a first embodiment of the present invention. FIG. 2 is a partial perspective schematic view schematically showing a shape of a silicon carbide substrate included in the silicon carbide semiconductor device of FIG. 1. FIG. 3 is a partial plan view schematically showing a cross section in a region III-III in FIG. 1 and showing a planar structure of an embedded p-type region. It is a partial plane schematic diagram which shows the planar structure of the 1st modification of a buried p-type area | region. It is a partial plane schematic diagram which shows the planar structure of the 2nd modification of a buried p-type area | region. It is a partial plane schematic diagram which shows the planar structure of the 3rd modification of a buried p-type area | region. It is a partial plane schematic diagram which shows the planar structure of the 4th modification of a buried p-type area | region. FIG. 3 is a partial cross-sectional schematic diagram schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 7 is a partial cross-sectional schematic diagram schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 7 is a partial cross-sectional schematic diagram schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 7 is a partial cross-sectional schematic diagram schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 10 is a partial schematic cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 12 is a partial cross-sectional schematic diagram schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 10 is a partial schematic cross sectional view schematically showing a seventh step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 12 is a partial cross-sectional schematic diagram schematically showing an eighth step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 11 is a partial schematic cross sectional view schematically showing a ninth step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 12 is a partial cross-sectional schematic diagram schematically showing a tenth step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 12 is a partial cross-sectional schematic diagram schematically showing an eleventh step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 22 schematically shows a configuration of a silicon carbide semiconductor device according to a second embodiment of the present invention, and is a partial cross-sectional schematic diagram in region XIX-XIX in FIG. 20. FIG. 20 is a partial plan view schematically showing a cross section in a region XX-XX in FIG. 19 and showing a planar structure of a buried p-type region and a buried n-type region. It is a figure which shows typically the breadth of a depletion layer in 100 to several thousand microseconds after MOSFET is turned on. It is a figure which shows typically the breadth of a depletion layer in case MOSFET is OFF. It is a figure which shows typically the breadth of a depletion layer immediately after MOSFET is turned on.

[Description of Embodiment of Present Invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

  First, the reason why it is difficult to perform high-speed switching in the MOSFET in which the buried p-type region is provided immediately below the bottom of the trench will be described.

  Referring to FIG. 21, a depletion layer is formed at the boundary between the buried p-type region and the n drift region. The region that is not depleted satisfies the electrical neutral condition. There are no carriers in the depletion layer, and an electric field is generated by space charge. Referring to FIG. 22, when the MOSFET is turned off, some or all of the holes (carriers) disappear in the buried p-type region. The buried p-type region is depleted and charged to a negative voltage due to the remaining space charge. Referring to FIG. 23, when the MOSFET is turned on, electrons are quickly injected into the n drift region to recover the electrical neutrality. However, the hole is not injected into the buried p-type region and the negative potential is maintained, and the depletion layer from the buried p-type region remains, so that the MOSFET exhibits high resistance. Referring to FIG. 21, 100 to several thousand microseconds after the MOSFET is turned on, holes are gradually injected into the buried p-type region to restore electrical neutrality. As the depletion layer shrinks, the resistance decreases and current begins to flow between the source electrode and the drain electrode of the MOSFET. For the above reasons, it is considered difficult to perform high-speed switching in a MOSFET in which a buried p-type region is provided immediately below the bottom of the trench.

  (1) Silicon carbide semiconductor device 100 according to the embodiment includes a silicon carbide substrate 10, a gate insulating film 91, and a gate electrode 92. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a. Silicon carbide substrate 10 includes a first impurity region 81 having a first conductivity type, a second impurity region 82 provided on first impurity region 81 and having a second conductivity type different from the first conductivity type, A third impurity region 83 which is provided on the second impurity region 82 so as to be separated from the impurity region 81 and constitutes the first main surface 10 a and which has the first conductivity type, and the second impurity region 81, And a fourth impurity region 84 which is separated from impurity region 82 and has the second conductivity type. Trench TR is provided in first main surface 10a of silicon carbide substrate 10. Trench TR is formed by side SW passing through third impurity region 83 and second impurity region 82 to first impurity region 81, and bottom BT located in first impurity region 81. Gate insulating film 91 is in contact with bottom BT and side SW of trench TR. Gate electrode 92 is in contact with gate insulating film 91 inside trench TR. The fourth impurity region 84 includes a first electric field relaxation region 11 provided between the second impurity region 82 and the boundary portion 82a of the first impurity region 81 and the second main surface 10b, and a bottom portion BT of the trench TR. The second electric field relaxation region 12 provided between the second main surface 10b and a part of the outer periphery of the first electric field relaxation region 11 and a part of the outer periphery of the second electric field relaxation region 12 are connected in plan view. And a third electric field relaxation region 13.

  Silicon carbide semiconductor device 100 according to (1) includes first electric field relaxation region 11 provided immediately below second impurity region 82, second electric field relaxation region 12 provided immediately below bottom portion BT of trench TR, The first electric field relaxation region 11 and the second electric field relaxation region 12 are connected by the third electric field relaxation region 13. Thereby, when the silicon carbide semiconductor device is switched from the off state to the on state, the second electric field relaxation region 11 passes through the first electric field relaxation region 11 and the third electric field relaxation region 13, and the second electric field relaxation region 12 Since carriers (holes) are supplied quickly, the depletion layer can be quickly eliminated. Therefore, switching from the off state to the on state can be performed at high speed while the electric field at the bottom portion BT of the trench TR is relaxed by the second electric field relaxation region 12 provided immediately below the bottom portion BT of the trench TR. As a result, a silicon carbide semiconductor device having a high breakdown voltage and capable of high-speed switching operation can be provided. In plan view, the third electric field relaxation region 13 is formed so as to connect a part of the outer periphery of the first electric field relaxation region 11 and a part of the outer periphery of the second electric field relaxation region 12. It is possible to suppress the region 13 from greatly blocking the current path. Therefore, the on-resistance of the silicon carbide semiconductor device can be reduced.

  (2) Preferably in silicon carbide semiconductor device 100 according to (1) above, in the direction along the normal direction of second main surface 10b, boundary surface 82b between second impurity region 82 and side SW, The region 20 sandwiched between the second main surface 10 b and the region sandwiched between the first electric field relaxation region 11 and the second electric field relaxation region 12 includes a first impurity region 81. That is, since the first impurity region 81 is arranged directly under the channel instead of the third electric field relaxation region 13, the current easily flows to the drain electrode, so that the on-resistance of the silicon carbide semiconductor device can be reduced. it can.

  (3) Preferably in silicon carbide semiconductor device 100 according to (1) or (2) above, in plan view, one of first electric field relaxation region 11 and second electric field relaxation region 12 corresponds to first electric field relaxation region 11 and It arrange | positions so that the other of the 2nd electric field relaxation area | region 12 may be enclosed. As a result, carriers supplied to eliminate the depletion layer can quickly diffuse in the relaxation region.

  (4) Preferably in silicon carbide semiconductor device 100 according to (3) above, one of first electric field relaxation region 11 and second electric field relaxation region 12 is formed along a polygonal outer shape in plan view. . Thereby, cells can be arranged with high density.

  (5) Preferably in silicon carbide semiconductor device 100 according to (4) above, the polygon is a hexagon. Thereby, the cells can be arranged with higher density.

  (6) Preferably in silicon carbide semiconductor device 100 according to (4) or (5) above, third electric field relaxation region 13 is one of first electric field relaxation region 11 and second electric field relaxation region 12 at a polygonal corner. Is in contact with In the corner portion of the polygon, the channel length formed on the boundary surface 82b of the side portion SW is longer than that in the other portions, the channel resistance is increased, and the on-current hardly flows. For this reason, when the 3rd electric field relaxation area | region 13 is arrange | positioned in the corner | angular part of a polygon, the increase in on-resistance can be suppressed compared with the case where the 3rd electric field relaxation area | region 13 is arrange | positioned in another part.

  (7) Preferably in silicon carbide semiconductor device 100 according to (1) or (2) above, second electric field relaxation region 12 has a stripe shape in plan view. Thereby, the degree of freedom regarding the area and arrangement of the first electric field relaxation region 11 and the third electric field relaxation region 13 is increased, and the depletion layer elimination speed and the on-resistance can be easily designed.

  (8) Preferably in silicon carbide semiconductor device 100 according to any one of (1) to (7), second electric field relaxation region 12 is provided separately from bottom portion BT of trench TR. As a result, current easily flows to the drain electrode side, so that the on-resistance of silicon carbide semiconductor device 100 can be reduced.

  (9) Preferably in silicon carbide semiconductor device 100 according to any one of (1) to (8) above, first electric field relaxation region 11, second electric field relaxation region 12, and third electric field relaxation region 13 are: Have the same impurity concentration. Thereby, the 1st electric field relaxation area | region 11, the 2nd electric field relaxation area | region 12, and the 3rd electric field relaxation area | region 13 can be formed in one process.

  (10) Preferably in silicon carbide semiconductor device 100 according to any one of (1) to (8) above, each of first electric field relaxation region 11 and third electric field relaxation region 13 is more than second electric field relaxation region 12. Has a high impurity concentration. Thereby, carriers (holes) can be effectively injected from the first electric field relaxation region 11 and the third electric field relaxation region 13 into the second electric field relaxation region without increasing the on-resistance so much.

  (11) Preferably in silicon carbide semiconductor device 100 according to any of (1) to (10) above, silicon carbide substrate 10 is sandwiched between first electric field relaxation region 11 and second electric field relaxation region 12. Further, a fifth impurity region 85 is provided which has a first conductivity type and has an impurity concentration higher than that of the first impurity region 81. Thereby, an increase in on-resistance due to a depletion layer extending laterally from the fourth impurity region 84 can be effectively suppressed.

  (12) Preferably in silicon carbide semiconductor device 100 according to any of (1) to (11) above, the first conductivity type is n-type and the second conductivity type is p-type. Thereby, high channel mobility can be obtained.

[Details of the embodiment of the present invention]
(Embodiment 1)
First, the configuration of MOSFET as silicon carbide semiconductor device according to the first embodiment of the present invention will be described.

  With reference to FIGS. 1 to 3, MOSFET 100 according to the first embodiment includes silicon carbide substrate 10, gate insulating film 91, gate electrode 92, interlayer insulating film 93, source electrode 94, and source wiring 95. And a drain electrode 98. MOSFET 100 is preferably configured to be able to apply a voltage of 600 V or higher between source electrode 94 and drain electrode 98, in other words, has a breakdown voltage of 600 V or higher. That is, MOSFET 100 is preferably a power semiconductor device having a high breakdown voltage.

  Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 80 and a silicon carbide epitaxial layer 21 provided on silicon carbide single crystal substrate 80. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a. Silicon carbide epitaxial layer 21 constitutes first main surface 10a, and silicon carbide single crystal substrate 80 constitutes second main surface 10b. Silicon carbide single crystal substrate 80 preferably has, for example, a polytype 4H hexagonal crystal structure. Silicon carbide single crystal substrate 80 includes an impurity such as nitrogen and has n type. Silicon carbide epitaxial layer 21 includes drift region 81 (first impurity region), body region 82 (second impurity region), source region 83 (third impurity region), contact region 87, and buried p-type region. 84 (fourth impurity region).

Drift region 81 is a first impurity region containing a donor impurity such as nitrogen, for example, and has n type (first conductivity type). The impurity concentration of drift region 81 is preferably not less than 1 × 10 ¹⁵ cm ^{−3 and not} more than 5 × 10 ¹⁶ cm ⁻³ , for example, 8 × 10 ¹⁵ cm ⁻³ .

Body region 82 is provided on drift region 81. Body region 82 is a second impurity region containing an acceptor impurity such as aluminum, for example, and has a p-type (second conductivity type different from the first conductivity type). The impurity concentration of body region 82 is preferably 1 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less, for example 1 × 10 ¹⁸ cm ⁻³ .

  Source region 83 is a third impurity region provided on body region 82 so as to be separated from drift region 81 by body region 82. Source region 83 includes a donor impurity such as nitrogen or phosphorus and has n type. Source region 83 constitutes first main surface 10a of silicon carbide substrate 10. Source region 83 has a higher impurity concentration than drift region 81.

  Contact region 87 is an impurity region provided in contact with source region 83 on body region 82. Contact region 87 contains an acceptor impurity such as aluminum and has p-type. Contact region 87 has a higher impurity concentration than body region 82. Contact region 87 is provided through source region 83 so as to connect body region 82 and first main surface 10a.

  Buried p-type region 84 is a fourth impurity region separated from body region 82 by drift region 81. The outer periphery of the buried p-type region 84 is provided so as to be surrounded by the drift region 81. Buried p-type region 84 includes an acceptor impurity such as aluminum and has p-type. Details of the buried p-type region 84 will be described later.

  Trench TR is provided in first main surface 10a of silicon carbide substrate 10. Trench TR is provided on first main surface 10 a of silicon carbide epitaxial layer 21. Trench TR is formed by side SW and bottom BT connected to side SW. Side SW passes through source region 83 and body region 82 and reaches drift region 81. Side SW includes channel surface 82 b of MOSFET 100 on body region 82. Bottom portion BT is located in drift region 81.

  Side SW of trench TR is preferably inclined with respect to first main surface 10a of silicon carbide substrate 10. For example, the side SW is inclined so that the opening of the trench TR is tapered toward the bottom BT. The plane orientation of the side SW is preferably 50 ° or more and 70 ° or less with respect to the {0001} plane, and 50 ° or more and 70 ° or less with respect to the (000-1) plane. More preferred. Side SW of trench TR may be formed perpendicular to first main surface 10a of silicon carbide substrate 10. Bottom portion BT of trench TR may have a flat shape substantially parallel to first main surface 10a of silicon carbide substrate 10. Trench TR may have a U-shape or a V-shape in a cross-sectional view (a visual field viewed along a direction parallel to second main surface 10b of silicon carbide substrate 10).

  FIG. 2 shows the silicon carbide substrate 10 taken out from the MOSFET 100 of FIG. 1, and FIG. 1 corresponds to the cross section of the region II in FIG. Referring to FIG. 2, source region 83 and body region 82 are exposed at side SW of trench TR. Drift region 81 is exposed at each of side SW and bottom BT of trench TR. A portion where bottom portion BT and side portion SW are connected constitutes a corner portion of trench TR, and electric field concentration tends to occur at the corner portion. In the present embodiment, trench TR extends so as to form a mesh having a honeycomb structure in a plan view (a visual field viewed along the normal direction of second main surface 10b of silicon carbide substrate 10). . In plan view, first main surface 10a of silicon carbide substrate 10 formed of source region 83 and contact region 87 has a polygonal shape, preferably a hexagonal shape. In plan view, each of body region 82, source region 83, and contact region 87 has a hexagonal outer shape.

Referring to FIG. 1, buried p-type region 84 includes a first electric field relaxation region 11, a second electric field relaxation region 12, and a third electric field relaxation region 13. Each of first electric field relaxation region 11, second electric field relaxation region 12, and third electric field relaxation region 13 is a p-type region containing an acceptor impurity such as aluminum. The first electric field relaxation region 11, the second electric field relaxation region 12, and the third electric field relaxation region 13 may have the same impurity concentration, or may have different impurity concentrations. Preferably, each of first electric field relaxation region 11 and third electric field relaxation region 13 has a higher impurity concentration than second electric field relaxation region 12. The impurity concentration of each of the first electric field relaxation region 11 and the third electric field relaxation region 13 is, for example, about 1 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁸ cm ⁻³ . The impurity concentration of each second electric field relaxation region 12 is, for example, about 1 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁷ cm ⁻³ .

  First electric field relaxation region 11 is provided between boundary portion 82 a of body region 82 and drift region 81 and second main surface 10 b of silicon carbide substrate 10. That is, the first electric field relaxation region 11 is provided immediately below the body region 82. Preferably, first electric field relaxation region 11 is located closer to second main surface 10b than bottom BT of trench TR in the normal direction of second main surface 10b. Second electric field relaxation region 12 is provided between bottom portion BT of trench TR and second main surface 10b of silicon carbide substrate 10. That is, the second electric field relaxation region 12 is provided immediately below the bottom portion BT of the trench TR. Second electric field relaxation region 12 may be in contact with bottom portion BT of trench TR or may be separated from bottom portion BT. Preferably, the first electric field relaxation region 11 is separated from the body region 82 to the second main surface 10b side by about 3 μm or less, and more preferably by about 2 μm or less. 1 indicates the flow of holes when the MOSFET is switched from the off state to the on state. The holes reach the first electric field relaxation region 11 from the body region 82 through the drift region 81, and are supplied from the first electric field relaxation region 11 to the second electric field relaxation region 12 through the third electric field relaxation region 13. Is done.

  Referring to FIG. 3, in a plan view, third electric field relaxation region 13 is provided so as to connect a part of the outer periphery of first electric field relaxation region 11 and a part of the outer periphery of second electric field relaxation region 12. . The shape of the outer periphery of first electric field relaxation region 11 is, for example, a polygon, and in the present embodiment, it is a hexagon. The shape of the outer periphery of the second electric field relaxation region 12 is, for example, a honeycomb shape. The third electric field relaxation region 13 may be provided so as to extend from one side of the first electric field relaxation region 11 having a hexagonal outer periphery to one side of the second electric field relaxation region 12 having a honeycomb shape.

  Referring to FIG. 3, first electric field relaxation region 11 is arranged so as to be surrounded by second electric field relaxation region 12 in plan view. In this case, the body region 82 is disposed so as to be surrounded by the gate electrode 92 in plan view. On the contrary, in FIG. 3, the arrangement of the first electric field relaxation region 11 may be replaced with the arrangement of the second electric field relaxation region 12. In other words, the second electric field relaxation region 12 may be disposed so as to be surrounded by the first electric field relaxation region 11. In this case, the gate electrode 92 is disposed so as to be surrounded by the body region 82 in plan view. That is, one of the first electric field relaxation region 11 and the second electric field relaxation region 12 may be disposed so as to surround the other of the first electric field relaxation region 11 and the second electric field relaxation region 12. Preferably, the third electric field relaxation region 13 extends from a part of the other outer periphery of the first electric field relaxation region 11 and the second electric field relaxation region 12 to one outer periphery of the first electric field relaxation region 11 and the second electric field relaxation region 12. It is formed to extend. In plan view, one of the first electric field relaxation region 11 and the second electric field relaxation region 12 is formed along a polygonal outer shape such as a quadrangle and a hexagon.

  Referring to FIG. 1, in a direction along the normal direction of second main surface 10b of silicon carbide substrate 10, boundary surface 82b between body region 82 and side portion SW of trench TR, and silicon carbide substrate 10 The region 20 sandwiched between the second main surface 10 b and the region sandwiched between the first electric field relaxation region 11 and the second electric field relaxation region 12 preferably includes a drift region 81. That is, part of the region 20 immediately below the channel surface 82 b and sandwiched between the first electric field relaxation region 11 and the second electric field relaxation region 12 is formed by the drift region 81. The first electric field relaxation region 11 may be provided only directly below a part of the body regions 82 among the plurality of body regions 82 separated from each other. That is, the first electric field relaxation region 11 is provided directly below a certain body region 82 and may not be provided directly below another body region 82.

  Referring to FIG. 3, in plan view, a third electric field relaxation region 13 is provided in a part of a region sandwiched between first electric field relaxation region 11 and second electric field relaxation region 12, and third electric field relaxation region A drift region 81 is provided in a portion where 13 is not provided.

  Referring to FIG. 4, third electric field relaxation region 13 may be in contact with one of first electric field relaxation region 11 and second electric field relaxation region 12 at a polygonal corner, for example. In the present embodiment, the third electric field relaxation region 13 is in contact with the corner of the first electric field relaxation region 11 having a hexagonal outer shape. The third electric field relaxation region 13 is in contact with the corner of the outer edge 12 a facing the first electric field relaxation region 11 in the second electric field relaxation region 12 provided so as to surround the first electric field relaxation region 11.

  Referring to FIG. 5, the outer periphery of first electric field relaxation region 11 may have a square shape in plan view. In this case, the shape of the cell is also a square shape. The second electric field relaxation region 12 may be provided in a lattice shape so as to surround the first electric field relaxation region having a square shape. The third electric field relaxation region 13 may be formed so as to extend from one side of the outer periphery of the first electric field relaxation region 11 to one side of the second electric field relaxation region 12 facing the one side. Further, the third electric field relaxation region 13 may be formed so as to extend from the corner of the outer periphery of the first electric field relaxation region 11 to the corner of the second electric field relaxation region 12 facing the corner.

  Referring to FIG. 6, in a plan view, first electric field relaxation region 11 and second electric field relaxation region 12 may have a stripe shape. In this case, the shape of the cell is also a stripe shape. In plan view, each of the first electric field relaxation region 11 and the second electric field relaxation region 12 has a rectangular shape, and one of the first electric field relaxation region 11 and the second electric field relaxation region 12 is the first electric field relaxation. It may be longer than the other of region 11 and second electric field relaxation region 12. The third electric field relaxation region 13 may be formed so as to extend from the long side of the rectangular first electric field relaxation region 11 to the long side of the rectangular second electric field relaxation region 12.

  Referring to FIG. 7, the length of first electric field relaxation region 11 is equal to the length of third electric field relaxation region 13 in the longitudinal direction (vertical direction in FIG. 7) of second electric field relaxation region 12. Good. Further, in the longitudinal direction of the second electric field relaxation region 12, the length of the first electric field relaxation region 11 may be larger or smaller than the length of the third electric field relaxation region 13.

  Referring to FIG. 1 again, gate insulating film 91 is in contact with bottom portion BT and side portion SW of trench TR. Gate insulating film 91 is made of, for example, a material containing silicon dioxide. Gate insulating film 91 is in contact with drift region 81 at bottom BT of trench TR, and is in contact with each of source region 83, body region 82, and drift region 81 at side SW of trench TR.

  Gate electrode 92 is provided inside trench TR so as to be in contact with gate insulating film 91 inside trench TR. The gate electrode 92 is made of polysilicon containing impurities, for example.

  Source electrode 94 is in contact with each of source region 83 and contact region 87 on first main surface 10a of silicon carbide substrate 10. The source electrode 94 is made of a material containing, for example, Ti, Al, and Si. The source electrode 94 is in ohmic contact with the source region 83. The source wiring 95 is in contact with the source electrode 94. Source wiring 95 is made of a material containing aluminum, for example.

  The interlayer insulating film 93 is provided on the gate electrode 92 and extends from one source electrode 94 to the other source electrode 94. Interlayer insulating film 93 is made of, for example, a material containing silicon dioxide, and electrically insulates gate electrode 92 and source electrode 94 from each other.

  Drain electrode 98 is in contact with silicon carbide single crystal substrate 80 on second main surface 10 b of silicon carbide substrate 10, and is electrically connected to drift region 81. The drain electrode 98 is made of a material containing, for example, NiSi or TiAlSi.

Next, a method for manufacturing MOSFET 100 according to the first embodiment will be described.
Referring to FIG. 8, first epitaxial layer 81 a is formed on silicon carbide single crystal substrate 80. Specifically, for example, by a CVD (Chemical Vapor Deposition) method using a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen gas (H ₂ ) as a carrier gas. First epitaxial layer 81 a containing silicon carbide is formed on silicon carbide single crystal substrate 80. In the epitaxial growth, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as impurities.

  Next, a buried p-type region 84 is formed. Referring to FIG. 9, an implantation mask (not shown) having an opening is formed on first epitaxial layer 81a, and impurities such as aluminum are introduced into first epitaxial layer 81a using the implantation mask. Ion implanted. Thereby, the 1st electric field relaxation area | region 11, the 2nd electric field relaxation area | region 12, and the 3rd electric field relaxation area | region 13 are formed. The third electric field relaxation region 13 is provided so as to connect the first electric field relaxation region 11 and the second electric field relaxation region 12. The first electric field relaxation region 11, the second electric field relaxation region 12, and the third electric field relaxation region 13 may have the same impurity concentration, or may have different impurity concentrations. Preferably, each of first electric field relaxation region 11 and third electric field relaxation region 13 has a higher impurity concentration than second electric field relaxation region 12. The first electric field relaxation region 11, the second electric field relaxation region 12, and the third electric field relaxation region 13 may be formed at the same time or may be formed by separate ion implantation. For example, each of the first electric field relaxation region 11 and the third electric field relaxation region 13 is formed at the same time, and the second electric field relaxation region 12 forms the first electric field relaxation region 11 and the third electric field relaxation region 13. It may be formed by a different ion implantation process.

  Next, the second epitaxial layer 81b is formed. As shown in FIG. 10, after the buried p-type region 84 is formed, a second epitaxial layer 81b containing silicon carbide is formed on first epitaxial layer 81a. The buried p-type region 84 is formed so as to be sandwiched between the first epitaxial layer 81a and the second epitaxial layer 81b. The second epitaxial layer 81b can be formed by a method similar to the method for forming the first epitaxial layer 81a.

  Next, body region 82 and source region 83 are formed. Referring to FIG. 11, body region 82 is formed by ion implantation of an impurity such as aluminum from the upper surface of second epitaxial layer 81 b. Also, source region 83 is formed by implanting impurities such as phosphorus into body region 82 at a depth shallower than body region 82. Instead of ion implantation, body region 82 and source region 83 may be formed by epitaxial growth with addition of impurities. Next, an impurity such as aluminum is ion-implanted into source region 83 to form contact region 87 (see FIG. 12).

  Next, heat treatment (activation annealing) is performed to activate the impurities ion-implanted into silicon carbide substrate 10. The temperature of activation annealing is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The activation annealing time is, for example, about 30 minutes. The atmosphere of activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

  Next, trench TR is formed in first main surface 10a of silicon carbide substrate 10. Referring to FIG. 13, mask layer 40 having an opening is formed on first main surface 10 a formed of source region 83 and contact region 87. As mask layer 40, for example, a silicon oxide film or the like can be used. The opening is formed corresponding to the position of trench TR (FIG. 1).

As shown in FIG. 14, in the opening of the mask layer 40, the source region 83, the body region 82, and a part of the drift region 81 are removed by etching. As an etching method, for example, reactive ion etching (RIE), particularly inductively coupled plasma (ICP) RIE can be used. Specifically, for example, ICP-RIE using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas can be used. By such etching, in the region where the trench TR (FIG. 1) is to be formed, the side portion substantially perpendicular to the first main surface 10a, the side portion is connected, and the first main surface 10a A recess TQ having a substantially parallel bottom is formed.

Next, thermal etching is performed in the recess TQ. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, Cl ₂ , BCL ₃ , SF ₆ , or CF ₄ . For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. or more and 1000 ° C. or less.

Note that the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon gas, helium gas or the like can be used. As described above, when the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower, the etching rate of SiC is, for example, about 70 μm / hour. Further, during the thermal etching, the mask layer 40 made of silicon oxide has a very high selectivity with respect to SiC, so that it is not substantially etched during the etching of SiC.

  As shown in FIG. 15, trench TR is formed in first main surface 10a of silicon carbide substrate 10 by the thermal etching described above. Trench TR is formed by side SW that passes through source region 83 and body region 82 and reaches drift region 81, and bottom BT located on drift region 81. Preferably, side SW of trench TR is inclined with respect to bottom BT, and the angle of side SW with respect to bottom BT is, for example, not less than 50 ° and not more than 70 °. Each of side portion SW and bottom portion BT is separated from buried p-type region 84. When each of the source region 83, the body region 82, and the drift region 81 is thermally etched to form the side portion SW of the trench TR, the mask layer 40 is not substantially etched, so that the mask layer 40 has the first main surface. It is left so that it may protrude from 10a on side SW of trench TR. Next, the mask layer 40 is removed by an arbitrary method such as etching.

  Next, a gate insulating film 91 is formed. Gate insulating film 91 is formed by thermally oxidizing silicon carbide substrate 10 in which trench TR is formed. Specifically, gate insulating film 91 is formed by heating silicon carbide substrate 10 in which trench TR is formed at, for example, about 1300 ° C. in an atmosphere containing oxygen. As shown in FIG. 16, gate insulating film 91 is formed so as to cover side SW and bottom BT of trench TR and first main surface 10a.

  After thermally oxidizing silicon carbide substrate 10, heat treatment (NO annealing) may be performed on silicon carbide substrate 10 in a nitrogen monoxide (NO) gas atmosphere. In NO annealing, silicon carbide substrate 10 is held for about 1 hour under conditions of a temperature of 1100 ° C. or higher and 1300 ° C. or lower. As a result, nitrogen atoms are introduced into the interface region between the gate insulating film 91 and the body region 82. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. As long as such nitrogen atoms can be introduced, a gas other than NO gas may be used as the atmospheric gas. Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The heating temperature for Ar annealing is preferably the same as or higher than the heating temperature for NO annealing, and is lower than the melting point of the gate insulating film 91. The time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of the interface state in the interface region between the gate insulating film 91 and the body region 82 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.

  Next, the gate electrode 92 is formed. As shown in FIG. 17, gate electrode 92 in contact with gate insulating film 91 is formed inside trench TR. Gate electrode 92 is arranged inside trench TR and is formed to face each of side portion SW and bottom portion BT of trench TR with gate insulating film 91 interposed therebetween. The gate electrode 92 is formed by, for example, LPCVD (Low Pressure Chemical Vapor Deposition).

  Next, an interlayer insulating film 93 is formed. Specifically, an interlayer insulating film 93 is formed so as to cover the gate electrode 92 and to be in contact with the gate insulating film 91. Preferably, the interlayer insulating film 93 is formed by a deposition method, more preferably a chemical vapor deposition method. Interlayer insulating film 93 is a material containing, for example, silicon dioxide.

  Next, the source electrode 94 is formed. Specifically, etching is performed so that openings are formed in the interlayer insulating film 93 and the gate insulating film 91, and the source region 83 and the contact region 87 are exposed from the interlayer insulating film 93 through the openings. Next, source electrode 94 in contact with each of source region 83 and contact region 87 is formed on first main surface 10a of silicon carbide substrate 10. Source electrode 94 is made of a material containing, for example, Ti, Al, and Si. Next, alloying annealing is performed. Specifically, source electrode 94 in contact with each of source region 83 and contact region 87 is held at a temperature of 900 ° C. or higher and 1100 ° C. or lower for about 5 minutes, for example. Thereby, at least a part of source electrode 94 reacts with silicon contained in silicon carbide substrate 10 to be silicided to form an alloy. As a result, a source electrode 94 that is in ohmic contact with the source region 83 is formed (see FIG. 18).

  Next, a source wiring 95 that is electrically connected to the source electrode 94 is formed. Source wiring 95 is formed on source electrode 94 and interlayer insulating film 93. Next, drain electrode 98 is formed in contact with second main surface 10b of silicon carbide substrate 10. As described above, MOSFET 100 (FIG. 1) according to the first embodiment is obtained.

Next, the function and effect of the MOSFET according to the first embodiment will be described.
MOSFET 100 according to the present embodiment has first electric field relaxation region 11 provided immediately below body region 82 and second electric field relaxation region 12 provided immediately below bottom portion BT of trench TR, The first electric field relaxation region 11 and the second electric field relaxation region 12 are connected by the third electric field relaxation region 13. Thus, when the MOSFET 100 is switched from the off state to the on state, carriers (holes) are passed from the body region 82 to the second electric field relaxation region 12 through the first electric field relaxation region 11 and the third electric field relaxation region 13. ) Is supplied quickly, so that the depletion layer can be quickly eliminated. Therefore, switching from the off state to the on state can be performed at high speed while the electric field at the bottom portion BT of the trench TR is relaxed by the second electric field relaxation region 12 provided immediately below the bottom portion BT of the trench TR. As a result, it is possible to provide the MOSFET 100 having a high breakdown voltage and capable of high-speed switching operation. In plan view, the third electric field relaxation region 13 is formed so as to connect a part of the outer periphery of the first electric field relaxation region 11 and a part of the outer periphery of the second electric field relaxation region 12. It is possible to suppress the region 13 from greatly blocking the current path. Therefore, the on-resistance of MOSFET 100 can be reduced.

  Further, according to MOSFET 100 according to the present embodiment, in a direction along the normal direction of second main surface 10b of silicon carbide substrate 10, boundary surface 82b of side portion SW between body region 82 and trench TR, Region 20 sandwiched between second main surface 10 b of silicon carbide substrate 10 and sandwiched between first electric field relaxation region 11 and second electric field relaxation region 12 includes drift region 81. That is, since the drift region 81 is disposed directly under the channel instead of the third electric field relaxation region 13, the current easily flows to the drain electrode 98. Therefore, the on-resistance of MOSFET 100 can be reduced.

  Furthermore, according to MOSFET 100 according to the present embodiment, one of first electric field relaxation region 11 and second electric field relaxation region 12 surrounds the other of first electric field relaxation region 11 and second electric field relaxation region 12 in plan view. Are arranged as follows. As a result, carriers supplied to eliminate the depletion layer can quickly diffuse in the relaxation region.

  Furthermore, according to MOSFET 100 according to the present embodiment, one of first electric field relaxation region 11 and second electric field relaxation region 12 is formed along a polygonal outer shape in plan view.

  Furthermore, according to MOSFET 100 according to the present embodiment, the polygon is a hexagon. Thereby, the cells can be arranged with higher density.

  Furthermore, according to MOSFET 100 according to the present embodiment, third electric field relaxation region 13 is in contact with one of first electric field relaxation region 11 and second electric field relaxation region 12 at a polygonal corner. In the corner portion of the polygon, the channel length formed on the boundary surface 82b of the side portion SW is longer than that in the other portions, the channel resistance is increased, and the on-current hardly flows. For this reason, when the 3rd electric field relaxation area | region 13 is arrange | positioned in the corner | angular part of a polygon, the increase in on-resistance can be suppressed compared with the case where the 3rd electric field relaxation area | region 13 is arrange | positioned in another part.

  Furthermore, according to MOSFET 100 according to the present embodiment, second electric field relaxation region 12 has a stripe shape in plan view. Thereby, the degree of freedom regarding the area and arrangement of the first electric field relaxation region 11 and the third electric field relaxation region 13 is increased, and the depletion layer elimination speed and the on-resistance can be easily designed.

  Furthermore, according to MOSFET 100 according to the present embodiment, second electric field relaxation region 12 is provided apart from bottom BT of trench TR. This makes it easier for current to flow to the drain electrode side, so that the on-resistance of MOSFET 100 can be reduced.

  Furthermore, according to MOSFET 100 according to the present embodiment, first electric field relaxation region 11, second electric field relaxation region 12, and third electric field relaxation region 13 have the same impurity concentration. Thereby, the 1st electric field relaxation area | region 11, the 2nd electric field relaxation area | region 12, and the 3rd electric field relaxation area | region 13 can be formed in one process.

  Furthermore, according to MOSFET 100 according to the present embodiment, each of first electric field relaxation region 11 and third electric field relaxation region 13 has a higher impurity concentration than second electric field relaxation region 12. Thereby, carriers (holes) can be effectively injected from the first electric field relaxation region 11 and the third electric field relaxation region 13 into the second electric field relaxation region without increasing the on-resistance so much.

  Furthermore, according to MOSFET 100 according to the present embodiment, the first conductivity type is n-type and the second conductivity type is p-type. Thereby, high channel mobility can be obtained.

(Embodiment 2)
Next, the structure of MOSFET as a silicon carbide semiconductor device according to the second embodiment of the present invention will be described. MOSFET 100 according to the second embodiment is different from MOSFET 100 according to the first embodiment in that silicon carbide substrate 10 has buried n-type regions 85 and 86, and other configurations are the same as those in the first embodiment. This is almost the same as the MOSFET 100. Therefore, the same code | symbol is attached | subjected about the same or corresponding element, and the description is not repeated.

Referring to FIGS. 19 and 20, silicon carbide substrate 10 has embedded n-type regions 85 and 86 provided between first electric field relaxation region 11 and second electric field relaxation region 12. Yes. Buried n-type regions 85 and 86 are fifth impurity regions containing an impurity such as nitrogen, for example, and have an n-type (first conductivity type) conductivity type. Buried n-type regions 85 and 86 have a higher impurity concentration than drift region 81. Preferably, buried n-type regions 85 and 86 have an impurity concentration of 1.5 to 5 times the impurity concentration of drift region 81. The impurity concentration of buried n-type regions 85 and 86 is preferably lower than that of buried p-type region 84. The impurity concentration of buried n-type regions 85 and 86 is, for example, about 4 × 10 ¹⁶ cm ⁻³ .

  Referring to FIG. 20, buried n-type regions 85 and 86 are preferably separated from each of first electric field relaxation region 11, second electric field relaxation region 12 and third electric field relaxation region 13. In plan view, the buried n-type region 85 is disposed so as to cover most of the outer periphery of the first electric field relaxation region 11 and is surrounded by the second electric field relaxation region 12. The embedded n-type region 86 has a hexagonal outer shape in plan view and is disposed so as to be surrounded by the second electric field relaxation region 12.

  According to the present embodiment, silicon carbide substrate 10 is provided between first electric field relaxation region 11 and second electric field relaxation region 12, has an n type, and is higher in impurity than drift region 81. It further includes a buried n-type region 85 having a concentration. Thereby, an increase in on-resistance due to a depletion layer extending in the lateral direction from the buried p-type region 84 can be effectively suppressed.

  In each of the above embodiments, the MOSFET is described as an example of the silicon carbide semiconductor device. However, the silicon carbide semiconductor device may be an IGBT (Insulated Gate Bipolar Transistor). In each of the above embodiments, the n-type is the first conductivity type and the p-type is the second conductivity type. However, the p-type is the first conductivity type and the n-type is the second conductivity type. Good. In this case, the donor and acceptor in the above description are also replaced. Further, the silicon carbide semiconductor device does not necessarily have to have a silicon carbide single crystal substrate, and the silicon carbide single crystal substrate may be omitted.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

DESCRIPTION OF SYMBOLS 10 Silicon carbide substrate 10a 1st main surface 10b 2nd main surface 11 1st electric field relaxation region 12 2nd electric field relaxation region 12a Outer edge 13 3rd electric field relaxation region 21 Silicon carbide epitaxial layer 40 Mask layer 80 Silicon carbide single crystal substrate 81 Drift region (first impurity region)
81a First epitaxial layer 81b Second epitaxial layer 82 Body region (second impurity region)
82a Boundary portion 82b Boundary surface (channel surface)
83 Source region (third impurity region)
84 buried p-type region (fourth impurity region)
85 buried n-type region (fifth impurity region)
86 n-type region 87 contact region 91 gate insulating film 92 gate electrode 93 interlayer insulating film 94 source electrode 95 source wiring 98 drain electrode 100 MOSFET (silicon carbide semiconductor device)
BT Bottom SW Side TQ Recess TR Trench

Claims (12)

A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface;
The silicon carbide substrate includes a first impurity region having a first conductivity type;
A second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type;
A third impurity region provided on the second impurity region so as to be separated from the first impurity region, constituting the first main surface, and having the first conductivity type;
A fourth impurity region separated from the second impurity region by the first impurity region and having the second conductivity type;
A trench is provided in the first main surface of the silicon carbide substrate,
The trench is formed by a side portion that penetrates through the third impurity region and the second impurity region to reach the first impurity region, and a bottom portion that is located in the first impurity region.
A gate insulating film in contact with the bottom and the side of the trench;
A gate electrode in contact with the gate insulating film inside the trench,
The fourth impurity region includes a first electric field relaxation region provided between the second impurity region and a boundary between the first impurity region and the second main surface, the bottom portion of the trench, and the first impurity region. A third electric field that connects a portion of the outer periphery of the first electric field relaxation region and a portion of the outer periphery of the second electric field relaxation region in plan view. A silicon carbide semiconductor device having a relaxation region.   A region sandwiched between a boundary surface between the second impurity region and the side portion and the second main surface in a direction along a normal line direction of the second main surface; 2. The silicon carbide semiconductor device according to claim 1, wherein a region sandwiched between one electric field relaxation region and said second electric field relaxation region includes said first impurity region.   2. The plan view, wherein one of the first electric field relaxation region and the second electric field relaxation region is disposed so as to surround the other of the first electric field relaxation region and the second electric field relaxation region. Item 3. A silicon carbide semiconductor device according to Item 2.   4. The silicon carbide semiconductor device according to claim 3, wherein said one of said first electric field relaxation region and said second electric field relaxation region is formed along a polygonal outer shape in plan view.   The silicon carbide semiconductor device according to claim 4, wherein the polygon is a hexagon.   6. The silicon carbide semiconductor device according to claim 4, wherein said third electric field relaxation region is in contact with said one of said first electric field relaxation region and said second electric field relaxation region at an angle of said polygon.   The silicon carbide semiconductor device according to claim 1, wherein the second electric field relaxation region has a stripe shape in plan view.   The silicon carbide semiconductor device according to claim 1, wherein the second electric field relaxation region is provided apart from the bottom portion of the trench.   9. The silicon carbide semiconductor device according to claim 1, wherein the first electric field relaxation region, the second electric field relaxation region, and the third electric field relaxation region have the same impurity concentration. .   9. The silicon carbide semiconductor device according to claim 1, wherein each of said first electric field relaxation region and said third electric field relaxation region has a higher impurity concentration than said second electric field relaxation region. .   The silicon carbide substrate is provided between the first electric field relaxation region and the second electric field relaxation region, has the first conductivity type, and has an impurity concentration higher than that of the first impurity region. The silicon carbide semiconductor device according to claim 1, further comprising a fifth impurity region.   The silicon carbide semiconductor device according to any one of claims 1 to 11, wherein the first conductivity type is an n-type and the second conductivity type is a p-type.

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