WO2013004072A1

WO2013004072A1 - Relaxation oscillator having low energy consumption and high performance

Info

Publication number: WO2013004072A1
Application number: PCT/CN2012/000884
Authority: WO
Inventors: 贺林
Original assignee: He Lin
Priority date: 2011-07-04
Filing date: 2012-06-28
Publication date: 2013-01-10
Also published as: CN102868396A

Abstract

Provided is a relaxation oscillator, comprising: a first and a second timing capacitors, a first and a second switch devices, a first and a second timing reference generators, a first and a second comparators, a first and a second charging paths, a first and a second discharging paths, a clock generator for generating a clock signal, a peak value reference generator for generating a peak value reference signal, and a sampling hold circuit. By using a high-precision sampling hold circuit, the signal value at the end of a charging or discharging stage of a timing capacitor is checked, and errors induced by charge injections are reduced. By means of feedback controls, the amplitude of the timing reference signal is automatically adjusted so as to compensate the changes in transmission delay, thereby precisely controlling the time of charging or discharging stage of the timing capacitors, and enhancing the stability of the oscillation frequency without increasing energy consumption.

Description

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A low power consumption high performance relaxation oscillator belongs to the technical field:

The present invention relates to an electronic circuit that focuses on a relaxed oscillator. Prior art and background technology:

Low-power design techniques are critical for wireless sensor networks that do not require frequent battery replacement. Since the data interaction between the wireless sensor nodes is sparse, it can be completed in a short time interval, so that the power consumption can be reduced by periodically waking up the sensing node and letting the node enter a sleep state at other times. purpose. Since the average power consumption is proportional to the relative ratio of the wake-sleep time, in order to reduce the average power consumption, it is necessary to reduce the waiting time spent on clock synchronization and communication channel detection, which translates into the accuracy of the clock (time reference) for each node. Claim.

Although the active quartz crystal can achieve tens of ppm accuracy, it is not suitable for wireless sensor networks due to its large size and high cost. Therefore, an on-chip fully integrated, relatively high-precision, low-power oscillator is required as a time reference.

The on-chip LC oscillator can achieve an accuracy of more than 100 ppm (refer to McCorquodale et al, IEEE Transactions on Circuits and Systems I, vol. 56, no. 5, pp. 943-956, May 2009), however due to this solution High-frequency oscillations are required, and power consumption is usually on the order of tens of mW, far exceeding the power budget of wireless sensor nodes. The ring oscillator operates in the sub-threshold region to achieve very low power consumption (several uW), but the accuracy can only be controlled at ±5%. The power consumption of the relaxation oscillator is similar to that of a ring oscillator, but the accuracy is relatively better, usually less than 1%, so it is ideal for wireless sensor networks.

Figure 1 is a circuit schematic of a conventional slack oscillator that provides periodic oscillating signals by staggering charge and discharge of capacitors 55, 60 (designated as timing capacitors to distinguish them from other capacitors). In addition to the timing capacitors 55, 60, the slack oscillator includes switching means 38, 43, charging paths 25, 30, discharge paths (also switches) 45, 50, comparators 15, 20, clock generator 0 (usually RS The latch can also be in other forms). The charging circuits 25 and 30 can be either a current source as shown in the figure or a resistor to precisely control the charging rates of the timing capacitors 55 and 60. The comparators 15, 20 compare the signals on the timing capacitors 54, 59 with the threshold voltages 5 and 10 (to distinguish them from the other threshold voltages, which are referred to as timing reference signals). The outputs of comparators 15, 20 control clock generator 0. Clock Generator 0 The output clock signals 85 and 90 control the switching devices 38 and 43, causing their interleaved pair of timing capacitors 55 and 60 to charge and discharge. The signal waveform of each node is shown in Figure 2.

From the time when the signal 54 (or 59) on the timing capacitor reaches the timing reference signal 5 (or 10) to the output change state of the clock generator 0, there is a transmission delay 1051, as shown in FIG. The propagation delay is mainly determined by the delay of the comparator. It is affected by factors such as the process, supply voltage, temperature, and input voltage variation. It is difficult to accurately control, resulting in changes in the oscillation frequency.

In order to improve the frequency variation caused by the uncertainty of the propagation delay, the traditional method is to reduce the transmission delay by the high-speed comparator and the high-speed digital circuit, but the power consumption of the comparator increases exponentially with the decrease of the delay, resulting in frequency accuracy. An insurmountable bottleneck. Tokunaga et al. of Japan's Panasonic Corporation proposed the concept of Power Average Feedback, which automatically adjusts the timing reference signal by detecting the average power of the oscillating signal to compensate for changes in transmission delay (refer to Y. Tokunaga, Et al., "An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage," ISSCC Dig. Tech. Papers, Feb. 2009, pp. 404-405) o But this method requires not only large The resistance component of the area also has problems such as inaccurate power detection, leakage on the timing capacitor due to leakage caused by power detection, and greatly limits the accuracy of this method.

In principle, the above problem can be avoided by replacing the power detection circuit described above with a sample-and-hold circuit to detect the signal at the end of the timing capacitor charging phase (Fig. 4). The conventional sample-and-hold circuit has at least one sample switch and a sample capacitor. The sampling switch is usually a MOS transistor. When the gate of the MOS transistor is coupled with a suitable control voltage, the crystal The body tube is turned on. However, due to the transistor's on-resistance, when the sampling switch is closed, the sampling capacitor does not immediately follow the change of the sampled signal, but has a response process. The smaller the on-resistance of the transistor, the response The faster the process. The signal on the timing capacitor is constantly changing. In order to accurately sample the signal value at the end of the charging phase, a fast response process, that is, a small on-resistance, is required. However, due to the transistor's on-off switching process, charge injection is applied to the sampling capacitor, which is itself one of the main sources of error in the sample-and-hold circuit. Reducing the on-resistance means an increase in the width of the transistor, which means an increase in charge injection. This drawback of the traditional sample-and-hold circuit makes it impossible to achieve higher precision. Purpose of the invention:

The invention aims at the problem that the oscillation frequency is unstable due to the uncertainty of the transmission delay in the relaxation oscillator, and proposes a novel high-precision sample-and-hold circuit to detect the signal value at the end of the timing capacitor charging (or discharge) phase, minus Small due to the error caused by charge injection, and through the feedback control, automatically adjust the amplitude of the timing reference signal to compensate for the change of the transmission delay, so that the timing of the charge (or discharge) phase of the timing capacitor is accurately controllable, and the power consumption is hardly increased. Under the premise, improve the stability of the oscillation frequency. The technical solution of the present invention - the method of staggering sample and hold by two sampling capacitors enables the sampling switch to have a long on-time, and uses a transistor with a small width and a large on-resistance to achieve accurate sampling, thereby reducing The charge injection error of the conventional sample-and-hold circuit improves the stability of the oscillation frequency.

It is worth mentioning that, for the convenience of description, only the case where the timing capacitor is charged by the current source (25, 30) or the resistor is discussed. In this case, the signal value at the end of the charging phase needs to be sampled. If you change the polarity of the slack oscillator, that is, discharge the timing capacitor through the current source or resistor, as shown in Figure 3, you need to sample the signal value at the end of the discharge phase.

The object of the invention is achieved by the following measures:

As shown in FIG. 1, the conventional relaxation oscillator includes a first timing capacitor 55, a second timing capacitor 60, a first switching device 38, a second switching device 43, a first charging path 25, a second charging path 30, and a first Discharge path 45 (also part of switch device 38), second discharge path 50 (also part of switch device 43), first comparator 15, second comparator 20, first timing reference generator 1, second Timing Reference Generator 2, Clock Generator 0 (usually an RS latch, or other form). The charging paths 25, 30 are current sources or resistors. The first switching device 38 includes switches 35 and 45. The state in which the switch 35 is closed, the switch 45 is open, and the timing capacitor 55 is charged through the first charging path 25 is defined as the first state of the first switching device 38. The state in which the switch 35 is opened and the switch 45 is closed, and the timing capacitor 55 is discharged through the first discharge path 45 is defined as the second state of the first switching device 38. The second switching device 43 includes switches 40 and 50. The switch 40 is closed, the switch 50 is opened, and the state in which the timing capacitor 60 is charged through the second charging path 30 is defined as the first state of the second switching device 43, the switch 40 is turned off, the switch 50 is closed, and the timing capacitor 60 is passed. The state in which the two discharge paths 50 are discharged is defined as the second state of the second switching device 43. The first timing reference generator 1 generates a first reference signal 5, and the second timing reference generator 2 generates a second reference signal 10. The first comparator 15 compares the signal 54 on the first timing capacitor with the timing reference signal 5, and the second comparator 20 compares the signal 59 on the second timing capacitor with the timing reference signal 10. The outputs of comparators 15, 20 control clock generator 0. The clock signals output from the clock generator 0, 85 and 90, control switch devices 38 and 43, such that they are interleaved in the first and second states, interleaving and discharging the timing capacitors 55 and 60. The signal waveform of each node is shown in Figure 2.

Our invention, based on the conventional relaxation oscillator shown in FIG. 1, replaces the first timing reference generator 1 with a first timing reference generator ₁₂₅ having first and second control terminals, and adds a new type of sample and hold. The circuit 105 and the peak reference generator 115 perform feedback control on the timing reference signal 5 through negative feedback. The simplified schematic is shown in FIG. Figure 5 shows the specific implementation details of the circuit. The sample and hold circuit 105 includes a first sampling capacitor 385 and a second sampling The capacitor 395, the first sample switch 355 and the second sampling switch 365, the first holding switch 345 and the second holding switch 375. The first hold switch 345 is coupled to the first sampling capacitor 385 and the output 104 of the sample and hold circuit, the second hold switch 375 is coupled to the second sampling capacitor 395 and the output 104 of the sample and hold circuit, the first sampling switch 355 is coupled with the timing capacitor 55 and the first The sampling capacitor 385, the second sampling switch 365 couples the timing capacitor 55 and the second sampling capacitor 395. In order to achieve interleaved sampling and holding of the first and second sampling capacitors, the clock generator 0 in the conventional slack oscillator is replaced with a new clock generator 300. In addition to the clock signals 85, 90, the clock generator 300 can also output a divided signal 315 for controlling the interleaving switching of the sampling capacitors 385, 395 between the sample and hold states. The divided signal 315 is divided by n times of the clock signals 85, 90, and n is greater than or equal to two. The frequency-divided signal 315 shown in FIG. 5 is divided by two (which may also be a clock signal of 85, 90 cycles of other integers greater than two). The divided signal 315 is a digital signal having a first level (high level) and a second level (low level).

When the frequency dividing signal 315 is at the first level (high level), the signal 314 is at a low level, the first holding switch 345 is closed, and the second holding switch 375 is disconnected from the first sampling switch 355, and the first sampling capacitor 385 is closed. The upper signal 348 is coupled to the output 104 of the sample and hold circuit; if the divided signal 315 is at the first level and the first switching device 38 is in the first state, the clock signal 85 is at a high level, and the second sampling switch 365 is closed. The second sampling capacitor 395 is charged simultaneously with the timing capacitor 55, and the signal ₃₆₈ is equal to the signal _54. If the frequency dividing signal 315 is at the first level and the first switching device 38 is in the second state, the clock signal 85 is at a low level. The second sampling switch 365 is open and the signal 368 on the second sampling capacitor 395 holds the signal value at the end of the charging phase of the timing capacitor 55.

When the frequency dividing signal 315 is at the second level (low level), the signal 314 is at a high level, the second holding switch 375 is closed, the first holding switch 345 is disconnected from the second sampling switch 365, and the first sampling capacitor 395 is closed. The upper signal 368 is coupled to the output 104 of the sample and hold circuit; if the divided signal 315 is at the second level and the first switching device 38 is in the first state, the clock signal 85 is at a high level, and the first sampling switch 355 is closed. The first sampling capacitor 385 is charged simultaneously with the timing capacitor 55, and the signal 348 is equal to the signal 54. If the frequency dividing signal 315 is at the second level and the first switching device 38 is in the second state, the clock signal 85 is at a low level. The first sampling switch 355 is turned off, and the signal 348 on the first sampling capacitor 385 holds the signal value at the end of the charging phase of the timing capacitor 55.

By interleaving sampling and holding as described above, the output 104 of the sample and hold circuit 105 is always equal to the signal value at the end of the charging phase of the timing capacitor 55.

The timing reference generator 125 is actually an amplifier, its first control terminal 104 is the inverting amplifier terminal of the amplifier, and the second control terminal 114 is the positive phase amplification terminal of the amplifier. The output of the sample and hold circuit 105 is coupled to a first control terminal 104 of the first timing reference generator, and the output of the peak reference generator 115 is coupled to a second control terminal 114 of the first timing reference generator to form a negative feedback such that The difference between the output signal 104 of the hold circuit 105 and the peak reference signal 114 is reduced. The timing and waveform of each node control signal are shown in Figure 6.

The divided signal 315 shown in FIG. 5 is divided by two, its frequency is equal to half of the frequency of the clock signals 85, 90, and the frequency is divided by the frequency of the clock signals 85, 90 and the frequency of the comparator output signals 75, 80. The frequency of signal 315 is also equal to half the frequency of the comparator output signals 75,80.

The implementation shown in Figure 5 only considers charging the timing capacitor with a current source (25, 30) or resistor. If the polarity of the slack oscillator is changed, the timing capacitor is discharged by the current source (25b, 30b) or the resistor, and the signal value at the end of the discharge phase (the second state of the switching device) needs to be sampled, as shown in FIG. .

When the frequency dividing signal 315b is at the first level (high level), the signal 314b is at a low level, the first holding switch 345b is closed, the second holding switch 375b is disconnected from the first sampling switch 355b, and the first sampling capacitor 385b is closed. The upper signal 348b is coupled to the output 104b of the sample and hold circuit; if the divided signal 315b is at the first level and the first switching device 38b is in the second state, the clock signal 85b is at a high level, and the timing capacitor 55b passes through the discharge path 25b. The discharge is performed, the second sampling switch 365b is closed, the second sampling capacitor 395b is simultaneously discharged with the timing capacitor 55b, and the signal 368b is equal to the signal 54b; if the frequency dividing signal 315b is at the first level and the first switching device 38b is in the first state At this time, the clock signal 85b is at a low level, the timing capacitor 55b is charged through the charging path 45b, the second sampling switch 365b is turned off, and the signal 368b on the second sampling capacitor 395b holds the signal value at the end of the discharging phase of the timing capacitor 55b.

When the frequency dividing signal 315b is at the second level (low level), the signal 314b is at a high level, and the second holding switch 375b is closed. The first hold switch 345b is disconnected from the second sampling switch 365b, the signal 368b on the first sampling capacitor 395b is coupled to the output 104b of the sample and hold circuit; if the divided signal 315b is at the second level and the first switching device 38b In the second state, the clock signal 85b is at a high level, the timing capacitor 55b is discharged through the discharge path 25b, the first sampling switch 355b is closed, the first sampling capacitor 385b is simultaneously discharged with the timing capacitor 55b, and the signal 348b is equal to the signal 54b. If the frequency dividing signal 315b is at the second level and the first switching device 38b is in the first state, the clock signal 85b is at a low level, the timing capacitor 55b is charged through the charging path 45b, and the first sampling switch 355b is turned off. Signal 348b on a sampling capacitor 385b holds the signal value at the end of the discharge phase of timing capacitor 55b.

By interleaving sampling and holding as described above, the output 104b of the sample and hold circuit 105b is always equal to the signal value at the end of the discharge phase of the timing capacitor 55b.

The timing reference generator 125b is actually an amplifier, its first control terminal 104b is the inverting amplification terminal of the amplifier, and the second control terminal 1 Mb is the positive phase amplification terminal of the amplifier. The output of the sample and hold circuit 105b is coupled to a first control terminal 104b of the first timing reference generator, and the output of the peak reference generator 115b is coupled to a second control terminal 114b of the first timing reference generator to form a negative feedback such that the sample is held The difference between the output signal 104b of the circuit 105b and the peak reference signal 114b is reduced.

The charging paths 25, 30 in the implementation shown in Figure 5 and the discharge paths 25b, 30b in the implementation shown in Figure 7 are current sources.

The charging paths 25, 30 in the implementation shown in Figure 5 and the discharge paths 25b, 30b in the implementation shown in Figure 7 can also be replaced by resistors.

To eliminate the low frequency noise and offset of amplifier 125, it can be modified into a chopper type amplifier, as shown in Figure 8. It includes a modulator 122 and a mixing amplifier 124. The modulator 124 has a first input 104, a second input 114, a first output 106, and a second output 116. The mixer amplifier 124 has a first input 106, a second input 116, and an output 5. The first input of amplifier 125 is the first input of modulator 122, the second input of amplifier 125 is the second input of modulator 122, and the output of amplifier 125 is the output of mixing amplifier 124. A first output of modulator 122 is coupled to a first input 106 of mixing amplifier 124, and a second output of modulator 122 is coupled to a second input 116 of mixing amplifier 124. Modulator 122 and mixing amplifier 124 are controlled by chopping clock 314. The chopping clock 314 is a digital control signal having a first level (high level) and a second level (low level). When the chopping clock 314 is at a first level, the signal 104 at the first input of the modulator 122 is coupled to the first output 106, and the signal 114 at the second input of the modulator 122 is coupled to the second output 116. The mixing amplifier 124 amplifies the signal on the second input 116 minus the signal on the first input 106. When the chopping clock 314 is at the second level, the signal 104 at the first input of the modulator 124 is coupled to the second output 116, and the signal 114 at the second input of the modulator 122 is coupled to the first output 106. The mixing amplifier 124 amplifies the signal on the first input 106 minus the signal on the second input 116. Advantages, characteristics or positive effects of the invention compared to the prior art:

The invention adopts a method of staggering sample and hold of two sampling capacitors, so that the sampling switch has a long on-time, and a transistor with a small width and a large on-resistance is used for accurate sampling, thereby reducing the traditional sample-and-hold circuit. Charge injection error, accurate sampling of the signal value at the end of the timing capacitor charging (or discharge) phase, and automatic adjustment of the amplitude of the timing reference signal through feedback control to compensate for changes in the transmission delay, so that the timing capacitor is charged (or discharged) The time of the phase is precisely controllable, and the stability of the oscillation frequency is improved without increasing the power consumption. BRIEF DESCRIPTION OF THE DRAWINGS:

Figure 1 Schematic diagram of the traditional relaxation oscillator clocked by the charging process

Figure 2 Figure 1 Signal timing and signal waveform of each node

Figure 3 is a schematic diagram of a conventional relaxation oscillator that is timed by a discharge process. Figure 4 Schematic diagram of the signal value at the end of the charging phase of the timing capacitor is read by the sample-and-hold circuit, and the schematic diagram of the negative feedback mechanism is used to automatically adjust the timing reference signal.

Figure 5 is a schematic diagram of applying a sample-and-hold circuit with two capacitors alternately sampled and held, reading the signal value at the end of the timing capacitor charging phase and feeding back the adjusted timing reference signal.

Figure 6 Figure 5 Signal timing and signal waveform of each node

Figure Ί Applying a sample-and-hold circuit with two capacitors alternately sampled and held, reading the signal value at the end of the timing capacitor discharge phase and feeding back the schematic diagram of adjusting the timing reference signal

Figure 8 Schematic diagram of the chopper amplifier

As shown in FIG. 5, the relaxation oscillator of the present invention includes a first timing capacitor 55, a second timing capacitor 60, a first switching device 38, a second switching device 43, a first charging path 25, a second charging path 30, and a first charging path. a discharge path 45, a second discharge path 50, a first comparator 15, a second comparator 20, a first timing reference generator 125, a second timing reference generator 130, a peak reference generator 115, a sample and hold circuit 105, Clock generator 300. The charging paths 25, 30 are current sources. The timing reference generators 125, 130 are actually amplifiers.

The first switching device 38 includes switches 35 and 45. The state in which the switch 35 is closed, the switch 45 is opened, and the timing capacitor 55 is charged through the first charging path 25 is defined as the first state of the first switching device 38. The state in which the switch 35 is opened and the switch 45 is closed, and the timing capacitor 55 is discharged through the first discharge path 45 is defined as the second state of the first switching device 38. The second shut-off device 43 includes switches 40 and 50. The switch 40 is closed, the switch 50 is opened, and the state in which the timing capacitor 60 is charged through the second charging path 30 is defined as the first state of the second switching device 43, the switch 40 is turned off, the switch 50 is closed, and the timing capacitor 60 is passed. The state in which the two discharge paths 50 are discharged is defined as the second state of the second switching device 43. The first timing reference generator 125 generates a first reference signal 5, and the second timing reference generator 130 generates a second reference signal 10. The first comparator 15 compares the signal 54 on the first timing capacitor with the timing reference signal 5, and the second comparator 20 compares the signal 59 on the second timing capacitor with the timing reference signal 10. The outputs of the comparators 15, 20 control the clock generator 300. The clock signals 85 and 90 output by the clock generator 300 control the switching devices 38 and 43, such that they are interleaved in the first and second states, and the timing capacitors 55 and 60 are alternately charged and discharged.

The sample and hold circuit 105 includes a first sampling capacitor 385 and a second sampling capacitor 395, a first sampling switch 355 and a second sampling switch 365, a first holding switch 345 and a second holding switch 375. The first hold switch 345 is coupled to the first sampling capacitor 385 and the output 104 of the sample and hold circuit, the second hold switch 375 is coupled to the second sampling capacitor 395 and the output 104 of the sample and hold circuit, the first sampling switch 355 is coupled with the timing capacitor 55 and the first The sampling capacitor 385, the second sampling switch 365 couples the timing capacitor 55 and the second sampling capacitor 395. To achieve interleaved sampling and holding of the first and second sampling capacitors, the clock generator 300 also outputs a divided signal 315 for controlling the interleaving switching of the sampling capacitors 385, 395 between the sample and hold states. The divided signal 315 is a digital signal having a first level (high level) and a second level (low level).

When the frequency dividing signal 315 is at the first level (high level), the signal 314 is at a low level, the first holding switch 345 is closed, and the second holding switch 375 is disconnected from the first sampling switch 355, the first sampling capacitor Signal 348 on 385 is coupled to output 104 of the sample and hold circuit; if divided signal 315 is at a first level and first switching device 38 is in a first state, clock signal 85 is at a high level, and second sampling switch 365 is closed. The second sampling capacitor 395 is charged simultaneously with the timing capacitor 55, and the signal 368 is equal to the signal 54. If the frequency dividing signal 315 is at the first level and the first switching device 38 is in the second state, the clock signal 85 is low. The second sampling switch 365 is turned off, and the signal 368 on the second sampling capacitor 395 holds the signal value at the end of the charging phase of the timing capacitor 55.

When the frequency dividing signal 315 is at the second level (low level), the signal 314 is at a high level, the second holding switch 375 is closed, the first holding switch 345 is disconnected from the second sampling switch 365, and the first sampling capacitor 395 is closed. The upper signal 368 is coupled to the output 104 of the sample and hold circuit; if the divided signal 315 is at the second level and the first switching device 38 is in the first state, the clock signal ⁸⁵ is at a high level, and the first sample is closed. The first sampling capacitor 385 is charged simultaneously with the timing capacitor 55, the signal 348 is equal to the signal 54; if the frequency dividing signal 315 is at the second level and the first switching device 38 is in the second In the state, the clock signal 85 is low, the first sampling switch 355 is turned off, and the signal 348 on the first sampling capacitor 385 holds the signal value at the end of the charging phase of the timing capacitor 55.

The output of the sample and hold circuit 105 is coupled to the first control terminal 104 of the first timing reference generator 125, and the output of the peak reference generator 115 is coupled to the second control terminal 114 of the first timing reference generator 125 to form a negative feedback. The difference between the output signal 104 of the sample and hold circuit 105 and the peak reference signal 114 is reduced.

The first timing reference generator 125 can be designed as a chopper type amplifier as shown in FIG. It includes a modulator 122 and a mixing amplifier 124. The modulator 124 has a first input 104, a second input 114, a first output 106, and a second output 116. Mixing amplifier 124 has a first input 106, a second input 116, and an output 5. The first input of amplifier 125 is the first input of modulator 122, the second input of amplifier 125 is the second input of modulator 122, and the output of amplifier 125 is the output of mixing amplifier 124. A first output of modulator 122 is coupled to a first input 106 of mixing amplifier 124, and a second output of modulator 122 is coupled to a second input 116 of mixing amplifier 124. Modulator 122 and mixing amplifier 124 are controlled by chopping clock 314. The chopping clock 314 is a digital control signal having a first level (high level) and a second level (low level). When the chopping clock 314 is at a first level, the signal 104 at the first input of the modulator 122 is coupled to the first output 106, and the signal 114 at the second input of the modulator 122 is coupled to the second output 116. The mixing amplifier 124 amplifies the signal on the second input 116 minus the signal on the first input 106. When chopping clock 314 is at a second level, signal 104 at the first input of modulator 124 is coupled to second output 116, and signal 114 at the second input of modulator 122 is coupled to first output 106. The mixing amplifier 124 amplifies the signal on the first input 106 minus the signal on the second input 116.

Claims

Claim WO 2013/004072 PCT/CN2012/000884

A relaxation oscillator comprising first and second timing capacitors, first and second switching devices, first and second timing reference generators, first and second comparators, first and second charging paths First and second discharge paths, a clock generator for generating a clock signal;

The switching device has first and second states;

The first timing reference generator generates a first timing reference signal, the second timing reference generator generates a second timing reference signal; the first state of the first switching device passes the first charging path to the The first timing capacitor is charged, and the second state of the first switching device discharges the first timing capacitor through the first discharging path;

The first state of the second switching device charges the second timing capacitor through the second charging path, and the second state of the second switching device passes the second discharging path to the second timing The capacitor is discharged;

The first comparator compares the signal on the first timing capacitor with the first timing reference signal,

The second comparator compares the signal on the second timing capacitor with the second timing reference signal;

The output of the comparator controls the clock generator, and the clock signal controls the switching device such that the first and second timing capacitors are staggered and discharged;

Its characteristics are:

Also included is a peak reference generator for generating a peak reference signal, a sample and hold circuit;

The sample and hold circuit includes first and second sampling capacitors, first and second sampling switches, first and second holding switches, the first holding switch coupling the first sampling capacitor and the sample and hold circuit Outputting, the second hold switch coupling the second sampling capacitor and an output of the sample and hold circuit, the first sampling switch coupling the first timing capacitor and the first sampling capacitor, the second sampling a switch coupling the first timing capacitor and the second sampling capacitor;

The clock generator further outputs a frequency-divided signal, the period of the frequency-divided signal is an integer multiple of a period of the clock signal, and the frequency-divided signal has first and second levels;

The frequency dividing signal and the clock signal control the sample and hold circuit, through the first and second steps, so that the sample and hold circuit outputs the first timing capacitor at the end of the first state of the first switching device Signal value - first step: when the frequency dividing signal is at the first level, the first holding switch is closed, the second holding switch is turned off, the first sampling switch is turned off, if the frequency dividing signal is at a first level and the first switching device is in a first state, the second sampling switch is closed, if the frequency dividing signal is at a first level and the first switching device is in a second state, the second The sample switch is turned off;

The second step: when the frequency dividing signal is at the second level, the second holding switch is closed, the first holding switch is turned off, the second sampling switch is turned off, if the frequency dividing signal is at the second level And the first sampling switch is closed when the switching device is in the first state, and the first sampling switch is turned off if the frequency dividing signal is at the second level and the switching device is in the second state;

Or through the third and fourth steps, causing the sample and hold circuit to output a signal value on the first timing capacitor at a second state end of the first switching device:

The second step: when the frequency dividing signal is at the first level, the first holding switch is closed, the second holding switch is turned off, the first sampling switch is turned off, if the frequency dividing signal is at the first level And the first switching device is in the second state, the second sampling switch is closed, and if the frequency dividing signal is at the first level and the first switching device is in the first state, the second sampling switch is off. Open

The fourth step: when the frequency dividing signal is at the second level, the second holding switch is closed, the first holding switch is turned off, the second sampling switch is turned off, if the frequency dividing signal is at the second level And the first sampling switch is closed when the switching device is in the second state, and the first sampling switch is turned off if the frequency dividing signal is at the second level and the switching device is in the first state;

The first timing reference generator further has first and second control terminals to adjust a size of the first timing reference signal; an output of the sample and hold circuit coupled to a first control of the first timing reference generator And the peak reference signal is coupled to the second control end of the first timing reference generator to adjust the timing reference signal such that a difference between the peak reference signals of the output signal of the sample and hold circuit is reduced.

2. The relaxation oscillator according to claim 1, wherein: the frequency division signal is a frequency division signal, and the frequency of the frequency division signal is half of a frequency of the output signal of the comparator. The relaxation oscillator of claim 1 wherein:

The timing reference generator is an amplifier having first and second inputs;

An output signal of the amplifier amplifies a signal on a second input of the amplifier minus a signal on the first input; a first input of the amplifier is a first control terminal of the timing reference generator The second input of the amplifier is the second control terminal of the timing reference generator, and the output of the amplifier is the output of the timing reference generator.

A relaxation oscillator according to the claims, characterized in that:

The charging path or the discharge path includes a current source.

The relaxation oscillator of claim 1 wherein:

The charging path or the discharge path includes a resistor.

A relaxation oscillator according to claim 3, characterized in that:

The clock generator also outputs a chopping clock, the chopping clock having first and second levels;

The amplifier further includes a modulator having first and second input terminals, first and second output terminals, a mixing amplifier having first and second input terminals and an output terminal;

a first input of the amplifier is a first input of the modulator, a second input of the amplifier is a second input of the modulator, and an output of the amplifier is the mixing amplifier Output

a first output of the modulator is coupled to a first input of the mixer amplifier, and a second output of the modulator is coupled to a second input of the mixer amplifier;

When the chopping clock is at a first level, a signal at a first input of the modulator is coupled to a first output of the modulator, and a signal at a second input of the modulator is coupled to the a second output of the modulator, the mixing amplifier amplifying a signal on the second input of the mixing amplifier minus a signal on the first input of the mixing amplifier;

When the chopping clock is at a second level, a signal at a first input of the modulator is coupled to a second output of the modulator, and a signal at a second input of the modulator is coupled to the At a first output of the modulator, the mixing amplifier amplifies a signal at a first input of the mixing amplifier minus a signal at a second input of the mixing amplifier.