WO2012153371A1 - Convertisseur a/n delta-sigma à fonction de correction de décalage du niveau continu - Google Patents

Convertisseur a/n delta-sigma à fonction de correction de décalage du niveau continu Download PDF

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Publication number
WO2012153371A1
WO2012153371A1 PCT/JP2011/004330 JP2011004330W WO2012153371A1 WO 2012153371 A1 WO2012153371 A1 WO 2012153371A1 JP 2011004330 W JP2011004330 W JP 2011004330W WO 2012153371 A1 WO2012153371 A1 WO 2012153371A1
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Prior art keywords
quantizer
offset
converter
integrator
input
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PCT/JP2011/004330
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English (en)
Japanese (ja)
Inventor
松川　和生
陽介 三谷
幸嗣 小畑
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パナソニック株式会社
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Publication of WO2012153371A1 publication Critical patent/WO2012153371A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/352—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M3/354—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M3/356—Offset or drift compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
    • H03M3/454—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Definitions

  • the present invention relates to a delta-sigma A / D converter, and more particularly to a technique for correcting an offset of an operational amplifier used in an integrator.
  • FIG. 7 is a diagram showing an example of a multi-cell current-driven D / A converter provided in the delta-sigma A / D converter.
  • the D / A converter 30 includes a plurality of cells 300, converts an input digital signal into an analog signal, and outputs the analog signal to an operational amplifier of the integrator (FIG. 7A).
  • Each cell 300 includes switches SW30 and SW31 and current sources 310, 311, and 312 connected to differential digital input signals (digital inverted input signal and digital non-inverting input signal) (FIG. 7B). Then, the switches SW30 and SW31 are controlled to be turned on / off by the differential digital input signal, current is output from one of the output terminals OUTP (+) and OUTM ( ⁇ ), and current is drawn from the other.
  • the current value of the current source 312 is set to a value larger than the current value of the current sources 310 and 311, for example, twice the value.
  • the digital forward rotation input signal becomes “H”
  • SW31 is turned on.
  • the digital inverted input signal becomes “L”, and therefore SW30 is turned off.
  • a difference current between the current source 312 and the current source 311 is drawn into OUTM ( ⁇ ), and the current of the current source 310 is output from OUTP (+).
  • a plurality of cells 300 are provided in parallel, and the D / A conversion is realized by connecting the output signals OUTP (+) and OUTM ( ⁇ ) of each cell 300 respectively.
  • each cell 300 has a parasitic capacitance C30.
  • An operational amplifier included in an integrator to which the output signals OUTP (+) and OUTM ( ⁇ ) of the D / A converter 30 are input has a differential input terminal (between the + side and the ⁇ side) due to manufacturing variation or the like. ) Has an offset. Due to the offset between the differential input terminals of the operational amplifier, different error charges are caused in the parasitic capacitance C30 of each cell 300 to be connected to the + side and the ⁇ side of the input terminal of the operational amplifier by the on / off control of the switches SW30 and SW31. Is accumulated. The error signal due to the accumulation of error charges deteriorates the characteristics of the A / D converter.
  • FIG. 8 is a diagram showing selection of each cell 300 of the D / A converter 30 in the DWA (Data Weighted Averaging) method which is a kind of DEM.
  • DWA Data Weighted Averaging
  • FIG. 8 shows an example of the D / A converter 30 having seven cells.
  • the control value (“H ( High) “or” L (Low) "), that is, which cell 300 the switch SW31 is turned on.
  • a signal obtained by inverting the control value of the switch SW31 is input to the switch SW30 to which the digitally inverted input signal is input.
  • the switch SW31 is turned on and the switch SW30 is turned off, while when “L”, the switch SW31 is turned off and the switch SW30 is turned on.
  • the selected cell 300 is shifted in order to reduce distortion due to a relative error caused by manufacturing variation among the cells 300 of the D / A converter 30.
  • the first cell and the second cell of the cell 300 are controlled to be “H”, that is, the first cell and the second cell.
  • SW31 is on-controlled
  • SW30 is off-controlled.
  • SW31 is controlled to be off while SW30 is controlled to be on.
  • the switch SW31 of the first cell and the second cell is turned off, and the SW31 of the third cell to the fifth cell is turned on, while the first cell, the second cell
  • the switch SW30 of the third cell is turned on, and the SW30 of the third to fifth cells is turned off.
  • the switch SW31 of the third cell to the fifth cell is turned off, and the SW31 of the sixth cell, the seventh cell, and the first cell is turned on, while 3
  • the switches SW30 of the fifth cell to the fifth cell are turned on, and the SW30 of the sixth cell, the seventh cell, and the first cell are turned off.
  • the shift operation as described above is similarly performed. As a result, distortion due to relative error due to manufacturing variations among the cells 300 of the D / A converter 30 is reduced.
  • the error signal due to the error charge due to the parasitic capacitance C30 of each cell 300 of the D / A converter 30 has a period twice that of the input analog signal. That is, the second harmonic of the input analog signal is generated, degrading the characteristics of the A / D converter (see Non-Patent Document 1 for details).
  • Measures against this problem are to reduce the parasitic capacitance C30 of each cell 300 of the D / A converter 30, and to reduce the offset of the operational amplifier included in the integrator.
  • the parasitic capacitance C30 has a limit even if it can be reduced by devising circuit constants and element layout. Therefore, the most effective means is to correct the offset of the operational amplifier included in the integrator and bring it close to “0”.
  • the specific offset voltage value to be corrected differs depending on the performance and accuracy required for the circuit or device on which the A / D converter is mounted. For example, the offset is 10 to 30 mV (an even larger offset due to manufacturing variations). It may be necessary to correct this to 5 mV or less.
  • an operational amplifier that causes a deterioration in characteristics is an operational amplifier used for an integrator of a loop filter, and is generally an operational amplifier that outputs a differential signal.
  • the offset correction method and the offset correction circuit disclosed in Patent Document 1 and Patent Document 2 are techniques for correcting the offset of a single-output operational amplifier, and applying this technique to an operational amplifier that outputs a differential signal is not possible. Have difficulty.
  • an object of the present invention is to realize offset correction of an operational amplifier used in a loop filter (integrator) of a delta sigma A / D converter with a small circuit scale.
  • a delta-sigma A / D converter includes an operational amplifier having an offset adjustment function, and uses the operational amplifier to integrate a difference between an input signal and a feedback signal, and the integrator A multi-cell configuration that digitally converts the integrator output signal output from, and D / A converts the quantizer output signal output from the quantizer and feeds back to the integrator as the feedback signal A DEM circuit provided between a feedback D / A converter, the quantizer and the feedback D / A converter, and distributing the quantizer output signal to each cell of the feedback D / A converter;
  • the operational amplifier which the integrator has by receiving the quantizer output signal and using the offset control signal based on the quantizer output signal In which it is provided an offset correction control unit for correcting the offset.
  • the offset correction control unit is used for the integrator of the loop filter by using the quantizer output signal output from the quantizer provided in the general delta-sigma A / D converter.
  • Perform offset correction of the operational amplifier thereby, offset correction can be performed with high accuracy without adding extra circuits such as a reference voltage and a comparator. That is, highly accurate offset correction can be realized with a small circuit scale.
  • a control circuit for controlling the circuit is necessary, and the influence on the circuit scale due to the increase of the offset correction control unit is the addition of a reference voltage or a comparator. Very small compared to.
  • the integrator of the delta-sigma A / D converter includes an input short-circuit switch that is connected between the differential input terminals of the operational amplifier and switches whether or not the differential input terminals are short-circuited. Is preferred.
  • the offset correction control unit controls the on / off operation of the input short switch by a first switch control signal, and the input short switch by the first switch control signal during offset correction. In this state, the differential input terminals are short-circuited, and the offset control signal is generated based on the quantizer output signal.
  • the offset correction control unit short-circuits the differential input terminals of the operational amplifier by the first switch control signal, and generates an offset control signal based on the quantizer output signal from the quantizer in this state. To do. Thereby, the offset of the operational amplifier can be corrected with high accuracy in a state where the differential input terminals of the operational amplifier are short-circuited. At this time, it is not necessary to add an extra circuit such as a reference voltage or a comparator, and highly accurate offset correction can be realized with a small circuit scale.
  • the offset correction control unit may correct the offset of the operational amplifier by the offset control signal based on the integrator output signal instead of the quantizer output signal.
  • high-precision DC offset correction can be realized with a small circuit scale in the delta-sigma A / D converter. This improves the distortion characteristics of the delta sigma A / D converter.
  • FIG. 1 is a diagram illustrating a configuration example of a delta-sigma A / D converter according to the first embodiment.
  • the delta sigma A / D converter 10 in FIG. 1 includes a loop filter 104, a quantizer input changeover switch 105, a quantizer 106, a DEM circuit 107, current-driven feedback D / A converters 108 and 109, and an offset.
  • a correction control unit 110 is provided.
  • the loop filter 104 includes an integrator 102 and a post-stage filter 103 connected to the subsequent stage.
  • the integrator 102 short-circuits between the operational amplifier 100 having an offset adjustment function and the differential input terminal of the operational amplifier 100. And an input short switch 101 for switching whether or not.
  • the post-stage filter 103 is a filter composed of an integrator, a resonator, and the like.
  • a quantizer input changeover switch 105 is provided between the post-stage filter 103 and the quantizer 106.
  • the quantizer input changeover switch 105 selects either the output signal from the integrator 102 before processing by the post-stage filter 103 or the signal output from the post-stage filter 103 via a resistor by a selection operation.
  • the connected signal is connected to the input of the quantizer 106.
  • the quantizer input changeover switch 105 selects a signal output from the post-filter 103 via a resistor and connects this signal to the input of the quantizer 106.
  • the input signal input to the delta sigma A / D converter 10 passes through the integrator 102 and the post filter 103 provided with the operational amplifier 100 and is converted into a digital value by the quantizer 106.
  • the converted digital value is fed back as an analog signal via the DEM circuit 107 and the feedback D / A converter 108, and a difference from the input signal is taken.
  • the delta sigma A / D converter 10 realizes delta sigma A / D conversion.
  • feedforward paths FP1 and FP2 are provided, and a part of the input signal passes through the feedforward path.
  • the offset correction control unit 110 outputs an offset control signal SC1, a drive stop signal SC2, and a switch control signal SC3, which will be described later, and an operational amplifier 100, an input short switch 101, a quantizer input changeover switch 105, and a feedback D / A conversion.
  • the devices 108 and 109 are controlled. In the present embodiment, description will be made assuming that both the input short switch 101 and the quantizer input changeover switch 105 are controlled by the switch control signal SC3. However, the control may be performed using separate control signals. Absent.
  • FIGS. 2A is a diagram illustrating a configuration example of the operational amplifier 100 having an offset adjustment function
  • FIG. 2B is a diagram illustrating a configuration example of the variable current sources 200 and 201 provided in the operational amplifier 100.
  • the offset adjustment of the operational amplifier 100 is a variable that supplies current to the input differential stage transistors Tr10 and Tr11 to which the differential input signals INM ( ⁇ ) and INP (+) are input to the gates. This can be realized by adjusting the differential balance of the current sources 200 and 201.
  • the operational amplifier 100 outputs the output signals OUTM ( ⁇ ) and OUTP (+) whose offsets are adjusted.
  • a bias voltage is applied to each of the bias terminals VBIAS1, VBIAS2, VBIAS3, and VBIAS4.
  • variable current sources 200 and 201 can be realized by a circuit diagram as shown in FIG. 2B, for example.
  • the variable current sources 200 and 201 in FIG. 2B are connected to the gates of a plurality of PMOS transistors Tr20 connected in parallel and a predetermined number (partially or all) of the PMOS transistors Tr20, and the power source or bias voltage VBIAS1.
  • a plurality of switches SW20 that connect the selected one and the gate of the transistor Tr20.
  • the selection operations of the plurality of switches SW20 of the variable current sources 200 and 201 are controlled by the offset control signals SC1A and SC1B, respectively.
  • the gate of the PMOS transistor Tr21 to which the switch SW20 is not connected is connected to the bias terminal VBIAS1.
  • the PMOS transistor Tr21 is not necessary.
  • variable current sources 200 and 201 connect a predetermined number of switches SW20 among the plurality of switches SW20 so that the bias voltage VBIAS1 is applied to the gate of the PMOS transistor Tr20.
  • the remaining switch SW20 is connected to the gate of the PMOS transistor Tr20 so that the power supply voltage is applied.
  • the operational amplifier 100 adjusts the offset of the differential input signals INM ( ⁇ ) and INP (+) by adjusting the current, and outputs the offset-adjusted output signals OUTM ( ⁇ ) and OUTP (+).
  • the range of the current that can be set by the variable current sources 200 and 201 is set to correct the assumed maximum offset generation amount for the assumed differential input signals INM ( ⁇ ) and INP (+). Set it to be larger than the required current value.
  • the settable current range (variable current width) of the variable current sources 200 and 201 may be set in advance or may be set from the outside.
  • variable current sources 200 and 201 are not limited to the above configuration as long as part or all of the supplied current can be varied.
  • the adjustment of the differential balance of the offset related to the operational amplifier 100 is not limited to the adjustment of the differential balance by current adjustment using the variable current sources 200 and 201.
  • the operational amplifier 100 is not limited to this configuration as long as it is an operational amplifier having an offset adjustment mechanism. For example, as in the operational amplifier 100A of FIG. 3, D / A converters 204 and 205 for applying a bias obtained by D / A converting the offset control signals SC1A and SC1B to the back gates of the input differential stage transistors Tr10 and Tr11, respectively. The offset may be adjusted using.
  • variable current sources 200 and 201 in FIG. 2 are not necessarily required, and in the example of FIG. 3, fixed current sources can be used for the current sources 202 and 203.
  • the offset control signals SC1A and SC1B input to the variable current sources 200 and 201 in FIG. 2 may increase or decrease the number of bits depending on the number of switches SW20.
  • a 4-bit signal is used when performing 16-stage current adjustment (for example, using 16 switches SW20), and a 5-bit signal is used when performing 32-stage current adjustment (for example, using 32 switches SW20). It is conceivable to use a signal.
  • offset control signal SC1A and the offset control signal SC1B may be used for the offset control signal SC1A and the offset control signal SC1B, or a part or all of the offset control signal SC1 may be shared.
  • FIG. 4 is a flowchart showing the operation of the delta-sigma A / D converter 10 in the control by the offset correction control unit 110, that is, the DC offset correction.
  • the quantizer 106 will be described as converting an input analog signal into a multi-bit digital signal.
  • the variable current source 200 will be described as a negative current source
  • the variable current source 201 will be described as a positive current source.
  • the variable current sources 200 and 201 each have 32 steps, and the current change is 1 ⁇ A per step. Further, when incrementing is repeated, the variable current sources 200 and 201 are alternately incremented step by step.
  • variable current source 200 may be a positive current source and the variable current source 201 may be a negative current source.
  • step number 32 and the step width 1 ⁇ A of the variable current sources 200 and 201 may be appropriately changed according to required accuracy, time available for offset adjustment, and the like.
  • the increment method for each step is not limited as long as the current can be changed stepwise, for example, one current source is incremented by several steps and then the other current source is incremented by several steps and then repeated. The method may be used. Further, it may be incremented by a plurality of steps.
  • preset values may be used, or a configuration may be set from the outside.
  • the offset correction control unit 110 sets the offset correction value of the operational amplifier 100 to the negative maximum value by the offset control signal SC1 (SC1A, SC1B) (step ST11). Specifically, the offset correction control unit 110 sets the current supplied from the variable current source 200 to the minimum value in the settable range by the offset control signal SC1 (SC1A, SC1B), while supplying from the variable current source 201. Set the current to the maximum value within the settable range.
  • the offset correction control unit 110 controls the input short switch 101 and the quantizer input changeover switch 105 by the switch control signal SC3 to short-circuit the differential input terminal of the operational amplifier 100 and to input the quantizer 106.
  • the output signal from the integrator 102 before the processing by the post-filter 103 is connected.
  • the offset correction control unit 110 stops driving the feedback D / A converters 108 and 109 by the drive stop signal SC2 (step ST12).
  • the output of the integrator 102 in which the differential balance of the operational amplifier 100 is tilted to the maximum on the negative side is input to the quantizer 106 via the quantizer input changeover switch 105.
  • the process waits for a predetermined time until the output of the integrator 102 is stabilized.
  • the offset correction control unit 110 determines whether or not the DC offset measurement value is positive based on the quantizer output signal from the quantizer 106 (step ST14). In step ST11 described above, since the differential balance of the operational amplifier 100 is tilted to the maximum in the negative side, the DC offset measurement value is negative at this time (“NO” in step ST14).
  • the offset correction control unit 110 increments the offset correction value of the operational amplifier 100 by one step in the positive direction related to the differential (step ST15), and waits for a predetermined time until the output of the integrator 102 is stabilized (step ST13).
  • incrementing the offset correction value by one step in the positive direction related to the differential means that the current supplied from the variable current source 200 that is set to the minimum value in step ST11 is incremented by one step in the positive direction related to the differential.
  • the current supplied from the current source 200 is increased by 1 ⁇ A. At this time, the current supplied from the variable current source 201 is not changed. In this state, the system waits for a predetermined time until the output of the integrator 102 is stabilized.
  • the offset correction control unit 110 determines whether or not the DC offset measurement value is positive based on the output signal of the quantizer 106 (step ST14). If the DC offset measurement value continues to be negative (“NO” in step ST14), the offset correction control unit 110 increments the offset correction value of the operational amplifier 100 in the positive direction related to the differential by one step (step ST15). Then, it waits for a predetermined time until the output of the integrator 102 is stabilized (step ST13).
  • “incrementing by 1 step in the positive direction related to differential” means that the current supplied from the variable current source 201 set to the maximum value in step ST11 is decreased by 1 ⁇ A. At this time, the current supplied from the variable current source 200 is not changed. In this state, the system waits for a predetermined time until the output of the integrator 102 is stabilized.
  • step ST14 when the measured value of the DC offset becomes positive (“Yes” in step ST14), that is, when the polarity of the output signal from the operational amplifier 100 is inverted, the offset correction control unit 110 is one step ahead.
  • the current DC offset measurement value is compared with the current DC offset measurement value to determine which DC offset measurement value is close to 0 (step ST16). Specifically, for example, when the differential is incremented by 31 steps in the positive direction, that is, 16 ⁇ A is added to the supply current of the variable current source 200 from the minimum value, and 15 ⁇ A is subtracted from the maximum value to the supply current of the variable current source 201. In this case, it is assumed that the measured value of the DC offset is positive, that is, it is determined as “Yes” in step ST14.
  • the case of incrementing 30 steps in the positive direction related to the differential which is one step before means adding 15 ⁇ A from the minimum value to the supply current of the variable current source 200 and increasing the supply current of the variable current source 201 from the maximum value. This is the case when 15 ⁇ A is reduced.
  • step ST16 it is determined which DC offset measured value is closer to 0 when the differential is incremented by 31 steps in the positive direction and when incremented by 30 steps.
  • step ST16 When the measured DC offset value is positive (current) is closer to 0 (“Yes” in step ST16), the current measured DC offset of the operational amplifier 100, that is, 31 steps in the above example.
  • the incremented value is held as an offset correction value, and the process is terminated (step ST17), that is, the normal operation is started.
  • step ST16 when one step before the DC offset measurement value becomes positive (previous) is closer to 0 (“NO” in step ST16), the previous DC offset measurement value of the operational amplifier 100, that is, 30 in the above example.
  • the step increment value is held as an offset correction value, and the process ends (step ST18), that is, shifts to a normal operation.
  • the offset correction of the operational amplifier 100 used for the loop filter 104 can be performed with high accuracy using the quantizer output signal digitally converted by the quantizer 106. Further, there is no need to add an extra circuit such as a reference voltage or a comparator.
  • step ST11 the offset correction value of the operational amplifier 100 is set to the negative maximum value, and the offset correction value is incremented in the positive direction related to the differential.
  • the offset correction is not limited to this method.
  • the offset correction value of the operational amplifier 100 may be set to a positive maximum value, and then this value may be incremented in the negative direction.
  • a method such as a binary search method may be used.
  • loop filter 104 is not limited to the configuration of FIG.
  • a configuration without the post-filter 103 or a configuration without the feedforward paths FP1 and FP2 can be considered.
  • an example of a configuration without the post filter 103 will be described.
  • FIG. 5 is a diagram illustrating another configuration example of the delta-sigma A / D converter according to the first embodiment. 5, the same reference numerals as those in FIG. 1 are attached to the same components as those in FIG. 1, and detailed description thereof is omitted here.
  • the difference from FIG. 1 is that the output of the integrator 102 is connected to the input of the quantizer 106 through a resistor because the loop filter 104A does not have the post-stage filter 103. It is a point that has been.
  • the output of the integrator 102 is directly connected to the input of the quantizer 106 when viewed from the plane of the signal potential of the output unit of the integrator 102 and the input unit of the quantizer 106 during offset correction. Therefore, the quantizer input changeover switch 105 connected to the preceding stage of the quantizer 106 in FIG. 1 is unnecessary.
  • the quantizer 106 may be configured by a flash A / D converter, for example.
  • the input signal of the quantizer 106 is connected to the gate of the input stage transistor. Further, when the offset is corrected, the feedback D / A converters 108 and 109 are not driven. Therefore, at the time of offset correction, the potentials of the signals at the output unit of the post-filter 103 and the input unit of the quantizer 106 are considered to be substantially equal. Therefore, even if a resistor is connected between the integrator 102 and the quantizer 106, it is considered to be substantially equivalent to a direct connection.
  • the offset correction of the operational amplifier 100 used in the loop filters 104 and 104A can be performed with high accuracy using the quantizer output signal digitally converted by the quantizer 106. . Further, offset correction can be performed with high accuracy without adding extra circuits such as a reference voltage and a comparator. That is, highly accurate offset correction can be realized with a small circuit scale. Note that a control circuit for controlling the circuit is also necessary for a general delta-sigma A / D conversion circuit, and the influence on the circuit scale due to the increase in the offset correction control unit 110 is compared with the addition of a reference voltage or a comparator. And very small.
  • the offset correction control unit 110 may share a signal and a circuit (for example, a counter) with a control circuit included in a general delta sigma A / D conversion circuit. Then, the degree of influence on the circuit scale due to the increase in the offset correction control unit 110 is further reduced.
  • a circuit for example, a counter
  • step ST14 the offset correction control unit 110 measures the DC offset at that time. The value is held as an offset correction value, and the process is terminated, that is, the normal operation is started.
  • FIG. 6 is a diagram illustrating a configuration example of a delta-sigma A / D converter according to the second embodiment.
  • the same components as those in FIG. 5 are denoted by the same reference numerals as those in FIG. 5, and detailed description thereof is omitted here.
  • the output of the integrator 102 is digitally converted by the quantizer 106, and the quantizer output signal output from the quantizer 106 is input to the offset correction unit 110.
  • the offset correction unit 110 performs offset correction based on the quantizer output signal.
  • the quantizer 106 such as a comparator or an A / D converter is unnecessary. Therefore, in this embodiment, the integrator output signal SD1 is directly input to the offset correction control unit 110 that is a logic circuit.
  • the delta-sigma A / D converters 10 and 10A since the integrator output signal SD1 is an analog output signal, the delta-sigma A / D converters 10 and 10A according to the first embodiment use the 1-bit quantizer 106 and The same operation is performed. That is, steps ST16 to ST18 are not necessary in the description of FIG. 4 described above, and when the DC offset measurement value becomes positive in step ST14 (“Yes” in step ST14), the offset correction control unit 110 performs the DC correction at that time. The offset measurement value is held as an offset correction value, and the process is terminated, that is, the normal operation is started.
  • the offset correction of the operational amplifier 100 used in the integrator 102 can be performed without using the quantizer 106.
  • offset correction can be performed with high accuracy without adding extra circuits such as a reference voltage and a comparator. That is, highly accurate offset correction can be realized with a small circuit scale.
  • the integrator output signal SD1 of the integrator 102 may be directly input to the offset correction control unit 110 that is a logic circuit.
  • the integrator output signal SD1 used in the present embodiment is not limited to the output signal OUTM ( ⁇ ) of the operational amplifier 100 illustrated in FIG.
  • the output signal OUTP (+) of the operational amplifier 100 may be used, or both output signals OUTM ( ⁇ ) and OUTP (+) may be used.
  • the operation of the offset correction control unit 110 may be started automatically at a predetermined timing such as when the power is turned on or after a predetermined time has elapsed since the power is turned on, or the start of processing is set from the outside. It may be configured.
  • the input short switch 101 and the quantizer input changeover switch 105 are controlled by the switch control signal SC3, and the feedback D / A converters 108 and 109 stop driving by the drive stop signal SC2.
  • the present invention is not limited to this.
  • the power may be turned on automatically at a predetermined timing such as when the power is turned on or after a predetermined time has elapsed since the power is turned on, and the normal operation state (off control) may be set after the processing by the offset correction control unit 110 ends.
  • the input short switch 101 is described as being connected between the differential input terminals of the operational amplifier 100 of the integrator 102, the present invention is not limited to this. For example, it may be connected between the differential input terminals of the integrator 102, or may be connected between the differential input terminals of the loop filter 104.
  • the delta-sigma A / D converter according to the present invention can improve the secondary distortion characteristic of the delta-sigma A / D converter with a small circuit scale. Therefore, it is useful in fields such as A / D converters for wireless receivers and audio, and A / D conversion of sensor signals.

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  • Analogue/Digital Conversion (AREA)

Abstract

L'invention porte sur un convertisseur A/N delta-sigma (10) qui comprend un intégrateur (102) comprenant un amplificateur opérationnel (100) à fonction d'ajustement de décalage, un quantificateur (106) pour une conversion numérique de signaux de sortie de l'intégrateur (102), un convertisseur N/A de rétroaction (108) pour une conversion N/A de signaux de sortie du quantificateur (106), un circuit DEM (107) agencé entre le quantificateur (106) et le convertisseur N/A de rétroaction (108), et une partie de commande de correction de décalage (110) qui, sur la base des signaux de sortie du quantificateur (106), corrige le décalage de l'amplificateur opérationnel (100) à l'aide d'un signal de commande de décalage (SC1).
PCT/JP2011/004330 2011-05-12 2011-07-29 Convertisseur a/n delta-sigma à fonction de correction de décalage du niveau continu WO2012153371A1 (fr)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015004829A1 (fr) * 2013-07-11 2015-01-15 パナソニック株式会社 Convertisseur numérique-analogique de courant, modulateur delta-sigma, et dispositif de communication
CN104635827A (zh) * 2014-12-12 2015-05-20 东南大学 直流失调消除电路
WO2015098057A1 (fr) * 2013-12-27 2015-07-02 株式会社ソシオネクスト Intégrateur, modulateur sigma-delta et dispositif de communication
JP2019057759A (ja) * 2017-09-19 2019-04-11 株式会社東芝 増幅回路、ａｄ変換器、無線通信装置、及びセンサシステム
JPWO2018135125A1 (ja) * 2017-01-17 2019-12-12 ソニーセミコンダクタソリューションズ株式会社 アナログ−デジタル変換器、固体撮像素子、及び、電子機器
CN113670357A (zh) * 2021-08-03 2021-11-19 深圳市汇川技术股份有限公司 信号处理方法及电路
WO2023162246A1 (fr) * 2022-02-28 2023-08-31 ファナック株式会社 Dispositif de détection de courant et dispositif d'entraînement de moteur muni de celui-ci

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001237706A (ja) * 2000-02-23 2001-08-31 Hitachi Ltd Δς型ａｄ変換器
JP2005026998A (ja) * 2003-07-02 2005-01-27 Renesas Technology Corp ビット変換回路またはシフト回路を内蔵した半導体集積回路およびａ／ｄ変換回路を内蔵した半導体集積回路並びに通信用半導体集積回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001237706A (ja) * 2000-02-23 2001-08-31 Hitachi Ltd Δς型ａｄ変換器
JP2005026998A (ja) * 2003-07-02 2005-01-27 Renesas Technology Corp ビット変換回路またはシフト回路を内蔵した半導体集積回路およびａ／ｄ変換回路を内蔵した半導体集積回路並びに通信用半導体集積回路

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015004829A1 (fr) * 2013-07-11 2015-01-15 パナソニック株式会社 Convertisseur numérique-analogique de courant, modulateur delta-sigma, et dispositif de communication
US9438268B2 (en) 2013-07-11 2016-09-06 Socionext Inc. Current type D/A converter, delta sigma modulator, and communications device
JPWO2015004829A1 (ja) * 2013-07-11 2017-03-02 株式会社ソシオネクスト 電流型ｄ／ａ変換器、デルタシグマ変調器および通信装置
WO2015098057A1 (fr) * 2013-12-27 2015-07-02 株式会社ソシオネクスト Intégrateur, modulateur sigma-delta et dispositif de communication
JPWO2015098057A1 (ja) * 2013-12-27 2017-03-23 株式会社ソシオネクスト 積分器、デルタシグマ変調器および通信装置
US9634688B2 (en) 2013-12-27 2017-04-25 Socionext Inc. Integrator, delta-sigma modulator, and communications device
CN104635827A (zh) * 2014-12-12 2015-05-20 东南大学 直流失调消除电路
JPWO2018135125A1 (ja) * 2017-01-17 2019-12-12 ソニーセミコンダクタソリューションズ株式会社 アナログ−デジタル変換器、固体撮像素子、及び、電子機器
JP2019057759A (ja) * 2017-09-19 2019-04-11 株式会社東芝 増幅回路、ａｄ変換器、無線通信装置、及びセンサシステム
CN113670357A (zh) * 2021-08-03 2021-11-19 深圳市汇川技术股份有限公司 信号处理方法及电路
WO2023162246A1 (fr) * 2022-02-28 2023-08-31 ファナック株式会社 Dispositif de détection de courant et dispositif d'entraînement de moteur muni de celui-ci

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