WO2012151410A1 - Novel doping process for solar cell manufacture - Google Patents

Novel doping process for solar cell manufacture Download PDF

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Publication number
WO2012151410A1
WO2012151410A1 PCT/US2012/036340 US2012036340W WO2012151410A1 WO 2012151410 A1 WO2012151410 A1 WO 2012151410A1 US 2012036340 W US2012036340 W US 2012036340W WO 2012151410 A1 WO2012151410 A1 WO 2012151410A1
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Prior art keywords
solar cell
phosphorous
tube
furnace
silicon
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PCT/US2012/036340
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French (fr)
Inventor
Jayendra Bhakta
Reese M. REYNOLDS
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Sandvik Thermal Process, Inc
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Publication of WO2012151410A1 publication Critical patent/WO2012151410A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates generally to the field of doping Si-based photovoltaic cells to form the emitter layer.
  • the fabrication of silicon wafer-based solar cells has generally utilized the diffusion of phosphorous (an n-type dopant) into p-doped (boron doped) substrates to form a P-N diode. This is true for both single crystalline and polycrystalline substrates. This P-N junction is responsible for the charge separation within the solar cell 15 once the electron-hole pairs have been formed by the absorption of the light in the solar cell. Generally, electrons and holes are known as carriers.
  • the electrons are conducted through the external circuit where they do work such as powering lights, etc. They recombine with holes at the rear surface of the solar cell and complete the circuit.
  • Carriers can recombine when they meet another carrier of the opposite charge, they can combine with defects or impurities within the bulk of the solar cell, and they can recombine at surfaces. All of these mechanisms decrease the efficiency of the solar cell.
  • the "quantum efficiency" of the solar cell is the ratio of the number of carriers collected by the solar cell to the number of photons of a given energy incident on the solar cell. The efficiency is sensitive to the wavelength of the light. As an example, blue light (shorter wavelengths) has a higher absorption coefficient and is strongly absorbed in the surface region of the solar cell. Red light (longer wavelengths) has a lower absorption coefficient and is transmitted deep into the bulk or through the solar cell.
  • the purpose of the solar cell is the generation of useful electrical power.
  • external circuit elements must be connected to the cell.
  • the resistance of the connections must be as low as possible.
  • good ohmic contacts (i.e. low resistance) to silicon are made by heavily doping the regions where the contact is made. However, this increases the
  • concentration of carriers in that region and increases the probability for recombination to occur in those regions. This issue is being addressed by selectively doping the regions of the silicon substrate to different levels. The contact regions are heavily doped and their area is minimized. The remainder of the surface is lightly doped to effectively absorb the light and generate the carriers.
  • the doping process is performed in a horizontal tube furnace.
  • a typical horizontal furnace will have 4 process tubes, each able to simultaneously process 500 or more wafers.
  • a P-containing source is introduced into the furnace.
  • the P-source of choice has been phosphorous oxy-chloride (POCb).
  • POCI3 is introduced at one end of the furnace along with O2.
  • the POCI3 and O2 react to form a deposit of P2O 5 on the surface that acts as a P- source for the doping of the Si.
  • the gases and by-products are exhausted at the other end of the tube.
  • PSG P-doped glass layer
  • the present invention provides process strategies for controlling the deposition of the P2O 5 on the surface as well as the diffusion of the dopant into the surface.
  • a novel time averaged approach to ensure uniform dopant at low dopant concentrations has been developed.
  • An exemplary method for doping a surface of p-type silicon with phosphorous to form an emitter region of a silicon based solar cell comprises positioning the silicon wafer in a vertical orientation within a furnace, and depositing a layer of P 2 O 5 on the surface of the silicon wafer by a plurality of sequenced deposition and annealing steps, wherein the sequenced deposition and annealing steps includes exposing the surface of the silicon wafer to a flow of POCI3 in a carrier gas and an oxidizing gas followed by diffusing the phosphorus into the silicon wafer.
  • FIG. 1 is a schematic of a horizontal furnace tube configuration.
  • FIG. 2 is a graph of sheet resistance versus phosphorous concentration.
  • FIG. 3 is a comparison of the standard recipe flow versus the Time Averaged Diffusion recipe flow.
  • FIG. 4 presents SIMS data comparing the phosphorous distribution for the Standard versus TAD processes.
  • FIG. 5 presents SIMS data of the near surface region comparing the phosphorous distribution for the Standard versus TAD processes.
  • FIG. 6 is a graph comparing the normalized device efficiency for the
  • FIG. 1 illustrates a schematic of a horizontal furnace tube assembly, 100.
  • a horizontal furnace system will comprise four tubes. Each tube is typically enclosed by a cylindrical heater (not shown) that gives the furnace a "flat zone" of 1440 mm.
  • the flat zone is defined as the length of the tube where the temperature deviates by less than 0.5°C after the system has stabilized.
  • 500 156mm x 156mm solar cell substrates can be easily accommodated within the flat zone.
  • the wafers can be loaded back-to-back and the tube can accommodate 1000 substrates. Future tube designs will further extend the flat zone to be able to process up to -2000 substrates per run by further extending the flat zone.
  • Furnace tube assembly, 100 includes a quartz tube, 102, that encloses the substrates.
  • Tube, 102 has a gas inlet, 104, and a gas outlet, 106.
  • the gas inlet is also known as the "source” and the gas outlet is known as the "load”.
  • the source describes the end of the tube where the source of the gas enters.
  • the load describes the end of the tube where the substrates are loaded. It will be clear to those skilled in the art that there are alternative configurations. For example, the "source" of the gas and the "loading" of the substrates can occur at the same end of the tube. The gas would be exhausted at the opposite end of the tube.
  • the tube may use a distributed gas injection system and a distributed exhaust system. Details of such a system are described in US patent application 12/71 1 ,838 filed on February 24, 2010 and entitled "Apparatus for
  • test substrates are held in a vertical orientation within the tube, 102.
  • test substrates are generally selected at the source end, 1 10, center, 1 12, and load, 1 14, end of the tube.
  • the test substrates are generally evaluated for doping level and doping uniformity.
  • Sheet resistance as measured by a 4-point probe is commonly used but additional techniques such as secondary ion mass spectrometry (SIMS) and spreading resistance probe (SRP) may also be used.
  • SIMS secondary ion mass spectrometry
  • SRP spreading resistance probe
  • FIG. 2 is a graph of sheet resistance versus phosphorous concentration at saturation. This graph is a compilation of data taken over a temperature range from about 800°C to about 1 100°C.
  • the solid solubility limit of phosphorous in silicon is temperature dependent. As the temperature is raised, more phosphorous can be incorporated into the silicon and the sheet resistance decreases. Typically for solar cells, the doping process temperature is between about 800°C and 900°C.
  • the target sheet resistance is usually between about 50 to about 100 ⁇ /sq.
  • the corresponding solid solubility limit is between about 2x10 20 to about 5x10 20 atoms/cm 3 . It is clear from FIG.
  • the sheet resistance is changing significantly for small changes in the phosphorous concentration.
  • FIG. 3 compares a "Standard" POCI 3 process recipe, 300, with one
  • This embodiment of the present invention has been termed "TAD” for "Time Averaged Diffusion".
  • TAD Time Averaged Diffusion
  • the substrates are loaded into the furnace and temperature is allowed to stabilize.
  • the insertion of 500 solar substrates and accompanying baffle wafers, quartz boats, and automation paddle significantly affect the isothermal environment of the furnace.
  • the insertion of the wafers is protected by a nitrogen purge within the tube so that the wafers surfaces are protected from oxidation.
  • the furnace is ramped to the desired setpoint, still under a protective nitrogen purge.
  • the doping/diffusion setpoint is typically between about 800°C and 900°C and
  • substrates are exposed to a flow of POCI3 in a carrier gas such as N 2 and an oxidizing gas such as O 2 for a predetermined amount of time.
  • This step allows the POCI 3 to react with the O2 to deposit a uniform layer of P2O 5 across all of the substrates within the tube.
  • the substrates near the source of the tube it is common for the substrates near the source of the tube to have a higher phosphorous concentration and a lower sheet resistance than those at the opposite end of the tube (i.e. the load end in FIG. 1 ). This negatively affects the efficiency of the solar cell and leads to yield loss within the manufacturing line.
  • This step is followed by an annealing step wherein the substrates are annealed in an inert atmosphere such as N 2 to diffuse the phosphorous into the substrate.
  • the exposure step and annealing step have been broken into substeps and combined.
  • the TAD process involves a number of sequential deposition/anneal pairs.
  • FIG. 3 illustrates the use of four deposition/anneal pairs. It has been determined that a minimum of two and advantageously a minimum of three deposition/anneal pairs are required to realize the benefits of the present invention. Those skilled in the art will realize that the total deposition time and the total annealing time are exactly the same inthe Standard versus the TAD process recipes.
  • FIG. 4 presents SIMS depth profile data that compare the Standard process with the TAD process.
  • the data presents the phosphorous concentration (in
  • SIMS will measure the total amount of phosphorous present. SIMS does not distinguish between electrically active and non-electrically active phosphorous. Therefore, the concentration as measured by SIMS will be higher than that indicated by the sheet resistance. It is clear that the phosphorous
  • the concentration of phosphorous in the near surface region of the wafer from the Standard process is above the solid solubility limit of phosphorous in silicon for the temperature range of the process (i.e. between 800°C and 850°C).
  • FIG. 5 presents SIMS depth profile data that compare the Standard process with the TAD process.
  • the data presents the phosphorous concentration (in
  • concentration in the first 0.01 ⁇ of the surface is an artifact of the SIMS depth profiling technique.
  • the apex of the curve is considered a good indication of the concentration at the surface.
  • tangent lines have been drawn from the apex to the y-axis.
  • the peak phosphorous concentration for the TAD process is very close to the solid solubility limit for this process temperature.
  • the phosphorous concentration for the Standard process is significantly higher than the solid solubility limit for this process temperature. This "extra" phosphorous (above the solid solubility limit) may negatively impact the light absorption and acts to increase the recombination velocity in the surface region of the solar cell. This leads to a decrease in efficiency.
  • FIG. 6 presents efficiency data for the Standard process versus the TAD process.
  • the data has been "normalized” to the highest value to protect the intellectual property of the manufacturer.
  • the error bars on this data are between 0.15 and 0.20 meaning that the STD and the TAD data are significantly different.
  • the Standard process performance is clearly inferior.
  • the TAD process exhibits excellent efficiency uniformity across the length of the tube.
  • the Standard process exhibits a dramatic loss of efficiency at the source end of the tube. This is attributed to the high concentration of phosphorous near the surface for substrates at the source end of the furnace.

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Abstract

Methods for doping the surface of p-type silicon with phosphorous to form the emitter region of a silicon based solar cell in a horizontal furnace are disclosed. The method maintains the exposure and diffusion times but lowers the phosphorous concentration in the near surface region of the solar cell and improves the uniformity of the solar cell efficiency and yield across all of the substrates in the tube.

Description

NOVEL DOPING PROCESS FOR SOLAR CELL MANUFACTURE
RELATED APPLICATION DATA
[0001] This application claims priority to U.S. Provisional Application No. 61/481 ,823, filed May 3, 201 1 , the entire contents of which are incorporated herein by reference.
FIELD OF THE DISCLOSURE
[0002] This invention relates generally to the field of doping Si-based photovoltaic cells to form the emitter layer.
BACKGROUND
[0003] In the discussion that follows, reference is made to certain structures and/or methods. However, the following references should not be construed as an admission that these structures and/or methods constitute prior art. Applicant expressly reserves the right to demonstrate that such structures and/or methods do not qualify as prior art against the present invention.
[0004] The fabrication of silicon wafer-based solar cells has generally utilized the diffusion of phosphorous (an n-type dopant) into p-doped (boron doped) substrates to form a P-N diode. This is true for both single crystalline and polycrystalline substrates. This P-N junction is responsible for the charge separation within the solar cell 15 once the electron-hole pairs have been formed by the absorption of the light in the solar cell. Generally, electrons and holes are known as carriers.
[0005] Ideally, the electrons are conducted through the external circuit where they do work such as powering lights, etc. They recombine with holes at the rear surface of the solar cell and complete the circuit. However, in practice, there are a number of mechanisms that interrupt this flow of carriers. Carriers can recombine when they meet another carrier of the opposite charge, they can combine with defects or impurities within the bulk of the solar cell, and they can recombine at surfaces. All of these mechanisms decrease the efficiency of the solar cell. The "quantum efficiency" of the solar cell is the ratio of the number of carriers collected by the solar cell to the number of photons of a given energy incident on the solar cell. The efficiency is sensitive to the wavelength of the light. As an example, blue light (shorter wavelengths) has a higher absorption coefficient and is strongly absorbed in the surface region of the solar cell. Red light (longer wavelengths) has a lower absorption coefficient and is transmitted deep into the bulk or through the solar cell.
[0006] The purpose of the solar cell is the generation of useful electrical power. To accomplish this purpose, external circuit elements must be connected to the cell. To minimize circuit losses, the resistance of the connections must be as low as possible. Typically, good ohmic contacts (i.e. low resistance) to silicon are made by heavily doping the regions where the contact is made. However, this increases the
concentration of carriers in that region and increases the probability for recombination to occur in those regions. This issue is being addressed by selectively doping the regions of the silicon substrate to different levels. The contact regions are heavily doped and their area is minimized. The remainder of the surface is lightly doped to effectively absorb the light and generate the carriers.
[0007] Typically, the doping process is performed in a horizontal tube furnace.
These systems provided high throughput (>2000 wafers per hour) and provide good control of the doping concentration and the doping uniformity. A typical horizontal furnace will have 4 process tubes, each able to simultaneously process 500 or more wafers. After the wafers are loaded and the temperature has stabilized, a P-containing source is introduced into the furnace. The P-source of choice has been phosphorous oxy-chloride (POCb). The POCI3 is introduced at one end of the furnace along with O2. The POCI3 and O2 react to form a deposit of P2O5 on the surface that acts as a P- source for the doping of the Si. The gases and by-products are exhausted at the other end of the tube. The P2O5, O2, and Si surface combine to form a P-doped glass layer (PSG) that acts as a dopant source. The wafers are then annealed for a sufficient amount of time for the phosphorous to diffuse into the surface. The PSG is removed during a later step in the solar cell manufacturing process.
[0008] Although horizontal furnaces have worked well for the doping process for many years, the target doping level has continued to decrease and the non-uniformity across the wafer and across the load has become more important. Current processes in horizontal furnaces induce small nonuniformities in the doping levels from one end of the tube to the other. This results in a significant decrease in the solar cell efficiency and yield at one end of the tube versus the other. As mentioned previously, small changes in the near surface region can have a dramatic effect on the efficiency of the solar cell.
[0009] Therefore, there is a need in the art to develop horizontal furnace processes that improve the across wafer and across load uniformity of the dopant process. The processes must work in at low dopant concentrations.
SUMMARY
[0010] Accordingly and advantageously the present invention provides process strategies for controlling the deposition of the P2O5 on the surface as well as the diffusion of the dopant into the surface. A novel time averaged approach to ensure uniform dopant at low dopant concentrations has been developed.
[0011] An exemplary method for doping a surface of p-type silicon with phosphorous to form an emitter region of a silicon based solar cell, the method comprises positioning the silicon wafer in a vertical orientation within a furnace, and depositing a layer of P2O5 on the surface of the silicon wafer by a plurality of sequenced deposition and annealing steps, wherein the sequenced deposition and annealing steps includes exposing the surface of the silicon wafer to a flow of POCI3 in a carrier gas and an oxidizing gas followed by diffusing the phosphorus into the silicon wafer.
[0012] These and other advantages are achieved in accordance with the present invention as described in detail below. BRIEF DESCRIPTION OF THE DRAWING
[0013] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The drawings are not to scale and the relative dimensions of various elements in the drawings are depicted schematically and not to scale.
[0014] The techniques of the present invention can readily be understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
[0015] FIG. 1 is a schematic of a horizontal furnace tube configuration.
[0016] FIG. 2 is a graph of sheet resistance versus phosphorous concentration.
[0017] FIG. 3 is a comparison of the standard recipe flow versus the Time Averaged Diffusion recipe flow.
[0018] FIG. 4 presents SIMS data comparing the phosphorous distribution for the Standard versus TAD processes.
[0019] FIG. 5 presents SIMS data of the near surface region comparing the phosphorous distribution for the Standard versus TAD processes.
[0020] FIG. 6 is a graph comparing the normalized device efficiency for the
Standard, TAD, and Process of Record doping processes.
DETAILED DESCRIPTION
[0021] FIG. 1 illustrates a schematic of a horizontal furnace tube assembly, 100. Typically, a horizontal furnace system will comprise four tubes. Each tube is typically enclosed by a cylindrical heater (not shown) that gives the furnace a "flat zone" of 1440 mm. The flat zone is defined as the length of the tube where the temperature deviates by less than 0.5°C after the system has stabilized. In advanced horizontal furnace systems, 500 156mm x 156mm solar cell substrates can be easily accommodated within the flat zone. Alternatively, the wafers can be loaded back-to-back and the tube can accommodate 1000 substrates. Future tube designs will further extend the flat zone to be able to process up to -2000 substrates per run by further extending the flat zone.
[0022] Furnace tube assembly, 100, includes a quartz tube, 102, that encloses the substrates. Tube, 102, has a gas inlet, 104, and a gas outlet, 106. In the configuration shown, the gas inlet is also known as the "source" and the gas outlet is known as the "load". The source describes the end of the tube where the source of the gas enters. The load describes the end of the tube where the substrates are loaded. It will be clear to those skilled in the art that there are alternative configurations. For example, the "source" of the gas and the "loading" of the substrates can occur at the same end of the tube. The gas would be exhausted at the opposite end of the tube.
[0023] Alternatively, the tube may use a distributed gas injection system and a distributed exhaust system. Details of such a system are described in US patent application 12/71 1 ,838 filed on February 24, 2010 and entitled "Apparatus for
Manufacture of Solar Cells" by Reynolds et al. which is hereby incorporated by reference in its entirety.
[0024] The substrates, 108, are held in a vertical orientation within the tube, 102. As a quality control measure, test substrates are generally selected at the source end, 1 10, center, 1 12, and load, 1 14, end of the tube. The test substrates are generally evaluated for doping level and doping uniformity. Sheet resistance as measured by a 4-point probe is commonly used but additional techniques such as secondary ion mass spectrometry (SIMS) and spreading resistance probe (SRP) may also be used. The 4- point probe only measures the electrically active phosphorous that has been
incorporated into the substrate.
[0025] FIG. 2 is a graph of sheet resistance versus phosphorous concentration at saturation. This graph is a compilation of data taken over a temperature range from about 800°C to about 1 100°C. The solid solubility limit of phosphorous in silicon is temperature dependent. As the temperature is raised, more phosphorous can be incorporated into the silicon and the sheet resistance decreases. Typically for solar cells, the doping process temperature is between about 800°C and 900°C. The target sheet resistance is usually between about 50 to about 100 Ω/sq. The corresponding solid solubility limit is between about 2x1020 to about 5x1020 atoms/cm3. It is clear from FIG. 2 that in the solar cell manufacturing region of the curve the sheet resistance is changing significantly for small changes in the phosphorous concentration. This adds complexity to the control of the phosphorous diffusion step in the manufacture of solar cells. This is to be contrasted with the legacy semiconductor phosphorous diffusion steps where the target sheet resistance was less than about 10 to about 20 Ω/sq. In this region, the sheet resistance is not as sensitive to changes in the phosphorous concentration. Additionally, the legacy semiconductor processes benefited from the ability to use higher temperatures.
[0026] FIG. 3 compares a "Standard" POCI3 process recipe, 300, with one
embodiment of the present invention, 302. This embodiment of the present invention has been termed "TAD" for "Time Averaged Diffusion". In both recipes, the substrates are loaded into the furnace and temperature is allowed to stabilize. The insertion of 500 solar substrates and accompanying baffle wafers, quartz boats, and automation paddle significantly affect the isothermal environment of the furnace. The insertion of the wafers is protected by a nitrogen purge within the tube so that the wafers surfaces are protected from oxidation. In the next step, the furnace is ramped to the desired setpoint, still under a protective nitrogen purge. For solar cell applications, the doping/diffusion setpoint is typically between about 800°C and 900°C and
advantageously between about 800°C and 850°C. There is a short recipe step wherein the furnace is allowed to reach thermal equilibrium.
[0027] At this point in the process recipe, embodiments of the present invention deviate from standard practice. In the Standard process flow recipe, 300, the
substrates are exposed to a flow of POCI3 in a carrier gas such as N2 and an oxidizing gas such as O2 for a predetermined amount of time. This step allows the POCI3 to react with the O2 to deposit a uniform layer of P2O5 across all of the substrates within the tube. However, it is common for the substrates near the source of the tube to have a higher phosphorous concentration and a lower sheet resistance than those at the opposite end of the tube (i.e. the load end in FIG. 1 ). This negatively affects the efficiency of the solar cell and leads to yield loss within the manufacturing line. This step is followed by an annealing step wherein the substrates are annealed in an inert atmosphere such as N2 to diffuse the phosphorous into the substrate.
[0028] In some embodiments of the present invention, the exposure step and annealing step have been broken into substeps and combined. The TAD process involves a number of sequential deposition/anneal pairs. FIG. 3 illustrates the use of four deposition/anneal pairs. It has been determined that a minimum of two and advantageously a minimum of three deposition/anneal pairs are required to realize the benefits of the present invention. Those skilled in the art will realize that the total deposition time and the total annealing time are exactly the same inthe Standard versus the TAD process recipes.
[0029] The remaining two steps in both process recipes are the same. The tube is purged of reactive gases and the temperature is lowered to a temperature suitable for unloading the substrates.
[0030] FIG. 4 presents SIMS depth profile data that compare the Standard process with the TAD process. The data presents the phosphorous concentration (in
atoms/cm3) as a function of depth into the silicon substrate for a substrate taken from the source end of the furnace. SIMS will measure the total amount of phosphorous present. SIMS does not distinguish between electrically active and non-electrically active phosphorous. Therefore, the concentration as measured by SIMS will be higher than that indicated by the sheet resistance. It is clear that the phosphorous
concentration is higher for the Standard process relative to the TAD process at all depths. Recall that the POCI3 exposure time and the diffusion time is exactly the same for both processes. The higher phosphorous concentration in the Standard process reduces the efficiency of the solar cell and leads to yield loss. Those skilled in the art will realize that the concentration of phosphorous in the near surface region of the wafer from the Standard process is above the solid solubility limit of phosphorous in silicon for the temperature range of the process (i.e. between 800°C and 850°C).
[0031] FIG. 5 presents SIMS depth profile data that compare the Standard process with the TAD process. The data presents the phosphorous concentration (in
atoms/cm3) as a function of depth into the silicon substrate for a substrate taken from the source end of the furnace for thenear surface region. This data is taken from the more extensive data presented in FIG. 4. The decrease in the phosphorous
concentration in the first 0.01 μιτι of the surface is an artifact of the SIMS depth profiling technique. The apex of the curve is considered a good indication of the concentration at the surface. To aid the reader's eye, tangent lines have been drawn from the apex to the y-axis.
[0032] The peak phosphorous concentration for the TAD process is very close to the solid solubility limit for this process temperature. The phosphorous concentration for the Standard process is significantly higher than the solid solubility limit for this process temperature. This "extra" phosphorous (above the solid solubility limit) may negatively impact the light absorption and acts to increase the recombination velocity in the surface region of the solar cell. This leads to a decrease in efficiency.
[0033] FIG. 6 presents efficiency data for the Standard process versus the TAD process. The data has been "normalized" to the highest value to protect the intellectual property of the manufacturer. The error bars on this data are between 0.15 and 0.20 meaning that the STD and the TAD data are significantly different. However, the Standard process performance is clearly inferior. Additionally, the TAD process exhibits excellent efficiency uniformity across the length of the tube. However, the Standard process exhibits a dramatic loss of efficiency at the source end of the tube. This is attributed to the high concentration of phosphorous near the surface for substrates at the source end of the furnace. [0034] Although the present invention has been described in connection with preferred embodiments thereof, it will be appreciated by those skilled in the art that additions, deletions, modifications, and substitutions not specifically described may be made without department from the spirit and scope of the invention as defined in the appended claims.

Claims

CLAIMS What is claimed is:
1 . A method for doping a surface of p-type silicon with phosphorous to form an emitter region of a silicon based solar cell, the method comprising:
positioning the silicon wafer in a vertical orientation within a furnace; and depositing a layer of P2O5 on the surface of the silicon wafer by a plurality of sequenced deposition and annealing steps,
wherein the sequenced deposition and annealing steps includes exposing the surface of the silicon wafer to a flow of POCI3 in a carrier gas and an oxidizing gas followed by diffusing the phosphorus into the silicon wafer.
2. The method of claim 1 , wherein a normalized yield across all the silicon wafers in the furnace is greater than 0.96.
3. The method of claim 2, wherein a normalized yield is greater than 0.98.
4. The method of claim 1 , wherein the method includes at least two sequenced deposition and annealing steps.
5. The method of claim 4, wherein the method includes at least three sequenced deposition and annealing steps.
6. A doped silicon wafer formed by the method of claim 1 .
PCT/US2012/036340 2011-05-03 2012-05-03 Novel doping process for solar cell manufacture WO2012151410A1 (en)

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