KR101816186B1 - Method for manufacturing solar cell - Google Patents

Abstract

Provided is a method for manufacturing a solar cell which can improve properties and efficiency of a solar cell by improving properties of a semiconductor substrate. According to an embodiment of the present invention, the method for manufacturing a solar cell comprises: a pre-heat treatment step of including a main treatment process of treating the semiconductor substrate with heat at the main treatment temperature of 1000-1100C in a furnace to decompose an oxygen precipitate in the semiconductor substrate or preventing activation of the oxygen precipitate; a step of forming a first conductive region composed of the semiconductor substrate and a separate semiconductor layer on one surface of the semiconductor substrate; and a step of forming a first electrode electrically connected to the first conductive region.

Description

[0001] METHOD FOR MANUFACTURING SOLAR CELL [0002]

The present invention relates to a method of manufacturing a solar cell, and more particularly, to a method of manufacturing a solar cell including a step of heat-treating a semiconductor substrate.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. The solar cell efficiency can be determined according to the characteristics and design of these various layers and electrodes. In order to commercialize solar cells, it is required to overcome low efficiency, and various layers and electrodes are required to be manufactured so as to maximize the efficiency of the solar cell.

For example, in a solar cell based on a semiconductor substrate, the characteristics of the semiconductor substrate may greatly affect the characteristics of the solar cell. In particular, when a semiconductor substrate contains impurities, defects may be generated due to impurities, which may significantly degrade the characteristics and efficiency of the solar cell. Accordingly, there is a need for a method of manufacturing a solar cell capable of minimizing a problem caused by impurities in a semiconductor substrate.

The present invention provides a method of manufacturing a solar cell capable of improving characteristics and efficiency of a solar cell by improving the characteristics of a semiconductor substrate.

A method of manufacturing a solar cell according to an embodiment of the present invention is a method of manufacturing a solar cell including a step of disposing the semiconductor substrate in a heat treatment furnace at a main processing temperature of 1000 to 1100 DEG C to decompose oxygen precipitates in the semiconductor substrate or to prevent activation of the oxygen precipitates A pre-heat treatment step including a main treatment step of heat treatment; Forming a first conductive type region on a surface of the semiconductor substrate, the first conductive type region being formed of a semiconductor layer separate from the semiconductor substrate; And forming a first electrode electrically connected to the first conductive type region.

According to the method for manufacturing a solar cell according to an embodiment of the present invention, a pre-heat treatment process performed in a simple process is performed to decompose oxygen precipitates or deactivate oxygen precipitates, thereby manufacturing a solar cell having excellent open voltage and efficiency . Particularly, since the oxygen concentration of the semiconductor substrate is a constant level, the present invention can be applied to a manufacturing method of a solar cell in which a problem due to oxygen precipitates can be greatly exerted.

1 is a cross-sectional view illustrating an example of a solar cell to which a method of manufacturing a solar cell according to an embodiment of the present invention can be applied.
2 is a rear plan view of the solar cell shown in Fig.
3A to 3H are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
4 is a temperature profile of a preheating process of a method of manufacturing a solar cell according to an embodiment of the present invention.
5 is a photoluminescence (PL) photograph of a solar cell according to Example and Comparative Example 1.
6 is a graph showing the results of measuring the implied open-circuit voltage (implied Voc) of the solar cell according to the example and the comparative example 1. FIG.
7 is a graph showing the results of measurement of the efficiency of the solar cell according to the example and the comparative example 1. Fig.
8 is a graph showing the results of measurement of the implicit open-circuit voltage of the solar cell according to the example and the comparative example 2. Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a method of manufacturing a solar cell according to an embodiment of the present invention will be described with reference to the accompanying drawings. Hereinafter, an example of a solar cell to which the manufacturing method of the solar cell according to the present embodiment can be applied will be described, and then a manufacturing method of the solar cell according to this embodiment will be described.

1 is a cross-sectional view illustrating an example of a solar cell to which a method of manufacturing a solar cell according to an embodiment of the present invention can be applied.

1, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10, a first conductivity type region 20 having a first conductivity type, a second conductivity type region 20 having a second conductivity type, Type region 30, as shown in FIG. The electrodes 42 and 44 include a first electrode 42 connected to the first conductivity type region 20 and a second electrode 44 connected to the second conductivity type region 30. The solar cell 100 further includes a passivation film (or intermediate passivation film, control passivation film) 22, a first passivation film 24, a second passivation film 34, an antireflection film 36, . This will be described in detail.

The semiconductor substrate 10 includes a base region 110 composed of a single crystal semiconductor (for example, single crystal silicon) having a first or second conductivity type including a first or second conductivity type dopant at a relatively low doping concentration . The base region 110 having a high degree of crystallinity and having few defects or the solar cell 100 based on the semiconductor substrate 10 has excellent electrical characteristics.

An anti-reflection structure that minimizes reflection can be formed on the front surface and / or the rear surface of the semiconductor substrate 10. For example, a texturing structure having a concavo-convex shape in the form of a pyramid or the like may be provided as an antireflection structure. The texturing structure formed on the semiconductor substrate 10 may have an irregular size and have a certain shape (e.g., a pyramid shape) having an outer surface formed along a specific crystal plane (e.g., (111) plane) of the semiconductor. When the surface roughness of the semiconductor substrate 10 is increased by the irregularities formed on the front surface of the semiconductor substrate 10 by such texturing, the reflectance of light incident through the front surface of the semiconductor substrate 10 can be reduced to minimize the optical loss.

In this embodiment, an antireflection structure is formed only on the front surface of the semiconductor substrate 10, and the rear surface of the semiconductor substrate 10 is a mirror polished surface. According to this, the rear surface of the semiconductor substrate 10 on which the passivation film 22 is formed is formed to have a surface roughness smaller than that of the front surface, so that the passivation film 22 can be formed more stably and uniformly. However, the present invention is not limited thereto. Therefore, when an antireflection structure is formed on the front and rear surfaces of the semiconductor substrate 10, an antireflection structure is not formed on the front and rear surfaces of the semiconductor substrate 10, or an antireflection structure is formed only on the rear surface of the semiconductor substrate 10 .

A first conductive type region 20 having a first conductive type may be disposed on one surface (e.g., a rear surface) of the semiconductor substrate 10. [ For example, a passivation film 22 may be formed on the semiconductor substrate 10, and a first conductive type region 20 may be formed on the passivation film 22. For example, the passivation film 22 may be formed entirely in contact with the rear surface of the semiconductor substrate 10. Then, the passivation film 22 can be easily formed without patterning, the structure can be simplified, and the carrier can be stably moved. However, the present invention is not limited thereto, and another film may be positioned between the semiconductor substrate 10 and the passivation film 22, and between the passivation film 22 and the first conductive type region 20. [

The passivation film 22 positioned between the semiconductor substrate 10 and the first conductivity type region 32 is formed such that majority carriers of the first conductivity type region 32 pass through the first conductivity type region 32 ). The passivation film 22 may serve as a dopant control or diffusion barrier to prevent excessive diffusion of the dopant of the first conductivity type region 32 into the semiconductor substrate 10. [ The passivation film 22 may include various materials capable of controlling the diffusion of the dopant and capable of transporting a plurality of carriers. For example, the passivation film 22 may include an oxide, a nitride, a semiconductor, a conductive polymer, and the like. In one example, the passivation film 22 may be a silicon oxide film containing silicon oxide. This is because the silicon oxide film has excellent passivation characteristics and is a smooth film of the carrier. In addition, the silicon oxide film can be easily formed on the surface of the semiconductor substrate 10 by various processes.

The passivation film 22 may have a thin thickness for carrier movement through the passivation film 22 as described above. The thickness of the passivation film 22 may be smaller than the thickness of the other insulating films (the antireflection film 36, the first and second passivation films 24 and 34). For example, the thickness of the passivation film 22 may be 5 nm or less (more specifically, 2 nm or less, for example, 0.5 to 2 nm). If the thickness of the passivation film 22 is greater than 5 nm, the carrier may be difficult to move and the solar cell 100 may not operate. If the thickness of the passivation film 22 is less than 0.5 nm, It may be difficult to form. The passivation film 22 may have a thickness of 2 nm or less (more specifically, 0.5 nm to 2 nm) in order to facilitate the movement of the carrier. At this time, the passivation film 22 may have a thickness of 0.5 nm to 1.5 nm so as to more smoothly move the carrier. However, the present invention is not limited thereto, and the thickness of the passivation film 22 may have various values.

The first conductive type region 20 may be a region having the first conductive type including the first conductive type dopant. For example, the first conductive type region 20 is formed in contact with the passivation film 22, so that the structure of the solar cell 100 is simplified and the carrier can be smoothly moved through the passivation film 22. However, the present invention is not limited thereto, and another film may be positioned between the passivation film 22 and the first conductive type region 20. [

The first conductive type region 20 may include the same semiconductor material as the semiconductor substrate 10 (more specifically, a single semiconductor material, for example, silicon). Then, the second conductive type region 30 may have characteristics similar to those of the semiconductor substrate 10, thereby minimizing a characteristic difference that may occur when the second conductive type region 30 includes different semiconductor materials. In this embodiment, the first conductive type region 20 is formed apart from the semiconductor substrate 10 and is formed by a process different from that of the semiconductor substrate 10, so that a crystal structure or crystallinity different from that of the semiconductor substrate 10 The structure is composed of separate semiconductor layers.

For example, the first conductivity type region 20 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (e.g., amorphous silicon, microcrystalline silicon, or polycrystalline silicon) that can be easily fabricated by various methods, And the first conductive type dopant. In particular, the first conductive type region 20 may comprise a polycrystalline semiconductor (e.g., polycrystalline silicon). Thus, it is possible to smooth the movement of the carrier due to the excellent electrical conductivity, and to induce the smooth movement of the carrier through the passivation film 22.

The first conductivity type region 20 may be formed separately from the semiconductor substrate 10 to reduce the problem of defects or open-circuit voltage drop that may occur in forming the doped region in the semiconductor substrate 10 . Thus, the open-circuit voltage of the solar cell 100 can be improved.

The second conductive type region 30 having the second conductive type may be disposed on the other side (e.g., the front side) of the semiconductor substrate 10. [ For example, in this embodiment, the second conductivity type region 30 may be a doped region formed by doping a part of the semiconductor substrate 10 with a second conductivity type dopant. Then, the base region 110 and the second conductive type region 30 may include the same crystal structure and semiconductor material as the semiconductor substrate 10, but may have different conductivity types or different doping densities. Specifically, when the base region 110 has the first conductivity type, the conductivity type of the base region 110 is different from that of the second conductivity type region 30, and the base region 110 has the second conductivity type The doping concentration of the second conductivity type region 30 is higher than the doping concentration of the base region 110. [

The first conductivity type region 20 having the first conductivity type is formed on the semiconductor substrate 10 with the same conductivity type as that of the semiconductor substrate 10, And the second conductive type region 30 having the second conductive type constitutes a rear electric field region forming a back surface field (BSF) having a higher doping concentration than the base region 110 And constitute an emitter region for forming a pn junction with the base region 110. Then, the second conductive type region 30 constituting the emitter region is located on the front side of the semiconductor substrate 10, so that the path of light bonded to the pn junction can be minimized. In addition, the second conductivity type region 30 may be formed separately from the semiconductor substrate 10 to reduce the area of the doped region in the semiconductor substrate 10, thereby minimizing the deterioration of the characteristics of the semiconductor substrate 10.

However, the present invention is not limited thereto. As another example, when the base region 110 has the second conductivity type, the first conductivity type region 20 constitutes the emitter region and the second conductivity type region 30 forms the same conductivity type as the semiconductor substrate 10 And forms a front electric field area forming a front surface field (FSF) having a higher doping concentration than the semiconductor substrate 10.

When the first or second conductivity type dopant is p-type, a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. When the first or second conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used. In one example, one of the first and second conductivity type dopants may be boron (B) and the other may be phosphorus (P).

The insulating layer may be formed entirely on the first and second conductive regions 20 and 30 except for the openings 102 and 104 corresponding to the first and second electrodes 42 and 44.

The first insulating layer may be entirely formed on the first conductive type region 20 except for the opening portion 102 and the opening 104 may be formed on the second conductive type region 30 The second insulating film may be entirely formed (for example, in contact with) the removed portion. The first passivation film 24 is formed on the first conductivity type region 20 as a first insulating film and the second passivation film 24 is formed as the second insulating film on the second conductivity type region 30 (For example, in contact with) a second passivation film 34 and an antireflection film 36 formed thereon (for example, in contact with the first passivation film 34). However, the present invention is not limited thereto, and the insulating film may have various arrangements according to a desired function.

Passivation films 24 and 34 are formed in contact with conductive regions 20 and 30 to passivate defects present in the surface or bulk of conductive regions 20 and 30. Accordingly, the open-circuit voltage (Voc) of the solar cell 100 can be increased by removing recombination sites of the minority carriers. The antireflection film 36 reduces the reflectivity of light incident on the front surface of the semiconductor substrate 10. The amount of light reaching the pn junction formed at the interface between the base region 110 and the second conductivity type region 30 can be increased by lowering the reflectance of light incident through the entire surface of the semiconductor substrate 10. [ Accordingly, the short circuit current Isc of the solar cell 100 can be increased. The open circuit voltage and the short-circuit current of the solar cell 100 can be increased by the passivation films 24 and 34 and the anti-reflection film 36, thereby improving the efficiency of the solar cell 100.

For example, the passivation films 24 and 34 or the antireflection film 36 may be formed of a material selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ And may have a multilayer structure in which any one single film or two or more films selected is combined. For example, the passivation films 24 and 34 may include a silicon oxide film, a silicon nitride film, or the like having a fixed positive charge when the conductive type regions 20 and 30 have an n type, An aluminum oxide film having a negative charge, and the like. In one example, the antireflective film 36 may comprise silicon nitride. However, the present invention is not limited thereto, and the passivation films 24 and 34 and the antireflection film 36 may include various materials.

For example, in the present embodiment, the first and second passivation films 24 and 34 and / or the antireflection film 36 may be an undoped insulating film which does not have a dopant or the like so as to have excellent insulating properties, have. However, the present invention is not limited thereto.

The first electrode 42 is electrically connected to the first conductive region 20 by locating (e.g., contacting) the first conductive region 20. The first electrode 42 may be electrically connected to the first conductivity type region 20 through the opening 102 formed in the first passivation film 24 (i.e., through the first passivation film 24) . Similarly, the second electrode 44 is electrically connected to the second conductivity type region 30 by locating (e.g., contacting) the second conductivity type region 30. The second electrode 44 is exposed through the opening 104 formed in the second passivation film 34 and the antireflection film 36 (i.e., through the second passivation film 34 and the antireflection film 36) And may be electrically connected to the conductive type region 30. The first and second electrodes 42 and 44 include various materials (more specifically, metal) and may have various shapes.

The planar shapes of the first and second electrodes 42 and 44 will be described in detail with reference to FIG. 2 is a rear plan view of the solar cell 100 shown in Fig.

Referring to FIG. 2, the first electrode 42 may include a plurality of finger electrodes 42a spaced apart from each other with a predetermined pitch. Although the finger electrodes 42a are parallel to each other and parallel to the edge of the semiconductor substrate 10, the present invention is not limited thereto. The first electrode 42 may include a bus bar electrode 42b formed in a direction crossing the finger electrodes 42a and connecting the finger electrodes 42a. Only one bus bar electrode 42b may be provided or a plurality of bus bar electrodes 42b may be provided with a larger pitch than the pitch of the finger electrodes 42a as shown in FIG. At this time, the width of the bus bar electrode 42b may be larger than the width of the finger electrode 42a, but the present invention is not limited thereto. Therefore, the width of the bus bar electrode 42b may be equal to or smaller than the width of the finger electrode 42a.

The finger electrode 42a and the bus bar electrode 42b of the first electrode 42 may all be formed through the first passivation film 24 which is the first insulating film. That is, the opening 102 may be formed corresponding to both the finger electrode 42a of the first electrode 42 and the bus bar electrode 42b. However, the present invention is not limited thereto. As another example, a finger electrode 42a of the first electrode 42 may be formed through the first passivation film 24, and a bus bar electrode 42b may be formed on the first passivation film 24. [ In this case, the opening 102 is formed in a shape corresponding to the finger electrode 42a, and may not be formed in a portion where only the bus bar electrode 42b is located.

The second electrode 44 may include a finger electrode and a bus bar electrode corresponding to the finger electrode 42a and the bus bar electrode 42b of the first electrode 42, respectively. The finger electrode 42a and the bus bar electrode 42b of the first electrode 42 may be directly applied to the finger electrode and the bus bar electrode of the second electrode 44. [ The content of the first passivation film 24 as the first insulating film in the first electrode 42 is directly applied to the second passivation film 34 and the antireflection film 36 as the second insulating film in the second electrode 44 . The width and pitch of the finger electrode 42a and the bus bar electrode 42b of the first electrode 42 may be the same as the width and pitch of the finger electrode and bus bar electrode of the second electrode 44 May be different.

However, the present invention is not limited thereto, and the first electrode 42 and the second electrode 44 may have different planar shapes, and various other modifications are possible.

As described above, in this embodiment, since the first and second electrodes 42 and 44 of the solar cell 100 have a certain pattern, the solar cell 100 can receive light from the front and back surfaces of the semiconductor substrate 10 A bi-facial structure. Accordingly, the amount of light used in the solar cell 100 can be increased to contribute to the efficiency improvement of the solar cell 100. However, the present invention is not limited thereto, and it is also possible that the first electrode 42 is formed entirely on the rear side of the semiconductor substrate 10. Various other variations are possible.

The first conductive type region 20 may be formed as a separate semiconductor layer from the semiconductor substrate 10 to minimize the doping region formed in the semiconductor substrate 10 to improve the characteristics of the semiconductor substrate 10. The second conductivity type region 30 located on the front surface of the semiconductor substrate 10 may be formed as a part of the semiconductor substrate 10 so that light absorption that may occur when a separate semiconductor layer is located on the semiconductor substrate 10 Can be minimized. Thus, the amount of light reaching the pn junction can be kept high.

However, since the first conductive type region 20 is formed of a semiconductor layer that is separate from the semiconductor substrate 10, the doping effect of the first conductive type region 20 does not reach the semiconductor substrate 10. For example, when the first conductivity type region 20 has the n-type conductivity, if the n-type conductivity type is doped to form the n-type doped region in the semiconductor substrate 10, The problem caused by the impurities can be reduced by gattering impurities in the inside of the substrate. It is difficult to expect such an effect in the present embodiment. That is, when the first conductivity type region 20 composed of a separate semiconductor layer has an n-type, the problem caused by impurities in the semiconductor substrate 10 may be more significant.

A manufacturing method of the solar cell 100 considering this will be described in detail with reference to FIGS. 3A to 3H and FIG. The detailed description will be omitted for the contents already described and only the contents not described will be described in detail.

3A to 3H are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

First, as shown in Figs. 3A and 3B, a semiconductor substrate 10 which is a silicon substrate is prepared. 3A, a silicon ingot 204 is formed by growing monocrystal silicon, and then the silicon ingot 204 is cut to a predetermined thickness to form a semiconductor substrate 10 as shown in FIG. 3B, (10).

As shown in FIG. 3A, in this embodiment, the silicon ingot 204 may be grown by a czochralski method. That is, the silicon is melted in the crucible 202, brought into contact with the solid single crystal silicon seed crystal (seed) 204a, and the single crystal is grown under the termination of the crystal while the silicon ingot 204 is formed. As described above, the silicon ingot 204 having a single crystal silicon can be formed by the Czochralski method, and other methods are hardly actually used.

Here, the crucible 202 may be made of quartz (SiO ₂ ). When the crucible 202 is made of quartz, the material in the crucible 202 can be heated to a high temperature and mixing of impurities such as metals can be prevented or minimized. However, the oxygen contained in the quartz can be decomposed during the growth process of the silicon ingot. Most of the oxygen again joins with the silicon to move toward the surface and emit into the air. However, as shown by arrows, ). ≪ / RTI > Thereby, oxygen may be present inside the silicon ingot 204. Such oxygen is mainly contained in the upper portion of the silicon ingot 204, and the oxygen concentration gradually decreases toward the lower portion.

Subsequently, as shown in FIG. 3B, the silicon ingot (reference numeral 204 in FIG. 3A, hereinafter the same) is cut so as to have a constant thickness and / or shape to form the semiconductor substrate 10. Thus, the semiconductor substrate 10 can be composed of a single crystal silicon substrate. Various methods known for cutting the silicon ingot 204 can be used.

Next, as shown in FIG. 3C, the semiconductor substrate 10 is subjected to a pre-heat treatment process. The pre-heat treatment process is a main process for decomposing oxygen precipitates (oxygen-induced stacking faults, for example, oxygen induced stacking faults (OIFS)) in the semiconductor substrate 10 or preventing the activation of oxygen precipitates Reference numeral P2 in Fig. 4). For reference, the oxygen induced stacking defect is referred to as a ring pattern defect because it has a circular pattern as shown in Fig.

As described above, oxygen may remain in the semiconductor substrate 10, and the higher the oxygen concentration is, the higher the possibility that oxygen forms precipitates such as oxygen-induced lamination defects and causes crystal defects. Particularly, as described above, since the upper portion of the silicon ingot 204 has a high oxygen concentration, a large amount of oxygen precipitates can be generated, and when the oxide precipitates are activated, they act as defects. Particularly, when a high-temperature heat treatment (for example, 850 DEG C to 1000 DEG C) is performed during the manufacturing process of the solar cell 100, a large amount of oxygen precipitates can be formed and activated. Here, the activation of the oxide precipitate means that when an impurity (for example, a metal impurity) in the semiconductor substrate 10 is caught in a trap of the oxygen precipitate, the corresponding portion is converted into a recombination site . If the oxide precipitate acts as a defect, the lifetime of the carrier can be reduced and the efficiency of the solar cell 100 can be lowered. In particular, when the n-type first conductivity type region 20 is formed separately from the semiconductor substrate 10, the gettering effect of the metal impurity that can be expected when forming the n-type doped region can not be expected at all, The problem due to the oxygen precipitates may become larger.

Although there is a method of reducing the oxygen concentration in the silicon ingot 204 in order to prevent the problem due to such oxygen precipitates, it is very difficult to control the concentration of oxygen dissolved in the silicon ingot 204 in the Czochralski method, Can severely limit the process cost. Alternatively, there is a method of preventing the problem due to oxygen precipitates and providing passivation using deuterium or the like, but it is difficult to actually apply the method because the process is very complicated.

In consideration of this, in this embodiment, before the other heat treatment is performed in the manufacturing process of the solar cell 100, the pre-heat treatment for decomposing the oxygen precipitate or preventing the activation of the oxygen precipitate is performed first. Referring to FIG. 4 together with FIG. 3C, a pre-heat treatment process for decomposing oxygen precipitates or preventing the activation of oxygen precipitates will be described in detail.

4 is a temperature profile of a preheating process of a method of manufacturing a solar cell according to an embodiment of the present invention. In this embodiment, in addition to the main processing step (P2) described above. And a temperature lowering step (P3) performed after the temperature raising step (P1) and / or the main processing step (P2) performed before the main processing step (P2). First, the main processing step (P2) will be described, and then the temperature raising step (P1) and the temperature reducing step (P3) will be described in more detail.

The main treatment process P2 may be performed in a common heat treatment furnace 206 and the main treatment temperature T2 of the main treatment process P2 may be 1000 to 1100 占 폚.

When the main treatment process (P2) is performed at the main treatment temperature (T2) of 1000 占 폚 to 1100 占 폚 at the main treatment temperature (T2), the oxygen precipitates inside the semiconductor substrate (10) It is possible to effectively prevent activation of oxygen precipitates by reducing the size or by preventing metal impurities from diffusing and being located in traps of oxygen precipitates. If the main treatment temperature (T2) is less than 1000 占 폚, the effect of decomposing the oxygen precipitate or deactivating the oxygen precipitate may not be obtained or may not be sufficient. This is thought to be because the main treatment temperature (T2) of 1000 DEG C or less does not provide sufficient heat to decompose the oxygen precipitate or deactivate the oxygen precipitate. In general heat treatment furnaces, it is difficult to achieve a temperature exceeding 1100 ° C or a high processing cost. In addition, the effect of decomposing the oxide precipitate or deactivating the oxide precipitate at a temperature exceeding 1100 占 폚 is not greatly increased, but the possibility of undesirable thermal shock or damage to the semiconductor substrate 10 is increased.

At this time, sufficient heat is provided to the semiconductor substrate 10 for a sufficient time to allow the semiconductor substrate 10 to decompose or deactivate the oxide precipitate at the main processing temperature T2 described above, so that the above-described effect can be realized . Accordingly, in the present embodiment, the main processing step P2 can be performed in the heat treatment furnace 206 in which the heat treatment of the semiconductor substrate 10 can be performed for a sufficient time. As an example, the main treatment process P2 may be performed for 3 to 30 minutes. If the process time of the main process P2 is less than 3 minutes, the effect of the main process P2 or the preheating process may not be sufficient. If the process time of the main process P2 exceeds 30 minutes, the process time may be increased without additional effect, and unnecessary changes or damage of the semiconductor substrate 10 may occur. For example, the process time of the main process P2 may be 15 minutes to 30 minutes so that the effect of the main process P2 can be stably realized. However, the present invention is not limited thereto, and the process time of the main treatment process P2 may be variously changed.

The heat treatment furnace 206 may be a heat treatment furnace of various structures which can be raised to the main treatment process P2 by a heat source (not shown) and maintained for the process time. The heat treatment furnace 206 can heat treat the semiconductor substrate 10 for a relatively long time without a large temperature change so that the decomposition or deactivation effect of the oxygen precipitates can be sufficiently obtained and the thermal shock or damage And the like can be minimized. Also, the heat treatment furnace 206 can easily obtain a device, and the price of the device is also very low.

For example, a tube furnace may be used as the heat treatment furnace 206, and the heat treatment furnace 206 may include quartz or may be made of quartz. As an example, the heat treatment furnace 206 may be a quartz tube heat treatment furnace. The tube heat treatment furnace is generally used and can be easily obtained, thereby reducing the burden on the equipment. If the heat treatment furnace 206 is made of quartz, the heat treatment furnace 206 can withstand the main treatment temperature T2 for a process time, and the mixing of impurities such as metals can be minimized. However, the present invention is not limited thereto, and the shape, material, etc. of the heat treatment furnace 206 may be variously modified.

Since the main process P2 is performed in the heat treatment furnace 206, the main process P2 can be performed on the plurality of semiconductor substrates 10 at the same time. For example, a plurality of semiconductor substrates 10 may be fixed to the fixing member 208 while being spaced apart from each other at regular intervals. The fixing member 208 to which the semiconductor substrate 10 is fixed can be heat-treated together with the heat-treating furnace 206. For example, a boat, a cassette, or the like may be used as the fixing member 208. However, the present invention is not limited thereto. A plurality of semiconductor substrates 10 can be simultaneously heat-treated in the heat treatment furnace 206 by various methods, fixing members 208 of various structures, or the like. When the plurality of semiconductor substrates 10 are heat-treated at the same time, the manufacturing cost can be greatly reduced.

On the other hand, when the rapid thermal processing (RTP) system is used, the semiconductor substrate is subjected to the heat treatment for a short time (for example, several seconds) to dissolve or deactivate the oxide precipitate It is difficult to conduct heat treatment for a sufficient time. In addition, the characteristics of the semiconductor substrate may change due to rapid temperature changes, or thermal shock or damage may be applied to the semiconductor substrate. For example, bending of the semiconductor substrate may occur. Also, since a pre-heat treatment process can be performed on only one semiconductor substrate, the process time and cost can be increased. In addition, since the rapid thermal processing apparatus is expensive, the burden on the equipment may increase.

(P1) which raises from the initial temperature (T1) to the main treatment temperature (T2) before the main treatment process (P2), and the end temperature (T3 (P3) for reducing the temperature up to a predetermined temperature. This will be explained in more detail.

The temperature raising step P1 which is performed before the main processing step P2 is a step of gradually increasing the temperature of the semiconductor substrate 10 from the initial temperature T1 to the main processing temperature T2. Damage or thermal shock of the semiconductor substrate 10 can be minimized by the temperature raising step P1. For example, the initial temperature T1 may be 600 to 750 占 폚. If the initial temperature T1 is less than 600 deg. C, the temperature difference from the main treatment temperature T2 is large, and the process time of the temperature raising step P1 may become long. If the initial temperature T1 exceeds 700 deg. C, the temperature change of the semiconductor substrate 10 may be large at the beginning of the temperature raising step P1. And the temperature rising rate of the temperature raising step P1 may be 10 to 15 占 폚 / min. If the temperature rising speed is less than 10 캜 / minute, the process time of the temperature raising step (P1) may be prolonged. It may be difficult to limit the rate of temperature rise above 15 ° C / min due to process limitations. However, the present invention is not limited thereto, and the initial temperature T1 and the temperature rising speed may have various values.

The temperature reducing step P3 performed after the main treatment step P2 is a step of gradually reducing the temperature of the semiconductor substrate 10 from the main treatment temperature T2 to the end temperature T3 to complete the preheating step . Damage or thermal shock of the semiconductor substrate 10 can be minimized by the temperature reduction step P3. As an example, the end temperature T3 may be 600 to 750 占 폚. If the termination temperature T3 is less than 600 deg. C, the temperature difference from the main processing temperature T2 is large, so that the process time of the temperature reducing process P3 may become long. If the termination temperature T3 exceeds 700 deg. C, the temperature change of the semiconductor substrate 10 after the temperature reducing step P3 may be large. The end temperature T3 may be equal to or different from the initial temperature T1.

As an example, the temperature reduction step P3 may be performed by natural cooling without a separate cooling device. This is because the decomposition or inactivation of the oxide precipitate is performed in the main treatment process P2 in this embodiment, so that the temperature reduction process P3 need not be limited to specific process conditions. Thus, the manufacturing process and the manufacturing process can be simplified. Accordingly, the temperature reduction rate in the temperature reduction step P3 can be smaller than the temperature rise rate in the temperature rise step P1. For example, the temperature reduction rate in the temperature reduction step P3 may be 5 to 10 占 폚 / min. Such a temperature reduction rate is a speed that can be easily realized by natural cooling and the like.

However, the present invention is not limited thereto, and various methods can be applied as the temperature reduction method, and the termination temperature T3 and the temperature reduction rate can have various values.

The above-described temperature raising step (P1) and / or the temperature reducing step (P3) may be performed inside the heat treatment furnace 206 in which the main treatment step (P2) is performed. At this time, the above-mentioned contents can be directly applied to the fixing method of the semiconductor substrate 10, the fixing member 208 in the temperature raising step (P1) and / or the temperature reducing step (P3). According to this, the temperature raising step P1, the main processing step P2 and the temperature reducing step P3 can be performed by a continuous process in the same apparatus (i.e., an in-situ process) have. For example, in the temperature raising step P1, the temperature of the semiconductor substrate 10 can be raised by using the heat source in the heat treatment furnace 206, and in the temperature reducing step P1, the heat source of the heat processing furnace 206 is not operated Or by natural cooling in the absence of the heat. However, the present invention is not limited thereto. Therefore, the temperature raising step P1 and / or the temperature reducing step P3 can be performed outside the heat treatment furnace 206 or inside another apparatus in which the main treatment step P2 is performed.

In this embodiment, the gas atmosphere in the pre-heat treatment step may include nitrogen gas. Nitrogen gas is an inert gas and has low reactivity, so it can inhibit the formation of unnecessary reactants and can reduce the process cost. The nitrogen gas may be used in at least one of the temperature raising step (P1), the main treatment step (P2) and the temperature reducing step (P3). As an example, nitrogen gas may be injected into the heat treatment furnace 206 in the temperature raising step P1 and the temperature reducing step P3, and may or may not be injected in the main treatment step P2.

At this time, the oxygen concentration of the semiconductor substrate 10 on which the pre-heat treatment process is performed may be 16 ppma or more. As described above, the higher the oxygen concentration, the greater the problem due to the oxygen precipitates. If the pre-heat treatment process is performed on the semiconductor substrate 10 having the oxygen concentration of 16 ppma or more, the effect of the pre-heat treatment process can be doubled have. In one example, the oxygen concentration of the semiconductor substrate 10 on which the pre-heat treatment process is performed may be 16 to 20 ppma. When the oxygen concentration of the semiconductor substrate 10 is 20 ppma or more, the oxygen concentration is too high, so that the semiconductor substrate 10 is often used as a defective semiconductor substrate 10. However, the present invention is not limited thereto. Therefore, the semiconductor substrate 10 having an oxygen concentration of 20 ppma or more can be used as the semiconductor substrate 10 of the solar cell 100 by performing a preheating process.

In this embodiment, a pre-heat treatment process for decomposing or deactivating oxide precipitates is performed before another pre-heat treatment process is performed in the manufacturing method of the solar cell 100, so that even if another pre-heat treatment process is performed after that, . Thus, the lifetime of the carrier can be increased and the efficiency of the solar cell 100 can be improved. For example, whether or not the bulk lifetime of the semiconductor substrate 10 is improved can be judged by photoluminescence (PL).

At this time, in this embodiment, the oxide precipitate can be decomposed or inactivated in the entire region of the semiconductor substrate 10 by one main processing step P2 having only one main processing temperature T2. This is because the entire area of the semiconductor substrate 10 should be used in the solar cell 100 and the oxide precipitates are simply decomposed or deactivated, so that the processes are not performed at various temperatures. Further, since the preheating process is performed at normal pressure, there is no need for a process, apparatus, etc. for controlling the pressure. It is not necessary to maintain the semiconductor substrate 10 for a long time at a high temperature which causes thermal shock or damage to the semiconductor substrate 10. Accordingly, the process temperature of the main process P2 is only 1000 to 1100 DEG C and the process time of the main process P2 is within 30 minutes and the total process time is within 4 hours (for example, within 3 hours, For example, within 1 hour), the manufacturing process can be simplified.

For example, in a semiconductor device such as a thin film transistor, a preheating process related to oxide precipitates is performed to improve the quality of a semiconductor substrate. The semiconductor substrate for a semiconductor device generally has a lower impurity concentration than that of the semiconductor substrate 10 used for the solar cell 100 up to several thousand times (for example, 9N or more). In order to manufacture a semiconductor substrate of higher quality than the semiconductor substrate 10 It is possible to carry out a preheating process for controlling the oxygen precipitates. However, the preheating process performed on the semiconductor device has a completely different purpose and effect than the preheating process of the present invention, and is performed in a completely different process. That is, since only the surface of the semiconductor substrate is used in a semiconductor device or the like, oxygen is diffused in the surface of the semiconductor substrate to form oxygen precipitates, and oxygen precipitates are grown to gutter the impurities, To remove defects or impurities on the surface of the substrate. Thus, defects on the surface of the semiconductor substrate are almost completely removed to form a denuded zone. In order to form such a defect-free region, the heat treatment process for diffusing oxygen into the interior, formation of oxygen precipitates, and growth of oxygen precipitates are different, and various heat treatment processes are performed for a very long total process time (at least 24 hours) . Or rapid cooling under limited process conditions using a cooler or the like in consideration of the formation or growth of oxygen precipitates, and the like. Accordingly, the process conditions can be very complicated.

As described above, according to this embodiment, it is possible to minimize the occurrence of defects due to oxygen precipitates by decomposing oxygen precipitates or preventing activation of oxygen precipitates by the pre-heat treatment process. In particular, as in the above-described embodiment, the first conductivity type region 20 having the n-type is formed of a semiconductor layer which is separate from the semiconductor substrate 10, so that the gettering effect that can be realized when forming the n- If you can not expect, you can have a bigger effect.

However, the present invention is not limited thereto, and the pre-heat treatment process can be performed at the time of manufacturing the various solar cells 100. Therefore, the first conductivity type region 20 may have a p-type. Alternatively, the first conductive type region 20 may be a doped region constituting a part of the semiconductor substrate 10, and / or the second conductive type region 20 may be a doped region constituting a part of the semiconductor substrate 10, Layer. Alternatively, the first and second conductivity type regions 20 and 30 are located together on one side (e.g., the back side) of the semiconductor substrate 10, and the first and second conductivity type regions 20 and 30 are doped regions, A separate semiconductor layer, or the like.

As described above, in this embodiment, the preheating process for decomposing or deactivating the oxide precipitate can be performed before the formation process of the anti-reflection structure of the semiconductor substrate 10 (the process shown in FIG. 3D). This is because, when there is a problem that impurities are adsorbed on the surface of the semiconductor substrate 10 during the pre-heat treatment process, it can be removed at the time of texturing for forming the antireflection structure. However, the present invention is not limited to this, and the above-described preheating process may be performed after forming the antireflection structure.

3D, a texturing process is performed on at least one of the front surface and the rear surface of the semiconductor substrate 10 to form an anti-reflection structure. Wet or dry texturing may be used for texturing of the semiconductor substrate 10. The wet texturing can be performed by immersing the semiconductor substrate 10 in the texturing solution, and has a short process time. In dry texturing, the surface of the semiconductor substrate 10 is cut by using a diamond grill or a laser, so that irregularities can be formed uniformly, but the processing time is long and damage to the semiconductor substrate 10 may occur. Alternatively, the semiconductor substrate 10 may be textured by reactive ion etching (RIE) or the like. As described above, the semiconductor substrate 10 can be textured in various ways in the present invention.

In this case, for example, in the present embodiment, the rear surface of the semiconductor substrate 10 is mirror polished so that the rear surface of the semiconductor substrate 10 has a flat surface. For example, after the front surface and the rear surface of the semiconductor substrate 10 are textured using an alkali solution, the rear surface of the semiconductor substrate 10 can be mirror polished using an acidic solution or the like. However, the present invention is not limited thereto.

In another embodiment, the texturing process may be performed after forming the passivation film 22 and the first conductive region 20 (or a semiconductor layer for forming the same). That is, the texturing process can be performed in various orders.

The passivation film 22 is formed entirely on the rear surface of the semiconductor substrate 10 as shown in Fig. 3E.

Here, the passivation film 22 may be formed by, for example, thermal oxidation, chemical oxidation, vapor deposition (e.g., APCVD, LPCVD). However, the present invention is not limited thereto, and the passivation film 22 may be formed by various methods.

A first conductive type region 20 is formed on the passivation film 22 on the rear side of the semiconductor substrate 10 and a second conductive type region 30 is formed on the front side of the semiconductor substrate 20, ).

Various methods can be applied to the method of forming the first conductivity type region 20. [ For example, the first conductivity type region 30 may be formed by chemical vapor deposition. Here, the first conductive type dopant may be included in the semiconductor layer in the step of forming the semiconductor layer constituting the first conductivity type region 30. Alternatively, after the semiconductor layer constituting the first conductivity type region 30 is formed, the first conductive layer 30 may be formed by various doping methods such as a thermal diffusion method, an ion implantation method, a method of performing heat treatment after forming a doped layer, Type dopant can be doped. Various methods known as the doping process for forming the second conductivity type region 30 can be used. For example, various methods such as an ion implantation method, a thermal diffusion method, a method of performing a heat treatment after forming a doped layer, and a laser doping method may be applied. The present invention is not limited thereto.

The passivation film 22 and / or the first conductivity type region 20 are formed only on the rear surface of the semiconductor substrate 10, but the present invention is not limited thereto. The passivation film 22 and / or the first conductive region 20 may be formed on the front surface and / or the side surface of the semiconductor substrate 10, and the passivation film 22 may be formed on the front surface and / The film 22 and / or the first conductivity type region 20 may be removed in a subsequent process.

Next, as shown in FIG. 3G, another insulating film is formed on the front and rear surfaces of the semiconductor substrate 10. That is, a first passivation film 24 is formed on the rear surface of the semiconductor substrate 10, and a second passivation film 34 and an antireflection film 36 are formed on the entire surface of the semiconductor substrate 10.

More specifically, the first passivation film 24 is formed entirely on the rear surface of the semiconductor substrate 10, and the second passivation film 34 and the antireflection film 36 are formed on the entire surface of the semiconductor substrate 10. The first or second passivation films 24 and 34 and the antireflection film 36 may be formed by various methods such as a vacuum deposition method, a chemical vapor deposition method, a spin coating method, a screen printing method or a spray coating method. The order of forming the first and second passivation films 24 and 34, and the antireflection film 36 is not limited.

Next, as shown in FIG. 3H, first and second electrodes 42 and 44 connected to the first and second conductivity type regions 32 and 34, respectively, are formed.

For example, a first opening 102 is formed in the first passivation film 24 by the patterning process, a second opening 104 is formed in the second passivation film 34 and the antireflection film 36, Then, the first and second electrodes 42 and 44 are formed while filling the first and second openings 102 and 104, respectively. At this time, the first and second openings 102 and 104 may be formed by laser ablation using a laser, or various methods using an etching solution or an etching paste. The first and second electrodes 42 and 44 may be formed by various methods such as a sputtering method, a plating method, and a deposition method. In particular, in this embodiment, the first and second electrodes 42 and 44 may be formed by a sputtering method.

However, the present invention is not limited thereto. As another example, after the first and second electrode forming paste is applied on the first passivation film 24, the second passivation film 34 and the antireflection film 36 by screen printing or the like, ) Or a laser firing contact or the like to form the first and second electrodes 42 and 44 of the above-described shape. In this case, since the openings 102 and 104 are formed at the time of forming the first and second electrodes 42 and 44, a step of forming the openings 102 and 104 may not be separately added.

According to the method for manufacturing a solar cell according to an embodiment of the present invention, a pre-heat treatment process performed in a simple process is performed to decompose oxygen precipitates or deactivate oxygen precipitates, thereby manufacturing a solar cell having excellent open voltage and efficiency . Particularly, since the oxygen concentration of the semiconductor substrate is a constant level, the present invention can be applied to a manufacturing method of a solar cell in which a problem due to oxygen precipitates can be greatly exerted.

Hereinafter, the present invention will be described in more detail with reference to experimental examples of the present invention. However, the experimental examples of the present invention are only for illustrating the present invention, and the present invention is not limited thereto.

Example

A plurality of solar cells having the structure shown in Fig. At this time, the semiconductor substrate was composed of the polycrystalline silicon layer having the n-type single crystal silicon substrate as the base region, the second conductivity type region having the p-type, and the first conductivity type region having the n-type. Prior to performing another process, a pre-heat treatment process was performed to decompose or prevent activation of oxygen precipitates in the heat treatment furnace. More specifically, the initial temperature was 600 占 폚, the temperature was raised at a temperature raising rate of 15 占 폚 / min, the heat treatment was performed at a main treatment temperature of 1000 占 폚 for 15 minutes, and the temperature was lowered to 600 占A preheating process was performed. Nitrogen gas was injected during the preheating process.

Comparative Example  One

A plurality of solar cells were manufactured in the same manner as in Example except that the preheating process was not performed.

Comparative Example  2

A plurality of solar cells were manufactured in the same manner as in Example except that the preheating process was performed in a rapid thermal processing apparatus, not in a heat treatment furnace, and the rate of temperature rise was different from that in Examples.

Photoluminescence (PL) photographs of the solar cells according to the example and the comparative example 1 were taken. A PL photograph of the solar cell according to the embodiment is shown in Fig. 5 (a), and a PL photograph of the solar cell according to the comparative example 1 is shown in Fig. 5 (b)

Referring to FIG. 5 (a), it can be seen that the solar cell according to the embodiment exhibits no or very small number of circular patterns due to oxygen induced stacking faults (OIFS). On the other hand, referring to FIG. 5 (b), it can be seen that the solar cell according to Comparative Example 1 exhibits a very dense and dense circular pattern due to oxygen induced defects. Accordingly, it can be seen that the oxide precipitates are decomposed or the oxygen precipitates are inactivated by the pre-heat treatment process performed in the embodiment, and thus the defects are minimized.

The implied open-circuit voltage (implied Voc) of the solar cell according to the embodiment and the comparative example 1 was measured and is shown in FIG. Referring to FIG. 6, it can be seen that the implicit open-circuit voltage of the solar cell according to the embodiment is higher than the implicit open-circuit voltage of the solar cell according to Comparative Example 1 as a whole. More specifically, in Comparative Example 1, the implicit open-circuit voltage greatly decreases as the oxygen concentration in the semiconductor substrate increases. This is because the oxygen precipitates become more serious as the oxygen concentration increases. On the other hand, in the embodiment, the implicit open-circuit voltage is maintained at a high level regardless of the oxygen concentration in the semiconductor substrate. Thus, it can be seen that the preheating process performed in the embodiment can be applied to the case where the problem due to oxygen precipitates can be increased due to the high oxygen concentration, thereby effectively solving the problem caused by oxygen precipitates, thereby improving the open circuit voltage.

The results of measuring the efficiency of the solar cell according to the embodiment and the comparative example 1 are shown in FIG. Referring to FIG. 7, it can be seen that the efficiency of the solar cell according to the embodiment is 0.4% higher than the efficiency of the solar cell according to the Comparative Example 1. It can be seen that the efficiency of the solar cell can be finally improved by improving the implicit open-circuit voltage by performing the pre-heat treatment process in the embodiment.

The results of measuring the implicit open-circuit voltage of the solar cell according to Examples and Comparative Example 2 are shown in FIG. Referring to FIG. 8, it can be seen that the implicit open-circuit voltage of the solar cell according to the embodiment is higher than the implicit open-circuit voltage of the solar cell according to the second comparative example. According to this, when the pre-heat treatment process is performed in the rapid thermal processing apparatus as in the comparative example, it is difficult to realize the effect thereof, and when the pre-heat treatment process is performed in the heat treatment furnace as in the embodiment, It can be seen that the implicit open-circuit voltage enhancement effect can be realized.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
10: semiconductor substrate
20: first conductivity type region
30: second conductivity type region
42: first electrode
44: Second electrode
204: Silicon ingot
206: heat treatment furnace
208: Fixing member

Claims (20)

A pre-heat treatment step of heat-treating the semiconductor substrate in a heat treatment furnace at a main treatment temperature of 1000 to 1100 占 폚 so as to decompose oxygen precipitates in the semiconductor substrate or prevent activation of the oxygen precipitates;
Forming an anti-reflection structure on one surface of the semiconductor substrate by texturing;
Forming a passivation film on the other surface of the semiconductor substrate having a surface roughness smaller than that of one surface of the semiconductor substrate;
Forming a first conductive type region on the passivation film, the first conductive type region being formed of a semiconductor layer different from the semiconductor substrate;
Forming a second conductive type region on the other surface of the semiconductor substrate by performing a doping process, the second conductive type region being a part of the semiconductor substrate;
Forming a first electrode electrically connected to the first conductive type region; And
Forming a second electrode electrically connected to the second conductive type region
Lt; / RTI >
Wherein the first conductivity type region has an n-type conductivity type. The method according to claim 1,
Wherein the main treatment step is performed for 3 to 30 minutes. The method according to claim 1,
Wherein the main treatment step is performed for 15 minutes to 30 minutes. delete The method according to claim 1,
Wherein the semiconductor substrate has an oxygen concentration of 16 ppma or more. The method according to claim 1,
Wherein the preheating step is performed by one main processing step having only a single main processing temperature. The method according to claim 1,
Wherein a plurality of the semiconductor substrates are heat-treated together in the main process step. The method according to claim 1,
Wherein the preheating step is performed at atmospheric pressure. The method according to claim 1,
Wherein the preheating step comprises:
A temperature raising step of raising the temperature from the initial temperature to the main treatment temperature before the main treatment step; And
A temperature reduction step of reducing the temperature from the main treatment temperature to the end temperature after the main treatment step
Further comprising the steps of: 10. The method of claim 9,
Wherein the initial temperature or the termination temperature is 600 to 750 占 폚. 10. The method of claim 9,
Wherein a temperature lowering rate of the temperature lowering process is lower than a temperature rising rate of the temperature raising process. 12. The method of claim 11,
The rate of temperature rise in the temperature raising step is 10 to 15 占 폚 / min,
Wherein the temperature reduction rate in the temperature reduction step is 5 to 10 占 폚 / min. 12. The method of claim 11,
In the temperature raising step, the semiconductor substrate is heated by the heat source in the heat treatment furnace,
Wherein the temperature lowering step is cooled by natural cooling. 10. The method of claim 9,
Wherein the temperature raising step, the main treatment step and the temperature reducing step are performed by a continuous process in the same apparatus. The method according to claim 1,
Wherein the gas atmosphere in the preheating step includes nitrogen gas. The method according to claim 1,
Wherein the heat treatment furnace is a tube furnace. The method according to claim 1,
Wherein the heat treatment furnace comprises quartz. The method according to claim 1,
The semiconductor substrate is a single crystal silicon substrate formed by cutting and forming a silicon ingot,
Wherein the silicon ingot is formed by a czochralski method. delete delete

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