WO2012147950A1 - Liquid crystal panel, liquid crystal display device, and television receiver - Google Patents

Liquid crystal panel, liquid crystal display device, and television receiver Download PDF

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Publication number
WO2012147950A1
WO2012147950A1 PCT/JP2012/061454 JP2012061454W WO2012147950A1 WO 2012147950 A1 WO2012147950 A1 WO 2012147950A1 JP 2012061454 W JP2012061454 W JP 2012061454W WO 2012147950 A1 WO2012147950 A1 WO 2012147950A1
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WIPO (PCT)
Prior art keywords
pixel
data signal
liquid crystal
substrate
signal line
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PCT/JP2012/061454
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French (fr)
Japanese (ja)
Inventor
酒井　保
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シャープ株式会社
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Publication of WO2012147950A1 publication Critical patent/WO2012147950A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present invention relates to the structure of two substrates included in a liquid crystal panel.
  • a liquid crystal panel in general, includes an active matrix substrate, a counter substrate facing the active matrix substrate, and a liquid crystal layer disposed between the two substrates.
  • the active matrix substrate includes a data signal line, a scanning signal line, a data signal line, and a data signal line.
  • a transistor connected to the scanning signal line and a pixel electrode connected to the transistor are formed, and a common electrode, a color filter, and a black matrix are formed on the counter substrate.
  • scanning signal lines and data signal lines of an active matrix substrate are driven by a source driver and a gate driver, respectively.
  • Reference 1 discloses a configuration in which a source driver and a gate driver are formed on the counter substrate side in order to increase the yield of the liquid crystal panel.
  • An object of the present invention is to realize a liquid crystal panel that can be driven at a higher speed.
  • the liquid crystal panel includes first and second substrates, a liquid crystal layer disposed between the first and second substrates, first and second pixels, a first conductor disposed on the liquid crystal layer, First and second transistors formed on one substrate, a first pixel electrode included in the first pixel, a second pixel electrode included in the second pixel, and first and second data signal lines,
  • the first and second pixel electrodes and the first data signal line are formed on the first substrate, the first transistor is electrically connected to the first data signal line and the first pixel electrode, and the second data signal line is the second data signal line.
  • the second data signal line and the first conductor are electrically connected to each other, and the second transistor is electrically connected to the first conductor and the second pixel electrode.
  • FIG. 3 is a circuit diagram illustrating a configuration of a liquid crystal panel (including pixels A to P) according to Embodiment 1.
  • FIG. It is a top view of the field corresponding to pixel A * B of the 1st substrate. It is a top view of the field corresponding to pixel A * B of the 2nd substrate.
  • FIG. 4 is a cross-sectional view of a pixel A (corresponding to A1-A1 ′ in FIGS. 2 and 3). It is a top view of the field corresponding to pixel C * D of the 1st substrate. It is a top view of the field corresponding to pixel C * D of the 2nd substrate.
  • 7 is a cross-sectional view of a pixel C (corresponding to A3-A3 ′ in FIGS.
  • FIG. 1 is a schematic diagram illustrating a configuration of a liquid crystal display device of Example 1.
  • FIG. 11 is a schematic diagram illustrating a driving method (vertical scanning period V1) of the liquid crystal display device of FIG.
  • FIG. 11 is a schematic diagram illustrating a driving method (vertical scanning period V2) of the liquid crystal display device of FIG.
  • FIG. 11 is a timing chart showing a driving method (data signal line driving method) of the liquid crystal display device of FIG. 10.
  • FIG. 11 is a schematic diagram illustrating a data writing method (first horizontal scanning period of a vertical scanning period V1) of the liquid crystal display device of FIG.
  • FIG. 11 is a schematic diagram illustrating a data writing method (second horizontal scanning period of a vertical scanning period V1) of the liquid crystal display device of FIG.
  • FIG. 11 is a schematic diagram illustrating a data writing method (first horizontal scanning period of a vertical scanning period V2) of the liquid crystal display device of FIG.
  • FIG. 11 is a schematic diagram illustrating a data writing method (second horizontal scanning period of a vertical scanning period V2) of the liquid crystal display device of FIG.
  • FIG. 11 is a timing chart showing a driving method (data signal line driving method) of the liquid crystal display device of FIG. 10.
  • FIG. 11 is a schematic diagram illustrating a data writing method (first horizontal scanning period of a vertical scanning period V1) of the liquid crystal display device
  • FIG. 3 is a cross-sectional view illustrating a configuration of an end portion (portion along a long side) of the liquid crystal panel of Example 1.
  • It is a schematic diagram which shows the structure of the display unit of this liquid crystal panel, (a) makes 3 pixels (R * G * B) a display unit, (b) shows 6 pixels (R * G * B *) When (Y, M, C) is used as a display unit, (c) shows a case where 6 pixels (R, G, B, G, M, Y) are used as a display unit.
  • FIG. 22 is a cross-sectional view of the pixel A in the modification of FIG. 21 (corresponding to A1-A1 ′ in FIG. 21).
  • FIG. 6 is a circuit diagram showing a configuration of a liquid crystal panel (including pixels A to P) of Example 2.
  • 6 is a schematic diagram illustrating a data writing method of the liquid crystal display device of Example 2.
  • FIG. FIG. 10 is a circuit diagram showing a configuration of a liquid crystal panel (including pixels A to P) of Example 3.
  • 6 is a schematic diagram illustrating a data writing method of the liquid crystal display device of Example 3.
  • FIG. FIG. 10 is a circuit diagram showing a configuration of a liquid crystal panel (including pixels A to P) of Example 4.
  • FIG. 10 is a schematic diagram illustrating a data writing method of the liquid crystal display device of Example 4.
  • FIG. 5 is a cross-sectional view showing a modification of FIG. 4 (corresponding to a1-a1 ′ in FIGS. 29 and 30).
  • FIG. 8 is a cross-sectional view showing a modification of FIG. 7 (corresponding to a3-a3 ′ in FIGS. 32 and 33).
  • FIG. 7 It is a schematic diagram which shows another structural example of this liquid crystal display device.
  • Embodiments of the present invention will be described with reference to FIGS. 1 to 34 as follows.
  • FIG. 1 is a circuit diagram illustrating a configuration of a liquid crystal panel according to the first embodiment.
  • a liquid crystal panel (1080 lines) compatible with HDTV (high definition television) is assumed, but this is only an example.
  • the scanning direction of the liquid crystal panel (the direction along the short side) is the column direction.
  • the configuration formed on one of the two substrates (first substrate) constituting the liquid crystal panel is indicated by a solid line, and the configuration formed on the other (second substrate) is indicated by a broken line.
  • the liquid crystal panel of Example 1 includes first and second substrates and a liquid crystal layer disposed between the first and second substrates, and includes a pixel electrode P1 in the pixel column PL1 as shown in FIG.
  • Pixel A, pixel B including pixel electrode P2, pixel C including pixel electrode P3, pixel D including pixel electrode P4, pixel E including pixel electrode P541, pixel F including pixel electrode P542, pixel A pixel G including the electrode P543 and a pixel H including the pixel electrode P544 are included.
  • the pixels A to D are continuously arranged in the upper half area of the liquid crystal panel (the area on the upstream side in the scanning direction when the liquid crystal panel is divided into two in the scanning direction). Are continuously arranged in the lower half area of the liquid crystal panel (the area that is downstream in the scanning direction when the liquid crystal panel is divided into two in the scanning direction).
  • pixel electrodes P1 to P4, scanning signal lines G1 to G4, data, and data are provided in the upper half area of the first substrate (the area on the upstream side in the scanning direction when the first substrate is divided into two in the scanning direction).
  • Signal lines DX1, DX2, DX1 ', DX2', transistors T1 to T4, and storage capacitor lines CS1 to CS4 are formed, and the upper half region of the second substrate (when the second substrate is divided into two in the scanning direction,
  • the data signal lines dx1, dx2, dx1 ′, dx2 ′ and the counter (common) electrode COM are formed in a region upstream in the scanning direction.
  • the data signal line DX1 (first substrate) and the data signal line dx1 (second substrate) do not overlap, but actually they overlap (described later).
  • the data signal line DX1 ′ The (first substrate) and the data signal line dx1 ′ (second substrate) overlap.
  • the pixel electrodes P1 to P4 are arranged in this order in the column direction between the data signal line DX1 and the data signal line DX1 ′, and the pixel electrode P1 is arranged downstream of the scanning signal line G1 in the scanning direction.
  • the pixel electrode P2 is disposed on the downstream side in the scanning direction of the scanning signal line G2, the pixel electrode P3 is disposed on the downstream side in the scanning direction of the scanning signal line G3, and the pixel electrode P4 is disposed in the scanning direction of the scanning signal line G4. It is arranged downstream.
  • the pixel electrode P1 is connected to the data signal line DX1 and the scanning signal line G1 through the transistor T1, and the pixel electrode P2 is connected to the data signal line DX1 ′ and the scanning signal line G2 through the transistor T2.
  • the electrode P3 is connected to the data signal line dx1 and the scanning signal line G3 via the transistor T3, and the pixel electrode P4 is connected to the data signal line dx1 ′ and the scanning signal line G4 via the transistor T4.
  • a liquid crystal capacitor is formed between each of the pixel electrodes P1 to P4 and the counter electrode COM.
  • the storage capacitor lines CS1 to CS4 are provided in parallel with the scanning signal lines.
  • the pixel P1 forms a storage capacitor with the storage capacitor line CS1
  • the pixel P2 forms a storage capacitor with the storage capacitor line CS2
  • the pixel P3 A storage capacitor line CS3 and a storage capacitor are formed
  • the pixel P4 forms a storage capacitor line CS4 and a storage capacitor.
  • pixel electrodes P541 to P544, scanning signal lines G541 to G544, data signals are provided in the lower half area of the first substrate (area that is downstream in the scanning direction when the first substrate is divided into two in the scanning direction).
  • Lines DY1, DY2, DY1 ′, DY2 ′, transistors T541 to T544, and storage capacitor lines CS541 to CS544 are formed, and the lower half region of the second substrate (scanning when the second substrate is divided into two in the scanning direction)
  • the data signal lines dy1, dy2, dy1 ′, dy2 ′ and the counter (common) electrode COM are formed in the region on the downstream side in the direction.
  • the data signal line DY1 (first substrate) and the data signal line dy1 (second substrate) do not overlap, but actually they overlap (described later).
  • the data signal line DY1 ′ The (first substrate) and the data signal line dy1 ′ (second substrate) overlap.
  • the pixel electrodes P541 to P544 are arranged in this order in the column direction between the data signal line DY1 and the data signal line DY1 ′, and the pixel electrode P541 is arranged downstream of the scanning signal line G541 in the scanning direction.
  • the pixel electrode P542 is disposed on the downstream side in the scanning direction of the scanning signal line G542, the pixel electrode P543 is disposed on the downstream side in the scanning direction of the scanning signal line G543, and the pixel electrode P544 is disposed in the scanning direction of the scanning signal line G544. It is arranged downstream.
  • the pixel electrode P541 is connected to the data signal line DY1 and the scanning signal line G541 via the transistor T541, and the pixel electrode P542 is connected to the data signal line DY1 ′ and the scanning signal line G542 via the transistor T542.
  • the electrode P543 is connected to the data signal line dy1 and the scanning signal line G543 via the transistor T543, and the pixel electrode P544 is connected to the data signal line dy1 ′ and the scanning signal line G544 via the transistor T544.
  • a liquid crystal capacitor is formed between each of the pixel electrodes P541 to P544 and the counter electrode COM.
  • the storage capacitor lines CS541 to CS544 are provided in parallel with the scanning signal lines, the pixel P541 forms a storage capacitor with the storage capacitor line CS541, the pixel P542 forms a storage capacitor with the storage capacitor line CS542, and the pixel P543 A storage capacitor line CS543 and a storage capacitor are formed, and the pixel P544 forms a storage capacitor line CS4 and a storage capacitor.
  • data signal lines DX1, DX1 ′, DX2 and DX2 ′ are arranged in this order on the upper half of the first substrate, and data signal lines dx1, dx1 ′, dx2 are arranged on the upper half of the second substrate.
  • dx2 ′ are arranged in this order, and the pixel electrode of the pixel I adjacent to the pixel A in the row direction is provided on the first substrate and is connected to the data signal line DX2 via the transistor, and is connected to the pixel B in the row direction.
  • the pixel electrode of the pixel J adjacent to the pixel J is provided on the first substrate, connected to the data signal line DX2 ′ via the transistor, and the pixel electrode of the pixel K adjacent to the pixel C in the row direction is provided on the first substrate.
  • the pixel electrode of the pixel L that is connected to the data signal line dx2 through the transistor and is adjacent to the pixel D in the row direction is provided on the first substrate, and is connected to the data signal line dx2 ′ through the transistor.
  • data signal lines DY1, DY1 ′, DY2 and DY2 ′ are arranged in this order on the lower half of the first substrate, and data signal lines dy1, dy1 ′ are arranged on the lower half of the second substrate.
  • Dy2 and dy2 ′ are arranged in this order, and the pixel electrode of the pixel M adjacent to the pixel E in the row direction is provided on the first substrate and is connected to the data signal line DY2 through the transistor.
  • the pixel electrode of the pixel N adjacent in the row direction is provided on the first substrate, is connected to the data signal line DY2 ′ via the transistor, and the pixel electrode of the pixel O adjacent to the pixel G in the row direction is the first substrate.
  • the pixel electrode of the pixel P adjacent to the pixel H in the row direction is provided on the first substrate and connected to the data signal line dy2 ′ via the transistor.
  • FIG. 2 is a plan view showing a configuration of a portion corresponding to the pixels A and B of the first substrate (SU1)
  • FIG. 3 is a plan view showing a configuration of a portion corresponding to the pixels A and B of the second substrate (SU2).
  • FIG. 4 is a cross-sectional view of the pixel A of the liquid crystal panel LCP (corresponding to A1-A1 ′ in FIGS. 2 and 3).
  • FIG. 5 is a plan view showing a configuration of a portion corresponding to the pixels C and D of the first substrate (SU1)
  • FIG. 6 shows a configuration of a portion corresponding to the pixels C and D of the second substrate (SU2).
  • FIG. 7 is a cross-sectional view of the pixel C of the liquid crystal panel LCP (corresponding to A3-A3 ′ in FIGS. 5 and 6).
  • the extending portion g1 of the scanning signal line G1 (gate electrode of the transistor T1) and the extending portion g3 of the scanning signal line G3 (of the transistor T3)
  • the gate insulating film 21 is formed so as to cover the extending portions g1 and g3, and the data signal lines DX1 and DX1 ′, the semiconductor layer 24 of the transistor T1, and the source electrode are formed on the gate insulating film 21.
  • 8 and the drain electrode 9 the semiconductor layer 24 of the transistor T3, and the source electrode 8 and the drain electrode 9 are formed, and from the passivation film 25 and the organic insulating film 26 thicker than this so as to cover the channels of the transistors T1 and T3.
  • An interlayer insulating film (channel protective film) is formed, and the pixel electrodes P1 and P3 and the relay electrode TM1 are formed on the interlayer insulating film.
  • TM4 ⁇ TM1 ' ⁇ TM4' is formed using a light-transmitting conductive film (ITO, etc.).
  • the data signal lines dx1 and dx1 ′ are formed on the glass substrate 32, and the metal coat film MC (insulating film) is formed so as to cover the data signal lines dx1 and dx1 ′.
  • a color filter CF and a black matrix BM are formed on the film MC, an overcoat film MC (insulating film) is formed so as to cover the color filter CF and the black matrix BM, and a counter (common) is formed on the overcoat film MC.
  • the electrode COM and the relay electrodes tm1 to tm4 ⁇ tm1 ′ to tm4 ′ are formed using a light-transmitting conductive film (ITO or the like).
  • the counter electrode COM can be formed as a single unit (solid) on the entire panel, which is desirable from the viewpoint of reducing the resistance of the counter electrode COM.
  • the parasitic capacitance between the counter electrode COM and the data signal line (of the second substrate SU2) may increase, and the counter electrode COM may be divided into a plurality of parts to avoid this.
  • the counter electrodes COM can be divided and formed in stripes, and each counter electrode COM can be sized to correspond to a plurality of pixel columns (vertical one pixel column ⁇ horizontal several pixels) in accordance with the panel process.
  • the data signal line dx1 on the second substrate is provided so as to overlap (coincides in plan view) with the data signal line DX1 on the first substrate.
  • dx1 ′ is provided so as to overlap with the data signal line DX1 ′ of the first substrate (coincides in plan view), and the liquid crystal layer LCL is filled between the first substrate SU1 and the second substrate SU2, and the liquid crystal layer LCL Conductive photospacers FS3 and FS3 ′ are formed (between the first and second substrates).
  • the relay electrode TM1 is formed so as to overlap the data signal line DX1, and so as to overlap the data signal line DX1 ′.
  • the relay electrode TM1 ′ is formed, and in plan view, the data signal line DX1, the source electrode 8 of the transistor T1 (not shown), the extending part g1 of the scanning signal line G1 (gate electrode of the transistor T1), and the drain electrode of the transistor T1 9 are arranged in this order in the row direction, and the source electrode 8 of the transistor T1, the extending portion g1 of the scanning signal line G1, and the drain electrode 9 of the transistor T1 overlap the semiconductor layer 24.
  • the data signal line DX1 and the relay electrode tm1 are connected via a contact hole 11d that penetrates the interlayer insulating film, and the relay electrode tm1 and the source electrode 8 of the transistor T1 are connected via a contact hole 11b that penetrates the interlayer insulating film.
  • the drain electrode 9 of the transistor T1 and the pixel electrode P1 are connected through a contact hole 11a that penetrates the interlayer insulating film.
  • the capacitor electrode 27 is disposed so as to overlap the storage capacitor line CS1, and the capacitor electrode 27 and the pixel electrode P1 are connected via the contact hole 11c.
  • the relay electrode tm1 is formed so as to overlap with the data signal line dx1, and also overlaps with the data signal line DX1 ′.
  • the relay electrode tm1 ′ is formed, the data signal line dx1 and the relay electrode tm1 are connected via the contact hole h1, and the data signal line dx1 ′ and the relay electrode tm1 ′ are connected via the contact hole h1 ′. ing.
  • the relay electrodes TM3 and TM4 are formed so as to overlap with the data signal line DX1, and also overlap with the data signal line DX1 ′. In this way, the relay electrodes TM3 ′ and TM4 ′ are formed.
  • the data signal line DX1, the source electrode 8 of the transistor T3 (not shown), the extending portion g3 of the scanning signal line G3 (the gate electrode of the transistor T1), and The drain electrode 9 of the transistor T3 is arranged in this order in the row direction, and the source electrode 8 of the transistor T3, the extending portion g3 of the scanning signal line G3, and the drain electrode 9 of the transistor T3 overlap with the semiconductor layer 24.
  • the relay electrode TM3 is in contact with the conductive photospacer FS3, the relay electrode TM3 and the source electrode 8 of the transistor T3 are connected via a contact hole 11b that penetrates the interlayer insulating film, and the drain electrode 9 of the transistor T3.
  • the pixel electrode P3 are connected through a contact hole 11a penetrating the interlayer insulating film.
  • the relay electrode TM4 ′ is in contact with the conductive photospacer FS4 ′, and the relay electrode TM4 ′ and the source electrode 8 of the transistor T4 are connected via a contact hole 11b that penetrates the interlayer insulating film, and the transistor T4.
  • the drain electrode 9 and the pixel electrode P4 are connected through a contact hole 11a penetrating the interlayer insulating film.
  • the capacitor electrode 27 is arranged so as to overlap with the storage capacitor line CS3, and the capacitor electrode 27 and the pixel electrode P3 are connected via the contact hole 11c.
  • the relay electrodes tm3 and tm4 are formed so as to overlap the data signal line dx1, and the data signal line DX1 ′ is formed.
  • the relay electrodes tm3 ′ and tm4 ′ are formed so as to overlap with each other, the data signal line dx1 and the relay electrode tm3 are connected via the contact hole h3, and the data signal line dx1 ′ and the relay electrode tm4 ′ are connected to the contact hole h4 ′.
  • the relay electrode tm3 is in contact with the conductive photospacer FS3, and the relay electrode tm4 'is in contact with the conductive photospacer FS4'.
  • the data signal line dx1 on the second substrate is connected via the contact hole h3, the relay electrode tm3 on the second substrate, the conductive photo spacer FS3 on the liquid crystal layer, the relay electrode TM3 on the first substrate, and the contact hole 11b.
  • the data signal line dx1 ′ of the second substrate includes the contact hole h4 ′, the relay electrode tm4 ′ of the second substrate, the conductive photospacer FS4 ′ of the liquid crystal layer, the relay electrode TM4 ′ of the first substrate, and the contact hole.
  • 11b is connected to the source electrode 8 of the transistor T4 on the first substrate.
  • the resistance value can be made uniform between the pixels A and C.
  • FIG. 8 is a schematic diagram showing the overall configuration of the first substrate
  • FIG. 9 is a schematic diagram showing the overall configuration of the second substrate
  • FIG. 10 is a schematic diagram showing the overall configuration of the liquid crystal panel.
  • the display area of the first substrate includes a plurality of scanning signal lines, a plurality of data signal lines, a plurality of transistors, and a plurality of pixel electrodes.
  • a plurality of source connection pads SP are arranged along two long sides (sides parallel to the row direction), and a plurality of source connection pads SP are arranged along two short sides (sides parallel to the column direction).
  • Gate connection pads GP are arranged.
  • the display area of the second substrate includes a plurality of data signal lines, and the non-display area of the second substrate has two long sides (sides parallel to the row direction).
  • a plurality of inter-substrate connection pads BP are arranged along the line. Each inter-substrate connection pad BP is connected to a data signal line. Then, after the first substrate in FIG. 8 and the second substrate in FIG. 9 are bonded together so that the data signal lines overlap each other, the liquid crystal material is filled to obtain the liquid crystal panel shown in FIG.
  • the signal line is connected to the source connection pad SP of the first substrate via the inter-substrate connection pad BP (second substrate) and the inter-substrate connection pad bp (first substrate).
  • FIG. 11 is a cross-sectional view showing the configuration of the end region TA of FIG.
  • the first substrate includes a source connection pad SP, a gate metal GM (same layer as the scanning signal line), a connection electrode CE (same layer as the data signal line), and an inter-substrate connection pad bp (pixel).
  • an inter-substrate connection pad BP in the same layer as the counter electrode
  • conductive connection beads BZ are provided between the first and second substrates.
  • the source connection pad SP is connected to the connection electrode CE through the gate metal GM, and the connection electrode CE is connected to the inter-substrate connection pad through the contact hole penetrating the interlayer insulating film (25, 26) of the first substrate.
  • the inter-substrate connection pad bp is connected to the inter-substrate connection pad BP of the second substrate via the connection beads BZ, and the inter-substrate connection pad BP penetrates the metal coat film MC and the overcoat film OC.
  • the hole is connected to the data signal line dx1 of the second substrate.
  • the source connection pad SP is connected to the source driver SDX via the flexible printed circuit board FC.
  • the source connection pad SP and the inter-substrate connection pad BP ⁇ bp are each formed of, for example, ITO. Since the gate metal GM is easily corroded, it is covered with the source connection pad SP (ITO) and an insulating film (the gate insulating film 21 and the interlayer insulating film 25).
  • each pixel corresponds to one primary color
  • the display units are R (red), G (green), and B (blue). It may be 3 pixels (see FIG. 12A), 6 pixels of R, G, B, Y (yellow), M (magenta), and C (cyan) (see FIG. 12B), or R 6 pixels of G, B, G, M, and Y may be used (see FIG. 12C).
  • the liquid crystal display device provided with the present liquid crystal panel is configured as shown in FIG. 13, for example, and the upper half of the data signal lines (DX1, DX2, DX1 ′, DX2 ′, dx1, dx2, dx1 ′, dx2 ′, etc.)
  • a source driver SDX that drives the data signal lines (DY1, DY2, DY1 ′, DY2 ′, dy1, dy2, dy1 ′, dy2 ′, etc.) on the lower half of the panel, and each scanning signal line
  • Two gate drivers GDL / GDR connected to both sides and a display control circuit DCC for controlling the source drivers SDX / SDY and the gate drivers GDL / GDR are provided.
  • FIGS. 14 and 15 are schematic diagrams showing a driving method of scanning signal lines of the present liquid crystal display device
  • FIG. 16 is a timing chart showing a driving method of data signal lines of the present liquid crystal display device. These are schematic diagrams showing a data writing method of the present liquid crystal display device.
  • each scanning signal line (G 1, G 2, g 3, g 4, and so on) are generated in the first horizontal scanning period (H 1) of a certain vertical scanning period (V 1).
  • G541, G542, g543, and g544) are simultaneously selected, and then eight scanning signal lines (G5, G6, g7, g8, G545, G546, g547, and g548) are simultaneously selected in the second horizontal scanning period (H2).
  • eight scanning signal lines G9, G10, g11, g12, G549, G550, g551, and g552) are simultaneously selected.
  • the data signal of the first line of the frame F2 is written to the pixels connected from the data signal line DX1 to the scanning signal line G1, and scanning is performed from the data signal line DX1 ′.
  • the data signal of the second line of the frame F2 is written to the pixel connected to the signal line G2, and the data signal of the third line of the frame F2 is written to the pixel connected to the scanning signal line G3 from the data signal line dx1.
  • the data signal of the fourth line of the frame F2 is written to the pixel connected to the scanning signal line G4 from the data signal line dx1 ′, and the 541st line of the frame F1 is written to the pixel connected to the scanning signal line G541 from the data signal line DY1. Is written to the pixels connected to the scanning signal line G542 from the data signal line DY1 ′.
  • a pixel in which the data signal of the 543rd line of the frame F1 is written to the pixel connected to the scanning signal line G543 from the data signal line dy1 and the data signal line dy1 ′ is connected to the scanning signal line G544 is written.
  • the data signal of the 544th line of the frame F1 is written into the frame F1.
  • the data signals from the data signal lines DX1 and DY1 have a positive polarity
  • the data signals from the data signal lines DX1 ′ and DY1 ′ have a positive polarity.
  • the data signal from the data signal lines dx1 and dy1 has a positive polarity
  • the data signal from the data signal lines dx1 ′ and dy1 ′ has a negative polarity.
  • the pixel A has a positive polarity
  • the pixel B has a negative polarity
  • the pixel C has a positive polarity
  • the pixel D has a negative polarity
  • the pixel E has a positive polarity
  • Pixel F has negative polarity
  • pixel G has positive polarity
  • pixel H has negative polarity.
  • the data signals from the data signal lines DX2 and DY2 have a negative polarity
  • the data signals from the data signal lines DX2 ′ and DY2 ′ have a positive polarity.
  • the polarity, the data signal from the data signal lines dx2 ⁇ dy2 has a negative polarity
  • the data signal from the data signal lines dx2 ′ ⁇ dy2 ′ has a positive polarity.
  • the pixel I adjacent to the pixel A in the row direction has a negative polarity
  • the pixel J adjacent to the pixel B in the row direction has a positive polarity
  • the pixel C The pixel K adjacent to the pixel in the row direction is negative polarity
  • the pixel L adjacent to the pixel D in the row direction is positive polarity
  • the pixel M adjacent to the pixel E in the row direction is negative polarity
  • the pixel N is adjacent to the pixel F in the row direction.
  • the pixel O adjacent to the pixel G in the row direction is negative polarity
  • the pixel P adjacent to the pixel H in the row direction is positive polarity.
  • the data signals from the data signal lines DX1 and DY1 are positive, and the data signals from the data signal lines DX1 ′ and DY1 ′ are negative.
  • the data signals from the data signal lines dx1 and dy1 have a positive polarity, and the data signals from the data signal lines dx1 ′ and dy1 ′ have a negative polarity.
  • data signals having polarities as shown in FIG. 18 are written into the four pixels following the pixel D and the four pixels following the pixel H.
  • the data signals from the data signal lines DX1 and DY1 have a negative polarity, and the data signal lines DX1 ′.
  • the data signal from data signal lines dx1 and dy1 has a negative polarity
  • the first horizontal scanning period (H1) of the vertical scanning period (V2) as shown in FIG.
  • the pixel A has a negative polarity
  • the pixel B has a positive polarity
  • the pixel C has a negative polarity
  • the pixel D has a positive polarity.
  • the pixel E has a negative polarity
  • the pixel F has a positive polarity
  • the pixel G has a negative polarity
  • the pixel H has a positive polarity (the data signal polarity from each data signal line is inverted every vertical scanning period).
  • the data signals from the data signal lines DX1 and DY1 have a negative polarity, and the data signal lines DX1 ′ and DY1 ′. From the data signal lines dx1 and dy1 have a negative polarity, and the data signals from the data signal lines dx1 ′ and dy1 ′ have a positive polarity.
  • the second horizontal scanning period (H2) of the vertical scanning period (V2) data signals having polarities as shown in FIG. 20 are written in the four pixels following the pixel D and the four pixels following the pixel H.
  • the liquid crystal panel can be driven at 8 ⁇ speed (the first and second substrates can be driven at 4 ⁇ speed), a liquid crystal display device (for example, a high-definition liquid crystal display device or It is suitable for a three-dimensional display compatible liquid crystal display device.
  • each of the first and second substrates is driven at a quadruple speed, but the present invention is not limited to this.
  • Each of the first and second substrates can be driven at a constant speed (1 ⁇ speed) or 2 ⁇ speed.
  • dot inversion driving as shown in FIGS. 17 to 20 can be realized while the polarity inversion period of the data signal of each data signal line is one vertical scanning period, and the power consumption of the source driver is suppressed and displayed. Improvement in quality can be achieved at the same time.
  • the data signal line DX1 is once connected to the source electrode 8 of the transistor T1 via the relay electrode TM1 in order to make the resistance value between the data signal line and the source electrode of the transistor uniform between the pixels A and C.
  • the relay electrode TM1 is removed, and as shown in FIG. 21 and FIG.
  • the extending portion of the signal line DX1 may be overlaid on the semiconductor layer 24, and the extending portion may function as a source electrode.
  • FIG. 2 to FIG. 7 can be modified as shown in FIG. 29 to FIG. That is, in the first substrate SU1, the relay electrodes TM1 ′, TM2, TM3 ′, TM4 are not formed, the conductive photospacers FS3 ′, FS4 are not provided, and the relay electrodes tm1, tm1 ′ are also formed in the second substrate SU2. Without forming the tm2, tm2 ′, tm3 ′, and tm4, the counter electrode COM is expanded to the formation region of the relay electrodes tm1, tm1 ′, tm2, tm2 ′, tm3 ′, and tm4. ) The resistance value can also be lowered.
  • Example 2 The liquid crystal panel of FIG. 1 is modified, and as shown in FIG. 23, for the upper half of the liquid crystal panel, the pixel electrode of the pixel A is connected to the data signal line DX1 through the transistor, and the pixel electrode of the pixel B is connected to the transistor The pixel electrode of the pixel C is connected to the data signal line dx1 ′ via the transistor, and the pixel electrode of the pixel D is connected to the data signal line DX1 ′ via the transistor.
  • the pixel electrode of the pixel I is connected to the data signal line dx2 through the transistor, the pixel electrode of the pixel J is connected to the data signal line DX2 through the transistor, and the pixel electrode of the pixel K is connected to
  • the transistor L is connected to the data signal line DX2 ′, the pixel electrode of the pixel L is connected to the data signal line dx2 ′ via the transistor, and the lower half of the liquid crystal panel is also connected to the upper half. It is also possible to have the same connection relationship.
  • the data signal polarities of the data signal lines DX1, DX1 ′, DX2, DX2′dX1, dX1 ′, dX2, and dX2 ′ are set to the first polarity, the second polarity, and the first polarity, respectively.
  • Polarity, 2nd polarity, 2nd polarity, 1st polarity, 2nd polarity, 1st polarity (1st and 2nd polarities are positive or negative polarity respectively
  • the lower half of the liquid crystal panel is driven in the same way as the upper half
  • Example 3 The liquid crystal panel of FIG. 1 is modified, and as shown in FIG. 25, the pixel electrode of the pixel A is connected to the data signal line DX1 through the transistor and the pixel electrode of the pixel B is connected to the transistor in the upper half of the liquid crystal panel. Is connected to the data signal line dx1, the pixel electrode of the pixel C is connected to the data signal line DX1 ′ via the transistor, and the pixel electrode of the pixel D is connected to the data signal line dx1 ′ via the transistor.
  • the pixel electrode of the pixel I is connected to the data signal line dx2 through the transistor, the pixel electrode of the pixel J is connected to the data signal line DX2 through the transistor, and the pixel electrode of the pixel K is connected to
  • the transistor L is connected to the data signal line dx2 ′, the pixel electrode of the pixel L is connected to the data signal line DX2 ′ via the transistor, and the lower half of the liquid crystal panel is also connected to the upper half. It is also possible to have the same connection relationship.
  • the data signal polarities of the data signal lines DX1, DX1 ′, DX2, DX2′dX1, dX1 ′, dX2, dX2 ′ are set to the first polarity, the first polarity, and the first polarity, respectively.
  • the lower half of the liquid crystal panel is driven in the same way as the upper half
  • dot inversion driving as shown in FIG. 26 can be realized.
  • the data signals of the data signal lines on the same substrate have the same polarity, interference between the data signal lines (influence of parasitic capacitance or the like) can be suppressed.
  • Example 4 The liquid crystal panel of FIG. 1 is modified, and as shown in FIG. 27, the pixel electrode of the pixel A is connected to the data signal line DX1 through the transistor and the pixel electrode of the pixel B is connected to the transistor in the upper half of the liquid crystal panel. Is connected to the data signal line dx1, the pixel electrode of the pixel C is connected to the data signal line DX1 ′ via the transistor, and the pixel electrode of the pixel D is connected to the data signal line dx1 ′ via the transistor.
  • the pixel electrode of the pixel I is connected to the data signal line DX2 through the transistor, the pixel electrode of the pixel J is connected to the data signal line dx2 through the transistor, and the pixel electrode of the pixel K is connected to
  • the transistor L is connected to the data signal line DX2 ′, the pixel electrode of the pixel L is connected to the data signal line dx2 ′ via the transistor, and the lower half of the liquid crystal panel is also connected to the upper half. It is also possible to have the same connection relationship.
  • the data signal polarities of the data signal lines DX1, DX1 ′, DX2, DX2′dX1, dX1 ′, dX2, dX2 ′ are set to the first polarity, the first polarity, the second polarity, respectively.
  • Polarity, 2nd polarity, 2nd polarity, 2nd polarity, 1st polarity, 1st polarity (1st and 2nd polarities are positive or negative polarity respectively
  • the lower half of the liquid crystal panel is driven in the same way as the upper half
  • the present liquid crystal panel includes the first and second substrates, the liquid crystal layer disposed between the first and second substrates, the first and second pixels, and the first liquid crystal layer disposed on the liquid crystal layer.
  • a conductor, first and second transistors formed on the first substrate, a first pixel electrode included in the first pixel, a second pixel electrode included in the second pixel, and first and second data signals First and second pixel electrodes and a first data signal line are formed on the first substrate, the first transistor is electrically connected to the first data signal line and the first pixel electrode, and the second data
  • the signal line is formed on the second substrate, the second data signal line and the first conductor are electrically connected, and the second transistor is electrically connected to the first conductor and the second pixel electrode. It is characterized by being.
  • the liquid crystal panel includes first and second substrates, a liquid crystal layer disposed between the first and second substrates, first and second pixels, a conductor, and first and second substrates formed on the first substrate.
  • One data signal line is formed on the first substrate, the first transistor is electrically connected to the first data signal line and the first pixel electrode, the second data signal line is formed on the second substrate, and the second data signal
  • the line and the conductor can be electrically connected, and the second transistor can be electrically connected to the conductor and the second pixel electrode.
  • the liquid crystal display device including the liquid crystal panel for example, as shown in FIG.
  • the first data signal line DX1 is driven by the first substrate data signal line driving circuit SDX1 connected to the first substrate, and the second data signal line DX1 is driven by the second substrate data signal line driving circuit SDX1.
  • the data signal line dx1 is driven by the second substrate data signal line driving circuit SDX2 connected to the second substrate.
  • the conductor may be provided on the liquid crystal layer (for example, a conductive spacer may be used), may be provided on a seal portion between both substrates, or may be provided on an end surface (side surface) of the liquid crystal panel. Good.
  • a counter electrode facing the first pixel electrode is formed on the second substrate, a first relay electrode is formed in the same layer as the first pixel electrode, and a second relay is formed in the same layer as the counter electrode.
  • An electrode is formed, the second data signal line and the second relay electrode are electrically connected, the first and second relay electrodes are electrically connected via the first conductor, and the first relay electrode and the second relay electrode A configuration in which one conductive electrode of two transistors is electrically connected may be employed.
  • the first conductor may be a spacer that adjusts the thickness of the liquid crystal layer.
  • the first and second data signal lines may be arranged so as to overlap each other.
  • a third relay electrode is formed in the same layer as the first pixel electrode, and the first data signal line and one conductive electrode of the first transistor are electrically connected via the third relay electrode. It can also be set as the structure which is.
  • the first substrate includes the third and fourth pixel electrodes and the third data signal line;
  • the three transistors are electrically connected to the third data signal line and the third pixel electrode, the fourth data signal line is formed on the second substrate, and the fourth data signal line and the second conductor are electrically connected.
  • the fourth transistor may be configured to be electrically connected to the second conductor and the fourth pixel electrode.
  • the present liquid crystal panel includes first to fourth scanning signal lines formed on a first substrate.
  • the first to fourth transistors are electrically connected to the first to fourth scanning signal lines, respectively, and the scanning direction is set.
  • the first to fourth pixels may be included in the same pixel column.
  • the first to fourth pixels in the pixel row may be arranged successively in the order of the first pixel, the third pixel, the second pixel, and the fourth pixel.
  • the first to fourth pixels in the pixel row may be arranged in succession in the order of the first pixel, the second pixel, the third pixel, and the fourth pixel.
  • the first to fourth pixels in the pixel row may be arranged successively in the order of the first pixel, the second pixel, the fourth pixel, and the third pixel.
  • an inter-substrate connection pad is provided in each non-display area of the first and second substrates, and the inter-substrate connection pad of the second substrate and the second data signal line are electrically connected.
  • the inter-substrate connection pad of the first substrate and the inter-substrate connection pad of the second substrate may be connected via a conductive photospacer or conductive beads.
  • a plurality of driver connection pads are provided on the first substrate, the first data signal line and one driver connection pad are electrically connected, and the inter-substrate connection pad of the first substrate is connected to another driver connection. It can also be set as the structure electrically connected with the pad.
  • This liquid crystal display device includes the liquid crystal panel.
  • the first and second scanning signal lines may be simultaneously selected.
  • the present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.
  • the present invention is suitable for a liquid crystal panel that requires high-speed driving.

Abstract

This liquid crystal panel comprises: first and second substrates; a liquid crystal layer arranged between the first and second substrates; first and second pixels; a first conductor arranged on the liquid crystal layer; first and second transistors formed on the first substrate; a first pixel electrode included in the first pixel; a second pixel electrode included in the second pixel; and first and second data signal lines. The liquid crystal panel is configured such that: the first and second pixel electrodes and the first data signal line are formed on the first substrate; the first transistor is electrically connected to the first data signal line and the first pixel electrode; the second data signal line is formed on the second substrate; the second data signal line and the first conductor are electrically connected; the second transistor is electrically connected to the first conductor and the second pixel electrode; and the liquid crystal panel can be driven at high speed.

Description

液晶パネル、液晶表示装置、テレビジョン受像機Liquid crystal panel, liquid crystal display device, television receiver
　本発明は、液晶パネルに含まれる２つの基板の構造に関する。 The present invention relates to the structure of two substrates included in a liquid crystal panel.
　一般に液晶パネルは、アクティブマトリクス基板とこれに対向する対向基板とこれら両基板間に配された液晶層とを備え、アクティブマトリクス基板には、データ信号線と、走査信号線と、データ信号線および走査信号線に接続されたトランジスタと、該トランジスタに接続された画素電極とが形成され、対向基板には、共通電極とカラーフィルタおよびブラックマトリクスとが形成される。液晶パネルを備えた液晶表示装置では、アクティブマトリクス基板の走査信号線およびデータ信号線がそれぞれ、ソースドライバおよびゲートドライバによって駆動される。なお、文献１には、液晶パネルの歩留まりを高めるため、対向基板側に、ソースドライバとゲートドライバを形成する構成が開示されている。 In general, a liquid crystal panel includes an active matrix substrate, a counter substrate facing the active matrix substrate, and a liquid crystal layer disposed between the two substrates. The active matrix substrate includes a data signal line, a scanning signal line, a data signal line, and a data signal line. A transistor connected to the scanning signal line and a pixel electrode connected to the transistor are formed, and a common electrode, a color filter, and a black matrix are formed on the counter substrate. In a liquid crystal display device including a liquid crystal panel, scanning signal lines and data signal lines of an active matrix substrate are driven by a source driver and a gate driver, respectively. Reference 1 discloses a configuration in which a source driver and a gate driver are formed on the counter substrate side in order to increase the yield of the liquid crystal panel.
日本国公開特許公報「特開平１１－２０２３６４号」公報Japanese Patent Publication “JP 11-202364 A”
　近年では高精細化や３次元表示を実現するべく、液晶パネルのさらなる高速駆動が求められているが、従来の液晶パネルでは、これ以上の高速駆動が難しいという問題がある。１水平走査期間をさらに短縮すると、必要な画素充電率を確保できなくなるおそれが高いためである。 In recent years, there has been a demand for higher-speed driving of liquid crystal panels in order to achieve higher definition and three-dimensional display. However, conventional liquid crystal panels have a problem that it is difficult to drive at higher speeds. This is because if the one horizontal scanning period is further shortened, there is a high possibility that a required pixel charging rate cannot be secured.
　本発明の目的は、さらなる高速駆動を可能とする液晶パネルを実現することにある。 An object of the present invention is to realize a liquid crystal panel that can be driven at a higher speed.
　本液晶パネルは、第１および第２基板と、第１および第２基板間に配された液晶層と、第１および第２画素と、上記液晶層に配された第１導電体と、第１基板に形成された第１および第２トランジスタと、第１画素に含まれる第１画素電極と、第２画素に含まれる第２画素電極と、第１および第２データ信号線とを備え、第１および第２画素電極並びに第１データ信号線が第１基板に形成され、第１トランジスタは第１データ信号線および第１画素電極と電気的に接続され、第２データ信号線は第２基板に形成され、第２データ信号線と第１導電体とが電気的に接続されるとともに、第２トランジスタは第１導電体および第２画素電極と電気的に接続されている。 The liquid crystal panel includes first and second substrates, a liquid crystal layer disposed between the first and second substrates, first and second pixels, a first conductor disposed on the liquid crystal layer, First and second transistors formed on one substrate, a first pixel electrode included in the first pixel, a second pixel electrode included in the second pixel, and first and second data signal lines, The first and second pixel electrodes and the first data signal line are formed on the first substrate, the first transistor is electrically connected to the first data signal line and the first pixel electrode, and the second data signal line is the second data signal line. The second data signal line and the first conductor are electrically connected to each other, and the second transistor is electrically connected to the first conductor and the second pixel electrode.
　上記構成によれば、例えば、第１および第２画素電極に同時にデータ信号を書き込むことが可能となり、さらなる高速駆動が実現される。 According to the above configuration, for example, it becomes possible to simultaneously write data signals to the first and second pixel electrodes, thereby realizing further high-speed driving.
実施例１の液晶パネル（画素Ａ～Ｐ含む）の構成を示す回路図である。3 is a circuit diagram illustrating a configuration of a liquid crystal panel (including pixels A to P) according to Embodiment 1. FIG. 第１基板の画素Ａ・Ｂに対応する領域の平面図である。It is a top view of the field corresponding to pixel A * B of the 1st substrate. 第２基板の画素Ａ・Ｂに対応する領域の平面図である。It is a top view of the field corresponding to pixel A * B of the 2nd substrate. 画素Ａの断面図（図２・３のＡ１－Ａ１’に対応）である。FIG. 4 is a cross-sectional view of a pixel A (corresponding to A1-A1 ′ in FIGS. 2 and 3). 第１基板の画素Ｃ・Ｄに対応する領域の平面図である。It is a top view of the field corresponding to pixel C * D of the 1st substrate. 第２基板の画素Ｃ・Ｄに対応する領域の平面図である。It is a top view of the field corresponding to pixel C * D of the 2nd substrate. 画素Ｃの断面図（図５・６のＡ３－Ａ３’に対応）である。7 is a cross-sectional view of a pixel C (corresponding to A3-A3 ′ in FIGS. 5 and 6). FIG. 第１基板の全体（端部を含む）のレイアウトを示す模式図である。It is a schematic diagram which shows the layout of the whole 1st board | substrate (an edge part is included). 第２基板の全体（端部を含む）のレイアウトを示す模式図である。It is a schematic diagram which shows the layout of the whole 2nd board | substrate (an edge part is included). 図８の第１基板と図９の第２基板との貼り合わせ例を示す模式図である。It is a schematic diagram which shows the example of bonding of the 1st board | substrate of FIG. 8, and the 2nd board | substrate of FIG. 実施例１の液晶表示装置の構成を示す模式図である。1 is a schematic diagram illustrating a configuration of a liquid crystal display device of Example 1. FIG. 図１０の液晶表示装置の駆動方法（垂直走査期間Ｖ１）を示す模式図である。FIG. 11 is a schematic diagram illustrating a driving method (vertical scanning period V1) of the liquid crystal display device of FIG. 図１０の液晶表示装置の駆動方法（垂直走査期間Ｖ２）を示す模式図である。FIG. 11 is a schematic diagram illustrating a driving method (vertical scanning period V2) of the liquid crystal display device of FIG. 図１０の液晶表示装置の駆動方法（データ信号線の駆動方法）を示すタイミングチャートである。11 is a timing chart showing a driving method (data signal line driving method) of the liquid crystal display device of FIG. 10. 図１０の液晶表示装置のデータ書き込み方法（垂直走査期間Ｖ１の第１水平走査期間）を示す模式図である。FIG. 11 is a schematic diagram illustrating a data writing method (first horizontal scanning period of a vertical scanning period V1) of the liquid crystal display device of FIG. 図１０の液晶表示装置のデータ書き込み方法（垂直走査期間Ｖ１の第２水平走査期間）を示す模式図である。FIG. 11 is a schematic diagram illustrating a data writing method (second horizontal scanning period of a vertical scanning period V1) of the liquid crystal display device of FIG. 図１０の液晶表示装置のデータ書き込み方法（垂直走査期間Ｖ２の第１水平走査期間）を示す模式図である。FIG. 11 is a schematic diagram illustrating a data writing method (first horizontal scanning period of a vertical scanning period V2) of the liquid crystal display device of FIG. 図１０の液晶表示装置のデータ書き込み方法（垂直走査期間Ｖ２の第２水平走査期間）を示す模式図である。FIG. 11 is a schematic diagram illustrating a data writing method (second horizontal scanning period of a vertical scanning period V2) of the liquid crystal display device of FIG. 実施例１の液晶パネルの端部（長辺に沿った部分）構成を示す断面図である。FIG. 3 is a cross-sectional view illustrating a configuration of an end portion (portion along a long side) of the liquid crystal panel of Example 1. 本液晶パネルの表示単位の構成を示す模式図であり、（ａ）は、３画素（Ｒ・Ｇ・Ｂ）を表示単位とする場合、（ｂ）は、６画素（Ｒ・Ｇ・Ｂ・Ｙ・Ｍ・Ｃ）を表示単位とする場合、（ｃ）は、６画素（Ｒ・Ｇ・Ｂ・Ｇ・Ｍ・Ｙ）を表示単位とする場合を示している。It is a schematic diagram which shows the structure of the display unit of this liquid crystal panel, (a) makes 3 pixels (R * G * B) a display unit, (b) shows 6 pixels (R * G * B *) When (Y, M, C) is used as a display unit, (c) shows a case where 6 pixels (R, G, B, G, M, Y) are used as a display unit. 第１基板の変形例（第１基板の画素Ａ・Ｂに対応する領域）を示す平面図である。It is a top view which shows the modification (area | region corresponding to pixel A * B of a 1st board | substrate) of a 1st board | substrate. 図２１の変形例での画素Ａの断面図（図２１のＡ１－Ａ１’に対応）である。FIG. 22 is a cross-sectional view of the pixel A in the modification of FIG. 21 (corresponding to A1-A1 ′ in FIG. 21). 実施例２の液晶パネル（画素Ａ～Ｐ含む）の構成を示す回路図である。FIG. 6 is a circuit diagram showing a configuration of a liquid crystal panel (including pixels A to P) of Example 2. 実施例２の液晶表示装置のデータ書き込み方法を示す模式図である。6 is a schematic diagram illustrating a data writing method of the liquid crystal display device of Example 2. FIG. 実施例３の液晶パネル（画素Ａ～Ｐ含む）の構成を示す回路図である。FIG. 10 is a circuit diagram showing a configuration of a liquid crystal panel (including pixels A to P) of Example 3. 実施例３の液晶表示装置のデータ書き込み方法を示す模式図である。6 is a schematic diagram illustrating a data writing method of the liquid crystal display device of Example 3. FIG. 実施例４の液晶パネル（画素Ａ～Ｐ含む）の構成を示す回路図である。FIG. 10 is a circuit diagram showing a configuration of a liquid crystal panel (including pixels A to P) of Example 4. 実施例４の液晶表示装置のデータ書き込み方法を示す模式図である。FIG. 10 is a schematic diagram illustrating a data writing method of the liquid crystal display device of Example 4. 図２の変形例を示す平面図である。It is a top view which shows the modification of FIG. 図３の変形例を示す平面図である。It is a top view which shows the modification of FIG. 図４の変形例（図２９・３０のａ１－ａ１’に対応）を示す断面図である。FIG. 5 is a cross-sectional view showing a modification of FIG. 4 (corresponding to a1-a1 ′ in FIGS. 29 and 30). 図５の変形例を示す平面図である。It is a top view which shows the modification of FIG. 図６の変形例を示す平面図である。It is a top view which shows the modification of FIG. 図７の変形例（図３２・３３のａ３－ａ３’に対応）を示す断面図である。FIG. 8 is a cross-sectional view showing a modification of FIG. 7 (corresponding to a3-a3 ′ in FIGS. 32 and 33). 本液晶表示装置の別構成例を示す模式図である。It is a schematic diagram which shows another structural example of this liquid crystal display device.
　本発明の実施の形態を、図１～３４を用いて説明すれば、以下のとおりである。 Embodiments of the present invention will be described with reference to FIGS. 1 to 34 as follows.
　〔実施例１〕
　図１は実施例１にかかる液晶パネルの構成を示す回路図である。なお、以下の説明では、ＨＤＴＶ（高精細度テレビジョン）対応の液晶パネル（１０８０ライン）を前提とするがこれは一例に過ぎない。また、説明の便宜のため、液晶パネルの走査方向（短辺に沿う方向）を列方向とする。また、原則として、液晶パネルを構成する２つの基板の一方（第１基板）に形成される構成を実線で、他方（第２基板）に形成される構成を破線で示すものとする。 [Example 1]
FIG. 1 is a circuit diagram illustrating a configuration of a liquid crystal panel according to the first embodiment. In the following description, a liquid crystal panel (1080 lines) compatible with HDTV (high definition television) is assumed, but this is only an example. For convenience of explanation, the scanning direction of the liquid crystal panel (the direction along the short side) is the column direction. In principle, the configuration formed on one of the two substrates (first substrate) constituting the liquid crystal panel is indicated by a solid line, and the configuration formed on the other (second substrate) is indicated by a broken line.
　実施例１の液晶パネルは、第１および第２基板と、第１および第２基板間に配された液晶層とを備え、図１に示すように、画素列ＰＬ１に、画素電極Ｐ１を含む画素Ａと、画素電極Ｐ２を含む画素Ｂと、画素電極Ｐ３を含む画素Ｃと、画素電極Ｐ４を含む画素Ｄと、画素電極Ｐ５４１を含む画素Ｅと、画素電極Ｐ５４２を含む画素Ｆと、画素電極Ｐ５４３を含む画素Ｇと、画素電極Ｐ５４４を含む画素Ｈとが含まれている。 The liquid crystal panel of Example 1 includes first and second substrates and a liquid crystal layer disposed between the first and second substrates, and includes a pixel electrode P1 in the pixel column PL1 as shown in FIG. Pixel A, pixel B including pixel electrode P2, pixel C including pixel electrode P3, pixel D including pixel electrode P4, pixel E including pixel electrode P541, pixel F including pixel electrode P542, pixel A pixel G including the electrode P543 and a pixel H including the pixel electrode P544 are included.
　なお、画素Ａ～画素Ｄは、液晶パネルの上半分の領域（液晶パネルを走査方向に２分割したときに、走査方向上流側となる領域）に、連続して並べられ、画素Ｅ～画素Ｈは、液晶パネルの下半分の領域（液晶パネルを走査方向に２分割したときに、走査方向下流側となる領域）に、連続して並べられている。 The pixels A to D are continuously arranged in the upper half area of the liquid crystal panel (the area on the upstream side in the scanning direction when the liquid crystal panel is divided into two in the scanning direction). Are continuously arranged in the lower half area of the liquid crystal panel (the area that is downstream in the scanning direction when the liquid crystal panel is divided into two in the scanning direction).
　ここで、第１基板の上半分の領域（第１基板を走査方向に２分割したときに、走査方向上流側となる領域）には、画素電極Ｐ１～Ｐ４、走査信号線Ｇ１～Ｇ４、データ信号線ＤＸ１・ＤＸ２・ＤＸ１’・ＤＸ２’、トランジスタＴ１～Ｔ４、および保持容量配線ＣＳ１～ＣＳ４が形成され、第２基板の上半分の領域（第２基板を走査方向に２分割したときに、走査方向上流側となる領域）には、データ信号線ｄｘ１・ｄｘ２・ｄｘ１’・ｄｘ２’および対向（共通）電極ＣＯＭが形成される。 Here, pixel electrodes P1 to P4, scanning signal lines G1 to G4, data, and data are provided in the upper half area of the first substrate (the area on the upstream side in the scanning direction when the first substrate is divided into two in the scanning direction). Signal lines DX1, DX2, DX1 ', DX2', transistors T1 to T4, and storage capacitor lines CS1 to CS4 are formed, and the upper half region of the second substrate (when the second substrate is divided into two in the scanning direction, The data signal lines dx1, dx2, dx1 ′, dx2 ′ and the counter (common) electrode COM are formed in a region upstream in the scanning direction.
　図１では、データ信号線ＤＸ１（第１基板）とデータ信号線ｄｘ１（第２基板）とが重なっていないが、実際には両者は重なっており（後述）、同様に、データ信号線ＤＸ１’（第１基板）とデータ信号線ｄｘ１’（第２基板）とが重なっている。そして、平面視において、データ信号線ＤＸ１とデータ信号線ＤＸ１’との間に画素電極Ｐ１～Ｐ４がこの順に列方向に並べられ、画素電極Ｐ１は、走査信号線Ｇ１の走査方向下流側に配され、画素電極Ｐ２は、走査信号線Ｇ２の走査方向下流側に配され、画素電極Ｐ３は、走査信号線Ｇ３の走査方向下流側に配され、画素電極Ｐ４は、走査信号線Ｇ４の走査方向下流側に配されている。 In FIG. 1, the data signal line DX1 (first substrate) and the data signal line dx1 (second substrate) do not overlap, but actually they overlap (described later). Similarly, the data signal line DX1 ′ The (first substrate) and the data signal line dx1 ′ (second substrate) overlap. In plan view, the pixel electrodes P1 to P4 are arranged in this order in the column direction between the data signal line DX1 and the data signal line DX1 ′, and the pixel electrode P1 is arranged downstream of the scanning signal line G1 in the scanning direction. The pixel electrode P2 is disposed on the downstream side in the scanning direction of the scanning signal line G2, the pixel electrode P3 is disposed on the downstream side in the scanning direction of the scanning signal line G3, and the pixel electrode P4 is disposed in the scanning direction of the scanning signal line G4. It is arranged downstream.
　画素電極Ｐ１は、トランジスタＴ１を介して、データ信号線ＤＸ１および走査信号線Ｇ１に接続され、画素電極Ｐ２は、トランジスタＴ２を介して、データ信号線ＤＸ１’および走査信号線Ｇ２に接続され、画素電極Ｐ３は、トランジスタＴ３を介して、データ信号線ｄｘ１および走査信号線Ｇ３に接続され、画素電極Ｐ４は、トランジスタＴ４を介して、データ信号線ｄｘ１’および走査信号線Ｇ４に接続される。なお、画素電極Ｐ１～Ｐ４それぞれと対向電極ＣＯＭとの間には液晶容量が形成される。また、保持容量配線ＣＳ１～ＣＳ４は各走査信号線と平行に設けられ、画素Ｐ１は保持容量配線ＣＳ１と保持容量を形成し、画素Ｐ２は保持容量配線ＣＳ２と保持容量を形成し、画素Ｐ３は保持容量配線ＣＳ３と保持容量を形成し、画素Ｐ４は保持容量配線ＣＳ４と保持容量を形成する。 The pixel electrode P1 is connected to the data signal line DX1 and the scanning signal line G1 through the transistor T1, and the pixel electrode P2 is connected to the data signal line DX1 ′ and the scanning signal line G2 through the transistor T2. The electrode P3 is connected to the data signal line dx1 and the scanning signal line G3 via the transistor T3, and the pixel electrode P4 is connected to the data signal line dx1 ′ and the scanning signal line G4 via the transistor T4. Note that a liquid crystal capacitor is formed between each of the pixel electrodes P1 to P4 and the counter electrode COM. The storage capacitor lines CS1 to CS4 are provided in parallel with the scanning signal lines. The pixel P1 forms a storage capacitor with the storage capacitor line CS1, the pixel P2 forms a storage capacitor with the storage capacitor line CS2, and the pixel P3 A storage capacitor line CS3 and a storage capacitor are formed, and the pixel P4 forms a storage capacitor line CS4 and a storage capacitor.
　一方、第１基板の下半分の領域（第１基板を走査方向に２分割したときに、走査方向下流側となる領域）には、画素電極Ｐ５４１～Ｐ５４４、走査信号線Ｇ５４１～Ｇ５４４、データ信号線ＤＹ１・ＤＹ２・ＤＹ１’・ＤＹ２’、トランジスタＴ５４１～Ｔ５４４、および保持容量配線ＣＳ５４１～ＣＳ５４４が形成され、第２基板の下半分の領域（第２基板を走査方向に２分割したときに、走査方向下流側となる領域）には、データ信号線ｄｙ１・ｄｙ２・ｄｙ１’・ｄｙ２’および対向（共通）電極ＣＯＭが形成される。 On the other hand, pixel electrodes P541 to P544, scanning signal lines G541 to G544, data signals are provided in the lower half area of the first substrate (area that is downstream in the scanning direction when the first substrate is divided into two in the scanning direction). Lines DY1, DY2, DY1 ′, DY2 ′, transistors T541 to T544, and storage capacitor lines CS541 to CS544 are formed, and the lower half region of the second substrate (scanning when the second substrate is divided into two in the scanning direction) The data signal lines dy1, dy2, dy1 ′, dy2 ′ and the counter (common) electrode COM are formed in the region on the downstream side in the direction.
　図１では、データ信号線ＤＹ１（第１基板）とデータ信号線ｄｙ１（第２基板）とが重なっていないが、実際には両者は重なっており（後述）、同様に、データ信号線ＤＹ１’（第１基板）とデータ信号線ｄｙ１’（第２基板）とが重なっている。そして、平面視において、データ信号線ＤＹ１とデータ信号線ＤＹ１’との間に画素電極Ｐ５４１～Ｐ５４４がこの順に列方向に並べられ、画素電極Ｐ５４１は、走査信号線Ｇ５４１の走査方向下流側に配され、画素電極Ｐ５４２は、走査信号線Ｇ５４２の走査方向下流側に配され、画素電極Ｐ５４３は、走査信号線Ｇ５４３の走査方向下流側に配され、画素電極Ｐ５４４は、走査信号線Ｇ５４４の走査方向下流側に配されている。 In FIG. 1, the data signal line DY1 (first substrate) and the data signal line dy1 (second substrate) do not overlap, but actually they overlap (described later). Similarly, the data signal line DY1 ′ The (first substrate) and the data signal line dy1 ′ (second substrate) overlap. In plan view, the pixel electrodes P541 to P544 are arranged in this order in the column direction between the data signal line DY1 and the data signal line DY1 ′, and the pixel electrode P541 is arranged downstream of the scanning signal line G541 in the scanning direction. The pixel electrode P542 is disposed on the downstream side in the scanning direction of the scanning signal line G542, the pixel electrode P543 is disposed on the downstream side in the scanning direction of the scanning signal line G543, and the pixel electrode P544 is disposed in the scanning direction of the scanning signal line G544. It is arranged downstream.
　画素電極Ｐ５４１は、トランジスタＴ５４１を介して、データ信号線ＤＹ１および走査信号線Ｇ５４１に接続され、画素電極Ｐ５４２は、トランジスタＴ５４２を介して、データ信号線ＤＹ１’および走査信号線Ｇ５４２に接続され、画素電極Ｐ５４３は、トランジスタＴ５４３を介して、データ信号線ｄｙ１および走査信号線Ｇ５４３に接続され、画素電極Ｐ５４４は、トランジスタＴ５４４を介して、データ信号線ｄｙ１’および走査信号線Ｇ５４４に接続される。なお、画素電極Ｐ５４１～Ｐ５４４それぞれと対向電極ＣＯＭとの間には液晶容量が形成される。また、保持容量配線ＣＳ５４１～ＣＳ５４４は各走査信号線と平行に設けられ、画素Ｐ５４１は保持容量配線ＣＳ５４１と保持容量を形成し、画素Ｐ５４２は保持容量配線ＣＳ５４２と保持容量を形成し、画素Ｐ５４３は保持容量配線ＣＳ５４３と保持容量を形成し、画素Ｐ５４４は保持容量配線ＣＳ４と保持容量を形成する。 The pixel electrode P541 is connected to the data signal line DY1 and the scanning signal line G541 via the transistor T541, and the pixel electrode P542 is connected to the data signal line DY1 ′ and the scanning signal line G542 via the transistor T542. The electrode P543 is connected to the data signal line dy1 and the scanning signal line G543 via the transistor T543, and the pixel electrode P544 is connected to the data signal line dy1 ′ and the scanning signal line G544 via the transistor T544. A liquid crystal capacitor is formed between each of the pixel electrodes P541 to P544 and the counter electrode COM. The storage capacitor lines CS541 to CS544 are provided in parallel with the scanning signal lines, the pixel P541 forms a storage capacitor with the storage capacitor line CS541, the pixel P542 forms a storage capacitor with the storage capacitor line CS542, and the pixel P543 A storage capacitor line CS543 and a storage capacitor are formed, and the pixel P544 forms a storage capacitor line CS4 and a storage capacitor.
　さらに図１では、第１基板の上半分には、データ信号線ＤＸ１、ＤＸ１’、ＤＸ２およびＤＸ２’がこの順に並べられ、第２基板の上半分には、データ信号線ｄｘ１、ｄｘ１’、ｄｘ２およびｄｘ２’がこの順に並べられており、画素Ａと行方向に隣接する画素Ｉの画素電極は、第１基板に設けられ、トランジスタを介してデータ信号線ＤＸ２に接続し、画素Ｂと行方向に隣接する画素Ｊの画素電極は、第１基板に設けられ、トランジスタを介してデータ信号線ＤＸ２’に接続し、画素Ｃと行方向に隣接する画素Ｋの画素電極は、第１基板に設けられ、トランジスタを介してデータ信号線ｄｘ２に接続し、画素Ｄと行方向に隣接する画素Ｌの画素電極は、第１基板に設けられ、トランジスタを介してデータ信号線ｄｘ２’に接続する。 Further, in FIG. 1, data signal lines DX1, DX1 ′, DX2 and DX2 ′ are arranged in this order on the upper half of the first substrate, and data signal lines dx1, dx1 ′, dx2 are arranged on the upper half of the second substrate. And dx2 ′ are arranged in this order, and the pixel electrode of the pixel I adjacent to the pixel A in the row direction is provided on the first substrate and is connected to the data signal line DX2 via the transistor, and is connected to the pixel B in the row direction. The pixel electrode of the pixel J adjacent to the pixel J is provided on the first substrate, connected to the data signal line DX2 ′ via the transistor, and the pixel electrode of the pixel K adjacent to the pixel C in the row direction is provided on the first substrate. The pixel electrode of the pixel L that is connected to the data signal line dx2 through the transistor and is adjacent to the pixel D in the row direction is provided on the first substrate, and is connected to the data signal line dx2 ′ through the transistor.
　同様に、図１では、第１基板の下半分には、データ信号線ＤＹ１、ＤＹ１’、ＤＹ２およびＤＹ２’がこの順に並べられ、第２基板の下半分には、データ信号線ｄｙ１、ｄｙ１’、ｄｙ２およびｄｙ２’がこの順に並べられており、画素Ｅと行方向に隣接する画素Ｍの画素電極は、第１基板に設けられ、トランジスタを介してデータ信号線ＤＹ２に接続し、画素Ｆと行方向に隣接する画素Ｎの画素電極は、第１基板に設けられ、トランジスタを介してデータ信号線ＤＹ２’に接続し、画素Ｇと行方向に隣接する画素Ｏの画素電極は、第１基板に設けられ、トランジスタを介してデータ信号線ｄｙ２に接続し、画素Ｈと行方向に隣接する画素Ｐの画素電極は、第１基板に設けられ、トランジスタを介してデータ信号線ｄｙ２’に接続する。 Similarly, in FIG. 1, data signal lines DY1, DY1 ′, DY2 and DY2 ′ are arranged in this order on the lower half of the first substrate, and data signal lines dy1, dy1 ′ are arranged on the lower half of the second substrate. , Dy2 and dy2 ′ are arranged in this order, and the pixel electrode of the pixel M adjacent to the pixel E in the row direction is provided on the first substrate and is connected to the data signal line DY2 through the transistor. The pixel electrode of the pixel N adjacent in the row direction is provided on the first substrate, is connected to the data signal line DY2 ′ via the transistor, and the pixel electrode of the pixel O adjacent to the pixel G in the row direction is the first substrate. The pixel electrode of the pixel P adjacent to the pixel H in the row direction is provided on the first substrate and connected to the data signal line dy2 ′ via the transistor. .
　図２は第１基板（ＳＵ１）の画素Ａ・Ｂに対応する部分の構成を示す平面図であり、図３は第２基板（ＳＵ２）の画素Ａ・Ｂに対応する部分の構成を示す平面図であり、図４は、液晶パネルＬＣＰの画素Ａの断面図（図２・３のＡ１－Ａ１’に対応）である。また、図５は第１基板（ＳＵ１）の画素Ｃ・Ｄに対応する部分の構成を示す平面図であり、図６は第２基板（ＳＵ２）の画素Ｃ・Ｄに対応する部分の構成を示す平面図であり、図７は、液晶パネルＬＣＰの画素Ｃの断面図（図５・６のＡ３－Ａ３’に対応）である。 FIG. 2 is a plan view showing a configuration of a portion corresponding to the pixels A and B of the first substrate (SU1), and FIG. 3 is a plan view showing a configuration of a portion corresponding to the pixels A and B of the second substrate (SU2). FIG. 4 is a cross-sectional view of the pixel A of the liquid crystal panel LCP (corresponding to A1-A1 ′ in FIGS. 2 and 3). FIG. 5 is a plan view showing a configuration of a portion corresponding to the pixels C and D of the first substrate (SU1), and FIG. 6 shows a configuration of a portion corresponding to the pixels C and D of the second substrate (SU2). FIG. 7 is a cross-sectional view of the pixel C of the liquid crystal panel LCP (corresponding to A3-A3 ′ in FIGS. 5 and 6).
　図４・７に示すように、第１基板ＳＵ１では、ガラス基板３１上に、走査信号線Ｇ１の延伸部ｇ１（トランジスタＴ１のゲート電極）と、走査信号線Ｇ３の延伸部ｇ３（トランジスタＴ３のゲート電極）とが形成され、延伸部ｇ１・ｇ３を覆うようにゲート絶縁膜２１が形成され、ゲート絶縁膜２１上に、データ信号線ＤＸ１・ＤＸ１’と、トランジスタＴ１の半導体層２４並びにソース電極８およびドレイン電極９と、トランジスタＴ３の半導体層２４並びにソース電極８およびドレイン電極９とが形成され、トランジスタＴ１・Ｔ３のチャネルを覆うように、パッシベーション膜２５およびこれよりも厚い有機絶縁膜２６からなる層間絶縁膜（チャネル保護膜）が形成され、層間絶縁膜上に、画素電極Ｐ１・Ｐ３および中継電極ＴＭ１～ＴＭ４・ＴＭ１’～ＴＭ４’が、透光性導電膜（ＩＴＯ等）を用いて形成される。 4 and 7, in the first substrate SU1, on the glass substrate 31, the extending portion g1 of the scanning signal line G1 (gate electrode of the transistor T1) and the extending portion g3 of the scanning signal line G3 (of the transistor T3) The gate insulating film 21 is formed so as to cover the extending portions g1 and g3, and the data signal lines DX1 and DX1 ′, the semiconductor layer 24 of the transistor T1, and the source electrode are formed on the gate insulating film 21. 8 and the drain electrode 9, the semiconductor layer 24 of the transistor T3, and the source electrode 8 and the drain electrode 9 are formed, and from the passivation film 25 and the organic insulating film 26 thicker than this so as to cover the channels of the transistors T1 and T3. An interlayer insulating film (channel protective film) is formed, and the pixel electrodes P1 and P3 and the relay electrode TM1 are formed on the interlayer insulating film. TM4 · TM1 '~ TM4' is formed using a light-transmitting conductive film (ITO, etc.).
　一方、第１基板ＳＵ２では、ガラス基板３２上にデータ信号線ｄｘ１・ｄｘ１’が形成され、データ信号線ｄｘ１・ｄｘ１’を覆うようにメタルコート膜ＭＣ（絶縁膜）が形成され、メタルコート絶縁膜ＭＣ上に、カラーフィルタＣＦおよびブラックマトリクスＢＭが形成され、カラーフィルタＣＦおよびブラックマトリクスＢＭを覆うようにオーバーコート膜ＭＣ（絶縁膜）が形成され、オーバーコート膜ＭＣ上に、対向（共通）電極ＣＯＭおよび中継電極ｔｍ１～ｔｍ４・ｔｍ１’～ｔｍ４’が、透光性導電膜（ＩＴＯ等）を用いて形成される。なお、対向電極ＣＯＭはパネル全体に単一形成（ベタ形成）することができ、対向電極ＣＯＭの低抵抗化の観点からはこれが望ましい。ただ、単一形成では対向電極ＣＯＭと（第２基板ＳＵ２の）データ信号線との寄生容量が大きくなるおそれがあり、これを避けるために、対向電極ＣＯＭを複数に分割形成してもよい。例えば、対向電極ＣＯＭをストライプ状に分割形成し、パネルプロセスに合わせて、各対向電極ＣＯＭを複数画素列（縦が１画素列×横が数画素）に対応する大きさとすることができる。 On the other hand, in the first substrate SU2, the data signal lines dx1 and dx1 ′ are formed on the glass substrate 32, and the metal coat film MC (insulating film) is formed so as to cover the data signal lines dx1 and dx1 ′. A color filter CF and a black matrix BM are formed on the film MC, an overcoat film MC (insulating film) is formed so as to cover the color filter CF and the black matrix BM, and a counter (common) is formed on the overcoat film MC. The electrode COM and the relay electrodes tm1 to tm4 · tm1 ′ to tm4 ′ are formed using a light-transmitting conductive film (ITO or the like). The counter electrode COM can be formed as a single unit (solid) on the entire panel, which is desirable from the viewpoint of reducing the resistance of the counter electrode COM. However, in the single formation, the parasitic capacitance between the counter electrode COM and the data signal line (of the second substrate SU2) may increase, and the counter electrode COM may be divided into a plurality of parts to avoid this. For example, the counter electrodes COM can be divided and formed in stripes, and each counter electrode COM can be sized to correspond to a plurality of pixel columns (vertical one pixel column × horizontal several pixels) in accordance with the panel process.
　また、図２～７に示すように、第２基板のデータ信号線ｄｘ１は、第１基板のデータ信号線ＤＸ１に重なる（平面視で一致する）ように設けられ、第２基板のデータ信号線ｄｘ１’は、第１基板のデータ信号線ＤＸ１’に重なる（平面視で一致する）ように設けられ、第１基板ＳＵ１および第２基板ＳＵ２間には、液晶層ＬＣＬが充填され、液晶層ＬＣＬ（第１および第２基板間）には、導電性フォトスペーサＦＳ３・ＦＳ３’が形成される。 As shown in FIGS. 2 to 7, the data signal line dx1 on the second substrate is provided so as to overlap (coincides in plan view) with the data signal line DX1 on the first substrate. dx1 ′ is provided so as to overlap with the data signal line DX1 ′ of the first substrate (coincides in plan view), and the liquid crystal layer LCL is filled between the first substrate SU1 and the second substrate SU2, and the liquid crystal layer LCL Conductive photospacers FS3 and FS3 ′ are formed (between the first and second substrates).
　図２～４に示すように、第１基板ＳＵ１の画素Ａ・Ｂに対応する領域では、データ信号線ＤＸ１と重なるように中継電極ＴＭ１が形成されるとともに、データ信号線ＤＸ１’と重なるように中継電極ＴＭ１’が形成され、平面視において、データ信号線ＤＸ１、トランジスタＴ１（図示せず）のソース電極８、走査信号線Ｇ１の延伸部ｇ１（トランジスタＴ１のゲート電極）およびトランジスタＴ１のドレイン電極９がこの順に行方向に並べられ、トランジスタＴ１のソース電極８、走査信号線Ｇ１の延伸部ｇ１およびトランジスタＴ１のドレイン電極９が半導体層２４と重なっている。また、データ信号線ＤＸ１と中継電極ｔｍ１とが層間絶縁膜を貫くコンタクトホール１１ｄを介して接続され、中継電極ｔｍ１とトランジスタＴ１のソース電極８とが層間絶縁膜を貫くコンタクトホール１１ｂを介して接続され、トランジスタＴ１のドレイン電極９と画素電極Ｐ１とが層間絶縁膜を貫くコンタクトホール１１ａを介して接続されている。さらに、保持容量配線ＣＳ１と重なるように容量電極２７が配され、容量電極２７と画素電極Ｐ１とがコンタクトホール１１ｃを介して接続されている。 As shown in FIGS. 2 to 4, in the region corresponding to the pixels A and B of the first substrate SU1, the relay electrode TM1 is formed so as to overlap the data signal line DX1, and so as to overlap the data signal line DX1 ′. The relay electrode TM1 ′ is formed, and in plan view, the data signal line DX1, the source electrode 8 of the transistor T1 (not shown), the extending part g1 of the scanning signal line G1 (gate electrode of the transistor T1), and the drain electrode of the transistor T1 9 are arranged in this order in the row direction, and the source electrode 8 of the transistor T1, the extending portion g1 of the scanning signal line G1, and the drain electrode 9 of the transistor T1 overlap the semiconductor layer 24. Further, the data signal line DX1 and the relay electrode tm1 are connected via a contact hole 11d that penetrates the interlayer insulating film, and the relay electrode tm1 and the source electrode 8 of the transistor T1 are connected via a contact hole 11b that penetrates the interlayer insulating film. The drain electrode 9 of the transistor T1 and the pixel electrode P1 are connected through a contact hole 11a that penetrates the interlayer insulating film. Further, the capacitor electrode 27 is disposed so as to overlap the storage capacitor line CS1, and the capacitor electrode 27 and the pixel electrode P1 are connected via the contact hole 11c.
　また、図２～４に示すように、第２基板ＳＵ２の画素Ａ・Ｂに対応する領域では、データ信号線ｄｘ１と重なるように中継電極ｔｍ１が形成されるとともに、データ信号線ＤＸ１’と重なるように中継電極ｔｍ１’が形成され、データ信号線ｄｘ１と中継電極ｔｍ１とがコンタクトホールｈ１を介して接続され、データ信号線ｄｘ１’と中継電極ｔｍ１’とがコンタクトホールｈ１’を介して接続されている。 As shown in FIGS. 2 to 4, in the region corresponding to the pixels A and B of the second substrate SU2, the relay electrode tm1 is formed so as to overlap with the data signal line dx1, and also overlaps with the data signal line DX1 ′. Thus, the relay electrode tm1 ′ is formed, the data signal line dx1 and the relay electrode tm1 are connected via the contact hole h1, and the data signal line dx1 ′ and the relay electrode tm1 ′ are connected via the contact hole h1 ′. ing.
　図５～７に示すように、第１基板ＳＵ１の画素Ｃ・Ｄに対応する領域では、データ信号線ＤＸ１と重なるように中継電極ＴＭ３・ＴＭ４が形成されるとともに、データ信号線ＤＸ１’と重なるように中継電極ＴＭ３’・ＴＭ４’が形成され、平面視において、データ信号線ＤＸ１、トランジスタＴ３（図示せず）のソース電極８、走査信号線Ｇ３の延伸部ｇ３（トランジスタＴ１のゲート電極）およびトランジスタＴ３のドレイン電極９がこの順に行方向に並べられ、トランジスタＴ３のソース電極８、走査信号線Ｇ３の延伸部ｇ３およびトランジスタＴ３のドレイン電極９が半導体層２４と重なっている。また、中継電極ＴＭ３が、導電性フォトスペーサＦＳ３と接触しており、中継電極ＴＭ３とトランジスタＴ３のソース電極８とが層間絶縁膜を貫くコンタクトホール１１ｂを介して接続され、トランジスタＴ３のドレイン電極９と画素電極Ｐ３とが層間絶縁膜を貫くコンタクトホール１１ａを介して接続されている。同様に、中継電極ＴＭ４’が、導電性フォトスペーサＦＳ４’と接触しており、中継電極ＴＭ４’とトランジスタＴ４のソース電極８とが層間絶縁膜を貫くコンタクトホール１１ｂを介して接続され、トランジスタＴ４のドレイン電極９と画素電極Ｐ４とが層間絶縁膜を貫くコンタクトホール１１ａを介して接続されている。さらに、保持容量配線ＣＳ３と重なるように容量電極２７が配され、容量電極２７と画素電極Ｐ３とがコンタクトホール１１ｃを介して接続されている。 As shown in FIGS. 5 to 7, in the region corresponding to the pixels C and D of the first substrate SU1, the relay electrodes TM3 and TM4 are formed so as to overlap with the data signal line DX1, and also overlap with the data signal line DX1 ′. In this way, the relay electrodes TM3 ′ and TM4 ′ are formed. In plan view, the data signal line DX1, the source electrode 8 of the transistor T3 (not shown), the extending portion g3 of the scanning signal line G3 (the gate electrode of the transistor T1), and The drain electrode 9 of the transistor T3 is arranged in this order in the row direction, and the source electrode 8 of the transistor T3, the extending portion g3 of the scanning signal line G3, and the drain electrode 9 of the transistor T3 overlap with the semiconductor layer 24. The relay electrode TM3 is in contact with the conductive photospacer FS3, the relay electrode TM3 and the source electrode 8 of the transistor T3 are connected via a contact hole 11b that penetrates the interlayer insulating film, and the drain electrode 9 of the transistor T3. And the pixel electrode P3 are connected through a contact hole 11a penetrating the interlayer insulating film. Similarly, the relay electrode TM4 ′ is in contact with the conductive photospacer FS4 ′, and the relay electrode TM4 ′ and the source electrode 8 of the transistor T4 are connected via a contact hole 11b that penetrates the interlayer insulating film, and the transistor T4. The drain electrode 9 and the pixel electrode P4 are connected through a contact hole 11a penetrating the interlayer insulating film. Further, the capacitor electrode 27 is arranged so as to overlap with the storage capacitor line CS3, and the capacitor electrode 27 and the pixel electrode P3 are connected via the contact hole 11c.
　また、図５～７に示すように、第２基板ＳＵ２の画素Ｃ・Ｄに対応する領域では、データ信号線ｄｘ１と重なるように中継電極ｔｍ３・ｔｍ４が形成されるとともに、データ信号線ＤＸ１’と重なるように中継電極ｔｍ３’・ｔｍ４’が形成され、データ信号線ｄｘ１と中継電極ｔｍ３とがコンタクトホールｈ３を介して接続され、データ信号線ｄｘ１’と中継電極ｔｍ４’とがコンタクトホールｈ４’を介して接続されている。また、中継電極ｔｍ３が、導電性フォトスペーサＦＳ３と接触するとともに、中継電極ｔｍ４’が、導電性フォトスペーサＦＳ４’と接触している。 As shown in FIGS. 5 to 7, in the region corresponding to the pixels C and D of the second substrate SU2, the relay electrodes tm3 and tm4 are formed so as to overlap the data signal line dx1, and the data signal line DX1 ′ is formed. The relay electrodes tm3 ′ and tm4 ′ are formed so as to overlap with each other, the data signal line dx1 and the relay electrode tm3 are connected via the contact hole h3, and the data signal line dx1 ′ and the relay electrode tm4 ′ are connected to the contact hole h4 ′. Connected through. Further, the relay electrode tm3 is in contact with the conductive photospacer FS3, and the relay electrode tm4 'is in contact with the conductive photospacer FS4'.
　このように、第２基板のデータ信号線ｄｘ１は、コンタクトホールｈ３、第２基板の中継電極ｔｍ３、液晶層の導電性フォトスペーサＦＳ３、第１基板の中継電極ＴＭ３、およびコンタクトホール１１ｂを介して、第１基板のトランジスタＴ３のソース電極８に接続される。同様に、第２基板のデータ信号線ｄｘ１’は、コンタクトホールｈ４’、第２基板の中継電極ｔｍ４’、液晶層の導電性フォトスペーサＦＳ４’、第１基板の中継電極ＴＭ４’、およびコンタクトホール１１ｂを介して、第１基板のトランジスタＴ４のソース電極８に接続される。 As described above, the data signal line dx1 on the second substrate is connected via the contact hole h3, the relay electrode tm3 on the second substrate, the conductive photo spacer FS3 on the liquid crystal layer, the relay electrode TM3 on the first substrate, and the contact hole 11b. , Connected to the source electrode 8 of the transistor T3 on the first substrate. Similarly, the data signal line dx1 ′ of the second substrate includes the contact hole h4 ′, the relay electrode tm4 ′ of the second substrate, the conductive photospacer FS4 ′ of the liquid crystal layer, the relay electrode TM4 ′ of the first substrate, and the contact hole. 11b is connected to the source electrode 8 of the transistor T4 on the first substrate.
　なお、図２・４のようにデータ信号線ＤＸ１を、一旦中継電極ＴＭ１（ＩＴＯ等）を介してトランジスタＴ１のソース電極８に接続することで、データ信号線とトランジスタのソース電極との間の抵抗値（寄生抵抗値）を、画素Ａ・Ｃ間で揃えることができる。 2 and 4, once the data signal line DX1 is connected to the source electrode 8 of the transistor T1 via the relay electrode TM1 (ITO or the like), the data signal line and the source electrode of the transistor are connected. The resistance value (parasitic resistance value) can be made uniform between the pixels A and C.
　図８は第１基板の全体構成を示す模式図であり、図９は第２基板の全体構成を示す模式図であり、図１０は、液晶パネルの全体構成を示す模式図である。図８に示すように、第１基板の表示領域には、複数の走査信号線と、複数のデータ信号線と、複数のトランジスタと、複数の画素電極とが含まれ、第１基板の非表示領域には、２つの長辺（行方向に平行な辺）それぞれに沿って複数のソース接続パッドＳＰが並べられるとともに、２つの短辺（列方向に平行な辺）それぞれに沿って、複数のゲート接続パッドＧＰが並べられている。
なお、複数のソース接続パッドＳＰの半数はデータ信号線に接続され、残り半数は、基板間接続パッドｂｐに接続され、各ゲート接続パッドＧＰは走査信号線に接続されている。
また、図９に示すように、第２基板の表示領域には、複数のデータ信号線が含まれ、第２基板の非表示領域には、２つの長辺（行方向に平行な辺）それぞれに沿って、複数の基板間接続パッドＢＰが並べられている。なお、各基板間接続パッドＢＰはデータ信号線に接続されている。そして、図８の第１基板と図９の第２基板とをそれぞれのデータ信号線同士が重なるように張り合わせた後に液晶材を充填すれば図１０に示す液晶パネルとなり、第２基板の各データ信号線は、基板間接続パッドＢＰ（第２基板）および基板間接続パッドｂｐ（第１基板）を介して、第１基板のソース接続パッドＳＰに接続される。 FIG. 8 is a schematic diagram showing the overall configuration of the first substrate, FIG. 9 is a schematic diagram showing the overall configuration of the second substrate, and FIG. 10 is a schematic diagram showing the overall configuration of the liquid crystal panel. As shown in FIG. 8, the display area of the first substrate includes a plurality of scanning signal lines, a plurality of data signal lines, a plurality of transistors, and a plurality of pixel electrodes. In the region, a plurality of source connection pads SP are arranged along two long sides (sides parallel to the row direction), and a plurality of source connection pads SP are arranged along two short sides (sides parallel to the column direction). Gate connection pads GP are arranged.
Note that half of the plurality of source connection pads SP are connected to the data signal line, the other half are connected to the inter-substrate connection pad bp, and each gate connection pad GP is connected to the scanning signal line.
As shown in FIG. 9, the display area of the second substrate includes a plurality of data signal lines, and the non-display area of the second substrate has two long sides (sides parallel to the row direction). A plurality of inter-substrate connection pads BP are arranged along the line. Each inter-substrate connection pad BP is connected to a data signal line. Then, after the first substrate in FIG. 8 and the second substrate in FIG. 9 are bonded together so that the data signal lines overlap each other, the liquid crystal material is filled to obtain the liquid crystal panel shown in FIG. The signal line is connected to the source connection pad SP of the first substrate via the inter-substrate connection pad BP (second substrate) and the inter-substrate connection pad bp (first substrate).
　図１１は、図１０の端部領域ＴＡの構成を示す断面図である。図１１に示されるように、第１基板には、ソース接続パッドＳＰ、ゲートメタルＧＭ（走査信号線と同層）、接続電極ＣＥ（データ信号線と同層）、基板間接続パッドｂｐ（画素電極と同層）が設けられ、第２基板には、基板間接続パッドＢＰ（対向電極と同層）が設けられ、第１および第２基板間に、導電性の接続ビーズＢＺが設けられる。ここでは、ソース接続パッドＳＰが、ゲートメタルＧＭを介して接続電極ＣＥに接続され、接続電極ＣＥが、第１基板の層間絶縁膜（２５・２６）を貫くコンタクトホールを介して基板間接続パッドｂｐに接続され、基板間接続パッドｂｐが、接続ビーズＢＺを介して第２基板の基板間接続パッドＢＰに接続され、基板間接続パッドＢＰが、メタルコート膜ＭＣおよびオーバーコート膜ＯＣを貫くコンタクトホールを介して、第２基板のデータ信号線ｄｘ１に接続されている。なお、ソース接続パッドＳＰはフレキシブルプリント基板ＦＣを介してソースドライバＳＤＸに接続される。また、ソース接続パッドＳＰおよび基板間接続パッドＢＰ・ｂｐはそれぞれ、例えば、ＩＴＯで形成される。なお、ゲートメタルＧＭは腐食しやすいので、ソース接続パッドＳＰ（ＩＴＯ）および絶縁膜（ゲート絶縁膜２１や層間絶縁膜２５）で被覆している。 FIG. 11 is a cross-sectional view showing the configuration of the end region TA of FIG. As shown in FIG. 11, the first substrate includes a source connection pad SP, a gate metal GM (same layer as the scanning signal line), a connection electrode CE (same layer as the data signal line), and an inter-substrate connection pad bp (pixel). In the second substrate, an inter-substrate connection pad BP (in the same layer as the counter electrode) is provided, and conductive connection beads BZ are provided between the first and second substrates. Here, the source connection pad SP is connected to the connection electrode CE through the gate metal GM, and the connection electrode CE is connected to the inter-substrate connection pad through the contact hole penetrating the interlayer insulating film (25, 26) of the first substrate. The inter-substrate connection pad bp is connected to the inter-substrate connection pad BP of the second substrate via the connection beads BZ, and the inter-substrate connection pad BP penetrates the metal coat film MC and the overcoat film OC. The hole is connected to the data signal line dx1 of the second substrate. The source connection pad SP is connected to the source driver SDX via the flexible printed circuit board FC. The source connection pad SP and the inter-substrate connection pad BP · bp are each formed of, for example, ITO. Since the gate metal GM is easily corroded, it is covered with the source connection pad SP (ITO) and an insulating film (the gate insulating film 21 and the interlayer insulating film 25).
　実施例１の液晶パネルでは、各画素（例えば、Ａ・Ｂ・Ｉ・Ｊ）は１つの原色に対応しており、表示単位は、Ｒ（赤）・Ｇ（緑）・Ｂ（青）の３画素でもよいし（図１２（ａ）参照）、Ｒ・Ｇ・Ｂ・Ｙ（黄）・Ｍ（マゼンダ）・Ｃ（シアン）の６画素でもよいし（図１２（ｂ）参照）、Ｒ・Ｇ・Ｂ・Ｇ・Ｍ・Ｙの６画素でもよい（図１２（ｃ）参照）。 In the liquid crystal panel of Example 1, each pixel (for example, A, B, I, and J) corresponds to one primary color, and the display units are R (red), G (green), and B (blue). It may be 3 pixels (see FIG. 12A), 6 pixels of R, G, B, Y (yellow), M (magenta), and C (cyan) (see FIG. 12B), or R 6 pixels of G, B, G, M, and Y may be used (see FIG. 12C).
　本液晶パネルを備えた液晶表示装置は、例えば、図１３のように構成され、パネル上半分のデータ信号線（ＤＸ１・ＤＸ２・ＤＸ１’・ＤＸ２’・ｄｘ１・ｄｘ２・ｄｘ１’・ｄｘ２’等）を駆動するソースドライバＳＤＸと、パネル下半分のデータ信号線（ＤＹ１・ＤＹ２・ＤＹ１’・ＤＹ２’・ｄｙ１・ｄｙ２・ｄｙ１’・ｄｙ２’等）を駆動するソースドライバＳＤＹと、各走査信号線の両側に接続する２つのゲートドライバＧＤＬ・ＧＤＲと、これらソースドライバＳＤＸ・ＳＤＹおよびゲートドライバＧＤＬ・ＧＤＲを制御する表示制御回路ＤＣＣとを備える。 The liquid crystal display device provided with the present liquid crystal panel is configured as shown in FIG. 13, for example, and the upper half of the data signal lines (DX1, DX2, DX1 ′, DX2 ′, dx1, dx2, dx1 ′, dx2 ′, etc.) A source driver SDX that drives the data signal lines (DY1, DY2, DY1 ′, DY2 ′, dy1, dy2, dy1 ′, dy2 ′, etc.) on the lower half of the panel, and each scanning signal line Two gate drivers GDL / GDR connected to both sides and a display control circuit DCC for controlling the source drivers SDX / SDY and the gate drivers GDL / GDR are provided.
　図１４・１５は、本液晶表示装置の走査信号線の駆動方法を示す模式図であり、図１６は、本液晶表示装置のデータ信号線の駆動方法を示すタイミングチャートであり、図１７～２０は、本液晶表示装置のデータ書き込み方法を示す模式図である。 FIGS. 14 and 15 are schematic diagrams showing a driving method of scanning signal lines of the present liquid crystal display device, and FIG. 16 is a timing chart showing a driving method of data signal lines of the present liquid crystal display device. These are schematic diagrams showing a data writing method of the present liquid crystal display device.
　本液晶表示装置では、図１４・１７～１８に示すように、ある垂直走査期間（Ｖ１）の第１水平走査期間（Ｈ１）に、８本の走査信号線（Ｇ１・Ｇ２・ｇ３・ｇ４・Ｇ５４１・Ｇ５４２・ｇ５４３・ｇ５４４）を同時選択し、次いで、第２水平走査期間（Ｈ２）に、８本の走査信号線（Ｇ５・Ｇ６・ｇ７・ｇ８・Ｇ５４５・Ｇ５４６・ｇ５４７・ｇ５４８）を同時選択し、第３水平走査期間（Ｈ３）に、８本の走査信号線（Ｇ９・Ｇ１０・ｇ１１・ｇ１２・Ｇ５４９・Ｇ５５０・ｇ５５１・ｇ５５２）を同時選択する。 In the present liquid crystal display device, as shown in FIGS. 14 and 17 to 18, eight scanning signal lines (G 1, G 2, g 3, g 4, and so on) are generated in the first horizontal scanning period (H 1) of a certain vertical scanning period (V 1). G541, G542, g543, and g544) are simultaneously selected, and then eight scanning signal lines (G5, G6, g7, g8, G545, G546, g547, and g548) are simultaneously selected in the second horizontal scanning period (H2). In the third horizontal scanning period (H3), eight scanning signal lines (G9, G10, g11, g12, G549, G550, g551, and g552) are simultaneously selected.
　これにより、例えば第１水平走査期間（Ｈ１）には、データ信号線ＤＸ１から走査信号線Ｇ１に接続する画素に、フレームＦ２の１ライン目のデータ信号が書き込まれ、データ信号線ＤＸ１’から走査信号線Ｇ２に接続する画素に、フレームＦ２の２ライン目のデータ信号が書き込まれ、データ信号線ｄｘ１から走査信号線Ｇ３に接続する画素に、フレームＦ２の３ライン目のデータ信号が書き込まれ、データ信号線ｄｘ１’から走査信号線Ｇ４に接続する画素に、フレームＦ２の４ライン目のデータ信号が書き込まれ、データ信号線ＤＹ１から走査信号線Ｇ５４１に接続する画素に、フレームＦ１の５４１ライン目のデータ信号が書き込まれ、データ信号線ＤＹ１’から走査信号線Ｇ５４２に接続する画素に、フレームＦ１の５４２ライン目のデータ信号が書き込まれ、データ信号線ｄｙ１から走査信号線Ｇ５４３に接続する画素に、フレームＦ１の５４３ライン目のデータ信号が書き込まれ、データ信号線ｄｙ１’から走査信号線Ｇ５４４に接続する画素に、フレームＦ１の５４４ライン目のデータ信号が書き込まれる。 Thus, for example, in the first horizontal scanning period (H1), the data signal of the first line of the frame F2 is written to the pixels connected from the data signal line DX1 to the scanning signal line G1, and scanning is performed from the data signal line DX1 ′. The data signal of the second line of the frame F2 is written to the pixel connected to the signal line G2, and the data signal of the third line of the frame F2 is written to the pixel connected to the scanning signal line G3 from the data signal line dx1. The data signal of the fourth line of the frame F2 is written to the pixel connected to the scanning signal line G4 from the data signal line dx1 ′, and the 541st line of the frame F1 is written to the pixel connected to the scanning signal line G541 from the data signal line DY1. Is written to the pixels connected to the scanning signal line G542 from the data signal line DY1 ′. A pixel in which the data signal of the 543rd line of the frame F1 is written to the pixel connected to the scanning signal line G543 from the data signal line dy1 and the data signal line dy1 ′ is connected to the scanning signal line G544 is written. The data signal of the 544th line of the frame F1 is written into the frame F1.
　ここで、第１水平走査期間（Ｈ１）には、図１６・１７に示すように、データ信号線ＤＸ１・ＤＹ１からのデータ信号がプラス極性、データ信号線ＤＸ１’・ＤＹ１’からのデータ信号がマイナス極性、データ信号線ｄｘ１・ｄｙ１からのデータ信号がプラス極性、データ信号線ｄｘ１’・ｄｙ１’からのデータ信号がマイナス極性となっている。これにより、第１水平走査期間（Ｈ１）では、図１７に示すように、画素Ａはプラス極性、画素Ｂはマイナス極性、画素Ｃはプラス極性、画素Ｄはマイナス極性、画素Ｅはプラス極性、画素Ｆはマイナス極性、画素Ｇはプラス極性、画素Ｈはマイナス極性となる。 Here, in the first horizontal scanning period (H1), as shown in FIGS. 16 and 17, the data signals from the data signal lines DX1 and DY1 have a positive polarity, and the data signals from the data signal lines DX1 ′ and DY1 ′ have a positive polarity. The negative polarity, the data signal from the data signal lines dx1 and dy1 has a positive polarity, and the data signal from the data signal lines dx1 ′ and dy1 ′ has a negative polarity. Thus, in the first horizontal scanning period (H1), as shown in FIG. 17, the pixel A has a positive polarity, the pixel B has a negative polarity, the pixel C has a positive polarity, the pixel D has a negative polarity, the pixel E has a positive polarity, Pixel F has negative polarity, pixel G has positive polarity, and pixel H has negative polarity.
　なお、図１６・１７に示すように、第１水平走査期間（Ｈ１）には、データ信号線ＤＸ２・ＤＹ２からのデータ信号がマイナス極性、データ信号線ＤＸ２’・ ＤＹ２’からのデータ信号がプラス極性、データ信号線ｄｘ２・ｄｙ２からのデータ信号がマイナス極性、データ信号線ｄｘ２’・ｄｙ２’からのデータ信号がプラス極性となっている。これにより、第１水平走査期間（Ｈ１）では、図１７に示すように、画素Ａと行方向に隣接する画素Ｉはマイナス極性、画素Ｂと行方向に隣接する画素Ｊはプラス極性、画素Ｃと行方向に隣接する画素Ｋはマイナス極性、画素Ｄと行方向に隣接する画素Ｌはプラス極性、画素Ｅと行方向に隣接する画素Ｍはマイナス極性、画素Ｆと行方向に隣接する画素Ｎはプラス極性、画素Ｇと行方向に隣接する画素Ｏはマイナス極性、画素Ｈと行方向に隣接する画素Ｐはプラス極性となる。 As shown in FIGS. 16 and 17, in the first horizontal scanning period (H1), the data signals from the data signal lines DX2 and DY2 have a negative polarity, and the data signals from the data signal lines DX2 ′ and DY2 ′ have a positive polarity. The polarity, the data signal from the data signal lines dx2 · dy2 has a negative polarity, and the data signal from the data signal lines dx2 ′ · dy2 ′ has a positive polarity. Thus, in the first horizontal scanning period (H1), as shown in FIG. 17, the pixel I adjacent to the pixel A in the row direction has a negative polarity, the pixel J adjacent to the pixel B in the row direction has a positive polarity, and the pixel C The pixel K adjacent to the pixel in the row direction is negative polarity, the pixel L adjacent to the pixel D in the row direction is positive polarity, the pixel M adjacent to the pixel E in the row direction is negative polarity, and the pixel N is adjacent to the pixel F in the row direction. Is positive polarity, the pixel O adjacent to the pixel G in the row direction is negative polarity, and the pixel P adjacent to the pixel H in the row direction is positive polarity.
　また、第２水平走査期間（Ｈ２）でも、図１６・１８に示すように、データ信号線ＤＸ１・ＤＹ１からのデータ信号がプラス極性、データ信号線ＤＸ１’・ＤＹ１’からのデータ信号がマイナス極性、データ信号線ｄｘ１・ｄｙ１からのデータ信号がプラス極性、データ信号線ｄｘ１’・ｄｙ１’からのデータ信号がマイナス極性となっている。これにより、第２水平走査期間（Ｈ２）では、画素Ｄに続く４画素および画素Ｈに続く４画素に、図１８に示すような極性のデータ信号が書き込まれる。 In the second horizontal scanning period (H2), as shown in FIGS. 16 and 18, the data signals from the data signal lines DX1 and DY1 are positive, and the data signals from the data signal lines DX1 ′ and DY1 ′ are negative. The data signals from the data signal lines dx1 and dy1 have a positive polarity, and the data signals from the data signal lines dx1 ′ and dy1 ′ have a negative polarity. As a result, in the second horizontal scanning period (H2), data signals having polarities as shown in FIG. 18 are written into the four pixels following the pixel D and the four pixels following the pixel H.
　一方、次の垂直走査期間（Ｖ２）の第１水平走査期間（Ｈ１）では、図１６・１９に示すように、データ信号線ＤＸ１・ＤＹ１からのデータ信号がマイナス極性、データ信号線ＤＸ１’・ＤＹ１’からのデータ信号がプラス極性、データ信号線ｄｘ１・ｄｙ１からのデータ信号がマイナス極性、データ信号線ｄｘ１’・ｄｙ１’からのデータ信号がプラス極性となる。これにより、垂直走査期間（Ｖ２）の第１水平走査期間（Ｈ１）では、図１９に示すように、画素Ａはマイナス極性、画素Ｂはプラス極性、画素Ｃはマイナス極性、画素Ｄはプラス極性、画素Ｅはマイナス極性、画素Ｆはプラス極性、画素Ｇはマイナス極性、画素Ｈはプラス極性となる（各データ信号線からのデータ信号極性は１垂直走査期間ごとに反転する）。 On the other hand, in the first horizontal scanning period (H1) of the next vertical scanning period (V2), as shown in FIGS. 16 and 19, the data signals from the data signal lines DX1 and DY1 have a negative polarity, and the data signal lines DX1 ′. The data signal from DY1 'has a positive polarity, the data signal from data signal lines dx1 and dy1 has a negative polarity, and the data signal from data signal lines dx1' and dy1 'has a positive polarity. Accordingly, in the first horizontal scanning period (H1) of the vertical scanning period (V2), as shown in FIG. 19, the pixel A has a negative polarity, the pixel B has a positive polarity, the pixel C has a negative polarity, and the pixel D has a positive polarity. The pixel E has a negative polarity, the pixel F has a positive polarity, the pixel G has a negative polarity, and the pixel H has a positive polarity (the data signal polarity from each data signal line is inverted every vertical scanning period).
　また、垂直走査期間（Ｖ２）の第２水平走査期間（Ｈ２）では、図１６・２０に示すように、データ信号線ＤＸ１・ＤＹ１からのデータ信号がマイナス極性、データ信号線ＤＸ１’・ＤＹ１’からのデータ信号がプラス極性、データ信号線ｄｘ１・ｄｙ１からのデータ信号がマイナス極性、データ信号線ｄｘ１’・ｄｙ１’からのデータ信号がプラス極性となっている。これにより、垂直走査期間（Ｖ２）の第２水平走査期間（Ｈ２）では、画素Ｄに続く４画素および画素Ｈに続く４画素に、図２０に示すような極性のデータ信号が書き込まれる。 In the second horizontal scanning period (H2) of the vertical scanning period (V2), as shown in FIGS. 16 and 20, the data signals from the data signal lines DX1 and DY1 have a negative polarity, and the data signal lines DX1 ′ and DY1 ′. From the data signal lines dx1 and dy1 have a negative polarity, and the data signals from the data signal lines dx1 ′ and dy1 ′ have a positive polarity. As a result, in the second horizontal scanning period (H2) of the vertical scanning period (V2), data signals having polarities as shown in FIG. 20 are written in the four pixels following the pixel D and the four pixels following the pixel H.
　このように、本液晶パネルは８倍速駆動（第１および第２基板それぞれを４倍速駆動すること）が可能となるため、高速駆動が要求される液晶表示装置（例えば、高精細液晶表示装置や３次元表示対応の液晶表示装置）に好適である。なお、本実施例では、第１および第２基板それぞれを４倍速で駆動しているが、これに限定されない。第１および第２基板それぞれを、等速（１倍速）や２倍速で駆動することも可能である。 As described above, since the liquid crystal panel can be driven at 8 × speed (the first and second substrates can be driven at 4 × speed), a liquid crystal display device (for example, a high-definition liquid crystal display device or It is suitable for a three-dimensional display compatible liquid crystal display device. In this embodiment, each of the first and second substrates is driven at a quadruple speed, but the present invention is not limited to this. Each of the first and second substrates can be driven at a constant speed (1 × speed) or 2 × speed.
　また、各データ信号線のデータ信号の極性反転周期を１垂直走査期間としながら、図１７～図２０に示されるようなドット反転駆動を実現することができ、ソースドライバの消費電力の抑制と表示品位の向上を両立させることができる。 Further, dot inversion driving as shown in FIGS. 17 to 20 can be realized while the polarity inversion period of the data signal of each data signal line is one vertical scanning period, and the power consumption of the source driver is suppressed and displayed. Improvement in quality can be achieved at the same time.
　図２では、データ信号線とトランジスタのソース電極との間の抵抗値を、画素Ａ・Ｃ間で揃えるため、データ信号線ＤＸ１を、一旦中継電極ＴＭ１を介してトランジスタＴ１のソース電極８に接続しているがこの構成に限定されない。データ信号線とトランジスタのソース電極との間の抵抗値を低く抑えることができるプロセスでは、中継電極ＴＭ１を除去し、図２１およびそのＡ１－Ａ１’断面図である図２２に示すように、データ信号線ＤＸ１の延伸部を半導体層２４に重ね、この延伸部をソース電極として機能させる構成でも構わない。 In FIG. 2, the data signal line DX1 is once connected to the source electrode 8 of the transistor T1 via the relay electrode TM1 in order to make the resistance value between the data signal line and the source electrode of the transistor uniform between the pixels A and C. However, it is not limited to this configuration. In the process in which the resistance value between the data signal line and the source electrode of the transistor can be kept low, the relay electrode TM1 is removed, and as shown in FIG. 21 and FIG. The extending portion of the signal line DX1 may be overlaid on the semiconductor layer 24, and the extending portion may function as a source electrode.
　なお、図２～図７を、図２９～図３４のように変形することも可能である。すなわち、第１基板ＳＵ１では、中継電極ＴＭ１’・ＴＭ２・ＴＭ３’・ＴＭ４を形成せず、導電性フォトスペーサＦＳ３’・ＦＳ４を設けず、また、第２基板ＳＵ２でも、中継電極ｔｍ１・ｔｍ１’・ｔｍ２・ｔｍ２’・ｔｍ３’・ｔｍ４を形成せずに、対向電極ＣＯＭを、中継電極ｔｍ１・ｔｍ１’・ｔｍ２・ｔｍ２’・ｔｍ３’・ｔｍ４の形成領域まで拡張し、対向電極ＣＯＭの（寄生）抵抗値を下げることもできる。 Note that FIG. 2 to FIG. 7 can be modified as shown in FIG. 29 to FIG. That is, in the first substrate SU1, the relay electrodes TM1 ′, TM2, TM3 ′, TM4 are not formed, the conductive photospacers FS3 ′, FS4 are not provided, and the relay electrodes tm1, tm1 ′ are also formed in the second substrate SU2. Without forming the tm2, tm2 ′, tm3 ′, and tm4, the counter electrode COM is expanded to the formation region of the relay electrodes tm1, tm1 ′, tm2, tm2 ′, tm3 ′, and tm4. ) The resistance value can also be lowered.
　〔実施例２〕
　図１の液晶パネルを変形し、図２３に示すように、液晶パネル上半分について、画素Ａの画素電極を、トランジスタを介して、データ信号線ＤＸ１に接続し、画素Ｂの画素電極を、トランジスタを介して、データ信号線ｄｘ１に接続し、画素Ｃの画素電極を、トランジスタを介して、データ信号線ｄｘ１’に接続し、画素Ｄの画素電極を、トランジスタを介して、データ信号線ＤＸ１’に接続し、画素Ｉの画素電極を、トランジスタを介して、データ信号線ｄｘ２に接続し、画素Ｊの画素電極を、トランジスタを介して、データ信号線ＤＸ２に接続し、画素Ｋの画素電極を、トランジスタを介して、データ信号線ＤＸ２’に接続し、画素Ｌの画素電極を、トランジスタを介して、データ信号線ｄｘ２’に接続し、さらに、液晶パネル下半分も上半分と同一の接続関係とすることもできる。 [Example 2]
The liquid crystal panel of FIG. 1 is modified, and as shown in FIG. 23, for the upper half of the liquid crystal panel, the pixel electrode of the pixel A is connected to the data signal line DX1 through the transistor, and the pixel electrode of the pixel B is connected to the transistor The pixel electrode of the pixel C is connected to the data signal line dx1 ′ via the transistor, and the pixel electrode of the pixel D is connected to the data signal line DX1 ′ via the transistor. The pixel electrode of the pixel I is connected to the data signal line dx2 through the transistor, the pixel electrode of the pixel J is connected to the data signal line DX2 through the transistor, and the pixel electrode of the pixel K is connected to The transistor L is connected to the data signal line DX2 ′, the pixel electrode of the pixel L is connected to the data signal line dx2 ′ via the transistor, and the lower half of the liquid crystal panel is also connected to the upper half. It is also possible to have the same connection relationship.
　この場合は、図２４に示すように、データ信号線ＤＸ１、ＤＸ１’、ＤＸ２、ＤＸ２’ｄＸ１、ｄＸ１’、ｄＸ２、ｄＸ２’それぞれのデータ信号の極性を、第１極性、第２極性、第１極性、第２極性、第２極性、第１極性、第２極性、第１極性とし（第１および第２極性はそれぞれ、プラスまたはマイナス極性）、さらに、液晶パネル下半分も上半分と同一駆動とし、各データ信号のデータ信号の極性反転周期を１垂直走査期間とすることで、図２４のようなドット反転駆動を実現することができる。 In this case, as shown in FIG. 24, the data signal polarities of the data signal lines DX1, DX1 ′, DX2, DX2′dX1, dX1 ′, dX2, and dX2 ′ are set to the first polarity, the second polarity, and the first polarity, respectively. Polarity, 2nd polarity, 2nd polarity, 1st polarity, 2nd polarity, 1st polarity (1st and 2nd polarities are positive or negative polarity respectively), and the lower half of the liquid crystal panel is driven in the same way as the upper half By setting the polarity inversion period of the data signal of each data signal as one vertical scanning period, dot inversion driving as shown in FIG. 24 can be realized.
　〔実施例３〕
　図１の液晶パネルを変形し、図２５に示すように、液晶パネル上半分について、画素Ａの画素電極を、トランジスタを介して、データ信号線ＤＸ１に接続し、画素Ｂの画素電極を、トランジスタを介して、データ信号線ｄｘ１に接続し、画素Ｃの画素電極を、トランジスタを介して、データ信号線ＤＸ１’に接続し、画素Ｄの画素電極を、トランジスタを介して、データ信号線ｄｘ１’に接続し、画素Ｉの画素電極を、トランジスタを介して、データ信号線ｄｘ２に接続し、画素Ｊの画素電極を、トランジスタを介して、データ信号線ＤＸ２に接続し、画素Ｋの画素電極を、トランジスタを介して、データ信号線ｄｘ２’に接続し、画素Ｌの画素電極を、トランジスタを介して、データ信号線ＤＸ２’に接続し、さらに、液晶パネル下半分も上半分と同一の接続関係とすることもできる。 Example 3
The liquid crystal panel of FIG. 1 is modified, and as shown in FIG. 25, the pixel electrode of the pixel A is connected to the data signal line DX1 through the transistor and the pixel electrode of the pixel B is connected to the transistor in the upper half of the liquid crystal panel. Is connected to the data signal line dx1, the pixel electrode of the pixel C is connected to the data signal line DX1 ′ via the transistor, and the pixel electrode of the pixel D is connected to the data signal line dx1 ′ via the transistor. The pixel electrode of the pixel I is connected to the data signal line dx2 through the transistor, the pixel electrode of the pixel J is connected to the data signal line DX2 through the transistor, and the pixel electrode of the pixel K is connected to The transistor L is connected to the data signal line dx2 ′, the pixel electrode of the pixel L is connected to the data signal line DX2 ′ via the transistor, and the lower half of the liquid crystal panel is also connected to the upper half. It is also possible to have the same connection relationship.
　この場合は、図２６に示すように、データ信号線ＤＸ１、ＤＸ１’、ＤＸ２、ＤＸ２’ｄＸ１、ｄＸ１’、ｄＸ２、ｄＸ２’それぞれのデータ信号の極性を、第１極性、第１極性、第１極性、第１極性、第２極性、第２極性、第２極性、第２極性とし（第１および第２極性はそれぞれ、プラスまたはマイナス極性）、さらに、液晶パネル下半分も上半分と同一駆動とし、各データ信号のデータ信号の極性反転周期を１垂直走査期間とすることで、図２６のようなドット反転駆動を実現することができる。また、同一基板の各データ信号線のデータ信号が同極性になるため、データ信号線間の干渉（寄生容量等の影響）を抑えることができる。 In this case, as shown in FIG. 26, the data signal polarities of the data signal lines DX1, DX1 ′, DX2, DX2′dX1, dX1 ′, dX2, dX2 ′ are set to the first polarity, the first polarity, and the first polarity, respectively. Polarity, 1st polarity, 2nd polarity, 2nd polarity, 2nd polarity, 2nd polarity (1st and 2nd polarities are positive or negative polarity respectively), and the lower half of the liquid crystal panel is driven in the same way as the upper half By setting the polarity inversion period of the data signal of each data signal as one vertical scanning period, dot inversion driving as shown in FIG. 26 can be realized. In addition, since the data signals of the data signal lines on the same substrate have the same polarity, interference between the data signal lines (influence of parasitic capacitance or the like) can be suppressed.
　〔実施例４〕
　図１の液晶パネルを変形し、図２７に示すように、液晶パネル上半分について、画素Ａの画素電極を、トランジスタを介して、データ信号線ＤＸ１に接続し、画素Ｂの画素電極を、トランジスタを介して、データ信号線ｄｘ１に接続し、画素Ｃの画素電極を、トランジスタを介して、データ信号線ＤＸ１’に接続し、画素Ｄの画素電極を、トランジスタを介して、データ信号線ｄｘ１’に接続し、画素Ｉの画素電極を、トランジスタを介して、データ信号線ＤＸ２に接続し、画素Ｊの画素電極を、トランジスタを介して、データ信号線ｄｘ２に接続し、画素Ｋの画素電極を、トランジスタを介して、データ信号線ＤＸ２’に接続し、画素Ｌの画素電極を、トランジスタを介して、データ信号線ｄｘ２’に接続し、さらに、液晶パネル下半分も上半分と同一の接続関係とすることもできる。 Example 4
The liquid crystal panel of FIG. 1 is modified, and as shown in FIG. 27, the pixel electrode of the pixel A is connected to the data signal line DX1 through the transistor and the pixel electrode of the pixel B is connected to the transistor in the upper half of the liquid crystal panel. Is connected to the data signal line dx1, the pixel electrode of the pixel C is connected to the data signal line DX1 ′ via the transistor, and the pixel electrode of the pixel D is connected to the data signal line dx1 ′ via the transistor. The pixel electrode of the pixel I is connected to the data signal line DX2 through the transistor, the pixel electrode of the pixel J is connected to the data signal line dx2 through the transistor, and the pixel electrode of the pixel K is connected to The transistor L is connected to the data signal line DX2 ′, the pixel electrode of the pixel L is connected to the data signal line dx2 ′ via the transistor, and the lower half of the liquid crystal panel is also connected to the upper half. It is also possible to have the same connection relationship.
　この場合は、図２８に示すように、データ信号線ＤＸ１、ＤＸ１’、ＤＸ２、ＤＸ２’ｄＸ１、ｄＸ１’、ｄＸ２、ｄＸ２’それぞれのデータ信号の極性を、第１極性、第１極性、第２極性、第２極性、第２極性、第２極性、第１極性、第１極性とし（第１および第２極性はそれぞれ、プラスまたはマイナス極性）、さらに、液晶パネル下半分も上半分と同一駆動とし、各データ信号のデータ信号の極性反転周期を１垂直走査期間とすることで、図２８のようなドット反転駆動を実現することができる。 In this case, as shown in FIG. 28, the data signal polarities of the data signal lines DX1, DX1 ′, DX2, DX2′dX1, dX1 ′, dX2, dX2 ′ are set to the first polarity, the first polarity, the second polarity, respectively. Polarity, 2nd polarity, 2nd polarity, 2nd polarity, 1st polarity, 1st polarity (1st and 2nd polarities are positive or negative polarity respectively), and the lower half of the liquid crystal panel is driven in the same way as the upper half By setting the polarity inversion period of the data signal of each data signal as one vertical scanning period, dot inversion driving as shown in FIG. 28 can be realized.
　以上のように、本液晶パネルは、第１および第２基板と、第１および第２基板間に配された液晶層と、第１および第２画素と、上記液晶層に配された第１導電体と、第１基板に形成された第１および第２トランジスタと、第１画素に含まれる第１画素電極と、第２画素に含まれる第２画素電極と、第１および第２データ信号線とを備え、第１および第２画素電極並びに第１データ信号線が第１基板に形成され、第１トランジスタは第１データ信号線および第１画素電極と電気的に接続され、第２データ信号線は第２基板に形成され、第２データ信号線と第１導電体とが電気的に接続されるとともに、第２トランジスタは第１導電体および第２画素電極と電気的に接続されていることを特徴とする。 As described above, the present liquid crystal panel includes the first and second substrates, the liquid crystal layer disposed between the first and second substrates, the first and second pixels, and the first liquid crystal layer disposed on the liquid crystal layer. A conductor, first and second transistors formed on the first substrate, a first pixel electrode included in the first pixel, a second pixel electrode included in the second pixel, and first and second data signals First and second pixel electrodes and a first data signal line are formed on the first substrate, the first transistor is electrically connected to the first data signal line and the first pixel electrode, and the second data The signal line is formed on the second substrate, the second data signal line and the first conductor are electrically connected, and the second transistor is electrically connected to the first conductor and the second pixel electrode. It is characterized by being.
　上記構成によれば、例えば、第１および第２画素電極に同時にデータ信号を書き込むことが可能となり、さらなる高速駆動が実現される。 According to the above configuration, for example, it becomes possible to simultaneously write data signals to the first and second pixel electrodes, thereby realizing further high-speed driving.
　本液晶パネルは、第１および第２基板と、第１および第２基板間に配された液晶層と、第１および第２画素と、導電体と、第１基板に形成された第１および第２トランジスタと、第１画素に含まれる第１画素電極と、第２画素に含まれる第２画素電極と、第１および第２データ信号線とを備え、第１および第２画素電極並びに第１データ信号線が第１基板に形成され、第１トランジスタは第１データ信号線および第１画素電極と電気的に接続され、第２データ信号線は第２基板に形成され、第２データ信号線と導電体とが電気的に接続されるとともに、第２トランジスタは導電体および第２画素電極と電気的に接続されている構成とすることもできる。この液晶パネルを備えた液晶表示装置では、例えば図３５に示すように、第１データ信号線ＤＸ１は、第１基板に接続された第１基板用データ信号線駆動回路ＳＤＸ１で駆動され、第２データ信号線ｄｘ１は第２基板に接続された第２基板用データ信号線駆動回路ＳＤＸ２で駆動される。なお、上記導電体は液晶層に設けても（例えば、導電性スペーサを用いても）よいし、両基板間のシール部分に設けてもよいし、液晶パネルの端面（側面）に設けてもよい。 The liquid crystal panel includes first and second substrates, a liquid crystal layer disposed between the first and second substrates, first and second pixels, a conductor, and first and second substrates formed on the first substrate. A second transistor; a first pixel electrode included in the first pixel; a second pixel electrode included in the second pixel; and first and second data signal lines. One data signal line is formed on the first substrate, the first transistor is electrically connected to the first data signal line and the first pixel electrode, the second data signal line is formed on the second substrate, and the second data signal The line and the conductor can be electrically connected, and the second transistor can be electrically connected to the conductor and the second pixel electrode. In the liquid crystal display device including the liquid crystal panel, for example, as shown in FIG. 35, the first data signal line DX1 is driven by the first substrate data signal line driving circuit SDX1 connected to the first substrate, and the second data signal line DX1 is driven by the second substrate data signal line driving circuit SDX1. The data signal line dx1 is driven by the second substrate data signal line driving circuit SDX2 connected to the second substrate. The conductor may be provided on the liquid crystal layer (for example, a conductive spacer may be used), may be provided on a seal portion between both substrates, or may be provided on an end surface (side surface) of the liquid crystal panel. Good.
　本液晶パネルでは、第２基板には第１画素電極と対向する対向電極が形成され、第１画素電極と同層に第１中継電極が形成されるとともに、対向電極と同層に第２中継電極が形成され、　第２データ信号線と第２中継電極とが電気的に接続され、第１および第２中継電極が第１導電体を介して電気的に接続され、第１中継電極と第２トランジスタの１つの導通電極とが電気的に接続されている構成とすることもできる。 In the present liquid crystal panel, a counter electrode facing the first pixel electrode is formed on the second substrate, a first relay electrode is formed in the same layer as the first pixel electrode, and a second relay is formed in the same layer as the counter electrode. An electrode is formed, the second data signal line and the second relay electrode are electrically connected, the first and second relay electrodes are electrically connected via the first conductor, and the first relay electrode and the second relay electrode A configuration in which one conductive electrode of two transistors is electrically connected may be employed.
　本液晶パネルでは、第１導電体は、液晶層の厚みを調整するスペーサである構成とすることもできる。 In the present liquid crystal panel, the first conductor may be a spacer that adjusts the thickness of the liquid crystal layer.
　本液晶パネルでは、第１および第２データ信号線が互いに重なるように配置されている構成とすることもできる。 In the present liquid crystal panel, the first and second data signal lines may be arranged so as to overlap each other.
　本液晶パネルでは、第１画素電極と同層に第３中継電極が形成され、第１データ信号線と第１トランジスタの１つの導通電極とが第３中継電極を介して電気的に接続されている構成とすることもできる。 In the present liquid crystal panel, a third relay electrode is formed in the same layer as the first pixel electrode, and the first data signal line and one conductive electrode of the first transistor are electrically connected via the third relay electrode. It can also be set as the structure which is.
　本液晶パネルでは、第３および第４画素と、上記液晶層に配された第２導電体と、第１基板に形成された第３および第４トランジスタと、第３画素に含まれる第３画素電極と、第４画素に含まれる第４画素電極と、第３および第４データ信号線を備え、第１基板には第３および第４画素電極と第３データ信号線とが形成され、第３トランジスタは第３データ信号線および第３画素電極と電気的に接続され、第２基板には第４データ信号線が形成され、第４データ信号線と第２導電体とが電気的に接続されるとともに、第４トランジスタは第２導電体および第４画素電極と電気的に接続されている構成とすることもできる。 In the present liquid crystal panel, the third and fourth pixels, the second conductor disposed in the liquid crystal layer, the third and fourth transistors formed on the first substrate, and the third pixel included in the third pixel. An electrode, a fourth pixel electrode included in the fourth pixel, and third and fourth data signal lines. The first substrate includes the third and fourth pixel electrodes and the third data signal line; The three transistors are electrically connected to the third data signal line and the third pixel electrode, the fourth data signal line is formed on the second substrate, and the fourth data signal line and the second conductor are electrically connected. In addition, the fourth transistor may be configured to be electrically connected to the second conductor and the fourth pixel electrode.
　本液晶パネルでは、第１基板に形成された第１～第４走査信号線を備え、第１～第４トランジスタはそれぞれ、第１～第４走査信号線と電気的に接続され、走査方向を列方向として、第１～第４画素が同一の画素列に含まれる構成とすることもできる。 The present liquid crystal panel includes first to fourth scanning signal lines formed on a first substrate. The first to fourth transistors are electrically connected to the first to fourth scanning signal lines, respectively, and the scanning direction is set. As the column direction, the first to fourth pixels may be included in the same pixel column.
　本液晶パネルでは、上記画素列で、上記第１～第４画素が、第１画素、第３画素、第２画素、および第４画素の順に連続して並んでいる構成とすることもできる。 In the present liquid crystal panel, the first to fourth pixels in the pixel row may be arranged successively in the order of the first pixel, the third pixel, the second pixel, and the fourth pixel.
　本液晶パネルでは、上記画素列で、上記第１～第４画素が、第１画素、第２画素、第３画素、および第４画素の順に連続して並んでいる構成とすることもできる。 In the present liquid crystal panel, the first to fourth pixels in the pixel row may be arranged in succession in the order of the first pixel, the second pixel, the third pixel, and the fourth pixel.
　本液晶パネルでは、上記画素列で、上記第１～第４画素が、第１画素、第２画素、第４画素、および第３画素の順に連続して並んでいる構成とすることもできる。 In the present liquid crystal panel, the first to fourth pixels in the pixel row may be arranged successively in the order of the first pixel, the second pixel, the fourth pixel, and the third pixel.
　本液晶パネルでは、第１および２基板それぞれの非表示領域に基板間接続パッドが設けられ、第２基板の基板間接続パッドと第２データ信号線とが電気的に接続されている構成とすることもできる。 In the present liquid crystal panel, an inter-substrate connection pad is provided in each non-display area of the first and second substrates, and the inter-substrate connection pad of the second substrate and the second data signal line are electrically connected. You can also
　本液晶パネルでは、第１基板の基板間接続パッドと第２基板の基板間接続パッドとが、導電性フォトスペーサあるいは導電性ビーズを介して接続されている構成とすることもできる。 In the present liquid crystal panel, the inter-substrate connection pad of the first substrate and the inter-substrate connection pad of the second substrate may be connected via a conductive photospacer or conductive beads.
　本液晶パネルでは、第１基板に複数のドライバ接続パッドが設けられ、第１データ信号線と１つのドライバ接続パッドとが電気的に接続され、第１基板の基板間接続パッドと別のドライバ接続パッドとが電気的に接続されている構成とすることもできる。 In the present liquid crystal panel, a plurality of driver connection pads are provided on the first substrate, the first data signal line and one driver connection pad are electrically connected, and the inter-substrate connection pad of the first substrate is connected to another driver connection. It can also be set as the structure electrically connected with the pad.
　本液晶表示装置は、上記液晶パネルを備える。 This liquid crystal display device includes the liquid crystal panel.
　本液晶表示装置では、第１および第２走査信号線が同時選択される構成とすることもできる。 In the present liquid crystal display device, the first and second scanning signal lines may be simultaneously selected.
　本発明は上記の実施の形態に限定されるものではなく、上記実施の形態を技術常識に基づいて適宜変更したものやそれらを組み合わせて得られるものも本発明の実施の形態に含まれる。 The present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.
　本発明は、高速駆動が要求される液晶パネルに好適である。 The present invention is suitable for a liquid crystal panel that requires high-speed driving.
　Ａ～Ｐ　画素
　Ｐ１～Ｐ４　画素電極
　Ｔ１～Ｔ４　トランジスタ
　ＤＸ１・ｄｘ１・ＤＸ１’・ｄｘ１’　データ信号線
　ＤＹ１・ｄｙ１・ＤＹ１’・ｄｙ１’　データ信号線
　ＦＳ３　導電性のフォトスペーサ（第１導電体）
　ＴＭ３　中継電極（第１中継電極）
　ｔｍ３　中継電極（第２中継電極）
　ＴＭ１　中継電極（第３中継電極）
　Ｇ１～Ｇ４　走査信号線
　ＣＯＭ　対向（共通）電極
　ＢＰ　ｂｐ　基板間接続パッド
　ＳＰ　ソース接続パッド（ドライバ接続パッド） A to P pixels P1 to P4 pixel electrodes T1 to T4 transistors DX1, dx1, DX1 ', dx1' data signal lines DY1, dy1, DY1 ', dy1' data signal lines FS3 conductive photospacer (first conductor)
TM3 relay electrode (first relay electrode)
tm3 relay electrode (second relay electrode)
TM1 relay electrode (third relay electrode)
G1 to G4 Scan signal line COM Counter (common) electrode BP bp Inter-substrate connection pad SP Source connection pad (driver connection pad)

Claims (15)

  1. 　第１および第２基板と、第１および第２基板間に配された液晶層と、第１および第２画素と、上記液晶層に配された第１導電体と、第１基板に形成された第１および第２トランジスタと、第１画素に含まれる第１画素電極と、第２画素に含まれる第２画素電極と、第１および第２データ信号線とを備え、
    　第１および第２画素電極並びに第１データ信号線が第１基板に形成され、
    　第１トランジスタは第１データ信号線および第１画素電極と電気的に接続され、
    　第２データ信号線は第２基板に形成され、
    　第２データ信号線と第１導電体とが電気的に接続されるとともに、第２トランジスタは第１導電体および第２画素電極と電気的に接続されている液晶パネル。     Formed on the first substrate, the first and second substrates, the liquid crystal layer disposed between the first and second substrates, the first and second pixels, the first conductor disposed on the liquid crystal layer, and the first substrate. First and second transistors, a first pixel electrode included in the first pixel, a second pixel electrode included in the second pixel, and first and second data signal lines,
    First and second pixel electrodes and a first data signal line are formed on the first substrate,
    The first transistor is electrically connected to the first data signal line and the first pixel electrode,
    The second data signal line is formed on the second substrate,
    A liquid crystal panel in which the second data signal line and the first conductor are electrically connected, and the second transistor is electrically connected to the first conductor and the second pixel electrode.
  2. 　第２基板には第１画素電極と対向する対向電極が形成され、
    　第１画素電極と同層に第１中継電極が形成されるとともに、対向電極と同層に第２中継電極が形成され、
    　第２データ信号線と第２中継電極とが電気的に接続され、第１および第２中継電極が第１導電体を介して電気的に接続され、第１中継電極と第２トランジスタの１つの導通電極とが電気的に接続されている請求項１記載の液晶パネル。     A counter electrode opposite to the first pixel electrode is formed on the second substrate,
    A first relay electrode is formed in the same layer as the first pixel electrode, and a second relay electrode is formed in the same layer as the counter electrode.
    The second data signal line and the second relay electrode are electrically connected, the first and second relay electrodes are electrically connected via the first conductor, and the first relay electrode and one of the second transistors The liquid crystal panel according to claim 1, wherein the conductive electrode is electrically connected.
  3. 　第１導電体は、液晶層の厚みを調整するスペーサである請求項１記載の液晶パネル。 The liquid crystal panel according to claim 1, wherein the first conductor is a spacer for adjusting a thickness of the liquid crystal layer.
  4. 　第１および第２データ信号線が互いに重なるように配置されている請求項１記載の液晶パネル。 2. The liquid crystal panel according to claim 1, wherein the first and second data signal lines are arranged so as to overlap each other.
  5. 　第１画素電極と同層に第３中継電極が形成され、
    　第１データ信号線と第１トランジスタの１つの導通電極とが第３中継電極を介して電気的に接続されている請求項２記載の液晶パネル。     A third relay electrode is formed in the same layer as the first pixel electrode;
    3. The liquid crystal panel according to claim 2, wherein the first data signal line and one conduction electrode of the first transistor are electrically connected via a third relay electrode.
  6. 　第３および第４画素と、上記液晶層に配された第２導電体と、第１基板に形成された第３および第４トランジスタと、第３画素に含まれる第３画素電極と、第４画素に含まれる第４画素電極と、第３および第４データ信号線を備え、
    　第１基板には第３および第４画素電極と第３データ信号線とが形成され、
    　第３トランジスタは第３データ信号線および第３画素電極と電気的に接続され、
    　第２基板には第４データ信号線が形成され、
    　第４データ信号線と第２導電体とが電気的に接続されるとともに、第４トランジスタは第２導電体および第４画素電極と電気的に接続されている請求項１記載の液晶パネル。     Third and fourth pixels; a second conductor disposed in the liquid crystal layer; third and fourth transistors formed on the first substrate; a third pixel electrode included in the third pixel; A fourth pixel electrode included in the pixel, and third and fourth data signal lines;
    Third and fourth pixel electrodes and a third data signal line are formed on the first substrate,
    The third transistor is electrically connected to the third data signal line and the third pixel electrode,
    A fourth data signal line is formed on the second substrate,
    The liquid crystal panel according to claim 1, wherein the fourth data signal line and the second conductor are electrically connected, and the fourth transistor is electrically connected to the second conductor and the fourth pixel electrode.
  7. 　第１基板に形成された第１～第４走査信号線を備え、
    　第１～第４トランジスタはそれぞれ、第１～第４走査信号線と電気的に接続され、
    　走査方向を列方向として、第１～第４画素が同一の画素列に含まれる請求項６記載の液晶パネル。     Comprising first to fourth scanning signal lines formed on a first substrate;
    The first to fourth transistors are electrically connected to the first to fourth scanning signal lines, respectively.
    The liquid crystal panel according to claim 6, wherein the first to fourth pixels are included in the same pixel column with the scanning direction as the column direction.
  8. 　上記画素列では、上記第１～第４画素が、第１画素、第３画素、第２画素、および第４画素の順に連続して並んでいる請求項７記載の液晶パネル。 8. The liquid crystal panel according to claim 7, wherein in the pixel column, the first to fourth pixels are successively arranged in the order of the first pixel, the third pixel, the second pixel, and the fourth pixel.
  9. 　上記画素列では、上記第１～第４画素が、第１画素、第２画素、第３画素、および第４画素の順に連続して並んでいる請求項７記載の液晶パネル。 8. The liquid crystal panel according to claim 7, wherein in the pixel column, the first to fourth pixels are successively arranged in the order of the first pixel, the second pixel, the third pixel, and the fourth pixel.
  10. 　上記画素列では、上記第１～第４画素が、第１画素、第２画素、第４画素、および第３画素の順に連続して並んでいる請求項７記載の液晶パネル。 The liquid crystal panel according to claim 7, wherein in the pixel column, the first to fourth pixels are successively arranged in the order of the first pixel, the second pixel, the fourth pixel, and the third pixel.
  11. 　第１および２基板それぞれの非表示領域に基板間接続パッドが設けられ、
    　第２基板の基板間接続パッドと第２データ信号線とが電気的に接続されている請求項１記載の液晶パネル。     Inter-substrate connection pads are provided in the non-display areas of the first and second substrates,
    The liquid crystal panel according to claim 1, wherein the inter-substrate connection pad of the second substrate is electrically connected to the second data signal line.
  12. 　第１基板の基板間接続パッドと第２基板の基板間接続パッドとが、導電性フォトスペーサあるいは導電性ビーズを介して接続されている請求項１１記載の液晶パネル。 12. The liquid crystal panel according to claim 11, wherein the inter-substrate connection pad of the first substrate and the inter-substrate connection pad of the second substrate are connected via a conductive photospacer or conductive beads.
  13. 　第１基板に複数のドライバ接続パッドが設けられ、
    　第１データ信号線と１つのドライバ接続パッドとが電気的に接続され、
    　第１基板の基板間接続パッドと別のドライバ接続パッドとが電気的に接続されている請求項１２記載の液晶パネル。     A plurality of driver connection pads are provided on the first substrate,
    The first data signal line and one driver connection pad are electrically connected,
    The liquid crystal panel according to claim 12, wherein the inter-substrate connection pad of the first substrate is electrically connected to another driver connection pad.
  14. 　請求項１～１３のいずれか１項に記載の液晶パネルを備える液晶表示装置。 A liquid crystal display device comprising the liquid crystal panel according to any one of claims 1 to 13.
  15. 　第１および第２走査信号線が同時選択される請求項１４に記載の液晶表示装置。 15. The liquid crystal display device according to claim 14, wherein the first and second scanning signal lines are simultaneously selected.
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US11735131B2 (en) 2017-02-17 2023-08-22 Semiconductor Energy Laboratory Co., Ltd. Display device
CN112103312A (en) * 2020-08-21 2020-12-18 信利（惠州）智能显示有限公司 AMOLED display module and display screen

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