WO2012141118A1 - Semiconductor device provided with fuse element - Google Patents

Semiconductor device provided with fuse element Download PDF

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Publication number
WO2012141118A1
WO2012141118A1 PCT/JP2012/059635 JP2012059635W WO2012141118A1 WO 2012141118 A1 WO2012141118 A1 WO 2012141118A1 JP 2012059635 W JP2012059635 W JP 2012059635W WO 2012141118 A1 WO2012141118 A1 WO 2012141118A1
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WO
WIPO (PCT)
Prior art keywords
power supply
fuse element
transistor
data
current
Prior art date
Application number
PCT/JP2012/059635
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French (fr)
Japanese (ja)
Inventor
築出　正樹
Original Assignee
ルネサスエレクトロニクス株式会社
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Filing date
Publication date
Application filed by ルネサスエレクトロニクス株式会社 filed Critical ルネサスエレクトロニクス株式会社
Priority to JP2013509890A priority Critical patent/JP5559935B2/en
Publication of WO2012141118A1 publication Critical patent/WO2012141118A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device that stores data irreversibly and in a nonvolatile manner, and more particularly, to a semiconductor device that includes a fuse element that stores data according to a conductive state of wiring.
  • Nonvolatile memory Semiconductor devices include a nonvolatile memory in which stored data is not lost even when power is not supplied.
  • Various types of nonvolatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory) have been developed.
  • EEPROM Electrical Erasable Programmable Read Only Memory
  • SoC System on Chip
  • an additional mask and an additional process are required because the structure for storing charges in the floating gate is mixedly mounted on the same semiconductor chip. It becomes necessary and the manufacturing cost becomes expensive.
  • non-volatile memory including a fuse element as a non-volatile memory that can be embedded on the same semiconductor chip without requiring an additional mask and an additional process.
  • the fuse element is an element capable of storing data depending on the conduction state of the wiring, and is a fuse element of a current blow type of a polysilicon wiring or a metal wiring.
  • a nonvolatile memory including a fuse element made of a polysilicon wiring whose surface is silicided is an irreversible memory in which written data cannot be erased because data is written by changing the conduction state of the wiring.
  • FIG. 13 is a schematic view showing a configuration of a nonvolatile memory including a conventional fuse element.
  • the nonvolatile memory 100 shown in FIG. 13 includes a fuse array 101 in which a plurality of memory cells 200 including fuse elements are arranged in a matrix, and a row decoder that supplies a selection signal to a word line WL (Word Line) of the fuse array 101.
  • RD Row Decoder
  • CD Column Decoder
  • control circuit 104 for controlling operations of row decoder 102 and column decoder 103, reference resistance and
  • a reference value generation circuit 105 that generates a reference word line voltage is provided.
  • a sense amplifier SA Sense Amplifier
  • I / O Input / Output
  • the input / output unit I / O inputs and outputs data in units of 16 bits.
  • FIG. 14 is a schematic diagram showing a configuration of a memory cell 200 of a nonvolatile memory 100 including a conventional fuse element.
  • a memory cell 200 illustrated in FIG. 14 includes a fuse element 201 that stores data according to a conductive state of a wiring, and a transistor 202 that connects a drain electrode to one end of the fuse element 201.
  • the fuse element 201 has the bit line BL connected to the other end, and the transistor 202 has the word line WL connected to the gate electrode.
  • FIG. 15 is a schematic diagram illustrating a configuration of a selection circuit 300 of a nonvolatile memory 100 including a conventional fuse element.
  • the selection circuit 300 shown in FIG. 15 amplifies the switching element 301 that connects the cutting power source EFV and the bit line BL, the level conversion circuit 302 that converts the signal level of the selection signal, and the voltage of the selection signal that has converted the signal level. And an amplifier 303 for generating a control signal for the switching element 301.
  • the selection circuit 300 is driven by a cutting power source EFV.
  • the nonvolatile memory 100 When writing data, the nonvolatile memory 100 inputs a selection signal to the level conversion circuit 302 of the column in which data is written, and amplifies the voltage of the selection signal converted from the signal level by the amplifier 303 to generate a control signal. .
  • the nonvolatile memory 100 controls the switching element 301 by the control signal generated by the amplifier 303 to connect the bit line BL and the high-voltage cutting power supply EFV.
  • the nonvolatile memory 100 controls the switching element 301 by a control signal to connect the bit line BL and the power supply EFV for cutting the core potential.
  • the nonvolatile memory 100 is connected to the fuse element 201 by the sense amplifier SA by the current flowing from the core potential cutting power source EFV to the fuse element 201.
  • the data is read by determining the disconnected / uncut state.
  • the nonvolatile memory 100 controls the connection between the bit line BL and the cutting power supply EFV by the selection circuit 300, the selection signal for selecting a column is unstable due to a malfunction of the selection circuit 300 when the power is turned on.
  • the bit line BL and the cutting power supply EFV set to a high voltage are inadvertently conducted, and the fuse element 201 may be erroneously cut.
  • the nonvolatile memory 100 when reading data, the nonvolatile memory 100 needs to lower the voltage applied to the fuse element 201 as compared with the time of writing so that the fuse element 201 is not accidentally disconnected.
  • the non-volatile memory 100 uses the cutting power supply EFV as the driving power supply for the selection circuit 300, and it is necessary to increase the resistance of the switching element 301 in order to reduce the voltage applied to the fuse element 201 so as not to malfunction. is there. Therefore, when the resistance of the switching element 301 becomes larger than the resistance of the fuse element 201 and the resistance of the fuse element is measured in units of arrays, the resistance of the switching element 301 is measured. The resistance cannot be measured accurately.
  • the nonvolatile memory 100 controls the connection between the bit line BL and the cutting power supply EFV by the selection circuit 300, the reliability cannot be evaluated with only the fuse element 201 and the transistor 202. It is necessary to evaluate the reliability including the selection circuit 300, which increases the development cost.
  • the nonvolatile memory 100 allows a current to flow through the fuse element 201 through the same path both when data is written and when data is read, the tendency of stress applied to the fuse element 201 when data is read, The tendency of stress applied to the fuse element 201 when writing is the same. Therefore, in the nonvolatile memory 100, as the number of times of reading data increases, the stress having the same tendency is accumulated in the fuse element 201, and the operation may become defective.
  • an object of the present invention is to provide a semiconductor device including a fuse element that stores data according to a conductive state of a wiring without requiring a selection circuit for controlling connection between a bit line and a power supply for cutting.
  • the present invention is a semiconductor device that stores data in an irreversible and non-volatile manner, and has one end connected to a power supply terminal capable of switching between a power supply voltage and a ground voltage, A fuse element that stores data according to a conductive state, one current electrode connected to the other end of the fuse element, a first transistor that controls a current flowing from the power supply terminal to the fuse element, and a first transistor in parallel, One current electrode is connected to the other end of the fuse element, a second transistor for controlling the current flowing from the fuse element to the power supply terminal, and a first logic circuit connected to the control electrode of the first transistor are provided.
  • the first logic circuit When writing data, the first logic circuit turns on the first transistor in accordance with the active state of the first word line and the first selection line connected to the first logic circuit, thereby supplying the power supply voltage. A current is passed from the terminal to the fuse element to cut the fuse element wiring.
  • the second transistor When reading data, the second transistor is turned on according to the active state of the second word line connected to the control electrode of the second transistor, and the current of the bit line connected to the other current electrode of the second transistor. From the fuse element to the power terminal of the ground voltage.
  • the first transistor is connected to the other end of the fuse element whose one end is connected to the power supply terminal, and is connected to the other end of the fuse element.
  • the second transistor for controlling the current flowing from the fuse element to the power supply terminal and the first logic circuit connected to the control electrode of the first transistor are provided, the power supply terminal that becomes the power supply voltage when the fuse is cut from the fuse element.
  • the semiconductor device according to the present invention does not need to include a selection circuit, the fuse element is not erroneously cut by malfunction of the selection circuit when the power is turned on.
  • the semiconductor device according to the present invention does not need to include a selection circuit that is driven by a power source that becomes a power supply voltage when the fuse element is cut, the selection circuit is configured to reduce the voltage applied to the fuse element when reading data. There is no need to increase the resistance of the switching element, and the resistance of the fuse element can be accurately measured in array units. Furthermore, since the semiconductor device according to the present invention does not need to include a selection circuit, accurate reliability can be evaluated using only the fuse element and the transistor, and the development cost can be reduced.
  • the semiconductor device according to the present invention uses a path through the first transistor when writing data and a path through the second transistor when reading data, so that data is read when data is written. Current can be passed through the fuse element through different paths. Therefore, the semiconductor device according to the present invention can operate stably without reducing the stress applied to the fuse element and increasing or limiting the number of times of reading data.
  • FIG. 1 is a schematic diagram showing a configuration of a memory cell according to a first embodiment of the present invention.
  • FIG. 6 is a schematic diagram for explaining an operation when data is written to a memory cell according to the first embodiment of the present invention.
  • 3 is a timing chart of signals when data is written to the memory cell according to the first embodiment of the present invention.
  • FIG. 7 is a schematic diagram for explaining an operation when data is read from the memory cell according to the first embodiment of the present invention.
  • FIG. 3 is a schematic diagram showing a configuration of a determination circuit that determines read data when data is read from the memory cell according to the first embodiment of the present invention
  • 4 is a timing chart of signals when data is read from the memory cell according to the first embodiment of the present invention. It is the schematic which shows the structure of the non-volatile memory which concerns on Embodiment 2 of this invention. It is the schematic which shows the structure of the memory cell which concerns on Embodiment 2 of this invention. It is the schematic for demonstrating operation
  • FIG. 10 is a schematic diagram for explaining an operation when data is read from a memory cell according to a second embodiment of the present invention.
  • FIG. 6 is a timing chart of signals when data is read from a memory cell according to a second embodiment of the present invention. It is the schematic which shows the structure of the non-volatile memory provided with the conventional fuse element. It is the schematic which shows the structure of the memory cell of a non-volatile memory provided with the conventional fuse element. It is the schematic which shows the structure of the selection circuit of a non-volatile memory provided with the conventional fuse element.
  • FIG. 1 is a schematic diagram showing a configuration of a nonvolatile memory according to Embodiment 1 of the present invention.
  • a nonvolatile memory 10 shown in FIG. 1 is a semiconductor device that stores data in an irreversible and nonvolatile manner.
  • the nonvolatile memory 10 includes a fuse array 1 in which a plurality of memory cells 20 including fuse elements are arranged in a matrix, a row decoder (RD) 2 that supplies a selection signal to the word lines WL of the fuse array 1, A column decoder (CD) 3 that selects a bit line BL, a control circuit 4 that controls operations of the row decoder 2 and the column decoder 3, and a reference value generation circuit 5 that generates a reference resistor and a reference word line voltage are provided.
  • RD row decoder
  • CD column decoder
  • a reference value generation circuit 5 that generates a reference resistor and a reference word line voltage
  • the fuse array 1 has two word lines WL for one row of memory cells 20.
  • the two word lines WL are the first word line WL (prog) used when writing data to the memory cell 20 (when programming (prog)), and when reading data from the memory cell 20 (reading).
  • the fuse array 1 has one bit line BL and one select line CSL (Column Select Line) for one column of memory cells 20.
  • the row decoder 2 supplies a selection signal to the word line WL (prog) when writing data to the memory cell 20, and supplies a selection signal to the word line WL (Read) when reading data from the memory cell 20. .
  • the column decoder 3 supplies a selection signal to the selection line CSL when writing data to the memory cell 20, and reads data from the bit line BL when reading data from the memory cell 20.
  • a sense amplifier SA for amplifying the voltage of the bit line BL and an input / output unit I / O for inputting / outputting data are also provided.
  • the voltage of the bit line BL can be read as data by being amplified by the sense amplifier SA.
  • the input / output unit I / O inputs and outputs data in units of 16 bits. Further, the column decoder 3 decodes with a 32-bit address when writing data into the memory cell 20.
  • FIG. 2 is a schematic diagram showing the configuration of the memory cell 20 according to the first embodiment of the present invention.
  • the memory cell 20 shown in FIG. 2 has one end connected to the terminal of the power supply EFV for cutting and an N-channel MOS (with a drain electrode connected to the other end of the fuse element 21 for storing data depending on the conductive state of the wiring.
  • NMOS N-channel MOS
  • NMOS transistors 22 and 23 and an AND circuit 24 connected to the gate electrode of the NMOS transistor 22.
  • the fuse element 21 is a storage element that is configured by a polysilicon wiring or a metal wiring, stores data by changing a resistance value by passing a large current through the wiring and cutting it.
  • the fuse element 21 is not limited to the case where the wiring is physically cut, but changes the wiring structure such as the shape of the wiring or the material distribution to change the conductive state (for example, resistance value) of the wiring. It only has to be made.
  • the polysilicon wiring may be formed on the surface with a silicide layer reacted with a metal such as titanium (Ti), cobalt (Co), or nickel (Ni).
  • the NMOS transistor (first transistor) 22 controls the current that flows from the terminal of the cutting power supply EFV to the fuse element 21.
  • the NMOS transistor 22 has a larger transistor size than the NMOS transistor 23 because a large current needs to flow in order to cut the wiring of the fuse element 21. Since the transistor size of the NMOS transistor 23 is smaller than the transistor size of the NMOS transistor 22, compared to the case where the transistor size of the NMOS transistor 23 and the transistor size of the NMOS transistor 22 are the same size, The nonvolatile memory 10 can be reduced in size.
  • the NMOS transistor (second transistor) 23 is connected in parallel to the NMOS transistor 22 and controls the current flowing from the fuse element 21 to the terminal of the cutting power supply EFV.
  • the NMOS transistor 23 is turned on when a selection signal is supplied to the word line WL (Read), and the current is disconnected from the fuse element 21 to the ground voltage in order to detect the conduction state of the fuse element 21. Flow to the terminal of the power supply EFV.
  • the AND circuit (first logic circuit) 24 has a word line WL (prog) and a selection line CSL connected to the input side, and a gate electrode of the NMOS transistor 22 connected to the output side.
  • the AND circuit 24 when both the selection signals input to the word line WL (prog) and the selection line CSL are “1”, the signal output to the gate electrode of the NMOS transistor 22 is “1”.
  • the NMOS transistor 22 is turned on when a signal of “1” is supplied to the gate electrode, and in order to cut the wiring of the fuse element 21, a large current is fused from the terminal of the cutting power supply EFV set to the power supply voltage. Flow to element 21.
  • the operation of the nonvolatile memory 10 will be described.
  • the operation of the nonvolatile memory 10 will be described separately when data is written to the memory cell 20 and when data is read from the memory cell 20.
  • FIG. 3 is a schematic diagram for explaining an operation when data is written in the memory cell 20 according to the first embodiment of the present invention.
  • the data stored in the memory cell 20 has a value of “0” or “1”
  • the fuse element 21 uses “0” data when the wiring is not cut, and “1” when the wiring is cut. ”Is stored. Therefore, data of “1” can only be substantially written, and storing “0” data is equivalent to not writing data of “1”. Therefore, writing data into the memory cell 20 is also referred to as programming data into the nonvolatile memory 10.
  • the case where the wiring of the fuse element 21 is cut will be described as data writing and will be described below.
  • FIG. 4 is a timing chart of signals when data is written to memory cell 20 according to the first embodiment of the present invention.
  • the selection signal input to the selection line CSL is “1” (selection line CSL is active), and then the selection signal input to the word line WL (prog) is “1” (word line WL). (Prog) becomes active), the memory cell 20 turns on the NMOS transistor 22.
  • a power supply voltage having a voltage high enough to flow a large current for cutting the wiring of the fuse element 21 when data is written to the memory cell 20 can be supplied to the terminal of the cutting power supply EFV.
  • the terminal of the cutting power supply EFV includes a pad (not shown), and can be set to the power supply voltage or the ground voltage from the outside of the nonvolatile memory 10.
  • the memory cell 20 turns on the NMOS transistor 22 to cut the wiring of the fuse element 21 by causing a current to flow from the terminal of the cutting power supply EFV set to the power supply voltage to the fuse element 21 in the direction indicated by the arrow A. To do.
  • the memory cell 20 stores the data “1” in the fuse element 21 by cutting the wiring of the fuse element 21.
  • a portion not operating when data is written is indicated by a broken line.
  • FIG. 5 is a schematic diagram for explaining an operation when data is read from the memory cell 20 according to the first embodiment of the present invention.
  • the memory cell 20 shown in FIG. 5 turns on the NMOS transistor 23 in accordance with the active state of the word line WL (Read) connected to the gate electrode of the NMOS transistor 23. It is assumed that the terminal of cutting power supply EFV is set to be a ground voltage when data is read from memory cell 20.
  • the memory cell 20 turns on the NMOS transistor 23 so that the current of the bit line BL connected to the source electrode of the NMOS transistor 23 is transferred from the fuse element 21 to the terminal of the cutting power supply EFV set to the ground voltage. Flow in the direction indicated by B.
  • the nonvolatile memory 10 can read data from the memory cell 20 by determining the voltage of the bit line BL that changes depending on the conduction state of the wiring of the fuse element 21 by the determination circuit 30. In the memory cell 20 shown in FIG. 5, a portion not operating when data is read is indicated by a broken line.
  • FIG. 6 is a schematic diagram showing a configuration of a determination circuit 30 that performs determination of read data when data is read from the memory cell 20 according to the first embodiment of the present invention.
  • the determination circuit 30 shown in FIG. 6 includes a switching element 31 that connects a core power supply terminal and a bit line BL, and a sense amplifier SA that is connected to the bit line BL.
  • This sense amplifier SA is also shown in FIG.
  • the terminal of the core power supply is a power supply terminal for supplying a current to the bit line BL when data is read, unlike the terminal of the cutting power supply EFV. Note that when data is written, the power supply voltage applied to the terminal of cutting power supply EFV is higher than the power supply voltage applied to the core power supply terminal when data is read.
  • the switching element 31 controls whether or not to connect the core power supply terminal and the bit line BL in accordance with the input signal / RD_Enable. Specifically, the switching element 31 connects the core power supply terminal and the bit line BL when the input signal / RD_Enable is “0”, and connects the core power supply terminal and bit when the input signal / RD_Enable is “1”. Do not connect to line BL.
  • the core power supply terminal and the bit line BL are not connected.
  • the core power supply is a power supply for supplying a power supply voltage for supplying a current to the bit line BL when data is read from the memory cell 20, and this power supply voltage generally supplies the fuse element 21 with power. It is lower than the power supply voltage given by the cutting power supply EFV when cutting. Further, the core power supply is often used as the entire operation power supply in the nonvolatile memory 10 shown in FIG.
  • the sense amplifier SA amplifies the voltage of the bit line BL when the terminal of the core power supply and the bit line BL are connected by the switching element 31, and the determination result is based on whether the amplified voltage is equal to or higher than a predetermined level. Is read as data OUT.
  • FIG. 7 is a timing chart of signals when data is read from memory cell 20 according to the first embodiment of the present invention.
  • the input signal / RD_Enable of “0” is input and the switching element 31 is turned on for t time. Turn on. When the switching element 31 is turned on, a current flows through the bit line BL, and the voltage of the bit line BL changes from 0V to aV.
  • the NMOS transistor 23 is turned on, and the current of the bit line BL is changed to the fuse element 21.
  • the current of the bit line BL does not flow to the terminal of the cutting power supply EFV set to the ground voltage via the fuse element 21, so that the voltage of the bit line BL is aV Does not change.
  • the current of the bit line BL flows to the terminal of the cutting power supply EFV set to the ground voltage via the fuse element 21, so that the bit line BL The voltage changes from aV to 0V.
  • the sense amplifier SA amplifies the voltage of the bit line BL and determines whether the amplified voltage is equal to or higher than a predetermined level. To do. When the amplified voltage is equal to or higher than a predetermined level, the sense amplifier SA determines that the wiring of the fuse element 21 is disconnected and reads “1” data as data OUT. On the other hand, when the amplified voltage is lower than a predetermined level, the sense amplifier SA determines that the wiring of the fuse element 21 is not cut (not cut), and reads “0” data as data OUT.
  • the nonvolatile memory 10 according to Embodiment 1 of the present invention is connected to the other end of the fuse element 21 whose one end is connected to the terminal of the cutting power supply EFV, and from the terminal of the cutting power supply EFV to the fuse.
  • the non-volatile memory 10 includes a selection circuit that controls the connection between the bit line BL and the terminal of the cutting power supply EFV in order to supply a current from the cutting power supply EFV that becomes a power supply voltage at the time of fuse cutting to the fuse element 21. There is no need to prepare. Since the nonvolatile memory 10 does not need to include a selection circuit, the fuse element 21 is not erroneously disconnected due to a malfunction of the selection circuit when the power is turned on.
  • the terminal of the power supply EFV for cutting is set to the ground voltage except when the wiring of the fuse element 21 is cut. Therefore, the control signal becomes indefinite when the power is turned on, and the NMOS transistor 22 is turned on. In this case, since no potential difference is generated between the fuse elements 21, the fuse element 21 is not erroneously cut. Since nonvolatile memory 10 normally writes data only at the time of a shipping test, the terminal of cutting power supply EFV is set to the ground voltage even when used in the market.
  • the nonvolatile memory 10 does not need to include a selection circuit that is driven by the cutting power supply EFV, the resistance of the switching element of the selection circuit is reduced in order to reduce the voltage applied to the fuse element 21 when the fuse element 21 is evaluated. There is no need to increase the resistance, and the resistance of the fuse element 21 can be accurately measured in array units. Since the nonvolatile memory 10 can accurately measure the resistance of the fuse element 21 in units of arrays, the wiring of the fuse element 21 is disconnected in addition to determining whether the fuse element 21 is good or not at the time of a shipment test. It is also possible to test the margin when doing so, improving the test quality of the product.
  • the nonvolatile memory 10 does not need to include a selection circuit, accurate reliability can be evaluated only with the fuse element 21 and the NMOS transistors 22 and 23, and the development cost can be reduced.
  • the nonvolatile memory 10 Since the nonvolatile memory 10 uses a path through the NOMS transistor 22 when writing data and a path through the NOMS transistor 23 when reading data, the nonvolatile memory 10 writes data and reads data. Thus, current can be passed through the fuse element 21 through different paths. Therefore, the nonvolatile memory 10 can operate stably without reducing the stress applied to the fuse element 21 and without increasing or limiting the number of times of reading data.
  • the nonvolatile memory 10 includes the NOMS transistor 23 between the fuse element 21 and the bit line BL, the initial charge of the bit line BL is only applied to the memory cell 20 in which the word line WL (read) is active. And the initial charge of the bit line BL does not flow to the other memory cells 20.
  • FIG. 8 is a schematic diagram showing the configuration of the nonvolatile memory according to Embodiment 2 of the present invention.
  • a nonvolatile memory 11 shown in FIG. 8 is a semiconductor device that stores data irreversibly and in a nonvolatile manner.
  • the nonvolatile memory 11 includes a fuse array 7 in which a plurality of memory cells 40 including fuse elements are arranged in a matrix, a row decoder (RD) 2 that supplies a selection signal to the word lines WL of the fuse array 7, A column decoder (CD) 3 that selects a bit line BL, a control circuit 4 that controls operations of the row decoder 2 and the column decoder 3, and a reference value generation circuit 5 that generates a reference resistor and a reference word line voltage are provided.
  • RD row decoder
  • CD column decoder
  • CD control circuit 4 that controls operations of the row decoder 2 and the column decoder 3
  • a reference value generation circuit 5 that generates a reference resistor and a reference word line voltage are provided.
  • the fuse array 7 has one word line WL for one row of memory cells 40.
  • the word line WL is common to the word line WL when data is written to the memory cell 40 (program (prog)) and the word line WL when data is read from the memory cell 40 (read).
  • the word line WL is non-volatile as compared with the case where the word line WL is configured with two word lines WL used when data is written to the memory cell 40 and word line WL used when data is read from the memory cell 40.
  • the memory 11 can be reduced in size.
  • the word line WL is the first word line WL (prog) used when writing data to the memory cell 40 and the first word line used when reading data from the memory cell 40. You may comprise by the word line WL (Read) of 2 word lines.
  • the fuse array 7 has one bit line BL and two selection lines CSL for one row of memory cells 40.
  • the two selection lines CSL are a selection line CSL (prog) of the first selection line used when writing data into the memory cell 40 and a selection line of the second selection line used when reading data from the memory cell 40. It consists of CSL (Read).
  • FIG. 9 is a schematic diagram showing a configuration of the memory cell 40 according to the second embodiment of the present invention.
  • the memory cell 40 shown in FIG. 9 has one end connected to the terminal of the power supply EFV for cutting, a fuse element 21 for storing data according to the conductive state of the wiring, and an NMOS transistor 22 for connecting a drain electrode to the other end of the fuse element 21. 23, an AND circuit 24 connected to the gate electrode of the NMOS transistor 22, and an AND circuit 41 connected to the gate electrode of the NMOS transistor 23.
  • the AND circuit (first logic circuit) 24 has a word line WL and a select line CSL (prog) connected to the input side, and a gate electrode of the NMOS transistor 22 connected to the output side.
  • the AND circuit 24 when both the selection signals input to the word line WL and the selection line CSL (prog) are “1”, the signal output to the gate electrode of the NMOS transistor 22 is “1”.
  • the NMOS transistor 22 is turned on when a signal of “1” is supplied to the gate electrode, and in order to cut the wiring of the fuse element 21, a large current is fused from the terminal of the cutting power supply EFV set to the power supply voltage. Flow to element 21.
  • the AND circuit (second logic circuit) 41 has a word line WL and a select line CSL (Read) connected to the input side, and a gate electrode of the NMOS transistor 23 connected to the output side.
  • the AND circuit 41 when the selection signals input to the word line WL and the selection line CSL (Read) are both “1”, the signal output to the gate electrode of the NMOS transistor 23 is “1”.
  • the NMOS transistor 23 is turned on when a signal of “1” is supplied to the gate electrode, and in order to detect the conduction state of the wiring of the fuse element 21, the current is disconnected from the fuse element 21 to the ground voltage. Flow to the terminal of the power supply EFV.
  • FIG. 10 is a schematic diagram for explaining an operation when data is written in the memory cell 40 according to the second embodiment of the present invention.
  • the data stored in the memory cell 40 has a value of “0” or “1”
  • the fuse element 21 uses “0” data when the wiring is not cut, and “1” when the wiring is cut. ”Is stored. Therefore, data of “1” can only be substantially written, and storing “0” data is equivalent to not writing data of “1”. Therefore, writing data into the memory cell 20 is also referred to as programming data into the nonvolatile memory 10.
  • the case where the wiring of the fuse element 21 is cut will be described below by expressing that data is written.
  • the AND circuit 24 turns on the NMOS transistor 22 in accordance with the active state of the word line WL and select line CSL (prog) connected to the AND circuit 24.
  • the timing chart of the operation to turn on the NMOS transistor 22 is the same as the timing chart of the timing chart shown in FIG. 4 in which the selection line CSL is replaced with the selection line CSL (prog) and the word line WL (prog) is replaced with the word line WL. It is. Therefore, illustration of a timing chart of signals when data is written in the memory cell 40 according to the second embodiment of the present invention is omitted.
  • the selection signal input to the selection line CSL (prog) becomes “1” (the selection line CSL (prog) is active), and then the selection is input to the word line WL.
  • the signal becomes “1” (the word line WL is activated) the memory cell 40 turns on the NMOS transistor 22.
  • a power supply voltage having a voltage high enough to flow a large current for cutting the wiring of the fuse element 21 when data is written to the memory cell 40 can be supplied to the terminal of the cutting power supply EFV. Shall be set to
  • the memory cell 40 By turning on the NMOS transistor 22, the memory cell 40 cuts the wiring of the fuse element 21 by causing a current to flow from the terminal of the cutting power supply EFV set to the power supply voltage to the fuse element 21 in the direction indicated by the arrow A. To do.
  • the memory cell 40 stores “1” data in the fuse element 21 by cutting the wiring of the fuse element 21. In the memory cell 40 shown in FIG. 10, a portion not operating when data is written is indicated by a broken line.
  • FIG. 11 is a schematic diagram for explaining an operation when data is read from the memory cell 40 according to the second embodiment of the present invention.
  • the AND circuit 41 turns on the NMOS transistor 23 in accordance with the active state of the word line WL (Read) and the selection line CSL (Read) connected to the AND circuit 41. It is assumed that the terminal of cutting power supply EFV is set to be a ground voltage when data is read from memory cell 40.
  • the memory cell 40 By turning on the NMOS transistor 23, the memory cell 40 causes the current of the bit line BL connected to the source electrode of the NMOS transistor 23 to flow from the fuse element 21 to the terminal of the cutting power supply EFV set to the ground voltage. Flow in the direction indicated by B.
  • the nonvolatile memory 11 reads data from the memory cell 40 by determining the voltage of the bit line BL that changes depending on the conduction state of the wiring of the fuse element 21 by the determination circuit 30. In the memory cell 40 shown in FIG. 11, a portion not operating when data is read is indicated by a broken line.
  • the determination circuit 30 has the same configuration as the determination circuit 30 shown in FIG.
  • FIG. 12 is a timing chart of signals when data is read from memory cell 40 according to the second embodiment of the present invention.
  • the input signal / RD_Enable of “0” is input and the switching element 31 is turned on for t time. Turn on. When the switching element 31 is turned on, a current flows through the bit line BL, and the voltage of the bit line BL changes from 0V to aV.
  • the selection signal input to the selection line CSL (read) becomes “1” (the selection line CSL (read) is active), and the selection signal input to the word line WL is “1” (the word line WL is active).
  • the NMOS transistor 23 is turned on, and the current of the bit line BL flows from the fuse element 21 to the terminal of the cutting power supply EFV set to the ground voltage.
  • the current of the bit line BL does not flow to the terminal of the cutting power supply EFV set to the ground voltage via the fuse element 21, so that the voltage of the bit line BL is aV Does not change.
  • the current of the bit line BL flows to the terminal of the cutting power supply EFV set to the ground voltage via the fuse element 21, so that the bit line BL The voltage changes from aV to 0V.
  • the sense amplifier SA amplifies the voltage of the bit line BL and determines whether the amplified voltage is equal to or higher than a predetermined level. To do. When the amplified voltage is equal to or higher than a predetermined level, the sense amplifier SA determines that the wiring of the fuse element 21 is disconnected and reads “1” data as data OUT. On the other hand, when the amplified voltage is lower than a predetermined level, the sense amplifier SA determines that the wiring of the fuse element 21 is not cut (not cut), and reads “0” data as data OUT.
  • the nonvolatile memory 11 further includes the AND circuit 41 connected to the gate electrode of the NMOS transistor 23.
  • the AND circuit 41 is the AND circuit 41.
  • the nonvolatile memory 11 grounds the current of the bit line BL from the fuse element 21 only to the memory cell 40 in which the selection signals input to the word line WL and the selection line CSL (read) are both “1”.
  • the current can be supplied to the terminal of the cutting power supply EFV set to a voltage, and the current consumed by the entire nonvolatile memory 11 can be reduced.
  • the non-volatile memory 11 causes the current of the bit line BL to flow from the fuse element 21 to the terminal of the cutting power supply EFV set to the ground voltage for one memory cell 40 from which data is read to read the data. Since no unnecessary current of the bit line BL is supplied to other memory cells 40 that are not output, the current consumed by the entire nonvolatile memory 11 can be reduced.
  • the nonvolatile memory 11 is not limited to a single memory cell 40 as a unit in which both selection signals input to the word line WL and the selection line CSL (read) are “1”. It is good.

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Abstract

This semiconductor device is provided with a fuse element (21), an NMOS transistor (22), an NMOS transistor (23), and an AND circuit (24), and stores data irreversibly and in a non-volatile manner. The fuse element (21) has one end connected to a terminal of a fuse-blowing power supply (EFV) capable of switching between a power supply voltage and a ground voltage, and stores data according to the electrical connection state of the wiring. The NMOS transistor (22) has a drain electrode connected to the other end of the fuse element (21) and controls current which flows from the terminal of the fuse-blowing power supply (EFV) to the fuse element (21). The NMOS transistor (23) has a drain electrode connected to the other end of the fuse element (21) in a manner which is parallel with respect to the NMOS transistor (22) and controls current which flows from the fuse element (21) to the terminal of the fuse-blowing power supply (EFV). The AND circuit is connected to the gate electrode of the NMOS transistor (22).

Description

[規則37.2に基づきISAが決定した発明の名称]　フューズ素子を備える半導体装置[Title of Invention Determined by ISA Based on Rule 37.2] Semiconductor Device with Fuse Element
　本発明は、データを不可逆かつ不揮発に記憶する半導体装置に関し、特に、配線の導通状態によりデータを記憶するフューズ素子を備える半導体装置に関する。 The present invention relates to a semiconductor device that stores data irreversibly and in a nonvolatile manner, and more particularly, to a semiconductor device that includes a fuse element that stores data according to a conductive state of wiring.
　半導体装置には、電源を供給しない状態であっても記憶したデータが消失することのない不揮発性メモリがある。当該不揮発性メモリには、ＥＥＰＲＯＭ（Electrically　Erasable　Programmable　Read　Only　Memory）などのさまざまな種類が開発されている。しかし、一つの半導体チップにシステムを集積したＳｏＣ（System　on　Chip）などに、ＥＥＰＲＯＭを利用する場合、フローティングゲートに電荷を蓄積する構成を同じ半導体チップ上に混載するため、追加マスクおよび追加プロセスが必要となり、製造コストが高価になる。 Semiconductor devices include a nonvolatile memory in which stored data is not lost even when power is not supplied. Various types of nonvolatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory) have been developed. However, when an EEPROM is used in a SoC (System on Chip) in which a system is integrated on one semiconductor chip, an additional mask and an additional process are required because the structure for storing charges in the floating gate is mixedly mounted on the same semiconductor chip. It becomes necessary and the manufacturing cost becomes expensive.
　そのため、追加マスクおよび追加プロセスを必要とせずに、同じ半導体チップ上に混載することが可能な不揮発性メモリとして、フューズ素子を備える不揮発性メモリがある。フューズ素子は、配線の導通状態によりデータを記憶することが可能な素子で、ポリシリコン配線あるいはメタル配線の電流溶断型のフューズ素子などである。 Therefore, there is a non-volatile memory including a fuse element as a non-volatile memory that can be embedded on the same semiconductor chip without requiring an additional mask and an additional process. The fuse element is an element capable of storing data depending on the conduction state of the wiring, and is a fuse element of a current blow type of a polysilicon wiring or a metal wiring.
　具体的に、特開２００８－７１８１９号公報（特許文献１）および特表２００６－５０９３１１号公報（特許文献２）には、表面がシリサイド化されたポリシリコン配線からなるフューズ素子を備える不揮発性メモリが開示してある。なお、フューズ素子を備える不揮発性メモリは、配線の導通状態を変化させてデータを書込むため、書込んだデータを消去することができない不可逆なメモリである。 Specifically, in Japanese Patent Application Laid-Open No. 2008-71819 (Patent Document 1) and Japanese Translation of PCT International Publication No. 2006-509911 (Patent Document 2), a nonvolatile memory including a fuse element made of a polysilicon wiring whose surface is silicided. Is disclosed. Note that a nonvolatile memory including a fuse element is an irreversible memory in which written data cannot be erased because data is written by changing the conduction state of the wiring.
　また、図１３は、従来のフューズ素子を備える不揮発性メモリの構成を示す概略図である。図１３に示す不揮発性メモリ１００は、フューズ素子を含むメモリセル２００をマトリックス状に複数配置してあるフューズアレイ１０１、フューズアレイ１０１のワード線ＷＬ（Word　Line）に選択信号を供給する行デコーダ（ＲＤ：Row　Decoder）１０２、フューズアレイ１０１のビット線ＢＬ（Bit　Line）を選択する列デコーダ（ＣＤ：Column　Decoder）１０３、行デコーダ１０２および列デコーダ１０３の動作を制御する制御回路１０４、参照抵抗および参照ワード線電圧を生成する参照値生成回路１０５を備えている。 FIG. 13 is a schematic view showing a configuration of a nonvolatile memory including a conventional fuse element. The nonvolatile memory 100 shown in FIG. 13 includes a fuse array 101 in which a plurality of memory cells 200 including fuse elements are arranged in a matrix, and a row decoder that supplies a selection signal to a word line WL (Word Line) of the fuse array 101. RD (Row Decoder) 102, column decoder (CD: Column Decoder) 103 for selecting a bit line BL (Bit Line) of fuse array 101, control circuit 104 for controlling operations of row decoder 102 and column decoder 103, reference resistance and A reference value generation circuit 105 that generates a reference word line voltage is provided.
　列デコーダ１０３を設けた側には、ビット線ＢＬの電圧を増幅するセンスアンプＳＡ（Sense　Amplifier）、およびデータの入出力を行なう入出力部Ｉ／Ｏ（Input/Output）も設けてある。なお、入出力部Ｉ／Ｏは、１６ビット単位でデータを入出力する。 On the side where the column decoder 103 is provided, a sense amplifier SA (Sense Amplifier) for amplifying the voltage of the bit line BL and an input / output unit I / O (Input / Output) for inputting and outputting data are also provided. The input / output unit I / O inputs and outputs data in units of 16 bits.
　図１４は、従来のフューズ素子を備える不揮発性メモリ１００のメモリセル２００の構成を示す概略図である。図１４に示すメモリセル２００は、配線の導通状態によりデータを記憶するフューズ素子２０１、フューズ素子２０１の一端にドレイン電極を接続するトランジスタ２０２を備えている。フューズ素子２０１は、ビット線ＢＬを他端に接続し、トランジスタ２０２は、ワード線ＷＬをゲート電極に接続してある。 FIG. 14 is a schematic diagram showing a configuration of a memory cell 200 of a nonvolatile memory 100 including a conventional fuse element. A memory cell 200 illustrated in FIG. 14 includes a fuse element 201 that stores data according to a conductive state of a wiring, and a transistor 202 that connects a drain electrode to one end of the fuse element 201. The fuse element 201 has the bit line BL connected to the other end, and the transistor 202 has the word line WL connected to the gate electrode.
　ビット線ＢＬは、行デコーダ１０２の選択回路３００を介して切断用電源ＥＦＶに接続してある。図１５は、従来のフューズ素子を備える不揮発性メモリ１００の選択回路３００の構成を示す概略図である。図１５に示す選択回路３００は、切断用電源ＥＦＶとビット線ＢＬとを接続するスイッチング素子３０１、選択信号の信号レベルを変換するレベル変換回路３０２、信号レベルを変換した選択信号の電圧を増幅してスイッチング素子３０１の制御信号を生成する増幅器３０３を備えている。なお、選択回路３００は、切断用電源ＥＦＶで駆動している。 The bit line BL is connected to the cutting power supply EFV via the selection circuit 300 of the row decoder 102. FIG. 15 is a schematic diagram illustrating a configuration of a selection circuit 300 of a nonvolatile memory 100 including a conventional fuse element. The selection circuit 300 shown in FIG. 15 amplifies the switching element 301 that connects the cutting power source EFV and the bit line BL, the level conversion circuit 302 that converts the signal level of the selection signal, and the voltage of the selection signal that has converted the signal level. And an amplifier 303 for generating a control signal for the switching element 301. The selection circuit 300 is driven by a cutting power source EFV.
　不揮発性メモリ１００は、データを書込むとき、データを書込む列のレベル変換回路３０２に選択信号を入力し、信号レベルを変換した選択信号の電圧を増幅器３０３で増幅して制御信号を生成する。不揮発性メモリ１００は、増幅器３０３で生成した制御信号によりスイッチング素子３０１を制御して、ビット線ＢＬと高電圧の切断用電源ＥＦＶとを接続する。不揮発性メモリ１００は、ビット線ＢＬと高電圧の切断用電源ＥＦＶとを接続した状態で、ワード線に選択信号を供給すると、図１４に示すトランジスタ２０２がオン状態となり、ビット線ＢＬを介して切断用電源ＥＦＶからフューズ素子２０１へ電流が流れ、フューズ素子２０１を切断して、データを書込む。 When writing data, the nonvolatile memory 100 inputs a selection signal to the level conversion circuit 302 of the column in which data is written, and amplifies the voltage of the selection signal converted from the signal level by the amplifier 303 to generate a control signal. . The nonvolatile memory 100 controls the switching element 301 by the control signal generated by the amplifier 303 to connect the bit line BL and the high-voltage cutting power supply EFV. In the nonvolatile memory 100, when a selection signal is supplied to the word line in a state where the bit line BL and the high-voltage cutting power supply EFV are connected, the transistor 202 shown in FIG. Current flows from cutting power supply EFV to fuse element 201, fuse element 201 is cut, and data is written.
　一方、不揮発性メモリ１００は、データを読出すとき、制御信号によりスイッチング素子３０１を制御して、ビット線ＢＬとコア電位の切断用電源ＥＦＶとを接続する。不揮発性メモリ１００は、ビット線ＢＬとコア電位の切断用電源ＥＦＶとを接続した状態で、コア電位の切断用電源ＥＦＶからフューズ素子２０１へ流れる電流により、センスアンプＳＡでフューズ素子２０１の配線の切断・未切断の状態を判定して、データを読出す。 On the other hand, when reading data, the nonvolatile memory 100 controls the switching element 301 by a control signal to connect the bit line BL and the power supply EFV for cutting the core potential. In the state where the bit line BL and the core potential cutting power source EFV are connected to each other, the nonvolatile memory 100 is connected to the fuse element 201 by the sense amplifier SA by the current flowing from the core potential cutting power source EFV to the fuse element 201. The data is read by determining the disconnected / uncut state.
特開２００８－７１８１９号公報JP 2008-71819 A 特表２００６－５０９３１１号公報JP-T-2006-509111
　しかし、不揮発性メモリ１００は、ビット線ＢＬと切断用電源ＥＦＶとの接続を選択回路３００で制御しているため、電源投入時、選択回路３００の誤動作により、列を選択する選択信号が不安定となり、誤ってビット線ＢＬと高電圧に設定された切断用電源ＥＦＶとが導通し、フューズ素子２０１を誤切断してしまうことがあった。 However, since the nonvolatile memory 100 controls the connection between the bit line BL and the cutting power supply EFV by the selection circuit 300, the selection signal for selecting a column is unstable due to a malfunction of the selection circuit 300 when the power is turned on. Thus, the bit line BL and the cutting power supply EFV set to a high voltage are inadvertently conducted, and the fuse element 201 may be erroneously cut.
　また、不揮発性メモリ１００は、データを読出すとき、フューズ素子２０１を誤って切断しないようにフューズ素子２０１に印加する電圧を書込み時に比べ低くする必要がある。しかし、不揮発性メモリ１００は、選択回路３００の駆動電源に切断用電源ＥＦＶを用いており、フューズ素子２０１に印加する電圧を誤動作しないよう低くするためにはスイッチング素子３０１の抵抗を大きくする必要がある。そのため、スイッチング素子３０１の抵抗が、フューズ素子２０１の抵抗よりも大きくなり、アレイ単位でフューズ素子の抵抗を測定する場合、スイッチング素子３０１の抵抗を測定することになり、アレイ単位でフューズ素子２１の抵抗を正確に測定することができない。 Further, when reading data, the nonvolatile memory 100 needs to lower the voltage applied to the fuse element 201 as compared with the time of writing so that the fuse element 201 is not accidentally disconnected. However, the non-volatile memory 100 uses the cutting power supply EFV as the driving power supply for the selection circuit 300, and it is necessary to increase the resistance of the switching element 301 in order to reduce the voltage applied to the fuse element 201 so as not to malfunction. is there. Therefore, when the resistance of the switching element 301 becomes larger than the resistance of the fuse element 201 and the resistance of the fuse element is measured in units of arrays, the resistance of the switching element 301 is measured. The resistance cannot be measured accurately.
　さらに、不揮発性メモリ１００は、ビット線ＢＬと切断用電源ＥＦＶとの接続を選択回路３００で制御しているため、フューズ素子２０１およびトランジスタ２０２のみで正確な信頼性を評価することができず、選択回路３００を含めた信頼性の評価を行なう必要があり、開発コストが高価になる。 Further, since the nonvolatile memory 100 controls the connection between the bit line BL and the cutting power supply EFV by the selection circuit 300, the reliability cannot be evaluated with only the fuse element 201 and the transistor 202. It is necessary to evaluate the reliability including the selection circuit 300, which increases the development cost.
　また、不揮発性メモリ１００は、データを書込むときも、データを読出すときも同じ経路でフューズ素子２０１に電流を流すため、データを読出すときフューズ素子２０１に与えるストレスの傾向と、データを書込むときフューズ素子２０１に与えるストレスの傾向とが同じになる。そのため、不揮発性メモリ１００は、データを読出す回数が増加するに従い、フューズ素子２０１に同じ傾向のストレスが蓄積され、動作が不良となることがあった。 In addition, since the nonvolatile memory 100 allows a current to flow through the fuse element 201 through the same path both when data is written and when data is read, the tendency of stress applied to the fuse element 201 when data is read, The tendency of stress applied to the fuse element 201 when writing is the same. Therefore, in the nonvolatile memory 100, as the number of times of reading data increases, the stress having the same tendency is accumulated in the fuse element 201, and the operation may become defective.
　そこで、本発明は、ビット線と切断用電源との接続を制御する選択回路を必要とせず、配線の導通状態によりデータを記憶するフューズ素子を備える半導体装置を提供することを目的とする。 Therefore, an object of the present invention is to provide a semiconductor device including a fuse element that stores data according to a conductive state of a wiring without requiring a selection circuit for controlling connection between a bit line and a power supply for cutting.
　上記課題を解決するために、本発明は、データを不可逆かつ不揮発に記憶する半導体装置であって、電源電圧と接地電圧とを切替え設定することが可能な電源端子に一端を接続し、配線の導通状態によりデータを記憶するフューズ素子と、フューズ素子の他端に一方の電流電極を接続し、電源端子からフューズ素子へ流す電流を制御する第１トランジスタと、第１トランジスタに対して並列に、フューズ素子の他端に一方の電流電極を接続し、フューズ素子から電源端子へ流す電流を制御する第２トランジスタと、第１トランジスタの制御電極に接続する第１論理回路とを備えている。データを書込むとき、第１論理回路は、第１論理回路に接続する第１ワード線および第１選択線の活性状態に応じて、第１トランジスタをオン状態にすることで、電源電圧の電源端子からフューズ素子へ電流を流してフューズ素子の配線を切断する。データを読出すとき、第２トランジスタは、第２トランジスタの制御電極に接続する第２ワード線の活性状態に応じて、オン状態となり、第２トランジスタの他方の電流電極に接続するビット線の電流を、フューズ素子から接地電圧の電源端子へ流す。 In order to solve the above problems, the present invention is a semiconductor device that stores data in an irreversible and non-volatile manner, and has one end connected to a power supply terminal capable of switching between a power supply voltage and a ground voltage, A fuse element that stores data according to a conductive state, one current electrode connected to the other end of the fuse element, a first transistor that controls a current flowing from the power supply terminal to the fuse element, and a first transistor in parallel, One current electrode is connected to the other end of the fuse element, a second transistor for controlling the current flowing from the fuse element to the power supply terminal, and a first logic circuit connected to the control electrode of the first transistor are provided. When writing data, the first logic circuit turns on the first transistor in accordance with the active state of the first word line and the first selection line connected to the first logic circuit, thereby supplying the power supply voltage. A current is passed from the terminal to the fuse element to cut the fuse element wiring. When reading data, the second transistor is turned on according to the active state of the second word line connected to the control electrode of the second transistor, and the current of the bit line connected to the other current electrode of the second transistor. From the fuse element to the power terminal of the ground voltage.
　本発明に係る半導体装置によれば、電源端子に一端が接続されたフューズ素子の他端に接続し、電源端子からフューズ素子へ流す電流を制御する第１トランジスタと、フューズ素子の他端に接続し、フューズ素子から電源端子へ流す電流を制御する第２トランジスタと、第１トランジスタの制御電極に接続する第１論理回路とを備えることで、フューズ切断時に電源電圧となる電源端子からフューズ素子へ電流を供給するために、ビット線と電源端子との接続を制御する選択回路を備える必要がない。本発明に係る半導体装置は、選択回路を備える必要がないので、電源投入時、この選択回路の誤動作により、フューズ素子を誤切断することがない。また、本発明に係る半導体装置は、フューズ素子の切断時に電源電圧となる電源で駆動する選択回路を備える必要がないので、データの読出し時にフューズ素子に印加する電圧を低くするために選択回路のスイッチング素子の抵抗を大きくする必要がなく、アレイ単位でフューズ素子の抵抗を正確に測定することができる。さらに、本発明に係る半導体装置は、選択回路を備える必要がないので、フューズ素子およびトランジスタのみで正確な信頼性を評価することができ、開発コストを安価にすることができる。また、本発明に係る半導体装置は、データを書込むとき第１トランジスタを介する経路を、データを読出すとき第２トランジスタを介する経路をそれぞれ用いるので、データを書込むときと、データを読出すときとで異なる経路でフューズ素子に電流を流すことができる。そのため、本発明に係る半導体装置は、フューズ素子に与えるストレスを減らして、データの読出し回数をより多く、または制限することなく安定して動作することができる。 According to the semiconductor device of the present invention, the first transistor is connected to the other end of the fuse element whose one end is connected to the power supply terminal, and is connected to the other end of the fuse element. In addition, since the second transistor for controlling the current flowing from the fuse element to the power supply terminal and the first logic circuit connected to the control electrode of the first transistor are provided, the power supply terminal that becomes the power supply voltage when the fuse is cut from the fuse element. In order to supply the current, there is no need to provide a selection circuit for controlling the connection between the bit line and the power supply terminal. Since the semiconductor device according to the present invention does not need to include a selection circuit, the fuse element is not erroneously cut by malfunction of the selection circuit when the power is turned on. In addition, since the semiconductor device according to the present invention does not need to include a selection circuit that is driven by a power source that becomes a power supply voltage when the fuse element is cut, the selection circuit is configured to reduce the voltage applied to the fuse element when reading data. There is no need to increase the resistance of the switching element, and the resistance of the fuse element can be accurately measured in array units. Furthermore, since the semiconductor device according to the present invention does not need to include a selection circuit, accurate reliability can be evaluated using only the fuse element and the transistor, and the development cost can be reduced. The semiconductor device according to the present invention uses a path through the first transistor when writing data and a path through the second transistor when reading data, so that data is read when data is written. Current can be passed through the fuse element through different paths. Therefore, the semiconductor device according to the present invention can operate stably without reducing the stress applied to the fuse element and increasing or limiting the number of times of reading data.
本発明の実施の形態１に係る不揮発性メモリの構成を示す概略図である。It is the schematic which shows the structure of the non-volatile memory which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係るメモリセルの構成を示す概略図である。1 is a schematic diagram showing a configuration of a memory cell according to a first embodiment of the present invention. 本発明の実施の形態１に係るメモリセルにデータを書込むときの動作を説明するための概略図である。FIG. 6 is a schematic diagram for explaining an operation when data is written to a memory cell according to the first embodiment of the present invention. 本発明の実施の形態１に係るメモリセルにデータを書込むときの信号のタイミングチャートである。3 is a timing chart of signals when data is written to the memory cell according to the first embodiment of the present invention. 本発明の実施の形態１に係るメモリセルからデータを読出すときの動作を説明するための概略図である。FIG. 7 is a schematic diagram for explaining an operation when data is read from the memory cell according to the first embodiment of the present invention. 本発明の実施の形態１に係るメモリセルからデータを読出す場合に、読出しデータの判定を行なう判定回路の構成を示す概略図である。FIG. 3 is a schematic diagram showing a configuration of a determination circuit that determines read data when data is read from the memory cell according to the first embodiment of the present invention; 本発明の実施の形態１に係るメモリセルからデータを読出すときの信号のタイミングチャートである。4 is a timing chart of signals when data is read from the memory cell according to the first embodiment of the present invention. 本発明の実施の形態２に係る不揮発性メモリの構成を示す概略図である。It is the schematic which shows the structure of the non-volatile memory which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係るメモリセルの構成を示す概略図である。It is the schematic which shows the structure of the memory cell which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係るメモリセルにデータを書込むときの動作を説明するための概略図である。It is the schematic for demonstrating operation | movement when writing data in the memory cell which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係るメモリセルからデータを読出すときの動作を説明するための概略図である。FIG. 10 is a schematic diagram for explaining an operation when data is read from a memory cell according to a second embodiment of the present invention. 本発明の実施の形態２に係るメモリセルからデータを読出すときの信号のタイミングチャートである。6 is a timing chart of signals when data is read from a memory cell according to a second embodiment of the present invention. 従来のフューズ素子を備える不揮発性メモリの構成を示す概略図である。It is the schematic which shows the structure of the non-volatile memory provided with the conventional fuse element. 従来のフューズ素子を備える不揮発性メモリのメモリセルの構成を示す概略図である。It is the schematic which shows the structure of the memory cell of a non-volatile memory provided with the conventional fuse element. 従来のフューズ素子を備える不揮発性メモリの選択回路の構成を示す概略図である。It is the schematic which shows the structure of the selection circuit of a non-volatile memory provided with the conventional fuse element.
　以下、本発明に係る実施の形態について図面を参照して説明する。
　　（実施の形態１）
　図１は、本発明の実施の形態１に係る不揮発性メモリの構成を示す概略図である。図１に示す不揮発性メモリ１０は、データを不可逆かつ不揮発に記憶する半導体装置である。不揮発性メモリ１０は、フューズ素子を含むメモリセル２０をマトリックス状に複数配置してあるフューズアレイ１、フューズアレイ１のワード線ＷＬに選択信号を供給する行デコーダ（ＲＤ）２、フューズアレイ１のビット線ＢＬを選択する列デコーダ（ＣＤ）３、行デコーダ２および列デコーダ３の動作を制御する制御回路４、参照抵抗および参照ワード線電圧を生成する参照値生成回路５を備えている。 Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a schematic diagram showing a configuration of a nonvolatile memory according to Embodiment 1 of the present invention. A nonvolatile memory 10 shown in FIG. 1 is a semiconductor device that stores data in an irreversible and nonvolatile manner. The nonvolatile memory 10 includes a fuse array 1 in which a plurality of memory cells 20 including fuse elements are arranged in a matrix, a row decoder (RD) 2 that supplies a selection signal to the word lines WL of the fuse array 1, A column decoder (CD) 3 that selects a bit line BL, a control circuit 4 that controls operations of the row decoder 2 and the column decoder 3, and a reference value generation circuit 5 that generates a reference resistor and a reference word line voltage are provided.
　フューズアレイ１は、一行のメモリセル２０に対して２本のワード線ＷＬを有している。２本のワード線ＷＬは、メモリセル２０にデータを書込むとき（プログラム時（prog））に用いる第１ワード線のワード線ＷＬ（prog）と、メモリセル２０からデータを読出すとき（リード時（Read））に用いる第２ワード線のワード線ＷＬ（Read）とで構成されている。また、フューズアレイ１は、一列のメモリセル２０に対して１本のビット線ＢＬと、１本の選択線ＣＳＬ（Column　Select　Line）とを有している。 The fuse array 1 has two word lines WL for one row of memory cells 20. The two word lines WL are the first word line WL (prog) used when writing data to the memory cell 20 (when programming (prog)), and when reading data from the memory cell 20 (reading). And the word line WL (Read) of the second word line used at the time (Read). The fuse array 1 has one bit line BL and one select line CSL (Column Select Line) for one column of memory cells 20.
　行デコーダ２は、メモリセル２０にデータを書込むとき、ワード線ＷＬ（prog）に選択信号を供給し、メモリセル２０からデータを読出すとき、ワード線ＷＬ（Read）に選択信号を供給する。 The row decoder 2 supplies a selection signal to the word line WL (prog) when writing data to the memory cell 20, and supplies a selection signal to the word line WL (Read) when reading data from the memory cell 20. .
　列デコーダ３は、メモリセル２０にデータを書込むとき、選択線ＣＳＬに選択信号を供給し、メモリセル２０からデータを読出すとき、ビット線ＢＬからデータを読出す。列デコーダ３を設けてある側には、ビット線ＢＬの電圧を増幅するセンスアンプＳＡ、およびデータの入出力を行なう入出力部Ｉ／Ｏも設けてある。ビット線ＢＬの電圧は、センスアンプＳＡで増幅することで、データとして読み出すことができる。なお、入出力部Ｉ／Ｏは、１６ビット単位でデータを入出力する。また、列デコーダ３は、メモリセル２０にデータを書込むとき、３２ビットのアドレスでデコードする。 The column decoder 3 supplies a selection signal to the selection line CSL when writing data to the memory cell 20, and reads data from the bit line BL when reading data from the memory cell 20. On the side where the column decoder 3 is provided, a sense amplifier SA for amplifying the voltage of the bit line BL and an input / output unit I / O for inputting / outputting data are also provided. The voltage of the bit line BL can be read as data by being amplified by the sense amplifier SA. The input / output unit I / O inputs and outputs data in units of 16 bits. Further, the column decoder 3 decodes with a 32-bit address when writing data into the memory cell 20.
　図２は、本発明の実施の形態１に係るメモリセル２０の構成を示す概略図である。図２に示すメモリセル２０は、切断用電源ＥＦＶの端子に一端を接続し、配線の導通状態によりデータを記憶するフューズ素子２１、フューズ素子２１の他端にドレイン電極を接続するＮチャネルＭＯＳ（ＮＭＯＳ）トランジスタ２２，２３、ＮＭＯＳトランジスタ２２のゲート電極に接続するＡＮＤ回路２４を備えている。 FIG. 2 is a schematic diagram showing the configuration of the memory cell 20 according to the first embodiment of the present invention. The memory cell 20 shown in FIG. 2 has one end connected to the terminal of the power supply EFV for cutting and an N-channel MOS (with a drain electrode connected to the other end of the fuse element 21 for storing data depending on the conductive state of the wiring. NMOS) transistors 22 and 23, and an AND circuit 24 connected to the gate electrode of the NMOS transistor 22.
　フューズ素子２１は、ポリシリコン配線、またはメタル配線で構成され、当該配線に大きな電流を流して切断することで抵抗値を変化させて、データを記憶する記憶素子である。なお、フューズ素子２１は、配線を物理的に切断する場合に限定されるものではなく、配線の形状または材料の分布といった配線の構造を変化させて、配線の導通状態（たとえば抵抗値）を変化させることができればよい。また、ポリシリコン配線は、チタン（Ｔｉ）、コバルト（Ｃｏ）、または、ニッケル（Ｎｉ）などの金属と反応させたシリサイド層を表面に形成してもよい。 The fuse element 21 is a storage element that is configured by a polysilicon wiring or a metal wiring, stores data by changing a resistance value by passing a large current through the wiring and cutting it. The fuse element 21 is not limited to the case where the wiring is physically cut, but changes the wiring structure such as the shape of the wiring or the material distribution to change the conductive state (for example, resistance value) of the wiring. It only has to be made. Further, the polysilicon wiring may be formed on the surface with a silicide layer reacted with a metal such as titanium (Ti), cobalt (Co), or nickel (Ni).
　ＮＭＯＳトランジスタ（第１トランジスタ）２２は、切断用電源ＥＦＶの端子からフューズ素子２１へ流す電流を制御する。ＮＭＯＳトランジスタ２２は、フューズ素子２１の配線を切断するために大きな電流を流す必要があるため、ＮＭＯＳトランジスタ２３に比べてトランジスタサイズを大きくしてある。なお、ＮＭＯＳトランジスタ２３のトランジスタサイズを、ＮＭＯＳトランジスタ２２のトランジスタサイズに比べて小さくしてあるので、ＮＭＯＳトランジスタ２３のトランジスタサイズと、ＮＭＯＳトランジスタ２２のトランジスタサイズとを同じサイズにした場合に比べて、不揮発性メモリ１０を小型化することができる。 The NMOS transistor (first transistor) 22 controls the current that flows from the terminal of the cutting power supply EFV to the fuse element 21. The NMOS transistor 22 has a larger transistor size than the NMOS transistor 23 because a large current needs to flow in order to cut the wiring of the fuse element 21. Since the transistor size of the NMOS transistor 23 is smaller than the transistor size of the NMOS transistor 22, compared to the case where the transistor size of the NMOS transistor 23 and the transistor size of the NMOS transistor 22 are the same size, The nonvolatile memory 10 can be reduced in size.
　ＮＭＯＳトランジスタ（第２トランジスタ）２３は、ＮＭＯＳトランジスタ２２に対して並列に接続してあり、フューズ素子２１から切断用電源ＥＦＶの端子へ流す電流を制御する。ＮＭＯＳトランジスタ２３は、ワード線ＷＬ（Read）に選択信号が供給されるとオン状態となり、フューズ素子２１の配線の導通状態を検知するために、電流をフューズ素子２１から接地電圧に設定された切断用電源ＥＦＶの端子へ流す。 The NMOS transistor (second transistor) 23 is connected in parallel to the NMOS transistor 22 and controls the current flowing from the fuse element 21 to the terminal of the cutting power supply EFV. The NMOS transistor 23 is turned on when a selection signal is supplied to the word line WL (Read), and the current is disconnected from the fuse element 21 to the ground voltage in order to detect the conduction state of the fuse element 21. Flow to the terminal of the power supply EFV.
　ＡＮＤ回路（第１論理回路）２４は、入力側にワード線ＷＬ（prog）および選択線ＣＳＬを、出力側にＮＭＯＳトランジスタ２２のゲート電極をそれぞれ接続してある。ＡＮＤ回路２４は、ワード線ＷＬ（prog）および選択線ＣＳＬに入力する選択信号がともに“１”の場合、ＮＭＯＳトランジスタ２２のゲート電極に出力する信号が“１”となる。ＮＭＯＳトランジスタ２２は、ゲート電極に“１”の信号が供給されるとオン状態となり、フューズ素子２１の配線を切断するために、大きな電流を電源電圧に設定された切断用電源ＥＦＶの端子からフューズ素子２１へ流す。 The AND circuit (first logic circuit) 24 has a word line WL (prog) and a selection line CSL connected to the input side, and a gate electrode of the NMOS transistor 22 connected to the output side. In the AND circuit 24, when both the selection signals input to the word line WL (prog) and the selection line CSL are “1”, the signal output to the gate electrode of the NMOS transistor 22 is “1”. The NMOS transistor 22 is turned on when a signal of “1” is supplied to the gate electrode, and in order to cut the wiring of the fuse element 21, a large current is fused from the terminal of the cutting power supply EFV set to the power supply voltage. Flow to element 21.
　次に、不揮発性メモリ１０の動作について説明する。不揮発性メモリ１０の動作は、メモリセル２０にデータを書込むときと、メモリセル２０からデータを読出すときとに分けて説明する。 Next, the operation of the nonvolatile memory 10 will be described. The operation of the nonvolatile memory 10 will be described separately when data is written to the memory cell 20 and when data is read from the memory cell 20.
　まず、図３は、本発明の実施の形態１に係るメモリセル２０にデータを書込むときの動作を説明するための概略図である。ここで、メモリセル２０に記憶させるデータは、“０”または“１”の値を有するものとし、フューズ素子２１は、配線を切断しない場合“０”のデータを、配線を切断する場合“１”のデータをそれぞれ記憶するものとする。故に、実質的に“１”のデータを書込むことしかできず、“０”データを記憶させることは、“１”のデータを書込まないことと等価である。そのため、メモリセル２０にデータを書込むことを、データを不揮発性メモリ１０にプログラムするともいう。本実施の形態１では、フューズ素子２１の配線を切断する場合を、データを書込むと表現して以下説明する。 First, FIG. 3 is a schematic diagram for explaining an operation when data is written in the memory cell 20 according to the first embodiment of the present invention. Here, the data stored in the memory cell 20 has a value of “0” or “1”, and the fuse element 21 uses “0” data when the wiring is not cut, and “1” when the wiring is cut. ”Is stored. Therefore, data of “1” can only be substantially written, and storing “0” data is equivalent to not writing data of “1”. Therefore, writing data into the memory cell 20 is also referred to as programming data into the nonvolatile memory 10. In the first embodiment, the case where the wiring of the fuse element 21 is cut will be described as data writing and will be described below.
　図３に示すメモリセル２０は、ＡＮＤ回路２４が、ＡＮＤ回路２４に接続するワード線ＷＬ（prog）および選択線ＣＳＬの活性状態に応じて、ＮＭＯＳトランジスタ２２をオン状態にする。ＮＭＯＳトランジスタ２２をオン状態にする動作を、タイミングチャートを用いて説明する。図４は、本発明の実施の形態１に係るメモリセル２０にデータを書込むときの信号のタイミングチャートである。図４に示すタイミングチャートでは、選択線ＣＳＬに入力する選択信号が“１”（選択線ＣＳＬが活性）となり、その後、ワード線ＷＬ（prog）に入力する選択信号が“１”（ワード線ＷＬ（prog）が活性）となることで、メモリセル２０は、ＮＭＯＳトランジスタ２２をオン状態にする。なお、切断用電源ＥＦＶの端子には、メモリセル２０にデータを書込むとき、フューズ素子２１の配線を切断するための大きな電流を流すことができる程度の高い電圧を有する電源電圧を供給できるように設定しておくものとする。具体的に、切断用電源ＥＦＶの端子は、図示していないパッドを含み、かつ不揮発性メモリ１０の外部から電源電圧か接地電圧かに設定することが可能な構成にしてある。 In the memory cell 20 shown in FIG. 3, the AND circuit 24 turns on the NMOS transistor 22 in accordance with the active state of the word line WL (prog) connected to the AND circuit 24 and the selection line CSL. An operation for turning on the NMOS transistor 22 will be described with reference to a timing chart. FIG. 4 is a timing chart of signals when data is written to memory cell 20 according to the first embodiment of the present invention. In the timing chart shown in FIG. 4, the selection signal input to the selection line CSL is “1” (selection line CSL is active), and then the selection signal input to the word line WL (prog) is “1” (word line WL). (Prog) becomes active), the memory cell 20 turns on the NMOS transistor 22. Note that a power supply voltage having a voltage high enough to flow a large current for cutting the wiring of the fuse element 21 when data is written to the memory cell 20 can be supplied to the terminal of the cutting power supply EFV. Shall be set to Specifically, the terminal of the cutting power supply EFV includes a pad (not shown), and can be set to the power supply voltage or the ground voltage from the outside of the nonvolatile memory 10.
　メモリセル２０は、ＮＭＯＳトランジスタ２２をオン状態にすることで、電源電圧に設定された切断用電源ＥＦＶの端子からフューズ素子２１へ矢印Ａで示す方向に電流を流してフューズ素子２１の配線を切断する。メモリセル２０は、フューズ素子２１の配線を切断することで、“１”のデータをフューズ素子２１に記憶する。なお、図３に示すメモリセル２０では、データを書込むときに動作していない部分を破線で示してある。 The memory cell 20 turns on the NMOS transistor 22 to cut the wiring of the fuse element 21 by causing a current to flow from the terminal of the cutting power supply EFV set to the power supply voltage to the fuse element 21 in the direction indicated by the arrow A. To do. The memory cell 20 stores the data “1” in the fuse element 21 by cutting the wiring of the fuse element 21. In the memory cell 20 shown in FIG. 3, a portion not operating when data is written is indicated by a broken line.
　次に、図５は、本発明の実施の形態１に係るメモリセル２０からデータを読出すときの動作を説明するための概略図である。図５に示すメモリセル２０は、ＮＭＯＳトランジスタ２３のゲート電極に接続するワード線ＷＬ（Read）の活性状態に応じて、ＮＭＯＳトランジスタ２３をオン状態にする。なお、切断用電源ＥＦＶの端子には、メモリセル２０からデータを読出すとき、接地電圧となるように設定しておくものとする。 Next, FIG. 5 is a schematic diagram for explaining an operation when data is read from the memory cell 20 according to the first embodiment of the present invention. The memory cell 20 shown in FIG. 5 turns on the NMOS transistor 23 in accordance with the active state of the word line WL (Read) connected to the gate electrode of the NMOS transistor 23. It is assumed that the terminal of cutting power supply EFV is set to be a ground voltage when data is read from memory cell 20.
　メモリセル２０は、ＮＭＯＳトランジスタ２３をオン状態にすることで、ＮＭＯＳトランジスタ２３のソース電極に接続するビット線ＢＬの電流を、フューズ素子２１から接地電圧に設定された切断用電源ＥＦＶの端子へ矢印Ｂで示す方向に流す。不揮発性メモリ１０は、フューズ素子２１の配線の導通状態により変化するビット線ＢＬの電圧を、判定回路３０で判定することによりメモリセル２０からデータを読出すことができる。なお、図５に示すメモリセル２０では、データを読出すときに動作していない部分を破線で示してある。 The memory cell 20 turns on the NMOS transistor 23 so that the current of the bit line BL connected to the source electrode of the NMOS transistor 23 is transferred from the fuse element 21 to the terminal of the cutting power supply EFV set to the ground voltage. Flow in the direction indicated by B. The nonvolatile memory 10 can read data from the memory cell 20 by determining the voltage of the bit line BL that changes depending on the conduction state of the wiring of the fuse element 21 by the determination circuit 30. In the memory cell 20 shown in FIG. 5, a portion not operating when data is read is indicated by a broken line.
　図６は、本発明の実施の形態１に係るメモリセル２０からデータを読出す場合に、読出しデータの判定を行なう判定回路３０の構成を示す概略図である。図６に示す判定回路３０は、コア電源の端子とビット線ＢＬとを接続するスイッチング素子３１、ビット線ＢＬに接続してあるセンスアンプＳＡを備えている。このセンスアンプＳＡは、図１にも図示されている。コア電源の端子は、切断用電源ＥＦＶの端子と異なり、データを読出すときにビット線ＢＬに電流を与える電源端子である。なお、データを書込むとき、切断用電源ＥＦＶの端子に与えられる電源電圧は、データを読出すとき、コア電源の端子に与えられる電源電圧より高い。 FIG. 6 is a schematic diagram showing a configuration of a determination circuit 30 that performs determination of read data when data is read from the memory cell 20 according to the first embodiment of the present invention. The determination circuit 30 shown in FIG. 6 includes a switching element 31 that connects a core power supply terminal and a bit line BL, and a sense amplifier SA that is connected to the bit line BL. This sense amplifier SA is also shown in FIG. The terminal of the core power supply is a power supply terminal for supplying a current to the bit line BL when data is read, unlike the terminal of the cutting power supply EFV. Note that when data is written, the power supply voltage applied to the terminal of cutting power supply EFV is higher than the power supply voltage applied to the core power supply terminal when data is read.
　スイッチング素子３１は、入力信号／ＲＤ＿Ｅｎａｂｌｅに応じて、コア電源の端子とビット線ＢＬとを接続するか否かを制御している。具体的に、スイッチング素子３１は、入力信号／ＲＤ＿Ｅｎａｂｌｅが“０”の場合、コア電源の端子とビット線ＢＬとを接続し、入力信号／ＲＤ＿Ｅｎａｂｌｅが“１”の場合、コア電源の端子とビット線ＢＬとを接続しない。コア電源の端子とビット線ＢＬとを接続しない。ここで、コア電源は、メモリセル２０からデータを読出すときに、ビット線ＢＬに電流を供給するための電源電圧を与えるための電源であり、この電源電圧は、一般的にフューズ素子２１を切断するときに切断用電源ＥＦＶにより与えられる電源電圧より低い。また、コア電源は、図１に示される不揮発性メモリ１０に全体の動作電源として使用されることが多い。 The switching element 31 controls whether or not to connect the core power supply terminal and the bit line BL in accordance with the input signal / RD_Enable. Specifically, the switching element 31 connects the core power supply terminal and the bit line BL when the input signal / RD_Enable is “0”, and connects the core power supply terminal and bit when the input signal / RD_Enable is “1”. Do not connect to line BL. The core power supply terminal and the bit line BL are not connected. Here, the core power supply is a power supply for supplying a power supply voltage for supplying a current to the bit line BL when data is read from the memory cell 20, and this power supply voltage generally supplies the fuse element 21 with power. It is lower than the power supply voltage given by the cutting power supply EFV when cutting. Further, the core power supply is often used as the entire operation power supply in the nonvolatile memory 10 shown in FIG.
　センスアンプＳＡは、スイッチング素子３１でコア電源の端子とビット線ＢＬとを接続した場合に、ビット線ＢＬの電圧を増幅し、増幅した電圧が所定のレベル以上か否かに応じて判定した結果を、データＯＵＴとして読出す。 The sense amplifier SA amplifies the voltage of the bit line BL when the terminal of the core power supply and the bit line BL are connected by the switching element 31, and the determination result is based on whether the amplified voltage is equal to or higher than a predetermined level. Is read as data OUT.
　メモリセル２０からデータを読出す動作を、タイミングチャートを用いて説明する。図７は、本発明の実施の形態１に係るメモリセル２０からデータを読出すときの信号のタイミングチャートである。図７に示すタイミングチャートでは、コア電源の端子とビット線ＢＬとを接続してビット線ＢＬに電流を流すために、ｔ時間、“０”の入力信号／ＲＤ＿Ｅｎａｂｌｅを入力してスイッチング素子３１をオン状態にする。スイッチング素子３１をオン状態にすると、ビット線ＢＬに電流が流れ、ビット線ＢＬの電圧が０ＶからａＶへ変化する。 The operation of reading data from the memory cell 20 will be described using a timing chart. FIG. 7 is a timing chart of signals when data is read from memory cell 20 according to the first embodiment of the present invention. In the timing chart shown in FIG. 7, in order to connect the core power supply terminal and the bit line BL and to cause a current to flow through the bit line BL, the input signal / RD_Enable of “0” is input and the switching element 31 is turned on for t time. Turn on. When the switching element 31 is turned on, a current flows through the bit line BL, and the voltage of the bit line BL changes from 0V to aV.
　その後、ワード線ＷＬ（read）に入力する選択信号が“１”（ワード線ＷＬ（read）が活性）となることで、ＮＭＯＳトランジスタ２３がオン状態となり、ビット線ＢＬの電流を、フューズ素子２１から接地電圧に設定された切断用電源ＥＦＶの端子へ流す。フューズ素子２１の配線が切断されている場合、ビット線ＢＬの電流はフューズ素子２１を介して接地電圧に設定された切断用電源ＥＦＶの端子へ流れることはないので、ビット線ＢＬの電圧はａＶから変化しない。一方、フューズ素子２１の配線が切断されていない（未切断）場合、ビット線ＢＬの電流はフューズ素子２１を介して接地電圧に設定された切断用電源ＥＦＶの端子へ流れるので、ビット線ＢＬの電圧はａＶから０Ｖへと変化する。 Thereafter, when the selection signal input to the word line WL (read) becomes “1” (the word line WL (read) is activated), the NMOS transistor 23 is turned on, and the current of the bit line BL is changed to the fuse element 21. To the terminal of the cutting power supply EFV set to the ground voltage. When the wiring of the fuse element 21 is cut, the current of the bit line BL does not flow to the terminal of the cutting power supply EFV set to the ground voltage via the fuse element 21, so that the voltage of the bit line BL is aV Does not change. On the other hand, when the wiring of the fuse element 21 is not cut (uncut), the current of the bit line BL flows to the terminal of the cutting power supply EFV set to the ground voltage via the fuse element 21, so that the bit line BL The voltage changes from aV to 0V.
　次に、センスアンプＳＡを駆動させる信号“１”がセンスアンプＳＡに入力されると、センスアンプＳＡは、ビット線ＢＬの電圧を増幅し、増幅した電圧が所定のレベル以上か否かを判定する。センスアンプＳＡは、増幅した電圧が所定のレベル以上の場合、フューズ素子２１の配線が切断されていると判定して、“１”のデータをデータＯＵＴとして読出す。一方、センスアンプＳＡは、増幅した電圧が所定のレベル未満の場合、フューズ素子２１の配線が切断されていない（未切断）と判定して、“０”のデータをデータＯＵＴとして読出す。 Next, when a signal “1” for driving the sense amplifier SA is input to the sense amplifier SA, the sense amplifier SA amplifies the voltage of the bit line BL and determines whether the amplified voltage is equal to or higher than a predetermined level. To do. When the amplified voltage is equal to or higher than a predetermined level, the sense amplifier SA determines that the wiring of the fuse element 21 is disconnected and reads “1” data as data OUT. On the other hand, when the amplified voltage is lower than a predetermined level, the sense amplifier SA determines that the wiring of the fuse element 21 is not cut (not cut), and reads “0” data as data OUT.
　以上のように、本発明の実施の形態１に係る不揮発性メモリ１０は、切断用電源ＥＦＶの端子に一端が接続されたフューズ素子２１の他端に接続し、切断用電源ＥＦＶの端子からフューズ素子２１へ流す電流を制御するＮＭＯＳトランジスタ２２と、フューズ素子２１の他端に接続し、フューズ素子２１から切断用電源ＥＦＶの端子へ流す電流を制御するＮＭＯＳトランジスタ２３と、ＮＭＯＳトランジスタ２２のゲート電極に接続するＡＮＤ回路２４とを備える。そのため、不揮発性メモリ１０は、フューズ切断時に電源電圧となる切断用電源ＥＦＶからフューズ素子２１へ電流を供給するために、ビット線ＢＬと切断用電源ＥＦＶの端子との接続を制御する選択回路を備える必要がない。不揮発性メモリ１０は、選択回路を備える必要がないので、電源投入時、この選択回路の誤動作により、フューズ素子２１を誤切断することがない。 As described above, the nonvolatile memory 10 according to Embodiment 1 of the present invention is connected to the other end of the fuse element 21 whose one end is connected to the terminal of the cutting power supply EFV, and from the terminal of the cutting power supply EFV to the fuse. An NMOS transistor 22 that controls the current that flows to the element 21, an NMOS transistor 23 that is connected to the other end of the fuse element 21, controls the current that flows from the fuse element 21 to the terminal of the cutting power supply EFV, and the gate electrode of the NMOS transistor 22 AND circuit 24 connected to. Therefore, the non-volatile memory 10 includes a selection circuit that controls the connection between the bit line BL and the terminal of the cutting power supply EFV in order to supply a current from the cutting power supply EFV that becomes a power supply voltage at the time of fuse cutting to the fuse element 21. There is no need to prepare. Since the nonvolatile memory 10 does not need to include a selection circuit, the fuse element 21 is not erroneously disconnected due to a malfunction of the selection circuit when the power is turned on.
　不揮発性メモリ１０は、フューズ素子２１の配線を切断するとき以外、切断用電源ＥＦＶの端子を接地電圧に設定してあるので、制御信号が電源投入時に不定となって、ＮＭＯＳトランジスタ２２がオン状態になってもフューズ素子２１間に電位差が生じないため、フューズ素子２１を誤切断することがない。なお、不揮発性メモリ１０は、データの書込みを、通常、出荷テスト時にのみ行なうので、市場で使用されるときも、切断用電源ＥＦＶの端子が接地電圧に設定される。 In the non-volatile memory 10, the terminal of the power supply EFV for cutting is set to the ground voltage except when the wiring of the fuse element 21 is cut. Therefore, the control signal becomes indefinite when the power is turned on, and the NMOS transistor 22 is turned on. In this case, since no potential difference is generated between the fuse elements 21, the fuse element 21 is not erroneously cut. Since nonvolatile memory 10 normally writes data only at the time of a shipping test, the terminal of cutting power supply EFV is set to the ground voltage even when used in the market.
　また、不揮発性メモリ１０は、切断用電源ＥＦＶで駆動する選択回路を備える必要がないので、フューズ素子２１の評価時にフューズ素子２１に印加する電圧を低くするために選択回路のスイッチング素子の抵抗を大きくする必要がなく、アレイ単位でフューズ素子２１の抵抗を正確に測定することができる。なお、不揮発性メモリ１０は、アレイ単位でフューズ素子２１の抵抗を正確に測定することができるので、出荷テスト時にフューズ素子２１の良品・不用品の判定だけではなく、フューズ素子２１の配線を切断するときのマージンもテストすることが可能となり、製品のテスト品質が向上する。 In addition, since the nonvolatile memory 10 does not need to include a selection circuit that is driven by the cutting power supply EFV, the resistance of the switching element of the selection circuit is reduced in order to reduce the voltage applied to the fuse element 21 when the fuse element 21 is evaluated. There is no need to increase the resistance, and the resistance of the fuse element 21 can be accurately measured in array units. Since the nonvolatile memory 10 can accurately measure the resistance of the fuse element 21 in units of arrays, the wiring of the fuse element 21 is disconnected in addition to determining whether the fuse element 21 is good or not at the time of a shipment test. It is also possible to test the margin when doing so, improving the test quality of the product.
　さらに、不揮発性メモリ１０は、選択回路を備える必要がないので、フューズ素子２１およびＮＭＯＳトランジスタ２２，２３のみで正確な信頼性を評価することができ、開発コストを安価にすることができる。 Furthermore, since the nonvolatile memory 10 does not need to include a selection circuit, accurate reliability can be evaluated only with the fuse element 21 and the NMOS transistors 22 and 23, and the development cost can be reduced.
　また、不揮発性メモリ１０は、データを書込むときＮＯＭＳトランジスタ２２を介する経路を、データを読出すときＮＯＭＳトランジスタ２３を介する経路をそれぞれ用いるので、データを書込むときと、データを読出すときとで異なる経路でフューズ素子２１に電流を流すことができる。そのため、不揮発性メモリ１０は、フューズ素子２１に与えるストレスを減らして、データの読出し回数をより多く、または制限することなく安定して動作することができる。 Since the nonvolatile memory 10 uses a path through the NOMS transistor 22 when writing data and a path through the NOMS transistor 23 when reading data, the nonvolatile memory 10 writes data and reads data. Thus, current can be passed through the fuse element 21 through different paths. Therefore, the nonvolatile memory 10 can operate stably without reducing the stress applied to the fuse element 21 and without increasing or limiting the number of times of reading data.
　さらに、不揮発性メモリ１０は、フューズ素子２１とビット線ＢＬとの間にＮＯＭＳトランジスタ２３を設けてあるので、ワード線ＷＬ（read）が活性しているメモリセル２０のみにビット線ＢＬの初期電荷が流れ、他のメモリセル２０にビット線ＢＬの初期電荷が流れることがない。 Further, since the nonvolatile memory 10 includes the NOMS transistor 23 between the fuse element 21 and the bit line BL, the initial charge of the bit line BL is only applied to the memory cell 20 in which the word line WL (read) is active. And the initial charge of the bit line BL does not flow to the other memory cells 20.
　　（実施の形態２）
　図８は、本発明の実施の形態２に係る不揮発性メモリの構成を示す概略図である。図８に示す不揮発性メモリ１１は、データを不可逆かつ不揮発に記憶する半導体装置である。不揮発性メモリ１１は、フューズ素子を含むメモリセル４０をマトリックス状に複数配置してあるフューズアレイ７、フューズアレイ７のワード線ＷＬに選択信号を供給する行デコーダ（ＲＤ）２、フューズアレイ７のビット線ＢＬを選択する列デコーダ（ＣＤ）３、行デコーダ２および列デコーダ３の動作を制御する制御回路４、参照抵抗および参照ワード線電圧を生成する参照値生成回路５を備えている。なお、不揮発性メモリ１１は、図１に示す不揮発性メモリ１０と同じ構成要素について、同じ符号を付して詳細な説明は省略する。 (Embodiment 2)
FIG. 8 is a schematic diagram showing the configuration of the nonvolatile memory according to Embodiment 2 of the present invention. A nonvolatile memory 11 shown in FIG. 8 is a semiconductor device that stores data irreversibly and in a nonvolatile manner. The nonvolatile memory 11 includes a fuse array 7 in which a plurality of memory cells 40 including fuse elements are arranged in a matrix, a row decoder (RD) 2 that supplies a selection signal to the word lines WL of the fuse array 7, A column decoder (CD) 3 that selects a bit line BL, a control circuit 4 that controls operations of the row decoder 2 and the column decoder 3, and a reference value generation circuit 5 that generates a reference resistor and a reference word line voltage are provided. In the nonvolatile memory 11, the same components as those in the nonvolatile memory 10 shown in FIG.
　フューズアレイ７は、一行のメモリセル４０に対して１本のワード線ＷＬを有している。ワード線ＷＬは、メモリセル４０にデータを書込むとき（プログラム時（prog））のワード線ＷＬと、メモリセル４０からデータを読出すとき（リード時（Read））のワード線ＷＬとを共通のワード線ＷＬで構成してある。そのため、ワード線ＷＬを、メモリセル４０にデータを書込むときに用いるワード線ＷＬと、メモリセル４０からデータを読出すときに用いるワード線ＷＬとの２本で構成する場合に比べて、不揮発性メモリ１１を小型化することができる。なお、ワード線ＷＬは、実施の形態１と同様、メモリセル４０にデータを書込むときに用いる第１ワード線のワード線ＷＬ（prog）と、メモリセル４０からデータを読出すときに用いる第２ワード線のワード線ＷＬ（Read）とで構成してもよい。 The fuse array 7 has one word line WL for one row of memory cells 40. The word line WL is common to the word line WL when data is written to the memory cell 40 (program (prog)) and the word line WL when data is read from the memory cell 40 (read). Of word lines WL. Therefore, the word line WL is non-volatile as compared with the case where the word line WL is configured with two word lines WL used when data is written to the memory cell 40 and word line WL used when data is read from the memory cell 40. The memory 11 can be reduced in size. As in the first embodiment, the word line WL is the first word line WL (prog) used when writing data to the memory cell 40 and the first word line used when reading data from the memory cell 40. You may comprise by the word line WL (Read) of 2 word lines.
　また、フューズアレイ７は、一列のメモリセル４０に対して１本のビット線ＢＬと、２本の選択線ＣＳＬとを有している。２本の選択線ＣＳＬは、メモリセル４０にデータを書込むときに用いる第１選択線の選択線ＣＳＬ（prog）と、メモリセル４０からデータを読出すときに用いる第２選択線の選択線ＣＳＬ（Read）とで構成してある。 Also, the fuse array 7 has one bit line BL and two selection lines CSL for one row of memory cells 40. The two selection lines CSL are a selection line CSL (prog) of the first selection line used when writing data into the memory cell 40 and a selection line of the second selection line used when reading data from the memory cell 40. It consists of CSL (Read).
　図９は、本発明の実施の形態２に係るメモリセル４０の構成を示す概略図である。図９に示すメモリセル４０は、切断用電源ＥＦＶの端子に一端を接続し、配線の導通状態によりデータを記憶するフューズ素子２１、フューズ素子２１の他端にドレイン電極を接続するＮＭＯＳトランジスタ２２，２３、ＮＭＯＳトランジスタ２２のゲート電極に接続するＡＮＤ回路２４、ＮＭＯＳトランジスタ２３のゲート電極に接続するＡＮＤ回路４１を備えている。なお、メモリセル４０は、図２に示すメモリセル２０と同じ構成要素について、同じ符号を付して詳細な説明は省略する。 FIG. 9 is a schematic diagram showing a configuration of the memory cell 40 according to the second embodiment of the present invention. The memory cell 40 shown in FIG. 9 has one end connected to the terminal of the power supply EFV for cutting, a fuse element 21 for storing data according to the conductive state of the wiring, and an NMOS transistor 22 for connecting a drain electrode to the other end of the fuse element 21. 23, an AND circuit 24 connected to the gate electrode of the NMOS transistor 22, and an AND circuit 41 connected to the gate electrode of the NMOS transistor 23. In the memory cell 40, the same components as those of the memory cell 20 shown in FIG.
　ＡＮＤ回路（第１論理回路）２４は、入力側にワード線ＷＬおよび選択線ＣＳＬ（prog）を、出力側にＮＭＯＳトランジスタ２２のゲート電極をそれぞれ接続してある。ＡＮＤ回路２４は、ワード線ＷＬおよび選択線ＣＳＬ（prog）に入力する選択信号がともに“１”の場合、ＮＭＯＳトランジスタ２２のゲート電極に出力する信号が“１”となる。ＮＭＯＳトランジスタ２２は、ゲート電極に“１”の信号が供給されるとオン状態となり、フューズ素子２１の配線を切断するために、大きな電流を電源電圧に設定された切断用電源ＥＦＶの端子からフューズ素子２１へ流す。 The AND circuit (first logic circuit) 24 has a word line WL and a select line CSL (prog) connected to the input side, and a gate electrode of the NMOS transistor 22 connected to the output side. In the AND circuit 24, when both the selection signals input to the word line WL and the selection line CSL (prog) are “1”, the signal output to the gate electrode of the NMOS transistor 22 is “1”. The NMOS transistor 22 is turned on when a signal of “1” is supplied to the gate electrode, and in order to cut the wiring of the fuse element 21, a large current is fused from the terminal of the cutting power supply EFV set to the power supply voltage. Flow to element 21.
　ＡＮＤ回路（第２論理回路）４１は、入力側にワード線ＷＬおよび選択線ＣＳＬ（Read）を、出力側にＮＭＯＳトランジスタ２３のゲート電極をそれぞれ接続してある。ＡＮＤ回路４１は、ワード線ＷＬおよび選択線ＣＳＬ（Read）に入力する選択信号がともに“１”の場合、ＮＭＯＳトランジスタ２３のゲート電極に出力する信号が“１”となる。ＮＭＯＳトランジスタ２３は、ゲート電極に“１”の信号が供給されるとオン状態となり、フューズ素子２１の配線の導通状態を検知するために、電流をフューズ素子２１から接地電圧に設定された切断用電源ＥＦＶの端子へ流す。 The AND circuit (second logic circuit) 41 has a word line WL and a select line CSL (Read) connected to the input side, and a gate electrode of the NMOS transistor 23 connected to the output side. In the AND circuit 41, when the selection signals input to the word line WL and the selection line CSL (Read) are both “1”, the signal output to the gate electrode of the NMOS transistor 23 is “1”. The NMOS transistor 23 is turned on when a signal of “1” is supplied to the gate electrode, and in order to detect the conduction state of the wiring of the fuse element 21, the current is disconnected from the fuse element 21 to the ground voltage. Flow to the terminal of the power supply EFV.
　次に、不揮発性メモリ１１の動作について説明する。不揮発性メモリ１１の動作は、メモリセル４０にデータを書込むときと、メモリセル４０からデータを読出すときとに分けて説明する。 Next, the operation of the nonvolatile memory 11 will be described. The operation of the nonvolatile memory 11 will be described separately when data is written to the memory cell 40 and when data is read from the memory cell 40.
　まず、図１０は、本発明の実施の形態２に係るメモリセル４０にデータを書込むときの動作を説明するための概略図である。ここで、メモリセル４０に記憶させるデータは、“０”または“１”の値を有するものとし、フューズ素子２１は、配線を切断しない場合“０”のデータを、配線を切断する場合“１”のデータをそれぞれ記憶するものとする。故に、実質的に“１”のデータを書込むことしかできず、“０”データを記憶させることは、“１”のデータを書込まないことと等価である。そのため、メモリセル２０にデータを書込むことを、データを不揮発性メモリ１０にプログラムするともいう。本実施の形態２でも、フューズ素子２１の配線を切断する場合を、データを書込むと表現して以下説明する。 First, FIG. 10 is a schematic diagram for explaining an operation when data is written in the memory cell 40 according to the second embodiment of the present invention. Here, it is assumed that the data stored in the memory cell 40 has a value of “0” or “1”, and the fuse element 21 uses “0” data when the wiring is not cut, and “1” when the wiring is cut. ”Is stored. Therefore, data of “1” can only be substantially written, and storing “0” data is equivalent to not writing data of “1”. Therefore, writing data into the memory cell 20 is also referred to as programming data into the nonvolatile memory 10. Also in the second embodiment, the case where the wiring of the fuse element 21 is cut will be described below by expressing that data is written.
　図１０に示すメモリセル４０は、ＡＮＤ回路２４が、ＡＮＤ回路２４に接続するワード線ＷＬおよび選択線ＣＳＬ（prog）の活性状態に応じて、ＮＭＯＳトランジスタ２２をオン状態にする。ＮＭＯＳトランジスタ２２をオン状態にする動作のタイミングチャートは、図４に示すタイミングチャートの選択線ＣＳＬを選択線ＣＳＬ（prog）に、ワード線ＷＬ（prog）をワード線ＷＬに読替えたタイミングチャートと同じである。そのため、本発明の実施の形態２に係るメモリセル４０にデータを書込むときの信号のタイミングチャートの図示を省略する。ＮＭＯＳトランジスタ２２をオン状態にする動作のタイミングチャートは、選択線ＣＳＬ（prog）に入力する選択信号が“１”（選択線ＣＳＬ（prog）が活性）となり、その後、ワード線ＷＬに入力する選択信号が“１”（ワード線ＷＬが活性）となることで、メモリセル４０は、ＮＭＯＳトランジスタ２２をオン状態にする。なお、切断用電源ＥＦＶの端子には、メモリセル４０にデータを書込むとき、フューズ素子２１の配線を切断するための大きな電流を流すことができる程度の高い電圧を有する電源電圧を供給できるように設定しておくものとする。 In the memory cell 40 shown in FIG. 10, the AND circuit 24 turns on the NMOS transistor 22 in accordance with the active state of the word line WL and select line CSL (prog) connected to the AND circuit 24. The timing chart of the operation to turn on the NMOS transistor 22 is the same as the timing chart of the timing chart shown in FIG. 4 in which the selection line CSL is replaced with the selection line CSL (prog) and the word line WL (prog) is replaced with the word line WL. It is. Therefore, illustration of a timing chart of signals when data is written in the memory cell 40 according to the second embodiment of the present invention is omitted. In the timing chart of the operation for turning on the NMOS transistor 22, the selection signal input to the selection line CSL (prog) becomes “1” (the selection line CSL (prog) is active), and then the selection is input to the word line WL. When the signal becomes “1” (the word line WL is activated), the memory cell 40 turns on the NMOS transistor 22. Note that a power supply voltage having a voltage high enough to flow a large current for cutting the wiring of the fuse element 21 when data is written to the memory cell 40 can be supplied to the terminal of the cutting power supply EFV. Shall be set to
　メモリセル４０は、ＮＭＯＳトランジスタ２２をオン状態とすることで、電源電圧に設定された切断用電源ＥＦＶの端子からフューズ素子２１へ矢印Ａで示す方向に電流を流してフューズ素子２１の配線を切断する。メモリセル４０は、フューズ素子２１の配線を切断することで、“１”のデータをフューズ素子２１に記憶する。なお、図１０に示すメモリセル４０では、データを書込むときに動作していない部分を破線で示してある。 By turning on the NMOS transistor 22, the memory cell 40 cuts the wiring of the fuse element 21 by causing a current to flow from the terminal of the cutting power supply EFV set to the power supply voltage to the fuse element 21 in the direction indicated by the arrow A. To do. The memory cell 40 stores “1” data in the fuse element 21 by cutting the wiring of the fuse element 21. In the memory cell 40 shown in FIG. 10, a portion not operating when data is written is indicated by a broken line.
　次に、図１１は、本発明の実施の形態２に係るメモリセル４０からデータを読出すときの動作を説明するための概略図である。図１１に示すメモリセル４０は、ＡＮＤ回路４１が、ＡＮＤ回路４１に接続するワード線ＷＬ（Read）および選択線ＣＳＬ（Read）の活性状態に応じて、ＮＭＯＳトランジスタ２３をオン状態にする。なお、切断用電源ＥＦＶの端子には、メモリセル４０からデータを読出すとき、接地電圧となるように設定しておくものとする。 FIG. 11 is a schematic diagram for explaining an operation when data is read from the memory cell 40 according to the second embodiment of the present invention. In the memory cell 40 illustrated in FIG. 11, the AND circuit 41 turns on the NMOS transistor 23 in accordance with the active state of the word line WL (Read) and the selection line CSL (Read) connected to the AND circuit 41. It is assumed that the terminal of cutting power supply EFV is set to be a ground voltage when data is read from memory cell 40.
　メモリセル４０は、ＮＭＯＳトランジスタ２３をオン状態にすることで、ＮＭＯＳトランジスタ２３のソース電極に接続するビット線ＢＬの電流を、フューズ素子２１から接地電圧に設定された切断用電源ＥＦＶの端子へ矢印Ｂで示す方向に流す。不揮発性メモリ１１は、フューズ素子２１の配線の導通状態により変化するビット線ＢＬの電圧を、判定回路３０で判定することでメモリセル４０からデータを読出す。なお、図１１に示すメモリセル４０では、データを読出すときに動作していない部分を破線で示してある。また、判定回路３０は、図６に示す判定回路３０と同じ構成であるため、詳細な説明は省略する。 By turning on the NMOS transistor 23, the memory cell 40 causes the current of the bit line BL connected to the source electrode of the NMOS transistor 23 to flow from the fuse element 21 to the terminal of the cutting power supply EFV set to the ground voltage. Flow in the direction indicated by B. The nonvolatile memory 11 reads data from the memory cell 40 by determining the voltage of the bit line BL that changes depending on the conduction state of the wiring of the fuse element 21 by the determination circuit 30. In the memory cell 40 shown in FIG. 11, a portion not operating when data is read is indicated by a broken line. The determination circuit 30 has the same configuration as the determination circuit 30 shown in FIG.
　メモリセル４０からデータを読出す動作を、タイミングチャートを用いて説明する。図１２は、本発明の実施の形態２に係るメモリセル４０からデータを読出すときの信号のタイミングチャートである。図１２に示すタイミングチャートでは、コア電源の端子とビット線ＢＬとを接続してビット線ＢＬに電流を流すために、ｔ時間、“０”の入力信号／ＲＤ＿Ｅｎａｂｌｅを入力してスイッチング素子３１をオン状態にする。スイッチング素子３１をオン状態にすると、ビット線ＢＬに電流が流れ、ビット線ＢＬの電圧が０ＶからａＶへ変化する。 The operation of reading data from the memory cell 40 will be described using a timing chart. FIG. 12 is a timing chart of signals when data is read from memory cell 40 according to the second embodiment of the present invention. In the timing chart shown in FIG. 12, in order to connect the terminal of the core power supply and the bit line BL and to allow a current to flow through the bit line BL, the input signal / RD_Enable of “0” is input and the switching element 31 is turned on for t time. Turn on. When the switching element 31 is turned on, a current flows through the bit line BL, and the voltage of the bit line BL changes from 0V to aV.
　その後、選択線ＣＳＬ（read）に入力する選択信号が“１”（選択線ＣＳＬ（read）が活性）となり、さらに、ワード線ＷＬに入力する選択信号が“１”（ワード線ＷＬが活性）となることで、ＮＭＯＳトランジスタ２３がオン状態となり、ビット線ＢＬの電流を、フューズ素子２１から接地電圧に設定された切断用電源ＥＦＶの端子へ流す。フューズ素子２１の配線が切断されている場合、ビット線ＢＬの電流はフューズ素子２１を介して接地電圧に設定された切断用電源ＥＦＶの端子へ流れることはないので、ビット線ＢＬの電圧はａＶから変化しない。一方、フューズ素子２１の配線が切断されていない（未切断）場合、ビット線ＢＬの電流はフューズ素子２１を介して接地電圧に設定された切断用電源ＥＦＶの端子へ流れるので、ビット線ＢＬの電圧はａＶから０Ｖへと変化する。 Thereafter, the selection signal input to the selection line CSL (read) becomes “1” (the selection line CSL (read) is active), and the selection signal input to the word line WL is “1” (the word line WL is active). As a result, the NMOS transistor 23 is turned on, and the current of the bit line BL flows from the fuse element 21 to the terminal of the cutting power supply EFV set to the ground voltage. When the wiring of the fuse element 21 is cut, the current of the bit line BL does not flow to the terminal of the cutting power supply EFV set to the ground voltage via the fuse element 21, so that the voltage of the bit line BL is aV Does not change. On the other hand, when the wiring of the fuse element 21 is not cut (uncut), the current of the bit line BL flows to the terminal of the cutting power supply EFV set to the ground voltage via the fuse element 21, so that the bit line BL The voltage changes from aV to 0V.
　次に、センスアンプＳＡを駆動させる信号“１”がセンスアンプＳＡに入力されると、センスアンプＳＡは、ビット線ＢＬの電圧を増幅し、増幅した電圧が所定のレベル以上か否かを判定する。センスアンプＳＡは、増幅した電圧が所定のレベル以上の場合、フューズ素子２１の配線が切断されていると判定して、“１”のデータをデータＯＵＴとして読出す。一方、センスアンプＳＡは、増幅した電圧が所定のレベル未満の場合、フューズ素子２１の配線が切断されていない（未切断）と判定して、“０”のデータをデータＯＵＴとして読出す。 Next, when a signal “1” for driving the sense amplifier SA is input to the sense amplifier SA, the sense amplifier SA amplifies the voltage of the bit line BL and determines whether the amplified voltage is equal to or higher than a predetermined level. To do. When the amplified voltage is equal to or higher than a predetermined level, the sense amplifier SA determines that the wiring of the fuse element 21 is disconnected and reads “1” data as data OUT. On the other hand, when the amplified voltage is lower than a predetermined level, the sense amplifier SA determines that the wiring of the fuse element 21 is not cut (not cut), and reads “0” data as data OUT.
　以上のように、本発明の実施の形態２に係る不揮発性メモリ１１は、ＮＭＯＳトランジスタ２３のゲート電極に接続するＡＮＤ回路４１をさらに備え、データを読出すとき、ＡＮＤ回路４１は、ＡＮＤ回路４１に接続するワード線ＷＬおよび選択線ＣＳＬ（read）の活性状態に応じて、ＮＭＯＳトランジスタ２３をオン状態にすることで、ビット線ＢＬの電流を、フューズ素子２１から接地電圧に設定された切断用電源ＥＦＶの端子へ流す。そのため、不揮発性メモリ１１は、ワード線ＷＬおよび選択線ＣＳＬ（read）に入力する選択信号がともに“１”となるメモリセル４０に対してのみ、ビット線ＢＬの電流を、フューズ素子２１から接地電圧に設定された切断用電源ＥＦＶの端子へ流すことができ、不揮発性メモリ１１全体で消費する電流を削減することができる。 As described above, the nonvolatile memory 11 according to the second embodiment of the present invention further includes the AND circuit 41 connected to the gate electrode of the NMOS transistor 23. When reading data, the AND circuit 41 is the AND circuit 41. By turning on the NMOS transistor 23 in accordance with the active state of the word line WL connected to the selection line and the selection line CSL (read), the current of the bit line BL is disconnected from the fuse element 21 to the ground voltage. Flow to the terminal of the power supply EFV. Therefore, the nonvolatile memory 11 grounds the current of the bit line BL from the fuse element 21 only to the memory cell 40 in which the selection signals input to the word line WL and the selection line CSL (read) are both “1”. The current can be supplied to the terminal of the cutting power supply EFV set to a voltage, and the current consumed by the entire nonvolatile memory 11 can be reduced.
　つまり、不揮発性メモリ１１は、データを読出す一つのメモリセル４０に対して、ビット線ＢＬの電流を、フューズ素子２１から接地電圧に設定された切断用電源ＥＦＶの端子へ流し、データを読出さない他のメモリセル４０に対して、無駄なビット線ＢＬの電流を流さないので、不揮発性メモリ１１全体で消費する電流を削減することができる。なお、不揮発性メモリ１１は、ワード線ＷＬおよび選択線ＣＳＬ（read）に入力する選択信号がともに“１”となる単位を、一つのメモリセル４０に限定するものではなく、複数のメモリセル４０としてもよい。 In other words, the non-volatile memory 11 causes the current of the bit line BL to flow from the fuse element 21 to the terminal of the cutting power supply EFV set to the ground voltage for one memory cell 40 from which data is read to read the data. Since no unnecessary current of the bit line BL is supplied to other memory cells 40 that are not output, the current consumed by the entire nonvolatile memory 11 can be reduced. The nonvolatile memory 11 is not limited to a single memory cell 40 as a unit in which both selection signals input to the word line WL and the selection line CSL (read) are “1”. It is good.
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した説明ではなく、請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　１，７，１０１　フューズアレイ、２，１０２　行デコーダ、３，１０３　列デコーダ、４，１０４　制御回路、５，１０５　参照値生成回路、１０，１１，１００　不揮発性メモリ、２０，４０，２００　メモリセル、２１，２０１　フューズ素子、２２，２３　ＮＭＯＳトランジスタ、２４，４１　ＡＮＤ回路、３０　判定回路、３１，３０１　スイッチング素子、２０２　トランジスタ、３００　選択回路、３０２　レベル変換回路、３０３　増幅器。 1,7,101 fuse array, 2,102 row decoder, 3,103 column decoder, 4,104 control circuit, 5,105 reference value generation circuit, 10, 11, 100 non-volatile memory, 20, 40, 200 memory cells 21, 201 fuse element, 22, 23 NMOS transistor, 24, 41 AND circuit, 30 determination circuit, 31, 301 switching element, 202 transistor, 300 selection circuit, 302 level conversion circuit, 303 amplifier.

Claims (7)

  1. 　データを不可逆かつ不揮発に記憶する半導体装置であって、
    　電源電圧と接地電圧とを切替えることが可能な電源端子に一端を接続し、配線の導通状態によりデータを記憶するフューズ素子と、
    　前記フューズ素子の他端に一方の電流電極を接続し、前記電源端子から前記フューズ素子へ流す電流を制御する第１トランジスタと、
    　前記第１トランジスタに対して並列に、前記フューズ素子の他端に一方の電流電極を接続し、前記フューズ素子から前記電源端子へ流す電流を制御する第２トランジスタと、
    　前記第１トランジスタの制御電極に接続する第１論理回路と
    　を備え、
    　データを書込むとき、前記第１論理回路は、前記第１論理回路に接続する第１ワード線および第１選択線の活性状態に応じて、前記第１トランジスタをオン状態にすることで、電源電圧の前記電源端子から前記フューズ素子へ電流を流して前記フューズ素子の配線を切断し、
    　データを読出すとき、前記第２トランジスタは、前記第２トランジスタの制御電極に接続する第２ワード線の活性状態に応じて、オン状態となり、前記第２トランジスタの他方の電流電極に接続するビット線の電流を、前記フューズ素子から接地電圧の前記電源端子へ流す、半導体装置。     A semiconductor device for storing data in an irreversible and nonvolatile manner,
    A fuse element that connects one end to a power supply terminal capable of switching between a power supply voltage and a ground voltage, and stores data according to a conductive state of the wiring;
    A first transistor for connecting one current electrode to the other end of the fuse element and controlling a current flowing from the power supply terminal to the fuse element;
    In parallel with the first transistor, one current electrode is connected to the other end of the fuse element, and a second transistor for controlling a current flowing from the fuse element to the power supply terminal;
    A first logic circuit connected to the control electrode of the first transistor;
    When writing data, the first logic circuit turns on the first transistor in accordance with the active state of the first word line and the first selection line connected to the first logic circuit, thereby supplying power. A current is passed from the power supply terminal of the voltage to the fuse element to cut the wiring of the fuse element;
    When reading data, the second transistor is turned on according to the active state of the second word line connected to the control electrode of the second transistor, and is connected to the other current electrode of the second transistor. A semiconductor device in which a current of a line is supplied from the fuse element to the power supply terminal of a ground voltage.
  2. 　データを不可逆かつ不揮発に記憶するメモリセルをマトリックス状に複数配置してある半導体装置であって、
    　前記メモリセルは、
    　電源電圧と接地電圧とを切替えることが可能な電源端子に一端を接続し、配線の導通状態によりデータを記憶するフューズ素子と、
    　前記フューズ素子の他端に一方の電流電極を接続し、前記電源端子から前記フューズ素子へ流す電流を制御する第１トランジスタと、
    　前記第１トランジスタに対して並列に、前記フューズ素子の他端に一方の電流電極を接続し、前記フューズ素子から前記電源端子へ流す電流を制御する第２トランジスタと、
    　前記第１トランジスタの制御電極に接続する第１論理回路と
    　を備え、
    　データを書込むとき、前記第１論理回路は、前記第１論理回路に接続する第１ワード線および第１選択線の活性状態に応じて、前記第１トランジスタをオン状態にすることで、電源電圧の前記電源端子から前記フューズ素子へ電流を流して前記フューズ素子の配線を切断し、
    　データを読出すとき、前記第２トランジスタは、前記第２トランジスタの制御電極に接続する第２ワード線の活性状態に応じて、オン状態となり、前記第２トランジスタの他方の電流電極に接続するビット線の電流を、前記フューズ素子から接地電圧の前記電源端子へ流す、半導体装置。     A semiconductor device in which a plurality of memory cells that store data in an irreversible and nonvolatile manner are arranged in a matrix,
    The memory cell is
    A fuse element that connects one end to a power supply terminal capable of switching between a power supply voltage and a ground voltage, and stores data according to a conductive state of the wiring;
    A first transistor for connecting one current electrode to the other end of the fuse element and controlling a current flowing from the power supply terminal to the fuse element;
    In parallel with the first transistor, one current electrode is connected to the other end of the fuse element, and a second transistor for controlling a current flowing from the fuse element to the power supply terminal;
    A first logic circuit connected to the control electrode of the first transistor;
    When writing data, the first logic circuit turns on the first transistor in accordance with the active state of the first word line and the first selection line connected to the first logic circuit, thereby supplying power. A current is passed from the power supply terminal of the voltage to the fuse element to cut the wiring of the fuse element;
    When reading data, the second transistor is turned on according to the active state of the second word line connected to the control electrode of the second transistor, and is connected to the other current electrode of the second transistor. A semiconductor device in which a current of a line is supplied from the fuse element to the power supply terminal of a ground voltage.
  3. 　前記第１トランジスタは、前記第２トランジスタに比べ、トランジスタサイズが大きい請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the first transistor has a larger transistor size than the second transistor.
  4. 　前記第２トランジスタの制御電極に接続する第２論理回路をさらに備え、
    　データを読出すとき、前記第２論理回路は、前記第２論理回路に接続する前記第２ワード線および第２選択線の活性状態に応じて、前記第２トランジスタをオン状態にすることで、前記ビット線の電流を、前記フューズ素子から接地電圧の前記電源端子へ流す、請求項１または２に記載の半導体装置。     A second logic circuit connected to the control electrode of the second transistor;
    When reading data, the second logic circuit turns on the second transistor in accordance with the active state of the second word line and the second selection line connected to the second logic circuit, The semiconductor device according to claim 1, wherein a current of the bit line is supplied from the fuse element to the power supply terminal of a ground voltage.
  5. 　前記第１論理回路に接続する前記第１ワード線と、前記第２論理回路に接続する前記第２ワード線とは、共通のワード線で構成してある、請求項４に記載の半導体装置。 5. The semiconductor device according to claim 4, wherein the first word line connected to the first logic circuit and the second word line connected to the second logic circuit are configured by a common word line.
  6. 　前記電源端子は、パッドを含み、かつ前記半導体装置の外部から電源電圧か接地電圧かに設定可能である、請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the power supply terminal includes a pad and can be set to a power supply voltage or a ground voltage from the outside of the semiconductor device.
  7. 　前記電源端子と異なり、前記データを読出すときに前記ビット線に電流を与えるコア電源端子を備え、前記データを書込むときに前記電源端子に与えられる電源電圧は、前記データを読出すときに前記コア電源端子に与えられる電源電圧より高い、請求項６記載の半導体装置。 Unlike the power supply terminal, it includes a core power supply terminal that supplies a current to the bit line when reading the data, and the power supply voltage applied to the power supply terminal when writing the data is when reading the data The semiconductor device according to claim 6, wherein the semiconductor device is higher than a power supply voltage applied to the core power supply terminal.
PCT/JP2012/059635 2011-04-13 2012-04-09 Semiconductor device provided with fuse element WO2012141118A1 (en)

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