WO2012140299A1 - Circuit en mode courant de première étape frontale pour la lecture de capteurs et circuit intégré - Google Patents

Circuit en mode courant de première étape frontale pour la lecture de capteurs et circuit intégré Download PDF

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Publication number
WO2012140299A1
WO2012140299A1 PCT/ES2012/070238 ES2012070238W WO2012140299A1 WO 2012140299 A1 WO2012140299 A1 WO 2012140299A1 ES 2012070238 W ES2012070238 W ES 2012070238W WO 2012140299 A1 WO2012140299 A1 WO 2012140299A1
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WO
WIPO (PCT)
Prior art keywords
transistors
current
transistor
circuit according
input
Prior art date
Application number
PCT/ES2012/070238
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English (en)
Spanish (es)
Inventor
David GASCÓN FORA
Andreu Sanuy Charles
Lluís GARRIDO BELTRAN
Original Assignee
Universitat De Barcelona
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universitat De Barcelona filed Critical Universitat De Barcelona
Publication of WO2012140299A1 publication Critical patent/WO2012140299A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/261—Amplifier which being suitable for instrumentation applications

Definitions

  • a first aspect of the present invention relates to a circuit in first-stage current mode for reading sensors, particularly for fast photosensors.
  • a second aspect of the invention relates to an integrated circuit comprising the circuit in the first frontal stage current mode.
  • CSP Load sensitive preamplifiers
  • Closed loop transimpedance has a better signal to noise ratio (SNR), however its bandwidth is typically limited by stability problems and its dynamic range by that of the closed loop amplifier.
  • SNR signal to noise ratio
  • Reading in current mode with a low input impedance stage is a better solution, typically through a common door or common base. After this the signal is processed inside the chip. This solution offers several advantages:
  • a low input impedance can be useful for improving temporal resolution, especially for some SiPM [1], and helps minimize crosstalk and interference problems.
  • High dynamic range for deeply submicron technologies where the supply voltage is limited to 1 or 2 V.
  • Current mode circuits are used in high energy physics ("High Energy Physics", HEP) in large accelerators [4], [5], [8], in medical imaging [1], [6], [7], [8], and in optical communications (for photodiode reading (PD) or avalanche PD (APD ) [9], [19], [20] High dynamic range
  • Detectors for large HEP colliders have to deal with a huge dynamic range, especially calorimetry subdetectors where a dynamic range of more than 15 bits is required. This is typically achieved using the following two techniques:
  • the time signal is usually obtained after discrimination of the input signal, so it is the jitter of the discriminated signal that limits the temporal resolution of the electronics.
  • the random jitter (or t ) (correlated with noise) is proportional to the noise and inversely proportional to the slope of the dS / dt signal, therefore, inversely proportional to the BW of the signal:
  • Patent application WO2009046151 describes an amplifier that uses the technique of signal division by means of current mirrors mentioned above.
  • it includes an input current mirror that replicates the input current and sends it to secondary mirrors of respective high and low profits.
  • input current mirror For high input currents some transistors of the input current mirror would enter the ohmic region and therefore the precise current replication would cease.
  • the dynamic range could be increased by increasing the W / L of the mirror transistors. However, this typically leads to degradation of bandwidth.
  • dynamic range and bandwidth in the
  • the present invention provides a circuit in the first frontal stage current mode for sensor reading, comprising an input stage for dividing an input current signal into two or more output currents, and where, contrary to the known proposals in which all current is sensed by a current mirror input stage, the current mode circuit input stage of the invention comprises, in a characteristic way, a common base / gate stage formed by a plurality of transistors arranged in two or more groups so that each of them provides, in a respective node, one of the two or more output current signals.
  • the first of the two or more groups of transistors provides, at its output node, a current higher than the second at its output node.
  • the first group of transistors comprises, for various embodiments, n branches of transistors in parallel, each formed by one or more
  • the second group comprises one or two branches of transistors formed by one or more transistors.
  • Each of the transistor branches is formed, for one embodiment, by a first transistor and a second transistor or hull transistor, connected in series.
  • the common base / gate stage comprises a voltage or current feedback circuit to decrease the input impedance thereof.
  • the current mode circuit of the first aspect of the invention comprises, for one embodiment, a high gain unit with an input connected to the output node of the first group and a low gain unit with an input connected to the output node of the second group , the high and low gain units being, for a preferred embodiment, current mirrors formed by two respective transistors to, respectively, copy the current from the output nodes.
  • the high gain current mirror includes a saturation control circuit dedicated to stabilizing the operating point of the stage on a common basis.
  • the outputs of the current mirrors mentioned in the previous paragraph are connected to the inputs of respective devices of a front stage providing different reading paths, according to an applied embodiment, or possible use, such as that related to the amplifier prototype for single photon detectors (PMT and SiPM) built by the present inventors and designed for the "Cherenkov observatory
  • the output of the current mirror of high gain is connected to the input of a unit of measurement of time, and at least the output of the mirror of low gain current is connected to the input of a unit of measurement of energy, the measurement units belonging to a reading system .
  • part or all of the transistors that form the different sections of the circuit in current mode of the first frontal stage of the first aspect of the invention are transistors are FET and / or BJT.
  • a second aspect of the invention relates to an integrated circuit comprising the current mode circuit of the first aspect.
  • the integrated circuit is implemented, for one embodiment, in BiCMOS technology.
  • the word "comprises” and its vanes are not intended to exclude other technical characteristics, additives, components or steps.
  • other objects, advantages and features of the invention will be derived partly from the description and partly from the practice of the invention.
  • the following examples and drawings are provided by way of illustration, and are not intended to be limiting of the present invention.
  • the present invention covers all possible combinations of particular and preferred embodiments indicated herein.
  • Figure 1 schematically shows the current mode circuit of the invention, for one embodiment.
  • Figure 2 shows the internal circuit of the common base / door entry stage shown in Figure 1, for one embodiment.
  • Figure 3 shows an alternative circuit to that illustrated in Figure 2, for another embodiment implementing a helmeted scheme.
  • Figure 4 shows a scheme similar to that of Figure 3, but including a voltage feedback circuit.
  • Figure 5 shows a scheme similar to that of Figure 4, but in this case including a current feedback circuit.
  • Figure 6 shows a low gain current mirror, alternative to that illustrated in Figure 1, for an embodiment including a common base amplifier and a hull scheme.
  • Figure 7 also shows a high gain current mirror, alternative to that illustrated in Figure 1, for an embodiment including a common base amplifier, a casted scheme and a control circuit.
  • Figure 8a shows an alternative embodiment to that illustrated in Figure 7, implementing a different control circuit.
  • Figure 8b shows an alternative embodiment to that illustrated in Figure 8a, adding adjustability to the saturation limit.
  • Figures 9a, 9b and 9c are graphs related to a prototype called PACTA designed and constructed to implement the circuit in the first frontal stage current mode of the present invention, for one embodiment, where Figure 9a shows the input pulses applied, and Figures 9b and 9c show respectively the high and low gain outputs thereof, for different amplitudes of the input pulse;
  • Figures 10a and 10b show the transfer function of the transimpedance gain for the high and low gain paths, obtained from the PACTA prototype, for, respectively, peak-to-peak values and values in terms of load (integral of the pulse).
  • Figures 1 1 a and 1 1 b are graphs showing the relative non-linearity for, respectively, the transimpedance gain and the load gain.
  • Figure 12 shows the frequency response for small signal of the high gain and low gain paths of the PACTA prototype.
  • Figure 13 shows the single photoelectron spectrum measured with the PACTA prototype at the nominal gain of the PMT (4.5x10 4 ).
  • Figure 14 shows the circuit in the first frontal stage current mode of the first aspect of the invention applied to precise measurements of time and energy.
  • the input current is divided by a factor na 1 simply by connecting the collector (or drain terminal) of n paired devices, so that most of the input current (ideally a n / n +1 factor) flows through the High gain path, while only about 1 / n +1 of the input current flows through the low gain path.
  • This idea is based on a precise current division even when the high gain path enters saturation.
  • the method of sensing the current after division is as important as the mechanism for dividing the input current; because, as stated above, the operating point of all paired parallel components must be as similar as possible due to second-order effects such as the Early effect or the modulation of the channel length. This is very complicated when considering the intention to work with high currents (peak currents of up to 20 mA).
  • the limiting factor is not the peak current value since, for example, the W / L ratio of M1 in Figure 1 can be increased as much as necessary to minimize the voltage variation in node a.
  • transimpedance amplifier For linear operation in small signal it is able to provide low input impedance, by both the voltage at the collector (drain) terminal of the common base (gate) transistor (node a in Figure 1) is stable as required. However, for large input currents the high gain path will be saturated and the feedback as regards the input impedance is lost.
  • the input current is divided by a factor n + 1 as long as the transistors Q n to Q 0 are in the region of active linear operation (saturation for FETs) and are equal and paired. Disposal techniques such as the common barycenter of transistors Q n to Q 0 make precise pairing possible. As in the current mirrors, the current of the different branches must be the same because the base-emitter voltage (or door-source) is the same by construction for all transistors (as long as these are the same). Of course, if second-order effects are considered, the mating of currents also depends on the collector-emitter (drain-source) voltage, and therefore on the variation in voltage at nodes a and b.
  • emitter degeneration is used in bipolar current mirrors to increase input and output impedances and improve mating [21]. Although it will not be remembered for each version of the circuit, emitter degeneration (or source) can be used in any of the following variations of the basic circuit.
  • Ibias polarization current source depends on a compromise between:
  • the effect of the voltage variation in the nodes a and b has much less impact on the collector-emitter (drain-source) voltage of Q ⁇ (the output impedance is increased) provided that the casted transistors Q c work also in the active linear region
  • G m gm without emitter degeneration
  • gm the transconductance of each of the transistors in common base (gate) Q ⁇ .
  • Gm gm / (1 + gmRe).
  • A is the gain of the error amplifier of Figure 4.
  • This type of feedback is applied directly to the preamplifier of the invention, for one embodiment.
  • the error amplifier must be of high bandwidth to avoid significant inductive effects on the input impedance, this is typically implemented as a common emitter (source) stage.
  • Vbe or Vgs
  • the common base transistor (door) Q F and the TIA in closed-loop broadband have lower power consumption than the broadband voltage amplifier A.
  • the transimpedance bandwidth can be almost as large as the gain frequency unit of the TIA amplifier.
  • Mcg can be a FET or a BJT.
  • the power mirror of Figure 6 must be modified to be used in the high gain path, adding a control circuit to prevent the malfunction of the stage in common base / door avoiding that, in case of high input current, transistors Q 0 , ... Q n ; Qco, - Qcn of the common base / gate stage enter the saturation region, if they are BJTs, or in the ohmic region, if they are FETs.
  • the control circuit is arranged in the high gain current mirror to avoid a significant voltage variation in the drain / collector node of the transistor that is connected to the output node a of the first group (see Figure 1) of the stage of common base / door, providing an alternative path to the excessive current part of the input current.
  • the transistor is the hull transistor M1 c, but for a simpler embodiment that does not include the hull transistor, this would be the M1 transistor.
  • FIGs 7, 8a and 8b illustrate different embodiments of the control circuit (designated as a saturation control circuit, although as stated above prevents the common base / gate stage from entering saturation or ohmic region, depending on the type of used transistors), having in common that they include, to provide the alternative path, a common base transistor Qcb (which for the illustrated embodiment is a BJT transistor, but for other embodiments it is a FET) with its emitter connected to the output node a of the first group of the common base / door stage and its collector connected to the transistor door of the current mirror M1, M2.
  • a common base transistor Qcb which for the illustrated embodiment is a BJT transistor, but for other embodiments it is a FET
  • control circuit further comprises, to provide the alternative path, two transistors connected as diodes Qod and Qoc2 with the collector of one Q oc i of them connected to the sources of the transistors of the current mirror M1, M2 and the emitter of the other Q 0C 2 connected to the doors / bases of the current mirror transistors M1 / M2.
  • the idea is to avoid a significant variation in voltage at the drain of M1 c by causing excess current to flow through the common base transistor Q C b and through the transistors connected as diodes Q oc i and
  • the gate-source voltage (Vgs) of M1 is proportional (quadratically in strong inversion) to its drain current.
  • M1 is sized so that its Vgs is such that the collector current of Qod and Qoc2 is almost negligible.
  • the base-emitter voltage (Vbe) of Q oc i and Qoc2 is still below the conduction value.
  • control circuit of Figure 7 can also be applied to simple current mirrors, without casted transistors.
  • An improved control circuit is shown in Figure 8a which, apart from the common base (or gate) transistor mentioned above Q C b, also comprises, to provide the alternative path, a transistor Q oc i with its collector connected to the sources / emitters of the current mirror transistors M1 / M2, its transmitter connected to the doors / bases of the current mirror transistors M1 / M2 and its base connected to the drain / collector of the current mirror transistor M2 that is not connected to the output node a of the first group of the common base / door stage (see Figure 1).
  • the transistor Q oc i is controlled by the voltage Vc-Vm, which is equal to its Vbe: - At rest or for low currents (when the high gain path works) the circuit is designed so that Vc-Vm ⁇ Vbe_ON, where
  • Vbe_ON is the conduction voltage of Q oc i - Therefore, for currents of Low input This current mirror works like a normal HF current mirror and the high gain path is valid.
  • the conduction point of Q oc i can be controlled by
  • transistors M1 and M2c dimensions of transistors M1 and M2c and by the voltage of transistors M1 and M2c
  • Illustrated can be FET or BJT transistors, depending on the embodiment. Results of the measures
  • a prototype, called PACTA, of the preamp for the CTA project that includes the innovations discussed here has been designed and manufactured as an Application Specific Integrated Circuit (ASIC) in the SiGe technology of 0.35 um from Austriamicrosystems, which combines CMOS and BJT devices.
  • ASIC Application Specific Integrated Circuit
  • a closed loop differential transimpedance amplifier follows each of the current mirrors presented previously; therefore the preamplifier has a differential voltage output and a transimpedance gain.
  • the current division scheme described in Figure 4 has been used for the prototype, with emitter degeneration for transistors Q ⁇ and with the circuit described in Figure 8.
  • Figures 9a, 9b and 9c show respectively the input and output pulses of the high and low gain.
  • the input pulses emulate the shape of the pulses of the fastest PMTs.
  • the high gain path works up to 1 mA input currents
  • the high gain path is saturated.
  • the current division functions properly and the low gain operates linearly up to peak input currents of more than 20 mA. It is worth commenting that the saturation time of the high gain path is very short, even for very large currents.
  • the relative linearity error is below 3% ( Figure 1 1 a and 1 1 b), both for peak measurements and for load measurements, for the linear range of both gains. Therefore, the dynamic range exceeds 16 bits.
  • the bandwidth of the high and low gain paths is about 500 MHz ( Figure 12).
  • the frequency response shows a certain high frequency resonance peak that can be minimized if necessary.
  • the single photoelectron spectrum ( Figure 13) has been measured with PACTA at the nominal gain of the PMT (4.5x10 4 ).
  • the spectral distribution of noise power referred to the input is about 10 pA / root (Hz), this translates into an equivalent noise load ("Equivalent Noise Charge” ENC) of about 5000 electrons for an integration time of about 10 ns.
  • the preamp works properly and meets the requirements.
  • the PACTA chip constitutes an experimental proof that it works correctly. The following describes different possible applications of the
  • FIG. 14 An interesting embodiment of the preamplifier of the invention is presented in Figure 14, where the output of the high gain current mirror is connects to the input of a unit of time measurements, and the output of the low gain current mirror is connected to the input of the unit of energy measurements, the units belonging to a reading system of which ([1], [6]) perform exact measurements of time and energy and where the signal is divided into two paths, for example for TOF systems.
  • a high gain path is used for temporary measurements and a low gain path for energy measurements, since the typical signal is well above the noise threshold (as in the case of PET).
  • the dynamic range of systems in classical mode is limited by the dynamic range of the current mirror [6].
  • the present invention allows the capabilities of the solution to be exploited much better in current mode:

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Amplifiers (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)

Abstract

Selon l'invention, un premier circuit comprend une étape d'entrée pour diviser un courant d'entrée en deux ou plus de deux courants de sortie, l'étape comprenant une étape de base/porte commune formée par une pluralité de transistors Qo,... Qn disposés formant deux ou plus de deux groupes de façon que chacun d'eux fournisse, dans un noeud respectif de sortie a, b, un des deux ou plus de deux signaux de courant de sortie. Dans un mode de réalisation préféré, deux miroirs à gain élevé et faible connectés sont également utilisés, respectivement, au noeud de sortie a du premier groupe et au noeud de sortie b du deuxième groupe, le miroir de courant à gain élevé comprenant un circuit de commande pour prévenir le mauvais fonctionnement de l'étape de base/porte commune en cas de courants élevés d'entrée.
PCT/ES2012/070238 2011-04-11 2012-04-10 Circuit en mode courant de première étape frontale pour la lecture de capteurs et circuit intégré WO2012140299A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ESP201130565 2011-04-11
ES201130565A ES2390305B1 (es) 2011-04-11 2011-04-11 Circuito en modo corriente de primera etapa frontal para la lectura de sensores y circuito integrado.

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WO2012140299A1 true WO2012140299A1 (fr) 2012-10-18

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3766543A (en) * 1970-12-09 1973-10-16 Philips Corp Current divider
US5721512A (en) * 1996-04-23 1998-02-24 Analog Devices, Inc. Current mirror with input voltage set by saturated collector-emitter voltage
US20090091393A1 (en) * 2007-10-03 2009-04-09 Qualcomm Incorporated Dual-path current amplifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3766543A (en) * 1970-12-09 1973-10-16 Philips Corp Current divider
US5721512A (en) * 1996-04-23 1998-02-24 Analog Devices, Inc. Current mirror with input voltage set by saturated collector-emitter voltage
US20090091393A1 (en) * 2007-10-03 2009-04-09 Qualcomm Incorporated Dual-path current amplifier

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CORSI, F ET AL.: "A selftriggered CMOS front-end for Silicon Photo-Multiplier detectors", ADVANCES IN SENSORS AND INTERFACES, 2009. I WAS 12009. 3RD INTERNATIONAL WORKSHOP, 25 June 2009 (2009-06-25), pages 79 - 84, XP031498617 *

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ES2390305A1 (es) 2012-11-08

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