WO2012140299A1 - First front stage current-mode circuit for reading sensors and integrated circuit - Google Patents

Abstract

The first circuit comprises an input stage for dividing an input current into two or more output currents, said stage comprising a common base/gate stage formed by a plurality of transistors Qo,... Qn arranged to form two or more groups, such that each group provides one of the two or more output current signals at a respective output node (a, b). In a preferred embodiment, the invention also includes high- and low-gain mirrors connected respectively to the output node (a) of the first group and to the output node (b) of the second group, said high-gain current mirror comprising a control circuit for preventing the malfunctioning of the common base/gate stage in the event of high input currents.

Description

 Circuit in first-stage current mode for sensor reading and integrated circuit

A first aspect of the present invention relates to a circuit in first-stage current mode for reading sensors, particularly for fast photosensors. A second aspect of the invention relates to an integrated circuit comprising the circuit in the first frontal stage current mode. STATE OF THE TECHNIQUE

There are currently many circuits for reading ultra sensitive photosensors such as the photomultiplier tube (PMT) or the silicon photomultiplier ("silicon photomultiplier", SiPM). To fully exploit the performance of PMTs or SiPMs the following features are desirable: high speed and low input impedance, high sensitivity and high dynamic range (which requires a low noise level) and low voltage operation (required for implementations in integrated circuit), which is achieved by working in current mode. Recently, with the emergence of solid-state photomultipliers (SiPM, MPPC, GAPDs, etc.) interest in current mode circuits has grown

Especially for low voltage and high speed applications. The most relevant proposals regarding the background of the present invention are described below.

Amplifiers in current mode for radiation detection

Load sensitive preamplifiers (CSP) have traditionally been used as front circuits for reading radiation detectors of many types (semiconductors, photosensors, gas, etc.) [1], [2], [ 3]. However, CSPs are quite limited in speed and therefore are not optimal for achieving good temporal resolutions or to minimize the effect of stacking. For this reason, in many applications the current pulse generated by the PMT or SiPM is converted to voltage by a small resistor and then read by a voltage amplifier. Although this works in those applications is not optimal in terms of noise since this resistance imposes a compromise between noise and BW. Amplifiers

Closed loop transimpedance has a better signal to noise ratio (SNR), however its bandwidth is typically limited by stability problems and its dynamic range by that of the closed loop amplifier.

Reading in current mode with a low input impedance stage is a better solution, typically through a common door or common base. After this the signal is processed inside the chip. This solution offers several advantages:

 - Low noise and high speed can be achieved simultaneously.

 - A low input impedance can be useful for improving temporal resolution, especially for some SiPM [1], and helps minimize crosstalk and interference problems.

 - Helps preserve a good dynamic range even for deeply submicron technologies where the supply voltage is limited to 1 or 2 V. Current mode circuits are used in high energy physics ("High Energy Physics", HEP) in large accelerators [4], [5], [8], in medical imaging [1], [6], [7], [8], and in optical communications (for photodiode reading (PD) or avalanche PD (APD ) [9], [19], [20] High dynamic range

Detectors for large HEP colliders have to deal with a huge dynamic range, especially calorimetry subdetectors where a dynamic range of more than 15 bits is required. This is typically achieved using the following two techniques:

 (1) Since, for an integrated circuit, the maximum signal is typically limited by the maximum supply voltage, the design of low noise electronics is crucial. An example of a low noise current mode amplifier is [4].

(2) Systems with two or more gains are used: the detector signal is divided or replicated and different gains are applied to each path, which has a lower dynamic range (usually 12 bits are sufficient). The following two important points should be considered:

(i) Although a dynamic range of 16 or 17 bits has been reported for calorimetry, the required bandwidth is below 100 MHz. Since the noise is proportional to the square root of the bandwidth this means that there is a clear compromise between noise (dynamic range) and bandwidth. For example, taking a preamp [4], with very low noise referred to the input (10 pA / sqrt (Hz)) and assuming a 500 MHz BW, the dynamic range would be limited to about 14 bits.

(¡I) The technique of signal division is performed either in the voltage domain, typically by resistive dividers or amplifiers with different gains ([10], [1 1], [12] or by transistors replica [15] ); or in the current domain by means of current mirrors ([13], [6]). A large bandwidth is also required for some medical applications such as computer tomography ([1], [14]) or for optical communications ([1 1]).

Time and energy measurements for medical imaging

Both in HEP, as in astrophysics and in medical imaging, precise temporal measures are frequently required with resolutions lower than 100 ps [1], especially for time-of-flight techniques (TOF))

It has long been recognized [16] that the statistical noise in positron electron tomography (PET) can be reduced by accurately measuring the difference in the arrival time of 511 keV photons from of annihilation of the positron. Various integrated circuits are being developed for TOF-PET [8], [1].

The time signal is usually obtained after discrimination of the input signal, so it is the jitter of the discriminated signal that limits the temporal resolution of the electronics. The random jitter (or _t ) (correlated with noise) is proportional to the noise and inversely proportional to the slope of the dS / dt signal, therefore, inversely proportional to the BW of the signal:

Consequently, both SNR (or S / N) and bandwidth must be optimized to achieve the minimum temporal resolution. Current mode circuits can be useful to achieve this.

As discussed above, circuits in current mode have a higher BW, because all signal nodes are low impedance nodes. In the case of SiPMs, the peak current increases as the input impedance of the amplifier decreases [1]. This improves the term dS / dt. However, this trend limits the dynamic range of the usual current mode circuits. There are the following two typical approaches:

 - Allow saturation of the preamp and make energy measurements using time-over-threshold techniques (ToT) [8].

- Create a double path, one for temporary measures and another, with lower gain, for energy measures. However, limitations in the dynamic range are still present in this type of solutions in current mode (in the first frontal stage) [6].

As stated before, [13], i.e. Patent application WO2009046151 describes an amplifier that uses the technique of signal division by means of current mirrors mentioned above. In particular, it includes an input current mirror that replicates the input current and sends it to secondary mirrors of respective high and low profits. For high input currents some transistors of the input current mirror would enter the ohmic region and therefore the precise current replication would cease. It could be argued that the dynamic range could be increased by increasing the W / L of the mirror transistors. However, this typically leads to degradation of bandwidth. In summary, there is a clear compromise between dynamic range and bandwidth in the

power amplifiers based on power mirrors. EXPLANATION OF THE INVENTION

It is desirable to offer an alternative to the state of the art that covers the gaps found here, and that, in particular, overcomes the aforementioned drawbacks that exist in proposals that use signal splitting techniques in the current domain through mirrors. of current. To that end, the present invention provides a circuit in the first frontal stage current mode for sensor reading, comprising an input stage for dividing an input current signal into two or more output currents, and where, contrary to the known proposals in which all current is sensed by a current mirror input stage, the current mode circuit input stage of the invention comprises, in a characteristic way, a common base / gate stage formed by a plurality of transistors arranged in two or more groups so that each of them provides, in a respective node, one of the two or more output current signals. For one embodiment, the first of the two or more groups of transistors provides, at its output node, a current higher than the second at its output node.

The first group of transistors comprises, for various embodiments, n branches of transistors in parallel, each formed by one or more

transistors, and the second group comprises one or two branches of transistors formed by one or more transistors.

Each of the transistor branches is formed, for one embodiment, by a first transistor and a second transistor or hull transistor, connected in series.

According to one embodiment, the common base / gate stage comprises a voltage or current feedback circuit to decrease the input impedance thereof. The current mode circuit of the first aspect of the invention comprises, for one embodiment, a high gain unit with an input connected to the output node of the first group and a low gain unit with an input connected to the output node of the second group , the high and low gain units being, for a preferred embodiment, current mirrors formed by two respective transistors to, respectively, copy the current from the output nodes. The high gain current mirror includes a saturation control circuit dedicated to stabilizing the operating point of the stage on a common basis.

The outputs of the current mirrors mentioned in the previous paragraph, are connected to the inputs of respective devices of a front stage providing different reading paths, according to an applied embodiment, or possible use, such as that related to the amplifier prototype for single photon detectors (PMT and SiPM) built by the present inventors and designed for the "Cherenkov observatory

Telescope Array "(CTA) (http://www.ctaobservatory.org), which will be described in a subsequent section. For a second applied embodiment, or possible use, related to a reading system, the output of the current mirror of high gain is connected to the input of a unit of measurement of time, and at least the output of the mirror of low gain current is connected to the input of a unit of measurement of energy, the measurement units belonging to a reading system .

Depending on the embodiment, part or all of the transistors that form the different sections of the circuit in current mode of the first frontal stage of the first aspect of the invention are transistors are FET and / or BJT.

Other embodiments of the current mode circuit of the first frontal stage of the invention are described in the appended claims 2 to 25, and in a subsequent section related to the detailed description of various embodiments.

A second aspect of the invention relates to an integrated circuit comprising the current mode circuit of the first aspect. The integrated circuit is implemented, for one embodiment, in BiCMOS technology. Throughout the description and the claims the word "comprises" and its vanes are not intended to exclude other technical characteristics, additives, components or steps. For those skilled in the art, other objects, advantages and features of the invention will be derived partly from the description and partly from the practice of the invention. The following examples and drawings are provided by way of illustration, and are not intended to be limiting of the present invention. In addition, the present invention covers all possible combinations of particular and preferred embodiments indicated herein. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 schematically shows the current mode circuit of the invention, for one embodiment. Figure 2 shows the internal circuit of the common base / door entry stage shown in Figure 1, for one embodiment.

Figure 3 shows an alternative circuit to that illustrated in Figure 2, for another embodiment implementing a helmeted scheme.

Figure 4 shows a scheme similar to that of Figure 3, but including a voltage feedback circuit.

Figure 5 shows a scheme similar to that of Figure 4, but in this case including a current feedback circuit.

Figure 6 shows a low gain current mirror, alternative to that illustrated in Figure 1, for an embodiment including a common base amplifier and a hull scheme. Figure 7 also shows a high gain current mirror, alternative to that illustrated in Figure 1, for an embodiment including a common base amplifier, a casted scheme and a control circuit. Figure 8a shows an alternative embodiment to that illustrated in Figure 7, implementing a different control circuit.

Figure 8b shows an alternative embodiment to that illustrated in Figure 8a, adding adjustability to the saturation limit.

Figures 9a, 9b and 9c are graphs related to a prototype called PACTA designed and constructed to implement the circuit in the first frontal stage current mode of the present invention, for one embodiment, where Figure 9a shows the input pulses applied, and Figures 9b and 9c show respectively the high and low gain outputs thereof, for different amplitudes of the input pulse;

Figures 10a and 10b show the transfer function of the transimpedance gain for the high and low gain paths, obtained from the PACTA prototype, for, respectively, peak-to-peak values and values in terms of load (integral of the pulse).

Figures 1 1 a and 1 1 b are graphs showing the relative non-linearity for, respectively, the transimpedance gain and the load gain.

Figure 12 shows the frequency response for small signal of the high gain and low gain paths of the PACTA prototype. Figure 13 shows the single photoelectron spectrum measured with the PACTA prototype at the nominal gain of the PMT (4.5x10 ⁴ ).

Figure 14 shows the circuit in the first frontal stage current mode of the first aspect of the invention applied to precise measurements of time and energy.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS The current mode circuit described in this invention was designed, in the form of a preamp, for an amplifier with the following set of demanding requirements:

Bandwidth greater than 500 MHz

Dynamic range of about 16 bits:

 - Noise threshold of about 500 nA rms, this translates into a spectral distribution of noise power referred to the input of about 10 pA / root (Hz), for a reading in current mode and the required BW.

 - Maximum peak current exceeding 20 mA.

Low input impedance (<20 Ohm)

 Relative nonlinearity error below 2%

Low voltage operation:

- Minimization of power consumption.

 - Implemented as an integrated circuit.

In order to comply with bandwidth, input impedance and low voltage operation, a current mode solution is chosen. However, it is very difficult to achieve the required dynamic range, even with a very low noise scheme ([4], [5]). For this reason, a two-gain preamp system has been investigated and proposed by the present invention. A classic solution of double gain creation by current mirrors [6] is not valid for this application, since the search for high dynamic range (> 20 mA) leads to an increase in the W / L ratio of transistors and this it causes degradation of bandwidth in the event that transistors of minimum length are already used, which is necessary for broadband applications. Therefore, amplifiers in which all input current is detected by a single current mirror have a compromise between dynamic range and bandwidth. On the contrary, a new solution based on the generation of the double gain per current division in the first frontal stage of the circuit has been explored by means of a common base / door entry stage, as provided by the present invention. The invention described herein is to divide the input current flowing through the common base input stage (in the case of BJT transistors) or common gate (in the case of FET transistors), as shown in Figure 1. This is achieved by dividing the transistor into common base or gate into n + 1 equal and paired components. The transistor level implementation is described below. In order to perform a precise current division the operating point of all paired components arranged in parallel must be almost equal. The input current is divided by a factor na 1 simply by connecting the collector (or drain terminal) of n paired devices, so that most of the input current (ideally a n / n +1 factor) flows through the High gain path, while only about 1 / n +1 of the input current flows through the low gain path. This idea is based on a precise current division even when the high gain path enters saturation. The method of sensing the current after division is as important as the mechanism for dividing the input current; because, as stated above, the operating point of all paired parallel components must be as similar as possible due to second-order effects such as the Early effect or the modulation of the channel length. This is very complicated when considering the intention to work with high currents (peak currents of up to 20 mA). In fact, the limiting factor is not the peak current value since, for example, the W / L ratio of M1 in Figure 1 can be increased as much as necessary to minimize the voltage variation in node a. However, this leads to a lower BW, since anyway, minimum channel length must be used to maximize the BW. Therefore, what really is a challenge is to preserve the dynamic range (maximum current) and high frequency (BW) performance

simultaneously. This is something that relates to the present invention.

Basically, there are the following two ways of sensing the AC current of the common base (door) stage:

- Using a transimpedance amplifier. For linear operation in small signal it is able to provide low input impedance, by both the voltage at the collector (drain) terminal of the common base (gate) transistor (node a in Figure 1) is stable as required. However, for large input currents the high gain path will be saturated and the feedback as regards the input impedance is lost.

- Using a power mirror. High frequency current mirrors can provide high bandwidth and low input impedance using adequate internal feedback [20]. However, large currents also lead to mirror saturation (some transistors will enter the ohmic region). This is not a problem as long as the current division block works properly since the signal will be read by the low gain path. But a large current in conventional current mirrors will lead to a variation in voltage at the node that could affect the accuracy of the current division. A new circuit is introduced in the high gain current mirror to avoid it (block "Saturation control circuit" in Figure 1), this is also part of the invention and will be described at the transistor level later. The basic scheme of the current division in the common base stage is depicted in Figure 2 at the transistor level, for one embodiment. The input current is divided by a factor n + 1 as long as the transistors Q _n to Q ₀ are in the region of active linear operation (saturation for FETs) and are equal and paired. Disposal techniques such as the common barycenter of transistors Q _n to Q ₀ make precise pairing possible. As in the current mirrors, the current of the different branches must be the same because the base-emitter voltage (or door-source) is the same by construction for all transistors (as long as these are the same). Of course, if second-order effects are considered, the mating of currents also depends on the collector-emitter (drain-source) voltage, and therefore on the variation in voltage at nodes a and b.

It is possible to linearize the transconductance, and therefore the input impedance, of the transistors by emitter degeneration; if a resistor is connected between the emitter terminal of each transistor and the input node and all resistors are also paired, the current division is still properly performed. In fact, it can improve the accuracy of the current division in technologies in which the

mating of resistors is better than that of transistors, which is a typical case. It is well known that emitter degeneration is used in bipolar current mirrors to increase input and output impedances and improve mating [21]. Although it will not be remembered for each version of the circuit, emitter degeneration (or source) can be used in any of the following variations of the basic circuit.

This is a class AB circuit, since the peak current can greatly exceed the idle current established by Ibias. The value of the Ibias polarization current source depends on a compromise between:

- Lower the Ibias current, which decreases the parallel noise and increases the maximum peak current; therefore, the smaller Ibias is, the greater the dynamic range.

- Increase the Ibias current, which increases the transconductance - and therefore decreases the input impedance - and increases the bandwidth and also the linearity for small signals.

As mentioned before, the accuracy of the current division also depends on an adequate agreement on the potentials of nodes a and b, to minimize the impact of the Early effect on BJTs or that of the modulation of the channel length on FETs. This concordance must be preserved for the entire dynamic range. A similar problem can be found in current mirrors, and as shown in the embodiment of Figure 3, a typical method is used to stabilize the collector-emitter (drain-source) voltage of each transistor Q¡ which consists of adding a hull transistor Q _c ¡in series with each of them. In this way, the effect of the voltage variation in the nodes a and b has much less impact on the collector-emitter (drain-source) voltage of Q¡ (the output impedance is increased) provided that the casted transistors Q _c work also in the active linear region

(saturation for FETs).

As mentioned before, it may be useful to reduce the input impedance of the cuircuit, which is

where G _m = gm without emitter degeneration; gm is the transconductance of each of the transistors in common base (gate) Q¡. With degeneration of emitter Re, Gm = gm / (1 + gmRe). Using voltage feedback ([4], [19]) the input impedance remains

where A is the gain of the error amplifier of Figure 4. This type of feedback is applied directly to the preamplifier of the invention, for one embodiment. The error amplifier must be of high bandwidth to avoid significant inductive effects on the input impedance, this is typically implemented as a common emitter (source) stage.

Also with the amplifier, all transistors of this stage must operate in the active linear region.

Current feedback of the style described in [9] or [6] degrades the accuracy of the current division, because a large fraction of the input current is taken by the feedback and the effect of dynamic variation on the division Current is not well controlled as it is in our proposal. However, an alternative current feedback is implemented, for another embodiment, based on a common base transistor (gate) Q _F and a differential broadband transimpedance amplifier (TIA), as shown in Figure 5. The input impedance would be then,

When compared to a voltage feedback where A is a common emitter (source) stage, this feedback is interesting for the following reasons:

 - Low voltage operation. The required margin is decreased by 1 voltage Vbe (or Vgs), that of the common emitter (source) stage of A.

- Lower current consumption, typically the common base transistor (door) Q _F and the TIA in closed-loop broadband have lower power consumption than the broadband voltage amplifier A. The transimpedance bandwidth can be almost as large as the gain frequency unit of the TIA amplifier.

 - The voltage at the base (gate) of transistors Q¡ is precisely controlled by a negative feedback loop (provided that the TIA amplifier has low output impedance). The scheme of the basic current mirror M1 / M2, used for the low-gain path is described in Figure 6, for an embodiment including the casted transistors M1 c and M2c (Figure 1 shows a simpler embodiment where both mirrors of High and low gain current do not include such casted transistors). It is a high frequency current mirror with the following characteristics [20]:

 - Cascodo (M1 c / M2c): to improve linearity and current matching, even for FETs with a channel length close to the minimum size.

- Amplifier in door (base) common Mcg. Feedback decreases the input impedance. The current source l _ba is needed to polarize this amplifier. Mcg can be a FET or a BJT.

The scheme depicted in Figure 6 works well when all transistors operate in saturation (for FETs) or in the linear active region (for BJTs). This is the case for the low gain path for the entire dynamic range. However, when the input current grows some of the transistors in the current mirror may enter the ohmic region (for FETs, saturation for BJTs). This happens for the current mirror of the high gain path. This is not a problem as long as the current division described in the previous section works accurately because the low gain path will provide the output signal. But, if some transistors are working in the ohmic region, the higher The drain current of M1 and M1 c lower will be the voltage at the drain of M 1 c, and if it is excessively low it will affect the operation of the current splitting circuit, because the current transistors Q _c in Figure 3 or Figure 4 will enter the saturation region and the division will no longer be precise.

To avoid this problem, the power mirror of Figure 6 must be modified to be used in the high gain path, adding a control circuit to prevent the malfunction of the stage in common base / door avoiding that, in case of high input current, transistors Q ₀ , ... Q _n ; Qco, - Qcn of the common base / gate stage enter the saturation region, if they are BJTs, or in the ohmic region, if they are FETs.

The control circuit is arranged in the high gain current mirror to avoid a significant voltage variation in the drain / collector node of the transistor that is connected to the output node a of the first group (see Figure 1) of the stage of common base / door, providing an alternative path to the excessive current part of the input current.

For the embodiments illustrated by Figures 7, 8a and 8b, the transistor is the hull transistor M1 c, but for a simpler embodiment that does not include the hull transistor, this would be the M1 transistor.

Figures 7, 8a and 8b illustrate different embodiments of the control circuit (designated as a saturation control circuit, although as stated above prevents the common base / gate stage from entering saturation or ohmic region, depending on the type of used transistors), having in common that they include, to provide the alternative path, a common base transistor Qcb (which for the illustrated embodiment is a BJT transistor, but for other embodiments it is a FET) with its emitter connected to the output node a of the first group of the common base / door stage and its collector connected to the transistor door of the current mirror M1, M2.

For the embodiment of Figure 7, the control circuit further comprises, to provide the alternative path, two transistors connected as diodes Qod and Qoc2 with the collector of one Q _oc i of them connected to the sources of the transistors of the current mirror M1, M2 and the emitter of the other Q _0C 2 connected to the doors / bases of the current mirror transistors M1 / M2. The idea is to avoid a significant variation in voltage at the drain of M1 c by causing excess current to flow through the common base transistor Q _C b and through the transistors connected as diodes Q _oc i and

The gate-source voltage (Vgs) of M1 is proportional (quadratically in strong inversion) to its drain current. For the quiescent current, M1 is sized so that its Vgs is such that the collector current of Qod and Qoc2 is almost negligible. For small input currents, the base-emitter voltage (Vbe) of Q _oc i and Qoc2 is still below the conduction value. But for large input currents, when the Vgs of M1 is approximately twice the conduction value of the transistors connected as diode Q _oc i and Qoc2, the current of these diodes will be appreciable and as it grows exponentially with the Vgs voltage of M1, any Excess current will circulate through the branch consisting of by Qcb, Qod and Qoc2- Given no excess current will circulate through the branch M1 / M1 c, the variation of the voltage at the drain of M1 c will not be significant. For this reason, in the illustrated embodiments of Figures 7, 8a and 8b, a BJT (Qcb) is used for the common base amplifier, but the use of an FET is also contemplated for other non-illustrated embodiments.

As stated before, the control circuit of Figure 7 can also be applied to simple current mirrors, without casted transistors. An improved control circuit is shown in Figure 8a which, apart from the common base (or gate) transistor mentioned above Q _C b, also comprises, to provide the alternative path, a transistor Q _oc i with its collector connected to the sources / emitters of the current mirror transistors M1 / M2, its transmitter connected to the doors / bases of the current mirror transistors M1 / M2 and its base connected to the drain / collector of the current mirror transistor M2 that is not connected to the output node a of the first group of the common base / door stage (see Figure 1).

The transistor Q _oc i is controlled by the voltage Vc-Vm, which is equal to its Vbe: - At rest or for low currents (when the high gain path works) the circuit is designed so that Vc-Vm << Vbe_ON, where

Vbe_ON is the conduction voltage of Q _oc i - Therefore, for currents of Low input This current mirror works like a normal HF current mirror and the high gain path is valid.

- When the input current grows, the drain current of M1, M2, M1 c and M2c also grows. Therefore Ve grows for a higher drain current (Vc = Vcas + VgsM2C, and VgsM2C grows with the current), while Vm decreases (Vm = Vcc-VgsM1, VgsM1 grows with the current). When Vc-Vm> Vbe_ON the excess current is taken by Q _oc i -

The conduction point of Q _oc i can be controlled by

dimensions of transistors M1 and M2c and by the voltage of

polarization of the helmeted Veas. In fact, a variation of this control circuit is presented in Figure 8b. In this variation the saturation current limit of the high gain can be controlled by the Vlim voltage, which sets the gate voltage of the casted transistor M3c of a mirror replica that also includes the transistor M3. This mirror can be sub-sized, to avoid degradation of the BW.

The saturation control circuit of Figures 8a and 8b has the following advantages:

- Negative feedback. Once Q _oc i enters conduction (in linear active region): if the drain current grows, Vc-Vm grows, so the Vbe of Qod grows too, then the collector current of Q _oc i grows leading to decrease the drain current of M1 c and thus that of M1.

 - Only one high-speed transistor is needed, so the response is very fast.

 - The circuit in Figure 8b allows you to adjust the saturation limit of the high gain mirror.

The implementation with only CMOS transistors is also possible; Channel n FETs with a large W / L ratio (not illustrated) can replace transistors Q _oc i and Qoc2- The key point is that the corresponding branch does not conduct virtually idle current and absorbs all excess current for currents large input; This can be achieved through proper sizing of transistors (W and L of M1, and FETs that replace Q _oc i and Qoc2) - In fact, all transistors

Illustrated can be FET or BJT transistors, depending on the embodiment. Results of the measures

A prototype, called PACTA, of the preamp for the CTA project that includes the innovations discussed here has been designed and manufactured as an Application Specific Integrated Circuit (ASIC) in the SiGe technology of 0.35 um from Austriamicrosystems, which combines CMOS and BJT devices.

A closed loop differential transimpedance amplifier follows each of the current mirrors presented previously; therefore the preamplifier has a differential voltage output and a transimpedance gain. The current division scheme described in Figure 4 has been used for the prototype, with emitter degeneration for transistors Q¡ and with the circuit described in Figure 8.

Figures 9a, 9b and 9c show respectively the input and output pulses of the high and low gain. The input pulses emulate the shape of the pulses of the fastest PMTs. The high gain path works up to 1 mA input currents

approximately, beyond this threshold the high gain path is saturated. However, the current division functions properly and the low gain operates linearly up to peak input currents of more than 20 mA. It is worth commenting that the saturation time of the high gain path is very short, even for very large currents. This

characteristic makes it possible to use time techniques on threshold or bi-linear amplification for dynamic range compression. The transfer function for both gains is shown in Figures 10a and 10b. As previously mentioned, the high gain path works linearly for input peak currents between 0 and 1 mA. The low gain is quite linear for the entire dynamic range.

The relative linearity error is below 3% (Figure 1 1 a and 1 1 b), both for peak measurements and for load measurements, for the linear range of both gains. Therefore, the dynamic range exceeds 16 bits. The bandwidth of the high and low gain paths is about 500 MHz (Figure 12). The frequency response shows a certain high frequency resonance peak that can be minimized if necessary.

The single photoelectron spectrum (Figure 13) has been measured with PACTA at the nominal gain of the PMT (4.5x10 ⁴ ). The spectral distribution of noise power referred to the input is about 10 pA / root (Hz), this translates into an equivalent noise load ("Equivalent Noise Charge" ENC) of about 5000 electrons for an integration time of about 10 ns.

In short, the preamp works properly and meets the requirements. With regard to the present invention, the PACTA chip constitutes an experimental proof that it works correctly. The following describes different possible applications of the

Preamp or circuit in current mode corresponding to the invention:

Applications of large dynamic range As discussed above, several applications in the field of scientific instrumentation require circuits in current mode of large dynamic range and high bandwidth at the same time, namely:

 - Calorimeters in high energy physics detectors.

 - Observatories and experiments of Astroparticles.

There are other applications for reading photosensors that require high bandwidth for which the application of the innovations discussed here could be investigated, namely:

 - Synchrotrons, neutron spallation sources and other nuclear facilities.

 - Computerized tomography

 - Optical communications

Precise measurements of time and energy

An interesting embodiment of the preamplifier of the invention is presented in Figure 14, where the output of the high gain current mirror is connects to the input of a unit of time measurements, and the output of the low gain current mirror is connected to the input of the unit of energy measurements, the units belonging to a reading system of which ([1], [6]) perform exact measurements of time and energy and where the signal is divided into two paths, for example for TOF systems. A high gain path is used for temporary measurements and a low gain path for energy measurements, since the typical signal is well above the noise threshold (as in the case of PET). However, the dynamic range of systems in classical mode is limited by the dynamic range of the current mirror [6]. The present invention allows the capabilities of the solution to be exploited much better in current mode:

 - Greater dynamic range

 o Lower noise to minimize jitter: Improve temporal accuracy o Highest peak signal: derived from higher signal to minimize jitter: Improve temporal accuracy

 o More flexibility at the sensor operating point (gain) and even at the type.

- A lower input impedance can be achieved without reaching saturation for SiPMs

 o For SiPMs the peak current increases with the decrease of the input impedance

 o Highest peak peak signal: derived from the highest signal to minimize jitter: Improve temporal accuracy

 o Minimize the recovery time for SiPM (only limited by RqCq, where Rq and Cq are the resistance and shutdown capacity respectively).

 - Each current mirror of each path can be optimized

completely or for linearity (eg low gain for energy measurements) or for speed (BW: temporal accuracy).

 o A greater bandwidth can be achieved for the same technology, compared to a solution where a single current mirror serves both paths ([6]).

These considerations are especially important for TOF systems, such as TOF-PET, about which interest has increased during last years. In addition, recent studies [22] argue that the optimal temporal resolution is obtained for rising edge discriminators with a very low threshold, achieving a temporal resolution even better than that of the constant fraction discriminators ("constant fraction"

discriminators "CFDs). This has implications in the dynamic range. The typical signal (51 1 KeV) is about 2000 photons, with a photodetection efficiency of around 50%, and the noise should be at the level of 0.1 photoelectrons to be able to set a very low threshold (although for SiPMs, the frequency of dark counts could force it to increase.) Therefore, the dynamic range for optimal measurements of time and energy is in fact at the level of the 14 bits. Dynamic range is beyond the performance of a classic high frequency current mode solution and the innovation presented here is potentially very interesting for TOF applications, such as TOF-PET.

References

[1] K. Iniewski "Electronics for Radiation Detection", Taylor & Francis, 2010.

[2] Callier, S .; Dulucq, F .; Fabbri, R .; from La Taille, C; Lutz, B .; Martin

Chassard, G .; Raux, L .; Shen, W .; "Silicon Photomultiplier integrated readout chip (SPIROC) for the ILC: Measurements and possible further development," Nuclear Science Symposium Conference Record (NSS / MIC), 2009 IEEE, vol., No., Pp. 42-46, Oct. 24 2009 -Nov. 1 2009

[3] IL148555 "Readout circuit for particle detector"

[4] R. L. Chase and S. Rescia "A linear low power remote preamplifier for the ATLAS liquid argon EM calorimeter", IEEE Trans. I nuc. Sci., 44: 1028, 1997 [5] N. Dressnandt, M. Newcomer, S. Rescia and E. Vernon "LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr Calorimeter", TWEPP-09: Topical Workshop on Electronics for Particle Physics, Paris, France, 21 - 25 Sep 2009

 [6] Corsi, F .; Foresta, M .; Marzocca, C; Kill, G .; Del Guerra, A .; "A self-triggered CMOS front-end for Silicon Photo-Multiplier detectors,", Advances in sensors and Interfaces, 2009. IWASI 2009. 3rd International Workshop on, vol., No., Pp. 79-84, 25-26 June 2009

[7] Herrero-Bosch, V .; Colom, RJ; Gadea, R .; Espinosa, J .; Monzo, JM; Esteve, R .; Sebastia, A .; Lerche, CW; Benlloch, JM; "PESIC: An Integrated Front-End for PET Applications, "Nuclear Science, IEEE Transactions on, vol.55, no.1, pp. 27-33, Feb. 2008

 [8] Powolny, F .; Auffray, E .; Hillemanns, H .; Vase, P .; Lecoq, P .; Meyer, T.C .; Moraes, D .; "A Novel Time-Based Readout Scheme for a Combined PET-CT Detector Using APDs" Nuclear Science, IEEE Transactions on, vol.55, no.5, pp.2465-2474, Oct. 2008

[9] F. Yuan, "Low-Voltage CMOS Current-Mode Preamplifier: Analysis and Design", IEEE Transactions on Circuits and Systems, Vol. 53, No. 1, 2006 [10] V. Radeka, "Electroncis for Calorimeters at the LHC ", Proceedings of the 7 ^th Workshop on Electronics for LHC Experiments, BNL - 68655, Stockholm, Sweden, September, 2001

[1 1] US2008217516 "Photodetector"

 [12] US7825735 "Dual-range linearized transimpedance amplifier system" [13] WO2009046151 "Dual-path current amplifier"

[14] WO2007029191 "Determination of low currents with high dynamic range for optical imaging"

 [15] US2007182506 "Splitter circuit including transistors"

 [16] Moses, W.W .; Ullisch, M .; "Factors influencing timing resolution in a commercial LSO PET camera," Nuclear Science, IEEE Transactions on, vol.53, no.1, pp. 78-85, Feb. 2006 doi: 10.1 109 / TNS.2005.862980

 [17] The CTA Consortium, "Design Concepts for the Cherenkov Telescope Array", August 2010, http://arxiv.org/abs/1008.3703

[18] S. Vorobiov et al., "NECTAr: New Electronics for the Cherenkov

Telescope Array ", Nucí. Instrum. Meth. Article in press (2010),

DOI: 10.1016 / j.nima.2010.08.1 12

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transimpedance amplifier for gigabit optical communication ", Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, 1998.

ISCAS '98, pp. 293-296 vol. 1, 1998

[20] F. Yuan "CMOS Current-Mode Circuits for Data Communications", Springer, 2006.

 [21] Paul R. Gray, Paul J. Hurst, Robert G. Meyer, Stephen H. Lewis,

"Analysis And Design Of Analog Integrated Circuits", 4th Edition, Wiley, 2008.

[22] W. Moses: "TOF PET Issues and constraints", Picosecond Workshop at Clermont Ferrand, 2010

Claims

one . Circuit in first-stage current mode for sensor reading, comprising an input stage for dividing a current input signal into at least two output current signals, characterized in that the input stage comprises a base stage / common door formed by a plurality of transistors (Q ₀ , ... Q _n ) arranged to form at least two groups so that each of them provides, in a respective output node (a, b), one of the at least Two output current signals.

2. Circuit according to claim 1, wherein the first of the at least two groups of transistors (Q ₀ , ... Q _n ), provides, at its output node (a), a current greater than a second group in its output node (b).

3. Circuit according to any of the preceding claims, wherein the first group comprises n branches of transistors in parallel, each formed by at least one transistor (Qi,... Q _n ), and the second group comprises at least one branch of transistor formed by at least one transistor (Q ₀ ).

4. Circuit according to claim 3, wherein the transistors (Q ₀ , ... Q _n ) are equal, or substantially equal, and paired transistors, having equal or close operating points.

5. Circuit according to claim 4, wherein first ends of all transistor branches are mutually connected to a common point where the input current signal enters.

A circuit according to claim 5, wherein a few second ends of the n branches of parallel transistors are connected to the output node (a) of the first group, and a second end of the branch of at least one transistor is connected to the node of exit (b) of the second group.

7. Circuit according to claim 6, wherein each of the transistor branches is formed by a transistor (Q ₀ , ... Q _n ), the first ends being the emitters / sources of the transistors (Q ₀ , ... Q _n ) and the second ends being the collectors / drains thereof, or vice versa, the bases / doors of all transistors (Q ₀ , ... Q _n ) being connected to each other.

8. Circuit according to claim 6, wherein each of the transistor branches is formed by a first transistor (Q ₀ , ... Q _n ) and a second transistor or casted transistor (Qco, - Qcn) connected in series, and where: - the first ends are the emitters / sources of the first transistors (Qo, ... Q _n ) and the second ends are the collectors / drains of the second transistors (Qco, - Qcn), or

- the first ends are the collectors / drains of the first transistors (Q ₀ , ... Q _n ) and the second ends are the emitters / sources of the second transistors (Qco, - Qcn) -

9. Circuit according to any of claims 3 to 8, wherein the branches of at least one transistor comprise only one transistor.

10. Circuit according to any of claims 5 to 9, wherein the common base / gate stage comprises a voltage or current feedback circuit to decrease the input impedance thereof.

eleven . Circuit according to claim 10, wherein the voltage feedback circuit comprises a high-bandwidth error amplifier (A) with its input connected to the common point at which the current signal enters, and with its output connected to the bases / doors of all transistors

(Qo, ... Q _n ).

12. Circuit according to claim 10, wherein the current feedback circuit comprises a common base / gate transistor (Q _F ) and a

high-bandwidth differential transimpedance amplifier (TIA), where the emitter / source of the base / common gate transistor (Q _F ) is connected to the common point where the current signal enters, the negative and positive amplifier inputs High bandwidth transimpedance differential (TIA) are respectively connected to the collector / drain and base / gate of the transistor in base / common gate (Q _F ), and its output is connected to the bases / gates of all transistors (Q ₀ , ... Q _n ) -

13. Circuit according to claim 2 or any of claims 3-12 as long as they depend on claim 2, further comprising at least one high gain unit with an input connected to the output node (a) of the first group and a unit low gain with an input connected to the output node (b) of the second group.

14. Circuit according to claim 13, wherein the high and low gain units are current mirrors formed by at least two respective transistors (M1, M2) to respectively copy the current from the output nodes (a, b ).

15. Circuit according to claim 14, wherein at least the high gain unit comprises a control circuit to prevent the malfunction of the stage in common base / gate avoiding that, in case of a high input current, the transistors (Q ₀ , ... Q _n ; Qco, - Qcn) of the common base / gate stage enter the saturation region, if they are BJTs, or in the ohmic region, if they are FETs.).

16. Circuit according to claim 15, which is arranged in the current mirror so as to avoid a significant variation of the voltage in the node corresponding to the collector / drain of the transistor (M1 or M1 c) connected to the output node (a) from the first group of the common base / door stage, providing an alternative path for the excessive current portion of the high input current.

17. Circuit according to claim 16, comprising, to provide the alternative path, at least one common base / gate transistor (Q _C b) with its emitter / source connected to the output node (a) of the first group of the stage in base / common door and its collector / drain connected to the door / base of the current mirror transistors (M1, M2).

18. Circuit according to claim 17, comprising, to provide the alternative path, two transistors connected as diodes (Q _oc i and C) with the collector / drain of one (Q _oc i) of them connected to the

sources / emitters of the transistors (M1, M2) of the current mirror and the emitter / source of the other (C) connected to the doors / bases of the

transistors (M1, M2) of the current mirror.

19. Circuit according to any of claims 14 to 18, wherein each of the current mirrors comprises casted transistors (M1 c, M2c), each connected in series to a respective one of the current mirror transistors (M1, M2).

20. Circuit according to claim 19 when it depends on claim 16, further comprising, to provide the alternative path, a transistor (Qod) with its collector / drain connected to the sources / emitters of the two transistors of the current mirror (M1 , M2), its emitter / source connected to the doors / bases of the two current mirror transistors (M1, M2), and its base / door connected to the drain / collector of the transistor (M2) of the two transistors (M1, M2) of the current mirror that is not connected to the output node (a) of the first group of the common base / gate stage or of a third transistor (M3) connected in parallel to the two transistors (M1, M2) with their door / base connected to them.

twenty-one . Circuit according to any of claims 14 to 20, wherein the outputs of the current mirrors are connected to the inputs of respective devices of a front stage providing reading paths with different gains.

22. Circuit according to any of claims 14 to 20, wherein the output of the high gain current mirror is connected to an input of a time measurement unit, and at least the output of the low gain current mirror is connected to an input of an energy measurement unit, the measurement units belonging to a reading system.

23. Circuit according to any of the preceding claims wherein at least part of the transistors (Q ₀ , ... Q _n ; Qco, - Qcn; M1, M2; M1 c, M2c; Q _oc i, Qoc2; Qcb) are transistors FET

24. Circuit according to any of the preceding claims wherein at least part of the transistors (Q ₀ , ... Q _n ; Qco, - Qcn; M1, M2; M1 c, M2c; Q _oc i, Qoc2; Qcb) are transistors BJT.

25. Circuit according to any of the preceding claims, comprising at least one preamp.

26. Integrated circuit comprising the circuit in the frontal first current mode as defined in any of the preceding claims.

27.- Integrated circuit according to claim 26, which is implemented in CMOS technology.