ES2390305B1 - FIRST STAGE FRONT STAGE CURRENT MODE FOR READING SENSORS AND INTEGRATED CIRCUIT. - Google Patents

Abstract

First-stage current mode circuit for reading sensors and integrated circuit. # The first circuit comprises an input stage to divide an input current into two or more output currents, stage comprising a base stage / common gate formed by a plurality of transistors Q {sub, O}? Q {sub, n} arranged forming two or more groups so that each of them provides, at a respective output node a, b, one of the two or more signals output current. For a preferred embodiment it further comprises high and low gain mirrors connected, respectively, to the output node a of the first group and to the output node b of the second group, the high-gain current mirror comprising a control circuit to prevent damage common base / door stage operation in case of high input currents.

Description

Front first stage current mode circuit for reading sensors and integrated circuit

5

A first aspect of the present invention relates to a front first stage current mode circuit for sensor reading, particularly for fast photosensors. A second aspect of the invention relates to an integrated circuit comprising the front first stage current mode circuit.

1O

STATE OF THE ART

15 20 25

There are currently many circuits for reading ultra sensitive photosensors such as the photomultiplier tube ("; photomultiplier tube"; PMT) or the silicon photomultiplier ("; silicon photomultiplier", SiPM). To fully exploit the performance of PMTs or SiPMs the following features are desirable: high speed and low input impedance, high sensitivity and large dynamic range (requiring a low noise level) and low voltage operation (required for implementations in integrated circuit), which is achieved by working in current mode. Recently, with the appearance of solid state photomultipliers (SiPM, MPPC, GAPDs, etc.) the interest in circuits in current mode has grown especially for low voltage and high speed applications. The most relevant proposals regarding the background of the present invention are described below. Current mode amplifiers for radiation detection

30

Charge sensitive preamplifiersquot ;, CSP's have been traditionally used as front circuits for reading radiation detectors of many types (semiconductors, photosensors, gaseous, etc.) [1], [2], [3]. However, CSPs are quite limited in speed and therefore not optimal for achieving good temporal resolutions or to minimize the effect of stacking.

35

For this reason, in many applications the current pulse generated by the PMT or SiPM is converted to voltage by a small resistance and then read by a voltage amplifier. Although this works in those

applications is not optimal in terms of noise since this resistance

imposes a compromise between noise and BW. Amplifiers

Closed-loop transimpedance have a better signal to noise ratio

(SNR), however its bandwidth is typically limited by

5

stability problems and its dynamic range by that of the loop amplifier

closed.

Take the reading in current mode with a low impedance stage of

entry is a better solution, typically through a common door or

1st

common base. After this the signal is processed within the chip. This

solution offers several advantages:

-Low noise and high speed can be achieved simultaneously.

-Low input impedance can be useful to improve resolution

temporary, especially for some SiPM [1], and helps to minimize

fifteen

crosstalk and interference problems.

-Helps preserve good dynamic range even for techies

deeply submicron where supply voltage is limited

at 1 or 2 V.

twenty

Current-mode circuits are used in high-energy physics (quot; High

Energy Physicsquot ;, HEP) in large accelerators [4], [5], [8], in image

medical [1], [6], [7], [8], and in optical communications (for reading

photodiodes (PO) or avalanche PO (APD) [9], [19], [20].

25

High dynamic range

Detectors for large HEP colliders have to deal with a

huge dynamic range, especially calorimetry subdetectors

where a dynamic range of more than 15 bits is required. This typically

30

Get it using the following two techniques:

(1) Since, for an integrated circuit, the maximum signal is typically

limited by the maximum supply voltage, the design of a

low noise electronics. An example of current mode amplifier

low noise is [4].

35

(2) Systems with two or more gains are used: the detector signal is divided

or replicate and different gains are applied to each path, which has a

lower dynamic range (usually 12 bits are sufficient).

The following two important points should be considered:

(i) Although a dynamic range of 16 or 17 has been reported for calorimetry

bits, the required bandwidth is below 100MHz. Since the

5

noise is proportional to the square root of the bandwidth this means

that there is a clear compromise between noise (dynamic range) and the width of

band. For example, taking a preamplifier [4], with very low noise

referred to the input (1 OpA / sqrt (Hz)) and assuming a BW of 500 M Hz, the

Dynamic range would be limited to about 14 bits.

1st

(ii) The signal division technique is performed either in the domain of the

voltage, typically by resistive dividers or amplifiers with

different gains ([1 0], [11], [12] or via replica transistors [15]); or

either in the current domain using current mirrors ([13], [6]).

fifteen

Large side width is also required for some applications

medical such as computed tomography ([1], [14]) or for communications

optical ([11]).

Time and energy measurements for medical imaging

twenty

Both HEP, astrophysics and medical imaging require

often precise time measurements with resolutions lower than

100 ps [1], especially for time-of-flight techniques (quot; Time-of-

Fiightquot ;, TOF))

25

It has long been recognized [16] that statistical noise in the

positron electron tomography ("positron emission tomography", PET) is

can reduce by accurately measuring the difference in the time of

arrival of 511 keV photons from the annihilation of the

30

positron. Various integrated circuits for TOF-PET are being developed

[8], [1].

The time signal is usually obtained after discrimination of

the input signal, therefore it is the jitter of the discriminated signal that limits

35

the temporary resolution of the electronics. The random jitter (at) (correlated

with noise) is proportional to noise and inversely proportional to

the slope of the dS / dt signal, therefore, inversely proportional to the BW of the

signal:

5

(one)

Consequently, both SNR (or S / N) and bandwidth must be

optimized to achieve minimum temporal resolution. The circuits in

1st

Running mode can be helpful in achieving this.

As discussed above, current mode circuits have a

higher BW, because all signal nodes are low impedance nodes.

fifteen

In the case of SiPMs, the peak current increases with decreasing

input impedance of the amplifier [1]. This improves the dS / dt term. Without

However, this trend limits the dynamic range of circuits in mode

usual stream. There are the following two typical approaches:

-Allow saturation of the preamplifier and perform energy measurements

twenty

using time over threshold techniques ("Time-over-Threshold", ToT) [8].

-Create a double path, one for temporary measures and one with less

gain, for energy measurements. However, limitations in range

dynamic are still present in these kinds of solutions so

current (in the first front stage) [6].

25

As stated before, [13], i.e. patent application W02009046151,

describes an amplifier that uses the signal division technique by

current mirrors mentioned above. In particular, it includes a

input current mirror that replicates the input current and sends it to

30

Secondary mirrors of respective high and low earnings. For high

input currents some input current mirror transistors

would enter the ohmic region and therefore the precise current replica

would cease. It could be argued that the dynamic range could be increased

increased the W / L of the mirror transistors. However, this leads

35

typically a degradation of bandwidth. In summary, there is a

clear compromise between dynamic range and bandwidth in

current mirrors-based current amplifiers.

EXPLANATION OF THE INVENTION

5 1st 15

It is desirable to offer an alternative to the state of the art that covers the gaps found here, and that, in particular, overcomes the aforementioned drawbacks that exist in the proposals that use techniques for dividing the signal in the current domain by means of mirrors. current. To that end, the present invention provides a front-first-stage current mode circuit for sensor reading, comprising an input stage for dividing an input current signal into two or more output currents, and where, contrary to Known proposals in which all the current is sensed by a current mirror input stage, the input stage of the current mode circuit of the invention characteristically comprises a common base / gate stage formed by a plurality of transistors arranged in two or more groups so that each of them provides, at a respective node, one of the two or more output current signals.

twenty

For one embodiment, the first of the two or more groups of transistors provides, at its output node, a higher current than the second at its output node.

25

The first group of transistors comprises, for various embodiments, n parallel transistor branches, each consisting of one or more transistors, and the second group comprising one or two transistor branches formed of one or more transistors.

30

Each of the branches of transistors is formed, for one embodiment, by a first transistor and a second transistor or cased transistor, connected in series.

35

According to an embodiment, the common base / gate stage comprises a feedback circuit in voltage or current to decrease the input impedance thereof.

The current mode circuit of the first aspect of the invention comprises, for one embodiment, a high gain unit with an input connected to the output node of the first group and a low gain unit with an input connected to the output node of the second group , being the units of high and low gain, for a preferred embodiment, current mirrors formed by two respective transistors to respectively copy the current from the output nodes. The high-gain current mirror includes a saturation control circuit dedicated to stabilizing the operating point of the common-base stage.

The outputs of the current mirrors mentioned in the previous paragraph, are connected to the inputs of respective devices of a front stage, providing different reading paths, according to an applied embodiment, or possible use, such as that related to the prototype amplifier for single photon detectors (PMT and SiPM) built by the present inventors and designed for the observatory "Cherenkov Telescope Arrayquot; (CTA) (http://www.ctaobservatory.org), which will be described in a subsequent section.

For a second applied embodiment, or possible use, related to a reading system, the output of the high gain current mirror is connected to the input of a time measurement unit, and at least the output of the gain current mirror Low is connected to the input of an energy measurement unit, the measurement units belonging to a reading system.

Depending on the embodiment, part or all of the transistors that make up the different sections of the current mode circuit of the first front stage of the first aspect of the invention are transistors are FET and / or BJT.

Other embodiments of the current mode circuit of the first front stage of the invention are described in appended claims 2 to 25, and in a subsequent section related to the detailed description of various embodiments.

A second aspect of the invention relates to an integrated circuit comprising the current mode circuit of the first aspect.

The integrated circuit is implemented, for one embodiment, in BiCMOS technology.

5 1st

Throughout the description and claims the word quot; comprisesquot; and its variants are not intended to exclude other technical characteristics, additives, components or steps. For those skilled in the art, other objects, advantages, and features of the invention will emerge in part from the description and in part from the practice of the invention. The following examples and drawings are provided by way of illustration, and are not intended to be limiting of the present invention. Furthermore, the present invention covers all possible combinations of particular and preferred embodiments indicated herein.

fifteen

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 schematically shows the current mode circuit of the invention, for one embodiment.

twenty

Figure 2 shows the internal circuit of the common base / door entry stage shown in Figure 1, for one embodiment.

25

Figure 3 shows an alternative circuit to that illustrated in Figure 2, for another embodiment implementing a cascaded scheme. Figure 4 shows a diagram similar to that of Figure 3, but including a voltage feedback circuit.

30

Figure 5 shows a diagram similar to that of Figure 4, but including in this case a current feedback circuit.

Figure 6 shows a low gain current mirror, alternative to that illustrated in Figure 1, for an embodiment including a common base amplifier and a schematic schematic.

Figure 7 also shows a high gain current mirror,

alternative to that illustrated in Figure 1, for an embodiment including a common base amplifier, a schematic schematic, and a control circuit.

Figure 8a shows an alternative embodiment to that illustrated in Figure 7, implementing a different control circuit.

Figure 8b shows an alternative embodiment to that illustrated in Figure 8a, adding adjustability to the saturation limit.

Figures 9a, 9b and 9c are graphs related to a prototype called PACTA designed and built to implement the front first stage current mode circuit of the present invention, for an embodiment, where Figure 9a shows the applied input pulses, and Figures 9b and 9c show respectively the high and low gain outputs thereof, for different amplitudes of the input pulse;

Figures 1 Oa and 1 Ob show the transfer function of the transimpedance gain for the high and low gain paths, obtained from the PACTA prototype, for, respectively, peak-to-peak and load-term values (pulse integrals). .

Figures 11 a and 11 b are graphs showing the relative non-linearity for, respectively, the transimpedance gain and the load gain.

Figure 12 shows the small signal frequency response of the high gain and low gain paths of the PACTA prototype.

Figure 13 shows the single photoelectron spectrum measured with the PACTA prototype at the nominal gain of the PMT (4.5x104).

Figure 14 shows the front first stage current mode circuit of the first aspect of the invention applied to precise measurements of time and energy.

DETAILED DESCRIPTION OF PARTICULAR REALIZATIONS

The current mode circuit described in this invention was designed, in

preamplifier form, for an amplifier with the following set of

demanding requirements:

5

Bandwidth greater than 500 M Hz

Dynamic range of about 16 bits:

-Noise threshold of about 500 nA rms, this translates into a distribution

noise power spectral referred to the input of about 1 Root Op (Hz),

1st

for a current mode reading and the required BW.

-Maximum peak current exceeding 20 mA.

Low input impedance (lt; 20 Ohm)

Relative nonlinearity error below 2%

Low voltage operation:

fifteen

-Minimization of power consumption.

-Implemented as an integrated circuit.

In order to meet the bandwidth, the input impedance and the

Under low voltage operation a current mode solution is chosen. Without

twenty

However, it is very difficult to achieve the required dynamic range, even with a

very low noise scheme ([4], [5]). For this reason, a system of

amplifier with two gains has been researched and proposed by the

present invention.

25

A classic solution for creating double gain by current mirrors

[6] is not valid for this application, since the search of high rank

dynamic (gt; 20 mA) leads to an increase in the W / L ratio of the

transistors and this causes bandwidth degradation in the event that

transistors of minimum length are already used, which is necessary for

30

broadband applications. Therefore, the amplifiers in which all

the input current is detected by a single current mirror

they present a compromise between dynamic range and bandwidth. For him

On the contrary, a new solution has been explored based on the generation of

the double current division gain in the front first stage of the

35

circuit by means of a common base / gate input stage, as

provided by the present invention.

The invention described here is to divide the flowing input current

through the common base input stage (in the case of transistors

BJT) or common gate (in the case of FET transistors), as

shown in Figure 1. This is accomplished by dividing the transistor into base or gate

5

common in n +1 equal and paired components. Implementation at the level

Transistor is described below. In order to carry out a division of

precise current the point of operation of all paired components

arranged in parallel should be almost the same. The input current is divided

by a factor of n to 1 simply by connecting the collector (or drain terminal)

1st

give paired devices, so most of the current

input (ideally a factor n 1n +1) flows through the high path

gain, while only about 1 1n +1 of the input current

of flows through the low gain path.

fifteen

This idea is based on a precise current division even when the

High gain path enters saturation. The method for sensing the

current after division is as important as the mechanism for

divide the input current; because, as previously stated, the

operating point of all paired parallel components must be

twenty

as similar as possible due to second order effects like the

Early effect or modulation of channel length. This is very complicated

when considering the intention to work with high currents (currents

peak up to 20 mA). In fact, the limiting factor is not the value of the

peak current since, for example, the W / L ratio of M1 in Figure 1

25

can be increased as much as necessary to minimize variation

voltage at node a. However, this leads to a lower BW, given

that anyway, minimum channel length should be used to maximize

the BW.

30

So what is really challenging is preserving the performance of

dynamic range (maximum current) and high frequency (BW)

simultaneously. This is something that relates to the present invention.

Basically, there are the following two ways to sense the AC current of the

35

common base (gate) stage:

-Using a transimpedance amplifier. For linear operation in

small signal is capable of providing low input impedance, for

both the voltage at the collector terminal (drain) of the transistor based

Common (gate) (node a in Figure 1) is stable as required. Without

However, for large input currents the high gain path

will saturate and the feedback in terms of input impedance will

5

misses.

-Using a current mirror. High frequency current mirrors

can provide high bandwidth and low input impedance

using adequate internal feedback [20]. However,

large currents also lead to mirror saturation (some

1st

transistors will enter the ohmic region). This is not a problem as long as

when the current division block works properly since

the signal will be read through the low gain path. But a current

large in conventional current mirrors will lead to a variation of

voltage at the node which could affect the accuracy of the current division.

fifteen

A new circuit is inserted into the high gain current mirror to

avoid it (block "Saturation Control Circuit" in Figure 1), this

it is also part of the invention and will be described at the transistor level more

ahead.

twenty

The basic scheme of current division in the common base stage is

depicted in Figure 2 at the transistor level, for one embodiment. The

input current is divided by a factor n + 1 as long as the

transistors On to Oo are in the region of active linear operation (saturation

for FETs) and are equal and paired. Disposal techniques such as

25

common barycenter of On to Oo transistors make pairing possible

precise. As in current mirrors, the current of the different

branches must be equal because the base-emitter (or gate-source) voltage is equal

by construction for all transistors (provided they are the same).

Of course, if second order effects are considered, the pairing of

30

currents also depends on the collector-emitter voltage (drain-source), and

therefore of the voltage variation in nodes a and b.

It is possible to linearize the transconductance, and therefore the impedance of

input of the transistors by emitter degeneration; if you connect

35

a resistance between the emitter terminal of each transistor and the

input and all resistors are paired also the division of

current is still properly performed. In fact, it can improve the

current division accuracy in technologies where the

pairing of resistors is better than that of transistors, which is a

typical case. It is well known that emitter degeneration is used in

bipolar current mirrors to increase input impedances and

5

output and improve mating [21]. Although it won't be remembered for every

version of the circuit, emitter (or source) degeneration can be used in

any of the following variations of the basic circuit.

This is a class AB circuit, since the peak current can exceed

1st

widely the quiescent current set by lbias. The value of the source

Bias current bias depends on a compromise between:

-Lower the current lbias, which decreases the parallel noise and increases the

peak peak current; therefore, the less lbias the greater the

Dynamic range.

fifteen

-Upload the lbias current, which increases transconductance -and therefore

decreases input impedance-and increases bandwidth and also

linearity for small signals.

As stated before, the accuracy of the current division depends

twenty

also of an adequate agreement in the potentials of the nodes a and

b, to minimize the impact of the Early effect on BJTs or that of modulation

of the length of the channel in FETs. This concordance must be preserved for

the entire dynamic range. A similar problem can be found in mirrors

current, and as shown in the embodiment of Figure 3, a

25

typical method to stabilize the collector-emitter (drain-source) voltage of

each transistor O, which consists of adding a cased transistor Oc, in series

With each one of them. In this way, the effect of the voltage variation in

nodes a and b have much less impact on collector-emitter voltage

(drain-source) of O¡ (the output impedance is increased) whenever the

30

Oc¡ hull transistors also work in the active linear region

(saturation for FETs).

As discussed before, it may be useful to reduce the impedance of

circuit entry, which is

z. = 1 (2)

(n + I) Gm

where Gm = gm without emitter degeneration; gm is the transconductance of each of the transistors on the common base (gate) Q¡. With degeneration of emitter Re, Gm = gm / (1 + gmRe). Using voltage feedback ([4], [19]) the input impedance remains

(3)

where A is the gain of the error amplifier of Figure 4. This type of feedback is applied directly to the preamplifier of the invention, for one embodiment. The error amplifier must be wide bandwidth to avoid significant inductive effects on the input impedance, it is typically implemented as a common emitter (source) stage. Also with the amplifier, all transistors in this stage must operate in the active linear region.

The current feedback of the style described in [9] or [6] degrades the accuracy of the current division, because a large fraction of the input current is taken by the feedback and the effect of dynamic variation in the division current is not well controlled as it is in our proposal. However, alternative current feedback is implemented, for another embodiment, based on a QF common base (gate) transistor and a broadband transimpedance differential amplifier (TIA), as shown in Figure 5. The impedance input would then be,

(4)

When compared to a voltage feedback where A is a stage

in common emitter (source), this feedback is interesting for

following reasons:

-Low voltage operation. The required margin is decreased by 1 voltage

5

Vbe (or Vgs), that of the stage in common emitter (source) of A.

-Lower current consumption, typically the base transistor (gate)

Common QF and Broadband Closed Loop TIA have lower

Power consumption than broadband voltage amplifier A. The

Transimpedance bandwidth can be almost as large as

1st

unity gain frequency of the TIA amplifier.

-The voltage at the base (gate) of transistors Q¡ is controlled with

precision by a negative feedback loop (as long as the

TIA amplifier has low output impedance).

fifteen

The scheme of the basic current mirror M1 / M2, used for the path of

low gain is described in Figure 6, for an embodiment including the

M1 e and M2c sheathed transistors (one embodiment is shown in Figure 1)

simpler where both high and low gain current mirrors do not

include such blasted transistors). It is a high current mirror

twenty

frequently with the following characteristics [20]:

-Hulling (M1 c / M2c): to improve linearity and pairing of

currents, even for FETs with channel length close to size

minimum.

-Common door amplifier (base) Mcg. Feedback decreases the

25

input impedance. Iba current source is needed to polarize

this amp. Mcg can be a FET or a BJT.

The scheme represented in Figure 6 works well when all the

transistors operate in saturation (for FETs) or in the linear active region

30

(for BJTs). This is the case for the low gain path for all

Dynamic range. However, when the input current grows some

of current mirror transistors can enter the ohmic region

(for FETs, saturation for BJTs). This happens for the current mirror

of the high gain path. This is not a problem as long as the

35

current division described in the previous section work exactly

because the low gain path will provide the output signal. But yes

some transistors are working in the ohmic region, the higher

the drain current of M1 and M1 e the lower the voltage in the drain of

M1 e, and if it is excessively low it will affect the operation of the

current division, because current transistors occur in Figure 3 or

Figure 4 will enter the saturation region and the split will no longer be accurate.

5

To avoid this problem, the current mirror in Figure 6 should be

modified to be used on the high gain road, adding a

control circuit to prevent the malfunction of the stage in

common base / door avoiding that, in case of high input current, the

1 O

transistors Oo, ... On; Oco, ... Stage ocn on base / common gate enter

the saturation region, if they are BJTs, or in the ohmic region, if they are FETs.

The control circuit is arranged in the high gain current mirror to

avoid significant voltage variation at the drain / collector node

fifteen

of the transistor that is connected to the output node a of the first group (see

Figure 1) of the common base / gate stage, providing a path

Alternative to the excessive current portion of the input current.

For the embodiments illustrated by Figures 7, 8a, and 8b, the transistor is the

twenty

blasted transistor M1 e, but for a simpler embodiment that does not include

the blasted transistor, this would be transistor M1.

Figures 7, 8a and 8b illustrate different embodiments of the control circuit.

(designated as saturation control circuit, although as has been

25

stated above prevents the common base / gate stage from saturating or

ohmic region, depending on the type of transistors used), taking into account

common including, to provide the alternative path, a transistor based

common Ocb (which for the illustrated embodiment is a BJT transistor, but for

other embodiments is a FET) with its emitter connected to the output node at

30

of the first group of the common base / door stage and its collector connected to

the gate of the transistors of the current mirror M1, M2.

For the embodiment of Figure 7, the control circuit further comprises,

to provide the alternative path, two transistors connected as diodes

35

Ooc1 and Ooc2 with the collector of one Ooc1 of them connected to the sources of the

current mirror transistors M1, M2 and the emitter of the other Ooc2

connected to the gates / bases of the current mirror transistors

M1 / M2. The idea is to avoid a significant variation of tension in the drain

of M1c causing excess current to flow through the transistor at

common base Ocb and through connected transistors like diodes Ooc1 and

Ooc2

5

The gate-source voltage (Vgs) of M1 is proportional (quadratically in

strong investment) to your drain stream. For quiescent current, M1

is dimensioned such that its Vgs is such that the collector current of

Ooc1 and Ooc2 are almost negligible. For small input currents, the

1O

base-emitter voltage (Vbe) of Ooc1 and Ooc2 is still below the value of

driving. But for large input currents, when the Vgs of M1

is approximately twice the conduction value of the transistors

connected as diode Ooc1 and Ooc2, the current of these diodes will be

appreciable and as it grows exponentially with the Vgs voltage of M1,

fifteen

any excess current will flow through the branch consisting of b

Ocb, Ooc1 and Ooc2 · Given that no excess current will circulate through the

branch M1 / M1 e, the variation of the voltage in the drain of M1 e will not be

significant. For this reason in the illustrated embodiments of Figures 7,

8a and 8b, a BJT (Qcb) is used for the common base amplifier, but use

twenty

A FET is also contemplated for other non-illustrated embodiments.

As mentioned before, the control circuit of Figure 7 can be

Also applied to simple current mirrors, without blasted transistors.

25

An improved control circuit is shown in Figure 8a which, apart from the

transistor on common base (or gate) mentioned before Ocb, in addition

it comprises, to provide the alternative path, an Ooc1 transistor with its

collector connected to the sources / emitters of the transistors of the

M1 / M2 current, its emitter connected to the gates / bases of the transistors

30

of the M 1 / M2 current mirror and its base connected to the drain / collector of the

M2 current mirror transistor that is not connected to the output node

a of the first group of the common base / door stage (see Figure 1).

The Ooc1 transistor is controlled by the Vc-Vm voltage, which is equal to its Vbe:

35

-Idle or for low currents (when the path of high gain

works) the circuit is designed so that Vc-Vmlt; lt; Vbe_ON, where

Vbe_ON is the conduction voltage of Ooc1 · Therefore, for currents of

low input this current mirror works like a current mirror

Normal HF and the high gain path is valid. -When the input current grows, the drain current of M1, M2, M1 e and M2c grows too. So Ve grows for a drain stream higher (Vc = Vcas + VgsM2C, and VgsM2C grows with the current), while that Vm decreases (Vm = Vcc-VgsM1, VgsM1 increases with the current). When Vc-Vmgt; Vbe_ON excess current is taken by Ooc1 ·

The Ooc1 conduction point can be controlled by dimensions of transistors M1 and M2c and by means of the polarization of the Veas waterfalls. In fact, Figure 8b shows a variation of this control circuit. In this variation the limit of High gain saturation current can be controlled by voltage Vlim, which sets the gate voltage of the M3c blasted transistor of a mirror replica that also includes the M3 transistor. This mirror It can be undersized to avoid degradation of the BW.

The saturation control circuit of Figures 8a and 8b presents the following advantages: -Negative feedback. Once Ooc1 enters conduction (in region linear active): if the drain current increases, Vc-Vm increases, so the Vbe of Ooc1 grows too, so the collector current of Ooc1 grows leading to decrease the drain current of M1 e and thus that of M1. -It only takes a high speed transistor, so the answer is very fast. -The circuit of Figure 8b allows adjusting the saturation limit of the mirror high gain.

Implementation with only CMOS transistors is also possible; FETs channel n with a large W / L ratio (not shown) can replace the transistors Ooc1 and Ooc2 · The key point is that the corresponding branch does not conduct virtually quiescent current and absorb all excess current for large input currents; this can be accomplished through proper dimensioning of the transistors (W and L of M1, and of the FETs that replace Ooc1 and Ooc2). In fact, all transistors Illustrated may be FETo BJT transistors, depending on the embodiment.

Measurement results

A prototype, called PACTA, of the preamplifier for the CTA project that

includes the innovations discussed here has been designed and manufactured as

5

Application Specific Integrated Circuit (quot; Application Specific lntegrated

Circuitquot ;, ASIC) on the 0.35 um SiGe technology from Austriamicrosystems,

that combines CMOS and BJT devices.

A closed-loop differential transimpedance amplifier follows each

1st

one of the current mirrors presented previously; therefore the

Preamplifier has a differential voltage output and a gain of

transimpedance. The current division scheme described in Figure 4

has been used for the prototype, with emitter degeneration for the

Qi transistors and with the circuit described in Figure 8.

fifteen

In Figures 9a, 9b and 9c the pulses of

input and output gain of high and low gain. The input pulses

they emulate the pulse shape of the faster PMTs. The way of

high gain works up to 1 mA input currents

twenty

approximately beyond this threshold the high gain path is

saturated. However, the current division works properly and the

Low gain operates linearly up to peak input currents of more than

20 mA.

25

It is worth commenting that the saturation time of the high path

gain is very short, even for very large currents. This

feature makes it possible to use time-over-threshold techniques or

bi-linear amplification for compression of the dynamic range. The function of

Transfer for both gains is shown in Figures 1 Oa and 1 Ob.

30

As previously discussed the high gain path works

linearly for peak input currents between 0 and 1 mA. The low

Gain is fairly linear for the entire dynamic range.

The relative linearity error is below 3% (Figure 11 a and 11 b), both

35

for peak measurements as for load measurements, for the linear range of

both gains. Therefore, the dynamic range exceeds 16 bits.

The bandwidth of the high and low gain roads is about 500

MHz (Figure 12). The frequency response shows a certain peak of

high frequency resonance that can be minimized if it is

necessary.

5

The single photoelectron spectrum (Figure 13) has been measured with PACTA at

nominal gain of PMT (4.5x1 04). The spectral power distribution

of noise referred to the input is about 1 Root Op (Hz), this translates into

an equivalent noise load ("Equivalent Noise Charge"; ENC) of about

1st

5000 electrons for an integration time of about 1 Ons.

In summary, the preamplifier works properly and meets the

requirements. As regards the present invention, the PACTA chip

it is an experimental test that it works correctly. TO

fifteen

Next, different possible applications of the

preamplifier or current mode circuit corresponding to the invention:

High dynamic range applications

twenty

As discussed above, various applications in the field of

Scientific instrumentation require wide-range current mode circuits

dynamic and high bandwidth at the same time, namely:

-Calorimeters in high energy physics detectors.

-Observatories and experiments of Astroparticles.

25

There are other photo sensor reading applications that require great

bandwidth for which the implementation of the innovations discussed

here it could be investigated, namely:

-Synchrotrons, neutron spallation sources and other facilities

30

nuclear.

-Computerized tomography

-Optical communications

Accurate measurements of time and energy

35

Figure 14 presents an interesting embodiment of the preamplifier of

the invention where the output of the high gain current mirror is

connects to the input of a time measurement unit, and the output of the

Low gain current mirror connects to the drive input

energy measurements, the units belonging to a reading system of

those who ([1], [6]) make exact measurements of time and energy and where

5

signal is divided into two paths, for example for TOF systems. One Way

high gain is used for temporary measurements and one low gain

for energy measurements, since the typical signal is more than

above the noise threshold (as in the case of PET).

1st

However, the dynamic range of classic mode systems is

limited by the dynamic range of the current mirror [6]. The present

invention allows to better exploit the capabilities of the solution in

current mode:

-Wider dynamic range

fifteen

o Lower noise to minimize jitter: Improve temporal accuracy

o Highest maximum peak signal: derived from the highest signal for

minimize jitter: improve temporal accuracy

o More flexibility in the point of operation of the sensor (gain) and

even in type.

twenty

-A lower input impedance can be achieved without reaching the

saturation for SiPM

o For the SiPM the peak current increases with the decrease of

the input impedance

o Highest maximum peak signal: derived from the highest signal for

25

minimize jitter: improve temporal accuracy

o Minimize recovery time for SiPMs (only limited by

RqCq, where Rq and Cq are the resistance and shutdown capacity

respectively).

-Each stream mirror of each path can be optimized

30

completely or for linearity (eg low gain for measurement of

energy) or for speed (BW: temporal accuracy).

o Greater bandwidth can be achieved for the same

technology, compared to a solution where a single mirror of

current serves both paths ([6]).

35

These considerations are especially important for TOF systems,

such as TOF-PET, about which interest has increased during

last years. Furthermore, recent studies [22] argue that the optimal temporal resolution is obtained for leading edge discriminators with a very low threshold, achieving a temporal resolution even better than that of constant fraction discriminators (CFDs) . This has implications for dynamic range. The typical signal (511 KeV) is about 2000 photons, with a photodetection efficiency of around 50%, and the noise should be at the level of 0.1 photoelectrons in order to establish a very low threshold (although for SiPM, the frequency of Darkness accounts might compel you to increase it.) Therefore, the dynamic range for optimal measurements of time and energy is in fact at the 14-bit level. Clearly, this dynamic range is beyond the capabilities of a classic high-frequency current mode solution, and the innovation presented here is potentially very interesting for TOF applications, such as TOF-PET.

References

[1] K. lniewski quot; Eiectronics for Radiation Detectionquot ;, Taylor & Francis, 201 O.

[2] Callier, S .; Dulucq, F .; Fabbri, R .; de La Taille, C .; Lutz, B .; Martin Chassard, G .; Raux, L .; Shen, W .; quot; Silicon Photomultiplier integrated readout chip (SPIROC) for the ILC: Measurements and possible further development, quot; Nuclear Science Symposium Conference Record (NSS / MIC), 2009 IEEE, vol., No., Pp.42-46, Oct. 24 2009-Nov. 1 2009

[3] IL148555 "Readout circuit for particle detector";

[4] R. L. Chase and S. Rescia quot; A linear low power remote preamplifier for the ATLAS liquid argon EM calorimeterquot ;, IEEE Trans. Nucl. Sci., 44: 1028, 1997

[5] N. Dressnandt, M. Newcomer, S. Rescia and E. Vernon quot; LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr Calorimeterquot ;, TWEPP-09: Topical Workshop on Electronics for Particle Physics, Paris, France , 21-25 Sep 2009

[6] Corsi, F .; Foresta, M .; Marzocca, C .; Matarrese, G .; Del Guerra, A .; quot; A self-triggered CMOS front-end for Silicon Photo-Multiplier detectors, quot ;, Advances in sensors and Interfaces, 2009. IWASI 2009. 3rd lnternational Workshop on, vol., no., pp.79-84, 25- June 26, 2009

[7] Herrero-Bosch, V .; Colom, R.J .; Gadea, R .; Espinosa, J .; Monzo, J.M .; Esteve, R .; Sebastia, A .; Lerche, C.W .; Benlloch, J.M .; quot; PESIC: An lntegrated

Front-End for PET Applications, quot; Nuclear Science, IEEE Transactions on,

vol. 55, no.1, pp.27 -33, Feb. 2008

[8] Powolny, F .; Auffray, E .; Hillemanns, H .; Jarron, P .; Lecoq, P .; Meyer, T.C .;

Moraes, D .; quot; A Novel Time-Based Readout Scheme for a Combined PET-CT

5

Detector Using APDsquot; Nuclear Science, IEEE Transactions on, vol.55, no.5,

pp.2465-2474, Oct. 2008

[9] F. Yuan, quot; Low-Voltage CMOS Current-Mode Preamplifier: Analysis and

Designquot ;, IEEE Transactions on Circuits and Systems, Vol. 53, No. 1, 2006

[1 O] V. Radeka, quot; Eiectroncis for Calorimeters at the LHCquot ;, Proceedings of the

1st

ylh Workshop on Electronics for LHC Experiments, BNL-68655, Stockholm,

Sweden, September, 2001

[11] US2008217516 quot; Photodetectorquot;

[12] US7825735 "Dual-range linearized transimpedance amplifier system";

[13] W02009046151 quot; Dual-path current amplifierquot;

fifteen

[14] W02007029191 quot; Determination of low currents with high dynamic range

for optical imagingquot;

[15] US2007182506 quot; Splitter circuit including transistorsquot;

[16] Moses, W.W .; Ullisch, M .; quot; Factors influencing timing resolution in a

commercial LSO PET camera, quot; Nuclear Science, IEEE Transactions on,

twenty

vol. 53, no.1, pp. 78-85, Feb. 2006 doi: 10.11 09 / TNS.2005.862980

[17] The CTA Consortium, quot; Design Concepts for the Cherenkov Telescope

Arrayquot ;, August 201 O, http://arxiv.org/abs/1 008.3703

[18] S. Vorobiov et al., Quot; NECTAr: New Electronics for the Cherenkov

Telescope Arrayquot ;, Nucl. lnstrum. Meth. Article in press (201 0),

25

DOI: 1 0.1 016 / j.nima.201 0.08.112

[19] Park, S.M .; Toumazou, C .; quot; Low noise current-mode CMOS

transimpedance amplifier for gigabit optical communicationquot ;, Proceedings of

the 1998 IEEE lnternational Symposium on Circuits and Systems, 1998.

ISCAS '98, pp. 293-296 vol.1, 1998

30

[20] F. Yuan quot; CMOS Current-Mode Circuits for Data Communicationsquot ;,

Springer, 2006.

[21] Paul R. Gray, Paul J. Hurst, Robert G. Meyer, Stephen H. Lewis,

quot; Analysis And Design Of Analog lntegrated Circuitsquot ;, 4th Edition, Wiley, 2008.

[22] W. Moses: quot; TOF PET lssues and constraintsquot ;, Picosecond Workshop at

35

Clermont Ferrand, 201 O

Claims (14)

5 1st

1. Front first stage current mode circuit for reading sensors, comprising an input stage for dividing a current input signal into at least two output current signals, characterized in that the input stage comprises a stage in common base / gate formed by a plurality of transistors (Oo, ... On) arranged forming at least two groups so that each of them provides, at a respective output node (a, b), one of the at least two output current signals.

15 20

2. Circuit according to claim 1, where the first of the at least two groups of transistors (Oo, ... On), provides, at its output node (a), a current greater than a second group at its output (b). 3. Circuit according to any of the preceding claims, where the first group comprises n branches of transistors in parallel, each one formed by at least one transistor (01, ... On), and the second group comprises at least one branch of transistor formed by at least one transistor (Oo). 4. Circuit according to claim 3, where the transistors (Oo, ... On) are equal, or substantially equal, and paired transistors, having equal or close operating points.

25

5. Circuit according to claim 4, where first ends of all the branches of transistors are mutually connected to a common point where the input current signal enters.

30

Circuit according to claim 5, where a few second ends of the n branches of transistors in parallel are connected to the output node (a) of the first group, and a second end of the branch of at least one transistor is connected to the node of output (b) of the second group.

35

7. Circuit according to claim 6, where each of the branches of transistors is formed by a transistor (Oo, ... On), the first ends being the emitters / sources of the transistors (Oo, ... On) and the second ends being the collectors / drains thereof, or vice versa,

the bases / gates of all transistors (Oa, ... On) being connected

each.

8. Circuit according to claim 6, where each of the branches of

5

transistors consists of a first transistor (Oa, ... On) and a second

transistor or cascade transistor (Oca, ... Ocn) connected in series, and where:

-the first ends are the emitters / sources of the first transistors

(Oa, ... On) and the second ends are the collectors / drains of the

second transistors (Oca, ... Ocn), or

1st

-the first ends are the collectors / drains of the first

transistors (Oa, ... On) and the second ends are the emitters / sources of

the second transistors (Oca, ... Ocn).

9. Circuit according to any of claims 3 to 8, where the branches of

fifteen

at least one transistor comprise only one transistor.

1O. Circuit according to any of claims 5 to 9, where the step of

common base / door comprises a voltage feedback circuit or

current to decrease its input impedance.

twenty

11. Circuit according to claim 1 O, wherein the feedback circuit of

voltage comprises a wide bandwidth error amplifier (A) with

its input connected to the common point where the current signal enters, and

with its output connected to the bases / gates of all transistors

25

(Oa, ... On).

12. Circuit according to claim 1 O, wherein the feedback circuit of

current comprises a common gate / base transistor (OF) and a

high bandwidth transimpedance differential amplifier (TIA),

30

where the emitter / source of the base / common gate (OF) transistor is

connected to the common point where the current signal enters, the inputs

negative and positive transimpedance differential amplifier (TIA) of

large bandwidth are respectively connected to the collector / drain

and base / gate of the transistor in base / common gate (OF), and its output is

35

connected to the bases / gates of all transistors (Oa, ... On).

13.

Circuit according to claim 2 or any of claims 3-12 insofar as they depend on claim 2, which further comprises at least one high gain unit with an input connected to the output node (a) of the first group and a gain unit It goes down with an input connected to the output node (b) of the second group.

14.

Circuit according to claim 13, where the high and low gain units are current mirrors formed by at least two respective transistors (M1, M2) to respectively copy the current coming from the output nodes (a, b).

fifteen.

Circuit according to claim 14, where at least the high gain unit comprises a control circuit to prevent the malfunction of the stage in base / common gate preventing that, in case of a high input current, the transistors (Oo, .. .On; Oco, ... Ocn) of the common base / gate stage enter the saturation region, if they are BJTs, or the ohmic region, if they are FETs.).

16.

Circuit according to claim 15, which is arranged in the current mirror so as to avoid a significant variation in the voltage at the node corresponding to the collector / drain of the transistor (M1 or M1 e) connected to the output node (a) of the first Common base / gate stage group, providing an alternative path for excessive current portion of the high input current.

17.

Circuit according to claim 16, comprising, to provide the alternative path, at least one common base / gate transistor (Ocb) with its emitter / source connected to the output node (a) of the first group of the base / gate stage and its collector / drain connected to the gate / base of the current mirror transistors (M1, M2).

18.

Circuit according to claim 17, comprising, to provide the alternative path, two transistors connected as diodes (Ooc1 and Ooc2) with the collector / drain of one (Ooc1) of them connected to the sources / emitters of the transistors (M1, M2 ) of the current mirror and the emitter / source of the other (Ooc2) connected to the doors / bases of the transistors (M1, M2) of the current mirror.

5

19. Circuit according to any one of claims 14 to 18, wherein each of the current mirrors comprises cased transistors (M 1e, M2c), each connected in series to a respective one of the current mirror transistors (M1, M2).

1st 15

20. Circuit according to claim 19 when it depends on claim 16, further comprising, to provide the alternative path, a transistor (Ooc1) with its collector / drain connected to the sources / emitters of the two current mirror transistors (M1 , M2), its emitter / source connected to the gates / bases of the two transistors of the current mirror (M1, M2), and its base / gate connected to the drain / collector of the transistor (M2) of the two transistors (M1, M2) of the current mirror that is not connected to the output node (a) of the first group of the common base / door stage or of a third transistor (M3) connected in parallel to the two transistors (M1, M2) with its door / base connected to theirs.

twenty

21. Circuit according to any of claims 14 to 20, where the outputs of the current mirrors are connected to the inputs of respective devices of a front stage providing reading paths with different gains.

25

22. Circuit according to any one of claims 14 to 20, wherein the output of the high gain current mirror is connected to an input of a time measurement unit, and at least the output of the low gain current mirror is connected to an input of an energy measurement unit, the measurement units belonging to a reading system.

30

23. Circuit according to any of the preceding claims where at least part of the transistors (Oo, ... On; Oco, ... Ocn; M1, M2; M1c, M2c; Ooc1, Ooc2; Ocb) are FET transistors.

35

24. Circuit according to any of the preceding claims where at least part of the transistors (Oo, ... On; Oco, ... Ocn; M1, M2; M1c, M2c; Ooc1, Ooc2; Ocb) are BJT transistors.

25.

Circuit according to any of the preceding claims, which it comprises at least one preamplifier.

26.

Integrated circuit comprising the front first stage current mode circuit as defined in any one of the preceding claims.

27.-Integrated circuit according to claim 26, which is implemented in CMOS technology.