WO2012137472A1 - Active matrix substrate and liquid crystal display device - Google Patents

Active matrix substrate and liquid crystal display device Download PDF

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Publication number
WO2012137472A1
WO2012137472A1 PCT/JP2012/002296 JP2012002296W WO2012137472A1 WO 2012137472 A1 WO2012137472 A1 WO 2012137472A1 JP 2012002296 W JP2012002296 W JP 2012002296W WO 2012137472 A1 WO2012137472 A1 WO 2012137472A1
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Prior art keywords
data
liquid crystal
gate
lines
pixel
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PCT/JP2012/002296
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French (fr)
Japanese (ja)
Inventor
誠二 金子
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シャープ株式会社
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present invention relates to an active matrix substrate and a liquid crystal display device.
  • the present invention relates to an active matrix substrate and a liquid crystal display device that can be driven at a low frequency and suppress display deterioration due to flickering of screen luminance.
  • Measures for reducing the power consumption of the display panel include increasing the aperture ratio of the panel in order to ensure excellent luminance and driving the panel at a low frequency.
  • the output of adjacent pixels is set to have a reverse polarity (dot inversion drive). This is because, by setting the outputs of adjacent pixels to opposite polarities, writing is averaged between the positive polarity and the negative polarity, and flicker becomes difficult to be visually recognized.
  • Patent Document 1 alternately generates a first timing signal corresponding to a first timing at which a positive drive voltage is to be applied and a second timing signal corresponding to a second timing at which a negative drive voltage is to be applied.
  • a timing generation driver for outputting to each of the liquid crystal display cells connected to the first data driver via the first data line and corresponding to the first timing signal input via the first gate line.
  • the first switching element for applying voltage to the second liquid crystal display cell connected to the second data driver via the second data line and input via the second gate line to the corresponding one liquid crystal display cell.
  • a liquid crystal display device including a second switching element that applies a voltage is disclosed.
  • the polarity of the drive voltage applied to the adjacent liquid crystal display element can be reversed without inverting the polarity of the data line drive voltage every horizontal period. It is described that a high-quality display without occurrence of luminance unevenness can be obtained and that the power consumed by driving the liquid crystal panel can be reduced.
  • Patent Document 1 Japanese Patent Document 1
  • two types of data drivers are required per panel, and a large amount of power is required to drive each data driver, and the manufacturing cost increases.
  • two gate lines and two data lines are required per pixel, the aperture ratio is reduced, and the power consumption of the backlight is increased accordingly.
  • An object of the present invention is to perform high-speed writing in an active matrix substrate and a liquid crystal display device including the same, thereby reducing power consumption and further reducing manufacturing costs.
  • the active matrix substrate of the present invention is m ⁇ n pixel units arranged in a matrix of m rows and n columns (m and n are integers of 2 or more);
  • the m first gate lines and the m second gate lines respectively corresponding to the m pixel rows of the m ⁇ n pixel portions extend in parallel with each other in the row direction and are spaced apart from each other in the column direction.
  • the gate line Including a data line to which a positive data signal is applied and a data line to which a negative data signal is applied, along the column direction so as to partition n pixel columns of the m ⁇ n pixel units.
  • each of the m pixel units included in the kth column (1 ⁇ k ⁇ n) pixel column is A liquid crystal element;
  • the (k + 1) th column data line and And a second switching element that switches a connection state with the liquid crystal element In response to a control signal disposed between the first and second gate lines corresponding to the pixel portion and applied to the other of the first and second gate lines, the (k + 1) th column data line and And a second switching element that switches a connection state with the liquid crystal element.
  • the pixel portion (herein referred to as the first pixel portion) included in the k-th pixel column, and the pixel column adjacent to it in the row direction and in the k + 1-th column (1 ⁇ k ⁇ n) will be described with respect to the pixel portion included in the pixel (here, the second pixel portion).
  • a positive data signal is applied to the kth and k + 2th data lines
  • a negative data signal is applied to the k + 1th data line
  • the first The first switching element of the pixel portion is provided to switch a connection state between the data line of the kth column and the liquid crystal element in response to a control signal applied to the first gate line.
  • a second switching element is provided to switch a connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the second gate line, and the first switching element of the second pixel unit
  • a switching element is provided to switch a connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the first gate line, and the second switching of the second pixel unit Device applied to second gate line It will be described which is provided to switch the connection state between the (k + 2) th column data line and the liquid crystal element in response to a control signal.
  • the control signal is applied to any one of the m first gate lines, while the control signal is not applied to any of the m second gate lines.
  • the control signal is applied to any one of the m second gate lines, while the control signal is not applied to any of the m first gate lines.
  • Driving is performed. Therefore, in the first driving period, when the first gate line corresponding to the first and second pixel portions is selected and the control signal is applied, the first pixel portion responds to the control signal.
  • the first switching element is turned on, and a positive driving voltage is applied to the liquid crystal element via the kth column data line to which the positive data signal is applied.
  • the first switching element is turned on in response to the control signal, and the liquid crystal element is negatively driven through the (k + 1) th column data line to which the negative data signal is applied. A voltage will be applied.
  • the first pixel portion receives a second signal in response to the control signal.
  • the switching element is turned on, and a negative drive voltage is applied to the liquid crystal element via the data line of the (k + 1) th column to which the negative data signal is applied.
  • the second switching element is turned on in response to the control signal, and the liquid crystal element is positively driven through the k + 2th column data line to which the positive data signal is applied. A voltage will be applied.
  • the first switching element of the first pixel unit is provided so as to switch a connection state between the data line of the kth column and the liquid crystal element in response to a control signal applied to the second gate line.
  • a second switching element of one pixel unit is provided to switch a connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the first gate line.
  • the first switching element is provided to switch the connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the second gate line, and Similarly, when the second switching element is provided so as to switch the connection state between the data line of the (k + 2) th column and the liquid crystal element in response to a control signal applied to the first gate line, Dot inversion Motion can be carried out.
  • the polarity of the data signal applied to each data line is not charged / discharged for each frame and inverted, and the drive voltage applied to each liquid crystal element of the adjacent first pixel portion and second pixel portion is determined. Since the polarity can be reversed, the power consumed by driving can be suppressed.
  • two switching elements are provided in one pixel portion, but one data line (here, the data line of the (k + 1) th column (1 ⁇ k ⁇ n))
  • a data signal is supplied to the second switching element of the pixel portion (first pixel portion) included in the k-th pixel row, while the pixel portion (second pixel portion) of the pixel portion (second pixel portion) included in the k + 1-th pixel row. Since the data signal is supplied to one switching element, it is only necessary to arrange one data line in each part that partitions adjacent pixel columns. Therefore, it is not necessary to arrange two data lines per pixel column in order to drive each of the first and second switching elements, and a large aperture ratio of the active matrix substrate can be ensured. The power consumption of the light can be suppressed.
  • the n + 1 data lines are arranged so that the data lines to which the positive data signal is applied and the data lines to which the negative data signal is applied are alternately arranged.
  • These data lines can be driven by a single type of data driver, and power consumption for driving the data driver can be suppressed as compared with the case where a plurality of types of data drivers are provided. Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Furthermore, the frame can be narrower than when a plurality of types of data drivers are provided.
  • the first switching elements or the second switching elements are on both sides of the first gate line and / or the second gate line. It is preferable that they are arranged to face each other.
  • the active matrix substrate of the present invention is preferably arranged so that the first gate lines and the second gate lines are alternately arranged in the column direction.
  • a pair of the first gate line and the second gate line is arranged so as to partition each pixel portion in the column direction. While the control signal is applied to the first gate line in the first driving period, the control signal is not applied to the second gate line, and the control signal is applied to the second gate line in the second driving period. On the other hand, no control signal is applied to the first gate line. That is, since a control signal is not applied to both the first gate line and the second gate line within the same frame, each pair of the first gate line and the second gate line is connected to each other. Even if a pair of both are arranged close to each other so as to partition the pixel portion in the column direction, it is possible to suppress deterioration in driving characteristics due to parasitic capacitance between the first gate line and the second gate line. .
  • the active matrix substrate of the present invention is preferably a thin film transistor (hereinafter also referred to as “TFT”) in which each of the first switching element and the second switching element includes an oxide semiconductor film.
  • TFT thin film transistor
  • each of the first switching element and the second switching element is a TFT including an oxide semiconductor film, high-speed writing drive is possible, and a change in luminance of the screen can be suppressed. It is possible to reduce the change in pixel potential due to TFT off-leak during the writing suspension period. Therefore, display deterioration due to flicker can be further suppressed.
  • the liquid crystal display device of the present invention includes the above-described active matrix substrate of the present invention, In the row direction, the data signals are applied to the n + 1 data lines so that the data lines to be applied with the positive data signal and the data lines to be applied with the negative data signal are alternately arranged in the row direction.
  • a first gate driver that does not apply a control signal to any of the gate lines; In the first driving period, no control signal is applied to any of the m second gate lines, and in the second driving period, any one of the m second gate lines.
  • a second gate driver for applying a control signal to be transmitted to the second switching element It is characterized by providing.
  • each data is arranged such that the data line to which the data driver applies the positive data signal and the data line to which the negative data signal is applied are alternately arranged in the row direction.
  • a signal is applied to each of the n + 1 data lines, and the first gate driver and the second gate driver are connected to any one of the m first gate lines in the first driving period. While the control signal transmitted to the first switching element is applied, the control signal is not applied to any of the m second gate lines, and the m second gates are applied during the second driving period.
  • a control signal to be transmitted to the second switching element is applied to any one of the lines, while a control signal is not applied to any of the m first gate lines.
  • Apply a voltage of Bets can be, also, it is possible to perform dot inversion driving for inverting the polarity of each pixel unit for each drive period.
  • a single type of data driver has alternating data lines to which positive data signals are applied and data lines to which negative data signals are applied in the row direction. Since the data signals are respectively applied to the n + 1 data lines so as to line up with each other, power consumption for driving the data driver can be suppressed as compared with the case where a plurality of types of data drivers are provided. Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Further, the frame can be narrower than when a plurality of types of data drivers are provided.
  • m first gate lines and m second gate lines respectively corresponding to m pixel rows of the pixel portion extend in parallel to each other in the row direction.
  • N + 1 data lines that are arranged and extend so as to partition the n pixel columns of the pixel portion are alternately arranged with data lines to which positive data signals are applied and data lines to which negative data signals are applied.
  • the pixel units are arranged side by side, and each pixel portion is connected to the liquid crystal element and the liquid crystal element in response to a control signal applied to one of the first and second gate lines.
  • the first A control signal is applied to the first gate line in the driving period to turn on the first switching element, and then a control signal is applied to the second gate line in the second driving period to activate the second switching element.
  • the voltage applied to the liquid crystal element in the adjacent pixel portion can be reversed, and the polarity of the voltage applied to each liquid crystal element can be reversed every driving period. That is, dot inversion driving can be performed.
  • the active matrix substrate By driving the active matrix substrate in this way, the polarity of the voltage applied to each liquid crystal element can be reversed without charging and discharging the polarity of the data signal applied to each data line. As a result, driving power can be suppressed.
  • two switching elements are provided in one pixel portion, but one data line (here, the data line in the (k + 1) th column (1 ⁇ k ⁇ n))
  • the control signal is supplied to the second switching element of the pixel unit included in the kth pixel column, while the control signal is supplied to the first switching element of the pixel unit included in the k + 1th pixel column.
  • the control signal is supplied to the first switching element of the pixel portion included in the k-th pixel column, while the control signal is supplied to the second switching element of the pixel portion included in the k + 1-th pixel column. Therefore, it is only necessary that one data line is arranged in each part that partitions adjacent pixel columns. Therefore, it is not necessary to arrange two data lines per pixel column in order to drive each of the first and second switching elements, and a large aperture ratio of the active matrix substrate can be ensured. The power consumption of the light can be suppressed.
  • the n + 1 data lines are arranged so that the data lines to which the positive data signal is applied and the data lines to which the negative data signal is applied are alternately arranged.
  • These data lines can be driven by a single type of data driver, and power consumption for driving the data driver can be suppressed as compared with the case where a plurality of types of data drivers are provided. Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Furthermore, the frame can be narrower than when a plurality of types of data drivers are provided.
  • FIG. 1 is a schematic configuration diagram of a liquid crystal display device of Embodiment 1.
  • FIG. FIG. 2 is an enlarged view of regions of four pixel portions Pjk, Pj (k + 1), P (j + 1) k, and P (j + 1) (k + 1) in FIG. 3 is an operation timing chart of the first embodiment.
  • FIG. 6 is an image diagram for explaining the operation of the first embodiment in (a) a first driving period and (b) a second driving period.
  • the graph which shows the relationship between the writing time and panel surface brightness
  • FIG. 1 shows a schematic configuration of the liquid crystal display device 10.
  • the liquid crystal display device 10 includes a reference voltage generation circuit 11 that generates and outputs a reference voltage of the entire device, a current amplifier 12 that amplifies a voltage signal from the reference voltage generation circuit 11 and outputs the current signal to a data driver 15 described later.
  • a plurality of first gate lines Ga (1), Ga (2),... And a plurality of second gate lines Gb (1), Gb (2),... (Hereinafter referred to as a plurality of second gate lines Gb (1), Gb (2),...) Based on the horizontal synchronization signal.
  • the two gate lines may be collectively referred to as a second gate line Gb.) And a plurality of data lines D (1) and D (2) based on the horizontal synchronization signal. , ... (Hereafter, data is collected from multiple data lines. Also referred to as D.) Of it comprises a single type of data driver 15 for applying a data signal to each of the.
  • the data driver 15 may be configured by one data driver, or may be configured by combining all the same types of data drivers.
  • the first gate line Ga, the second gate line Gb, and the data line D are formed on the active matrix substrate 20.
  • m ⁇ n pixel portions P11, P12,... are arranged in a matrix of m rows ⁇ n columns.
  • m and n are integers of 2 or more.
  • Each of the m ⁇ n pixel portions P is an intersection of the jth pixel row and the kth pixel column at integers j and k where 1 ⁇ j ⁇ m and 1 ⁇ k ⁇ n + 1.
  • the pixel portion Pjk is arranged in the area to be processed.
  • the plurality of first gate lines Ga are provided so as to correspond to m pixel rows of the m ⁇ n pixel portions and to extend in parallel with each other in the row direction.
  • Each of the m first gate lines Ga has the first gate line Ga (j) arranged in the j-th row.
  • a plurality of second gate lines Gb are provided so as to respectively correspond to m pixel rows of the m ⁇ n pixel portions and to extend in parallel with each other along the row direction.
  • Each of these m second gate lines Gb has the second gate line Gb (j) arranged in the j-th row.
  • the first gate line Ga (j) and the second gate line Gb (j) in the j-th row are arranged so as to be separated from each other in the column direction.
  • the n + 1 data lines D are provided so as to extend in parallel with each other along the column direction so as to partition n pixel columns of the m ⁇ n pixel portions P. Each of these n + 1 data lines D has a data line D (k) arranged in the k-th column.
  • the n + 1 data lines D include a data line to which a positive data signal is applied and a data line to which a negative data signal is applied, and a data line to which a positive data signal is applied and a negative data signal. Are arranged so as to be alternately arranged with data lines to which is applied.
  • Each pixel portion P includes a liquid crystal element 21, a first TFT 22 that is a first switching element, a second TFT 23 that is a second switching element, and a storage capacitor 24 for memory.
  • Each of the first TFT 22 and the second TFT includes an oxide semiconductor film as a semiconductor film. Examples of the oxide semiconductor film include indium gallium zinc composite oxide (IGZO).
  • the liquid crystal element 21 has one terminal connected to the counter electrode.
  • the storage capacitor 24 has one terminal connected to the common sources 22S and 23S of the first TFT 22 and the second TFT 23, and the other terminal connected to the counter electrode.
  • the first TFT 22 is disposed between the first gate line Ga (j) and the second gate line Gb (j).
  • the first TFT 22 can switch the connection state between the data line D (k) in the kth column and the liquid crystal element 21 (liquid crystal element CLa) in response to a control signal applied to the first gate line Ga (j).
  • the gate 22G is connected to the first gate line Ga (j) in the j-th row
  • the drain 22D is connected to the data line D (k) in the k-th column
  • the source 22S is connected to the other terminal of the liquid crystal element 21. It is connected to the.
  • the second TFT 23 is disposed between the first gate line Ga (j) and the second gate line Gb (j).
  • the second TFT 23 has a gate so that the connection state between the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 can be switched in response to a control signal applied to the second gate line Gb (j).
  • 23G is connected to the second gate line Gb (j) of the jth row, the drain 23D is connected to the data line D (k + 1) of the (k + 1) th column, and the source 23S is connected to the other terminal of the liquid crystal element 21. It is connected.
  • the first TFT 22 switches the connection state between the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 (liquid crystal element CLb) in response to a control signal applied to the first gate line Ga (j).
  • the gate 22G is connected to the first gate line Ga (j) in the jth row
  • the drain 22D is connected to the data line D (k + 1) in the (k + 1) th column
  • the source 22S is connected to the liquid crystal element 21. Is connected to the other terminal.
  • the second TFT 23 has a gate so that the connection state between the data line D (k + 2) in the (k + 2) th column and the liquid crystal element 21 can be switched in response to a control signal applied to the second gate line Gb (j).
  • 23G is connected to the second gate line Gb (j) of the jth row
  • the drain 23D is connected to the data line D (k + 2) of the (k + 2) th column
  • the source 23S is connected to the other terminal of the liquid crystal element 21. It is connected.
  • the first TFT 22 switches the connection state between the data line D (k) in the kth column and the liquid crystal element 21 (liquid crystal element CLc) in response to a control signal applied to the second gate line Gb (j + 1).
  • the gate 22G is connected to the second gate line Gb (j + 1) in the (j + 1) th row
  • the drain 22D is connected to the data line D (k) in the kth column
  • the source 22S is connected to the liquid crystal element 21. Is connected to the other terminal.
  • the second TFT 23 can switch the connection state between the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 in response to a control signal applied to the first gate line Ga (j + 1).
  • the gate 23G is connected to the first gate line Ga (j + 1) of the (j + 1) th row
  • the drain 23D is connected to the data line D (k + 1) of the (k + 1) th column
  • the source 23S is connected to the liquid crystal element 21. Connected to the other terminal.
  • the first TFT 22 is connected to the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 (liquid crystal element CLd) in response to a control signal applied to the second gate line Gb (j + 1).
  • the gate 22G is connected to the second gate line Gb (j + 1) of the (j + 1) th row
  • the drain 22D is connected to the data line D (k + 1) of the (k + 1) th column
  • the source 22S Is connected to the other terminal of the liquid crystal element 21.
  • the second TFT 23 can switch the connection state between the liquid crystal element 21 and the data line D (k + 2) of the (k + 2) th column in response to a control signal applied to the first gate line Ga (j + 1).
  • the gate 23G is connected to the first gate line Ga (j + 1) in the (j + 1) th row
  • the drain 23D is connected to the data line D (k + 2) in the (k + 2) th column
  • the source 23S is connected to the liquid crystal element 21. Connected to the other terminal.
  • the n + 1 data lines D are arranged such that data lines to which positive data signals are always applied and data lines to which negative data signals are always applied are alternately arranged in the row direction. That is, the data driver 15 always applies a positive data signal to the data line D (o) in the o-th column with respect to the odd integer o (1 ⁇ o ⁇ n + 1) and is an even integer e. A negative data signal is always applied to the data line D (e) of the e-th column with respect to (2 ⁇ e ⁇ n + 1), or for an integer o (1 ⁇ o ⁇ n + 1) which is an odd number.
  • a negative-polarity data signal is always applied to the o-th data line D (o), and the even-numbered integer e (2 ⁇ e ⁇ n + 1) is applied to the e-th data line D (e).
  • e even-numbered integer
  • e negative-polarity data signal
  • a positive data signal is always applied to the data lines D (k) and D (k + 2), and a negative data signal is always applied to the data line D (k + 1).
  • a signal is applied.
  • the first gate driver 13 selects the first gate line Ga (j), and the first gate line Ga (j) becomes H level. Thereby, a control signal is applied to the first TFT 22 of the pixel portion Pjk from the first gate driver 13 to be turned on, and a positive data signal is transmitted from the data driver 15 through the data line D (k). Therefore, a positive drive voltage is applied to the liquid crystal element CLa during the first drive period.
  • a first gate line Ga (j) is becomes H level
  • the control signal from the first gate driver 13 is turned on is applied to the 1TFT22 pixel portion Pj (k + 1), A negative data signal is transmitted from the data driver 15 via the data line D (k + 1). Therefore, a negative drive voltage is applied to the liquid crystal element CLb during the first drive period.
  • the first gate line Ga (j + 1) becomes the H level.
  • the control signal is applied to the second TFT 23 of the pixel portion P (j + 1) k from the first gate driver 13 to be turned on, and the negative polarity is transmitted from the data driver 15 via the data line D (k + 1). Data signals are transmitted. Therefore, a negative drive voltage is applied to the liquid crystal element CLc during the first drive period.
  • the first gate driver 13 selects the forward first following gate line Ga on the basis of the horizontal synchronizing signal, in a first drive period, positive or negative driving voltage to each liquid crystal element Applied.
  • the second gate driver 14 selects the second gate line Gb to (j), the second gate line Gb (j) becomes the H level.
  • a control signal is applied to the second TFT 23 of the pixel portion Pjk from the second gate driver 14 to turn it on, and a negative data signal is transmitted from the data driver 15 via the data line D (k + 1).
  • the Therefore, a negative drive voltage is applied to the liquid crystal element CLa during the second drive period.
  • the second gate driver 14 selects second gate line Gb the (j + 1) at time t 4, the second gate line Gb (j + 1) becomes the H level.
  • a control signal is applied to the first TFT 22 of the pixel portion P (j + 1) k from the second gate driver 14 to turn it on, and positive data from the data driver 15 via the data line D (k).
  • a signal is transmitted. Therefore, a positive drive voltage is applied to the liquid crystal element CLc during the second drive period.
  • the second gate driver 14 selects the forward order second gate line Gb based on a horizontal synchronizing signal, in a second drive period, positive or negative driving voltage to each liquid crystal element Applied.
  • a positive data signal is always applied to the data line D (k) and the data line D (k + 2), and a negative data signal is always applied to the data line D (k + 1).
  • positive, negative, negative, and positive drive voltages are applied to the liquid crystal elements CLa, CLb, CLc, and CLd, respectively.
  • negative, positive, positive, and negative drive voltages are applied to the liquid crystal elements CLa, CLb, CLc, and CLd, respectively. Therefore, the polarity of the data signal applied to each data line D can be reversed between adjacent liquid crystal elements without reversing the polarity, and the voltage applied to each liquid crystal element CLa, CLb, CLc, CLd. Can be inverted every frame.
  • the first gate driver 13, the second gate driver 14, and the data driver 15 are provided outside the active matrix substrate 20, but these are formed in the peripheral region of the active matrix substrate 20. It may be.
  • each liquid crystal element 21 is transmitted by always transmitting a positive polarity data signal or a negative polarity data signal without charging and discharging the polarity of the data signal applied to each data line D. Since the polarity of the voltage applied to can be reversed, driving power consumption can be suppressed. In addition, since the polarity of the voltage applied to each liquid crystal element 21 can be inverted without charging and discharging the polarity of the data signal applied to each data line D, stable control can be performed at high speed. Is possible.
  • FIGS. 5A to 5C show the relationship between the writing time and the panel surface brightness when the flicker pattern is displayed on the screen in the drive that pauses after high-speed writing.
  • the write time for each frame in FIG. 5A is A [msec]
  • FIG. 5B is the write time 2/3 ⁇ A [msec]
  • FIG. 5C is the write time 1/2 ⁇ . A case of A [msec] is shown. From FIG. 5, it is known that as the writing time for each frame becomes shorter, the luminance amplitude becomes smaller and the flickering of the screen luminance is reduced.
  • first TFT 22 and second TFT 23 are provided in one pixel portion P, but one data line D (here, for example, the data line in the (k + 1) th column) D (k + 1)) provides a data signal to the second TFT 23 of the pixel unit Pjk included in the kth pixel column, while the pixel unit Pj (k + 1) included in the k + 1th pixel column.
  • the first TFT 22 is configured to provide a data signal, or a data signal is applied to the first TFT 22 of the pixel portion P (j + 1) k included in the kth pixel column, while the k + 1th column.
  • the data signal is supplied to the second TFT 23 of the pixel portion P (j + 1) (k + 1) included in the pixel column, the adjacent pixel columns (the k-th column and the k + 1-th column) It is only necessary that one data line D is arranged in each part that divides the area. Therefore, it is not necessary to arrange two data lines per pixel column in order to drive each of the first TFT 22 and the second TFT 23, and the aperture ratio of the active matrix substrate 20 can be secured large. As a result, the backlight Power consumption can be suppressed.
  • the n + 1 data lines D are arranged such that data lines to which a positive data signal is applied and data lines to which a negative data signal is applied are alternately arranged. Therefore, it is possible to drive these data lines D with a single type of data driver 15, and power consumption for driving the data driver 15 can be suppressed as compared with the case where a plurality of types of data drivers are provided. . Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Furthermore, the frame can be narrower than when a plurality of types of data drivers are provided.
  • the first gate lines Ga and the second gate lines Gb are arranged on the active matrix substrate 20 so as to be alternately arranged in the column direction.
  • a pair of the first gate line Ga (j + 1) and the second gate line Gb (j) is arranged so as to partition the pixel row of the jth row and the pixel row of the j + 1th row in the column direction.
  • the Rukoto In the first driving period, a control signal is applied to the first gate line Ga, while no control signal is applied to the second gate line Gb, and in the second driving period, a control signal is applied to the second gate line Gb. On the other hand, no control signal is applied to the first gate line Ga.
  • the first gate line Ga (j + 1) and the second gate line Gb (j) are arranged so as to partition the j-th pixel row and the j + 1-th pixel row in the column direction, the pair of first gate lines Ga ( j + 1) and the second gate line Gb (j) can suppress the deterioration of drive characteristics due to parasitic capacitance.
  • the first gate lines Ga and the second gate lines Gb are arranged so as to be alternately arranged in the column direction on the active matrix substrate 20, but as shown in FIG.
  • the first gate line Ga and the second gate line Gb may be arranged so as not to be arranged alternately.
  • the second TFT 23 of the pixel portion Pjk and the first TFT 22 of the pixel portion P (j + 1) k are two second gate lines. They are arranged opposite to each other across Gb (j) and Gb (j + 1).
  • the second TFT 23 of the pixel portion P (j ⁇ 1) k and the first TFT 22 of the pixel portion Pjk are two first gate lines. They are arranged opposite to each other across Gb (j-1) and Gb (j). That is, the first TFT 22 and the second TFT 23 are arranged opposite to each other via the two first gate lines Ga or the two second gate lines Gb, thereby ensuring a large aperture ratio of the active matrix substrate 20. can do.
  • the n + 1 data lines D are described as including a data line to which a positive data signal is always applied and a data line to which a negative data signal is always applied.
  • a positive data signal is applied to a specific data line D (here, data line D (k)), and in another case, a negative data signal is applied to the data line D (k).
  • the polarity of the voltage applied to the specific data line D (k) may be inverted every plural frames. Even in this case, since the dot inversion drive can be performed without inverting the polarity of the data signal applied to each data line for each frame, the polarity of the voltage applied to the data line for each frame as described above. The power consumption can be reduced as compared with the case of inversion.
  • the present invention is useful for an active matrix substrate and a liquid crystal display device.
  • the present invention is useful for an active matrix substrate and a liquid crystal display device that can be driven at a low frequency and suppress display deterioration due to flickering of screen brightness.

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Abstract

In n+1 data lines (D) of an active matrix substrate of the present invention, data lines to which an anodic data signal is applied and data lines to which a cathodic data signal is applied are arranged alternately in the row direction. Pixel sections (P1k - Pmk) each include: a liquid crystal element (21); a first switching element (22) that switches the connection state of the liquid crystal element (21) and the data line (D(k)) of the kth column in response to a control signal that is applied to one of first and second gate lines (Ga(j), Gb(j)); and a second switching element (23) that switches the connection state of the liquid crystal element (21) and the data line (D(k+1)) of the (k+1)th column in response to a control signal that is applied to the other of the first and second gate lines (Ga(j), Gb(j)). According to the present invention, power consumption can be reduced because dot inversion drive can be performed without inverting the polarity of the data signal that is applied to each of the data lines in each single frame. The present invention is applicable to liquid crystal display devices.

Description

アクティブマトリクス基板及び液晶表示装置Active matrix substrate and liquid crystal display device
　本発明は、アクティブマトリクス基板及び液晶表示装置に関する。特に、本発明は、低周波数で駆動可能であって且つ画面輝度のチラツキ（フリッカ）による表示の劣化を抑制したアクティブマトリクス基板及び液晶表示装置に関する。 The present invention relates to an active matrix substrate and a liquid crystal display device. In particular, the present invention relates to an active matrix substrate and a liquid crystal display device that can be driven at a low frequency and suppress display deterioration due to flickering of screen luminance.
　近年、電子ブック用端末や携帯電話等のディスプレイとして用いられる表示パネルには、低消費電力化の要求が高まっている。 In recent years, there has been an increasing demand for lower power consumption in display panels used as displays for electronic book terminals and mobile phones.
　表示パネルの低消費電力化の手段としては、優れた輝度を確保するためにパネルの開口率を高めることや、低周波数でパネルの駆動を行うことが挙げられる。 Measures for reducing the power consumption of the display panel include increasing the aperture ratio of the panel in order to ensure excellent luminance and driving the panel at a low frequency.
　低周波数駆動を行う場合には、画面輝度のチラツキ（フリッカ）対策が必須となる。フリッカはデータ書き込みを高速化することにより抑制可能であることが知られており、高速書き込みによりフリッカを抑制しつつ低消費電力で駆動可能な表示装置が求められている。 Measures for flickering of screen brightness are essential when driving at low frequencies. It is known that flicker can be suppressed by speeding up data writing, and a display device that can be driven with low power consumption while suppressing flicker by high-speed writing is required.
　また、フリッカが視認されにくくするための対策として、隣接する画素の出力を逆極性とすること（ドット反転駆動）が行われている。これは、隣接する画素の出力を逆極性にすることにより、正極性と負極性とで書き込みが平均化され、フリッカが視認されにくくなるものである。 Also, as a countermeasure for making it difficult for the flicker to be visually recognized, the output of adjacent pixels is set to have a reverse polarity (dot inversion drive). This is because, by setting the outputs of adjacent pixels to opposite polarities, writing is averaged between the positive polarity and the negative polarity, and flicker becomes difficult to be visually recognized.
　特許文献１には、正極側駆動電圧を印加すべき第１のタイミングに相当する第１タイミング信号、及び負極側駆動電圧を印加すべき第２のタイミングに相当する第２タイミング信号を交互に生成して出力するタイミング生成ドライバと、第１データ線を介して第１データドライバに接続され且つ第１ゲート線を介して入力される第１タイミング信号により対応する各液晶表示セルに正極側駆動電圧を印加する第１スイッチング素子と、第２データ線を介して第２データドライバに接続され且つ第２ゲート線を介して入力される第２タイミング信号により対応する一の液晶表示セルに負極側駆動電圧を印加する第２スイッチング素子と、を備えた液晶表示装置が開示されている。そして、この液晶表示装置によれば、データ線駆動電圧の極性を１水平期間毎に反転させることなしに、隣接する液晶表示素子に印加する駆動電圧の極性を逆転させることができるため、フリッカや輝度ムラの発生が無い高品質の表示が得られ、また液晶パネルの駆動で消費される電力の低減が図れると記載されている。 Patent Document 1 alternately generates a first timing signal corresponding to a first timing at which a positive drive voltage is to be applied and a second timing signal corresponding to a second timing at which a negative drive voltage is to be applied. And a timing generation driver for outputting to each of the liquid crystal display cells connected to the first data driver via the first data line and corresponding to the first timing signal input via the first gate line. The first switching element for applying voltage to the second liquid crystal display cell connected to the second data driver via the second data line and input via the second gate line to the corresponding one liquid crystal display cell. A liquid crystal display device including a second switching element that applies a voltage is disclosed. According to this liquid crystal display device, the polarity of the drive voltage applied to the adjacent liquid crystal display element can be reversed without inverting the polarity of the data line drive voltage every horizontal period. It is described that a high-quality display without occurrence of luminance unevenness can be obtained and that the power consumed by driving the liquid crystal panel can be reduced.
特開平０６－２６６３１５号公報Japanese Patent Laid-Open No. 06-266315
　しかしながら、特許文献１の構成によれば、データドライバが１つのパネルあたり２種類必要となり、各データドライバを駆動するために大きな消費電力が必要となり、しかも、製造コストが嵩む問題がある。また、１画素あたりにゲート線２本、データ線２本を要するので、開口率が小さくなり、その分、バックライトの消費電力が大きくなってしまう。 However, according to the configuration of Patent Document 1, two types of data drivers are required per panel, and a large amount of power is required to drive each data driver, and the manufacturing cost increases. Further, since two gate lines and two data lines are required per pixel, the aperture ratio is reduced, and the power consumption of the backlight is increased accordingly.
　本発明は、アクティブマトリクス基板やそれを備えた液晶表示装置において、高速書き込みを行い、消費電力を低減し、さらに製造コストを低減することを目的とする。 An object of the present invention is to perform high-speed writing in an active matrix substrate and a liquid crystal display device including the same, thereby reducing power consumption and further reducing manufacturing costs.
　本発明のアクティブマトリクス基板は、
　ｍ行ｎ列（ｍ，ｎは、２以上の整数）のマトリクス状に配列されたｍ×ｎ個の画素部と、
　上記ｍ×ｎ個の画素部のｍ行の画素行にそれぞれ対応し、行方向に沿って互いに並行して延びると共に列方向に互いに離間するｍ本の第１のゲート線及びｍ本の第２のゲート線と、
　正極性のデータ信号が印加されるデータ線及び負極性のデータ信号が印加されるデータ線を含み、上記ｍ×ｎ個の画素部のｎ列の画素列を区画するように列方向に沿って互いに並行して延びると共に該正極性のデータ信号が印加されるデータ線と該負極性のデータ信号が印加されるデータ線とが行方向に交互に並ぶように配置されるｎ＋１本のデータ線と、を備え、
　上記ｍ×ｎ個の画素部のうち第ｋ列目（１≦ｋ≦ｎ）の画素列に含まれるｍ個の画素部の各々は、
　　液晶素子と、
　　上記画素部に対応する第１及び第２ゲート線の間に配置され、該第１及び第２のゲート線のうち一方に印加される制御信号に応答して、第ｋ列目のデータ線と上記液晶素子との接続状態を切り替える第１のスイッチング素子と、
　　上記画素部に対応する第１及び第２ゲート線の間に配置され、該第１及び第２のゲート線のうち他方に印加される制御信号に応答して、第ｋ＋１列目のデータ線と上記液晶素子との接続状態を切り替える第２のスイッチング素子と、を含むことを特徴とする。 The active matrix substrate of the present invention is
m × n pixel units arranged in a matrix of m rows and n columns (m and n are integers of 2 or more);
The m first gate lines and the m second gate lines respectively corresponding to the m pixel rows of the m × n pixel portions extend in parallel with each other in the row direction and are spaced apart from each other in the column direction. The gate line,
Including a data line to which a positive data signal is applied and a data line to which a negative data signal is applied, along the column direction so as to partition n pixel columns of the m × n pixel units. N + 1 data lines that extend in parallel with each other and are arranged so that the data lines to which the positive polarity data signal is applied and the data lines to which the negative polarity data signal is applied are alternately arranged in the row direction; With
Of the m × n pixel units, each of the m pixel units included in the kth column (1 ≦ k ≦ n) pixel column is
A liquid crystal element;
In response to a control signal disposed between the first and second gate lines corresponding to the pixel portion and applied to one of the first and second gate lines, the kth data line and A first switching element that switches a connection state with the liquid crystal element;
In response to a control signal disposed between the first and second gate lines corresponding to the pixel portion and applied to the other of the first and second gate lines, the (k + 1) th column data line and And a second switching element that switches a connection state with the liquid crystal element.
　上記の構成のアクティブマトリクス基板の駆動について、第ｋ列目の画素列に含まれる画素部（ここでは第１画素部とする）と、それに行方向に隣接し、且つ第ｋ＋１列目の画素列に含まれる画素部（ここでは第２画素部とする）とについて（１≦ｋ＜ｎ）、説明する。ここでは、第ｋ列目及び第ｋ＋２列目のデータ線には正極性のデータ信号が印加され、第ｋ＋１列目のデータ線には負極性のデータ信号が印加される場合、且つ、第１画素部の第１のスイッチング素子が第１ゲート線に印加される制御信号に応答して第ｋ列目のデータ線と上記液晶素子との接続状態を切り替えるように設けられ、第１画素部の第２のスイッチング素子が第２ゲート線に印加される制御信号に応答して第ｋ＋１列目のデータ線と上記液晶素子との接続状態を切り替えるように設けられ、第２画素部の第１のスイッチング素子が第１ゲート線に印加される制御信号に応答して第ｋ＋１列目のデータ線と上記液晶素子との接続状態を切り替えるように設けられ、そして、第２画素部の第２のスイッチング素子が第２ゲート線に印加される制御信号に応答して第ｋ＋２列目のデータ線と上記液晶素子との接続状態を切り替えるように設けられている場合について説明する。 Regarding the driving of the active matrix substrate having the above-described configuration, the pixel portion (herein referred to as the first pixel portion) included in the k-th pixel column, and the pixel column adjacent to it in the row direction and in the k + 1-th column (1 ≦ k <n) will be described with respect to the pixel portion included in the pixel (here, the second pixel portion). Here, a positive data signal is applied to the kth and k + 2th data lines, and a negative data signal is applied to the k + 1th data line, and the first The first switching element of the pixel portion is provided to switch a connection state between the data line of the kth column and the liquid crystal element in response to a control signal applied to the first gate line. A second switching element is provided to switch a connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the second gate line, and the first switching element of the second pixel unit A switching element is provided to switch a connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the first gate line, and the second switching of the second pixel unit Device applied to second gate line It will be described which is provided to switch the connection state between the (k + 2) th column data line and the liquid crystal element in response to a control signal.
　第１の駆動期間においては、ｍ本の第１のゲート線のいずれか１本に制御信号が印加される一方でｍ本の第２のゲート線のいずれにも制御信号が印加されず、一方、第２の駆動期間においては、ｍ本の第２のゲート線のいずれか１本に制御信号が印加される一方でｍ本の第１のゲート線のいずれにも制御信号が印加されないように駆動が行われる。そのため、第１の駆動期間においては、第１及び第２画素部に対応する第１のゲート線が選択されて制御信号が印加されると、第１画素部では、その制御信号に応答して第１のスイッチング素子がオンとなり、正極性のデータ信号が印加された第ｋ列目のデータ線を介して液晶素子には正の駆動電圧が印加されることとなる。また、第２画素部では、その制御信号に応答して第１のスイッチング素子がオンとなり、負極性のデータ信号が印加された第ｋ＋１列目のデータ線を介して液晶素子には負の駆動電圧が印加されることとなる。第２の駆動期間においては、第１及び第２画素部に対応する第２のゲート線が選択されて制御信号が印加されると、第１画素部では、その制御信号に応答して第２のスイッチング素子がオンとなり、負極性のデータ信号が印加された第ｋ＋１列目のデータ線を介して液晶素子には負の駆動電圧が印加されることとなる。また、第２画素部では、その制御信号に応答して第２のスイッチング素子がオンとなり、正極性のデータ信号が印加された第ｋ＋２列目のデータ線を介して液晶素子には正の駆動電圧が印加されることとなる。 In the first driving period, the control signal is applied to any one of the m first gate lines, while the control signal is not applied to any of the m second gate lines. In the second driving period, the control signal is applied to any one of the m second gate lines, while the control signal is not applied to any of the m first gate lines. Driving is performed. Therefore, in the first driving period, when the first gate line corresponding to the first and second pixel portions is selected and the control signal is applied, the first pixel portion responds to the control signal. The first switching element is turned on, and a positive driving voltage is applied to the liquid crystal element via the kth column data line to which the positive data signal is applied. In the second pixel portion, the first switching element is turned on in response to the control signal, and the liquid crystal element is negatively driven through the (k + 1) th column data line to which the negative data signal is applied. A voltage will be applied. In the second driving period, when a second gate line corresponding to the first and second pixel portions is selected and a control signal is applied, the first pixel portion receives a second signal in response to the control signal. The switching element is turned on, and a negative drive voltage is applied to the liquid crystal element via the data line of the (k + 1) th column to which the negative data signal is applied. In the second pixel portion, the second switching element is turned on in response to the control signal, and the liquid crystal element is positively driven through the k + 2th column data line to which the positive data signal is applied. A voltage will be applied.
　したがって、上記の構成のアクティブマトリクス基板によれば、第１の駆動期間では、第１画素部、第２画素部にはそれぞれ正、負の駆動電圧が印加され、第２の駆動期間では、第１画素部、第２画素部にはそれぞれ負、正の駆動電圧が印加されることとなるので、各画素部においてフレーム毎に印加される電圧の極性を反転させてドット反転駆動を行うことができ、結果として、フリッカや輝度ムラが視認されにくく、高品質の表示が得られる。 Therefore, according to the active matrix substrate having the above-described configuration, positive and negative drive voltages are applied to the first pixel portion and the second pixel portion in the first drive period, respectively, and in the second drive period, Since negative and positive drive voltages are applied to the one pixel portion and the second pixel portion, dot inversion drive can be performed by inverting the polarity of the voltage applied for each frame in each pixel portion. As a result, flicker and luminance unevenness are not easily recognized, and a high-quality display can be obtained.
　なお、第１画素部の第１のスイッチング素子が第２ゲート線に印加される制御信号に応答して第ｋ列目のデータ線と上記液晶素子との接続状態を切り替えるように設けられ、第１画素部の第２のスイッチング素子が第１ゲート線に印加される制御信号に応答して第ｋ＋１列目のデータ線と上記液晶素子との接続状態を切り替えるように設けられ、第２画素部の第１のスイッチング素子が第２ゲート線に印加される制御信号に応答して第ｋ＋１列目のデータ線と上記液晶素子との接続状態を切り替えるように設けられ、そして、第２画素部の第２のスイッチング素子が第１ゲート線に印加される制御信号に応答して第ｋ＋２列目のデータ線と上記液晶素子との接続状態を切り替えるように設けられている場合についても、同様に、ドット反転駆動を行うことができる。 The first switching element of the first pixel unit is provided so as to switch a connection state between the data line of the kth column and the liquid crystal element in response to a control signal applied to the second gate line. A second switching element of one pixel unit is provided to switch a connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the first gate line. The first switching element is provided to switch the connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the second gate line, and Similarly, when the second switching element is provided so as to switch the connection state between the data line of the (k + 2) th column and the liquid crystal element in response to a control signal applied to the first gate line, Dot inversion Motion can be carried out.
　このとき、各データ線に印加されるデータ信号の極性を１フレーム毎に充放電させて反転させることなく、隣接する第１画素部と第２画素部のそれぞれの液晶素子に印加する駆動電圧の極性を逆転させることができるので、駆動で消費される電力を抑制することができる。 At this time, the polarity of the data signal applied to each data line is not charged / discharged for each frame and inverted, and the drive voltage applied to each liquid crystal element of the adjacent first pixel portion and second pixel portion is determined. Since the polarity can be reversed, the power consumed by driving can be suppressed.
　また、上記の構成によれば１つの画素部に２つのスイッチング素子が設けられているが、１本のデータ線（ここでは、第ｋ＋１列目のデータ線（１≦ｋ＜ｎ））は、第ｋ列目の画素列に含まれる画素部（第１画素部）の第２スイッチング素子にデータ信号を与える一方、第ｋ＋１列目の画素列に含まれる画素部（第２画素部）の第１スイッチング素子にデータ信号を与えるように構成されているので、隣接する画素列を区画する各部分にデータ線が１本ずつ配置されていればよい。このため、第１及び第２のスイッチング素子を各々駆動するために１つの画素列あたり２本のデータ線を配置する必要が無く、アクティブマトリクス基板の開口率を大きく確保でき、その結果として、バックライトの消費電力を抑制することができる。 Further, according to the above configuration, two switching elements are provided in one pixel portion, but one data line (here, the data line of the (k + 1) th column (1 ≦ k <n)) A data signal is supplied to the second switching element of the pixel portion (first pixel portion) included in the k-th pixel row, while the pixel portion (second pixel portion) of the pixel portion (second pixel portion) included in the k + 1-th pixel row. Since the data signal is supplied to one switching element, it is only necessary to arrange one data line in each part that partitions adjacent pixel columns. Therefore, it is not necessary to arrange two data lines per pixel column in order to drive each of the first and second switching elements, and a large aperture ratio of the active matrix substrate can be ensured. The power consumption of the light can be suppressed.
　さらに、上記の構成によれば、ｎ＋１本のデータ線は正極性のデータ信号が印加されるデータ線と負極性のデータ信号が印加されるデータ線が交互に並ぶように配置されているので、これらのデータ線を単一種類のデータドライバで駆動することが可能であり、複数種類のデータドライバを設ける場合よりもデータドライバ駆動のための消費電力を抑制することができる。また、複数種類のデータドライバを設ける場合よりも製造コストを低減することができる。さらに、複数種類のデータドライバを設ける場合よりも狭額縁化することができる。 Further, according to the above configuration, the n + 1 data lines are arranged so that the data lines to which the positive data signal is applied and the data lines to which the negative data signal is applied are alternately arranged. These data lines can be driven by a single type of data driver, and power consumption for driving the data driver can be suppressed as compared with the case where a plurality of types of data drivers are provided. Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Furthermore, the frame can be narrower than when a plurality of types of data drivers are provided.
　本発明のアクティブマトリクス基板は、列方向に隣接する画素部において、上記第１スイッチング素子同士または上記第２スイッチング素子同士が上記第１のゲート線及び／または第２のゲート線を挟んで両側に対向して配置されることが好ましい。 In the active matrix substrate of the present invention, in the pixel portion adjacent in the column direction, the first switching elements or the second switching elements are on both sides of the first gate line and / or the second gate line. It is preferable that they are arranged to face each other.
　本発明のアクティブマトリクス基板は、上記第１のゲート線と上記第２のゲート線とが列方向において交互に並ぶように配置されることが好ましい。 The active matrix substrate of the present invention is preferably arranged so that the first gate lines and the second gate lines are alternately arranged in the column direction.
　上記の構成によれば、第１のゲート線と第２のゲート線の一対が各画素部を列方向に区画するように配置されることとなる。第１の駆動期間では第１のゲート線に制御信号が印加される一方、第２ゲート線には制御信号が印加されず、第２の駆動期間では第２のゲート線に制御信号が印加される一方、第１ゲート線には制御信号が印加されない。つまり、第１のゲート線と第２のゲート線には同一フレーム内に両ゲート線に対し制御信号が印加されることがないので、第１のゲート線と第２のゲート線の一対が各画素部を列方向に区画するように両者の一対が近くに配置されても、第１のゲート線と第２のゲート線との間での寄生容量による駆動特性の劣化を抑制することができる。 According to the above configuration, a pair of the first gate line and the second gate line is arranged so as to partition each pixel portion in the column direction. While the control signal is applied to the first gate line in the first driving period, the control signal is not applied to the second gate line, and the control signal is applied to the second gate line in the second driving period. On the other hand, no control signal is applied to the first gate line. That is, since a control signal is not applied to both the first gate line and the second gate line within the same frame, each pair of the first gate line and the second gate line is connected to each other. Even if a pair of both are arranged close to each other so as to partition the pixel portion in the column direction, it is possible to suppress deterioration in driving characteristics due to parasitic capacitance between the first gate line and the second gate line. .
　本発明のアクティブマトリクス基板は、上記第１スイッチング素子及び上記第２スイッチング素子のそれぞれが酸化物半導体膜を備えた薄膜トランジスタ（Thin Film Transistor、以下「ＴＦＴ」とも称する）であることが好ましい。 The active matrix substrate of the present invention is preferably a thin film transistor (hereinafter also referred to as “TFT”) in which each of the first switching element and the second switching element includes an oxide semiconductor film.
　上記の構成によれば、第１スイッチング素子及び第２スイッチング素子のそれぞれが酸化物半導体膜を備えたＴＦＴであるので、高速書き込み駆動が可能となり、画面の輝度変化を抑制することができると共に、書き込み休止期間のＴＦＴオフリークによる画素電位変化を低減することができる。そのため、フリッカによる表示の劣化をさらに抑制することができる。 According to the above configuration, since each of the first switching element and the second switching element is a TFT including an oxide semiconductor film, high-speed writing drive is possible, and a change in luminance of the screen can be suppressed. It is possible to reduce the change in pixel potential due to TFT off-leak during the writing suspension period. Therefore, display deterioration due to flicker can be further suppressed.
　本発明の液晶表示装置は、上述した本発明のアクティブマトリクス基板と、
　行方向において正極性のデータ信号の印加の対象となるデータ線と負極性のデータ信号の印加の対象となるデータ線とが交互に並ぶように、各データ信号を上記ｎ＋１本のデータ線にそれぞれ印加するデータドライバと、
　第１の駆動期間では、上記ｍ本の第１のゲート線のいずれか１本に上記第１のスイッチング素子に送信する制御信号を印加し、第２の駆動期間では、上記ｍ本の第１のゲート線のいずれにも制御信号を印加しない第１のゲートドライバと、
　上記第１の駆動期間では、上記ｍ本の第２のゲート線のいずれにも制御信号を印加せず、上記第２の駆動期間では、上記ｍ本の第２のゲート線のいずれか１本に上記第２のスイッチング素子に送信する制御信号を印加する第２のゲートドライバと、
を備えることを特徴とする。 The liquid crystal display device of the present invention includes the above-described active matrix substrate of the present invention,
In the row direction, the data signals are applied to the n + 1 data lines so that the data lines to be applied with the positive data signal and the data lines to be applied with the negative data signal are alternately arranged in the row direction. A data driver to be applied;
In the first driving period, a control signal to be transmitted to the first switching element is applied to any one of the m first gate lines. In the second driving period, the m first gate lines are applied. A first gate driver that does not apply a control signal to any of the gate lines;
In the first driving period, no control signal is applied to any of the m second gate lines, and in the second driving period, any one of the m second gate lines. A second gate driver for applying a control signal to be transmitted to the second switching element;
It is characterized by providing.
　上記の構成によれば、データドライバが正極性のデータ信号の印加の対象となるデータ線と負極性のデータ信号の印加の対象となるデータ線とが行方向に交互に並ぶように、各データ信号を上記ｎ＋１本のデータ線にそれぞれ印加し、且つ、第１ゲートドライバ及び第２ゲートドライバは、第１の駆動期間においては、上記ｍ本の第１のゲート線のいずれか１本に上記第１のスイッチング素子に送信する制御信号を印加する一方でｍ本の第２のゲート線のいずれにも制御信号を印加せず、第２の駆動期間においては、上記ｍ本の第２のゲート線のいずれか１本に上記第２のスイッチング素子に送信する制御信号を印加する一方でｍ本の第１のゲート線のいずれにも制御信号を印加しないので、隣接する画素部同士で逆極性の電圧を印加することができ、また、各駆動期間毎に各画素部の極性を反転するドット反転駆動を行うことができる。 According to the above configuration, each data is arranged such that the data line to which the data driver applies the positive data signal and the data line to which the negative data signal is applied are alternately arranged in the row direction. A signal is applied to each of the n + 1 data lines, and the first gate driver and the second gate driver are connected to any one of the m first gate lines in the first driving period. While the control signal transmitted to the first switching element is applied, the control signal is not applied to any of the m second gate lines, and the m second gates are applied during the second driving period. A control signal to be transmitted to the second switching element is applied to any one of the lines, while a control signal is not applied to any of the m first gate lines. Apply a voltage of Bets can be, also, it is possible to perform dot inversion driving for inverting the polarity of each pixel unit for each drive period.
　また、上記の構成によれば、単一種類のデータドライバが、行方向において正極性のデータ信号の印加の対象となるデータ線と負極性のデータ信号の印加の対象となるデータ線とが交互に並ぶように、各データ信号を上記ｎ＋１本のデータ線にそれぞれ印加するので、複数種類のデータドライバを設ける場合よりもデータドライバ駆動のための消費電力を抑制することができる。また、複数種類のデータドライバを設ける場合よりも製造コストを低減することができる。また、複数種類のデータドライバを設ける場合よりも狭額縁化することができる。 In addition, according to the above configuration, a single type of data driver has alternating data lines to which positive data signals are applied and data lines to which negative data signals are applied in the row direction. Since the data signals are respectively applied to the n + 1 data lines so as to line up with each other, power consumption for driving the data driver can be suppressed as compared with the case where a plurality of types of data drivers are provided. Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Further, the frame can be narrower than when a plurality of types of data drivers are provided.
　本発明のアクティブマトリクス基板は、画素部のｍ行の画素行にそれぞれ対応するｍ本の第１のゲート線及びｍ本の第２のゲート線が行方向に沿って互いに並行して延びるように配置され、画素部のｎ列の画素列を区画するように延びるｎ＋１本のデータ線が正極性のデータ信号が印加されるデータ線と負極性のデータ信号が印加されるデータ線とが交互に並ぶように配置され、各画素部が、液晶素子と、第１及び第２のゲート線のうち一方に印加される制御信号に応答して第ｋ列目のデータ線と液晶素子との接続状態を切り替える第１のスイッチング素子と、第１及び第２のゲート線のうち他方に印加される制御信号に応答して第ｋ＋１列目のデータ線と液晶素子との接続状態を切り替える第２のスイッチング素子と、を含むので、第１の駆動期間において第１のゲート線に制御信号を印加して第１のスイッチング素子をオンにし、次いで、第２の駆動期間において第２のゲート線に制御信号を印加して第２のスイッチング素子をオンにすることにより、隣接する画素部の液晶素子に印加される電圧を逆極性とすることができると共に、各液晶素子に印加される電圧の極性を１駆動期間毎に反転することができる。つまり、ドット反転駆動を行うことができる。そして、このようにアクティブマトリクス基板の駆動を行うことにより、各データ線に印加されるデータ信号の極性を充放電させて反転させることなく各液晶素子に印加される電圧の極性を反転することができるので、駆動電力を抑制することができる。 In the active matrix substrate of the present invention, m first gate lines and m second gate lines respectively corresponding to m pixel rows of the pixel portion extend in parallel to each other in the row direction. N + 1 data lines that are arranged and extend so as to partition the n pixel columns of the pixel portion are alternately arranged with data lines to which positive data signals are applied and data lines to which negative data signals are applied. The pixel units are arranged side by side, and each pixel portion is connected to the liquid crystal element and the liquid crystal element in response to a control signal applied to one of the first and second gate lines. A first switching element that switches between the first and second gate lines, and a second switching that switches a connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the other of the first and second gate lines. Element, so that the first A control signal is applied to the first gate line in the driving period to turn on the first switching element, and then a control signal is applied to the second gate line in the second driving period to activate the second switching element. By turning on the voltage, the voltage applied to the liquid crystal element in the adjacent pixel portion can be reversed, and the polarity of the voltage applied to each liquid crystal element can be reversed every driving period. That is, dot inversion driving can be performed. By driving the active matrix substrate in this way, the polarity of the voltage applied to each liquid crystal element can be reversed without charging and discharging the polarity of the data signal applied to each data line. As a result, driving power can be suppressed.
　また、本発明によれば１つの画素部に２つのスイッチング素子が設けられているが、１本のデータ線（ここでは、第ｋ＋１列目のデータ線（１≦ｋ＜ｎ））は、第ｋ列目の画素列に含まれる画素部の第２スイッチング素子に制御信号を与える一方で第ｋ＋１列目の画素列に含まれる画素部の第１スイッチング素子に制御信号を与えるように構成されている、或いは、第ｋ列目の画素列に含まれる画素部の第１スイッチング素子に制御信号を与える一方で第ｋ＋１列目の画素列に含まれる画素部の第２スイッチング素子に制御信号を与えるように構成されているので、隣接する画素列を区画する各部分にデータ線が１本ずつ配置されていればよい。このため、第１及び第２のスイッチング素子を各々駆動するために１つの画素列あたり２本のデータ線を配置する必要が無く、アクティブマトリクス基板の開口率を大きく確保でき、その結果として、バックライトの消費電力を抑制することができる。 In addition, according to the present invention, two switching elements are provided in one pixel portion, but one data line (here, the data line in the (k + 1) th column (1 ≦ k <n)) The control signal is supplied to the second switching element of the pixel unit included in the kth pixel column, while the control signal is supplied to the first switching element of the pixel unit included in the k + 1th pixel column. Alternatively, the control signal is supplied to the first switching element of the pixel portion included in the k-th pixel column, while the control signal is supplied to the second switching element of the pixel portion included in the k + 1-th pixel column. Therefore, it is only necessary that one data line is arranged in each part that partitions adjacent pixel columns. Therefore, it is not necessary to arrange two data lines per pixel column in order to drive each of the first and second switching elements, and a large aperture ratio of the active matrix substrate can be ensured. The power consumption of the light can be suppressed.
　さらに、本発明によれば、ｎ＋１本のデータ線が正極性のデータ信号が印加されるデータ線と負極性のデータ信号が印加されるデータ線とが交互に並ぶように配置されているので、これらのデータ線を単一種類のデータドライバで駆動することが可能であり、複数種類のデータドライバを設ける場合よりもデータドライバ駆動のための消費電力を抑制することができる。また、複数種類のデータドライバを設ける場合よりも製造コストを低減することができる。さらに、複数種類のデータドライバを設ける場合よりも狭額縁化することができる。 Further, according to the present invention, the n + 1 data lines are arranged so that the data lines to which the positive data signal is applied and the data lines to which the negative data signal is applied are alternately arranged. These data lines can be driven by a single type of data driver, and power consumption for driving the data driver can be suppressed as compared with the case where a plurality of types of data drivers are provided. Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Furthermore, the frame can be narrower than when a plurality of types of data drivers are provided.
実施形態１の液晶表示装置の概略構成図である。1 is a schematic configuration diagram of a liquid crystal display device of Embodiment 1. FIG. 図１のうち４つの画素部Ｐjk，Ｐj(k+1)，Ｐ(j+1)k，Ｐ(j+1)(k+1)の領域の拡大図である。FIG. 2 is an enlarged view of regions of four pixel portions Pjk, Pj (k + 1), P (j + 1) k, and P (j + 1) (k + 1) in FIG. 実施形態１の動作タイミングチャートである。3 is an operation timing chart of the first embodiment. 実施形態１の動作説明のための（ａ）第１の駆動期間及び（ｂ）第２の駆動期間におけるイメージ図である。FIG. 6 is an image diagram for explaining the operation of the first embodiment in (a) a first driving period and (b) a second driving period. １フレームの書き込み時間が（ａ）Ａ［ｍｓｅｃ］、（ｂ）２／３×Ａ［ｍｓｅｃ］、及び（ｃ）１／２×Ａ［ｍｓｅｃ］における書き込み時間とパネル表面輝度の関係を示すグラフである。The graph which shows the relationship between the writing time and panel surface brightness | luminance in (a) A [msec], (b) 2 / 3xA [msec], and (c) 1 / 2xA [msec] in the writing time of 1 frame It is. 変形例の液晶表示装置の概略構成図である。It is a schematic block diagram of the liquid crystal display device of a modification.
　以下、図面を参照して本発明の実施の形態について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　　＜実施形態１＞
　図１は、液晶表示装置１０の概略構成を示す。 <Embodiment 1>
FIG. 1 shows a schematic configuration of the liquid crystal display device 10.
　液晶表示装置１０は、装置全体の基準電圧を生成し出力する基準電圧作成回路１１と、基準電圧作成回路１１からの電圧信号を電流増幅して後述のデータドライバ１５へと出力する電流アンプ１２と、コントローラ（不図示）からの水平同期信号に基づいて複数本の第１ゲート線Ｇａ(1)，Ｇａ(2)，…（以下、複数本の第１ゲート線をまとめて第１ゲート線Ｇａと称することもある。）のそれぞれを制御する第１ゲートドライバ１３と、水平同期信号に基づいて複数本の第２ゲート線Ｇｂ(1)，Ｇｂ(2)，…（以下、複数本の第２ゲート線をまとめて第２ゲート線Ｇｂと称することもある。）のそれぞれを制御する第２ゲートドライバ１４と、水平同期信号に基づいて複数本のデータ線Ｄ(1)，Ｄ(2)，…（以下、複数本のデータ線をまとめてデータ線Ｄと称することもある。）のそれぞれにデータ信号を印加する単一種類のデータドライバ１５と、を備える。データドライバ１５は、１つのデータドライバで構成されていてもよく、全て同種類のデータドライバを組み合わせて構成されていてもよい。なお、第１ゲート線Ｇａ、第２ゲート線Ｇｂ及びデータ線Ｄは、アクティブマトリクス基板２０上に形成されている。 The liquid crystal display device 10 includes a reference voltage generation circuit 11 that generates and outputs a reference voltage of the entire device, a current amplifier 12 that amplifies a voltage signal from the reference voltage generation circuit 11 and outputs the current signal to a data driver 15 described later. , Based on a horizontal synchronization signal from a controller (not shown), a plurality of first gate lines Ga (1), Ga (2),... And a plurality of second gate lines Gb (1), Gb (2),... (Hereinafter referred to as a plurality of second gate lines Gb (1), Gb (2),...) Based on the horizontal synchronization signal. The two gate lines may be collectively referred to as a second gate line Gb.) And a plurality of data lines D (1) and D (2) based on the horizontal synchronization signal. , ... (Hereafter, data is collected from multiple data lines. Also referred to as D.) Of it comprises a single type of data driver 15 for applying a data signal to each of the. The data driver 15 may be configured by one data driver, or may be configured by combining all the same types of data drivers. The first gate line Ga, the second gate line Gb, and the data line D are formed on the active matrix substrate 20.
　　（アクティブマトリクス基板２０）
　アクティブマトリクス基板２０には、ｍ×ｎ個の画素部Ｐ11，Ｐ12，…（以下、複数の画素部をまとめて画素部Ｐと称することもある。）がｍ行×ｎ列のマトリクス状に配列されている。ここで、ｍ，ｎは２以上の整数とする。これらのｍ×ｎ個の画素部Ｐのそれぞれは、１≦ｊ≦ｍ及び１≦ｋ≦ｎ＋１である整数ｊ，ｋにおいて、第ｊ行目の画素行と第ｋ列目の画素列の交差する領域に画素部Ｐjkが配置されている。 (Active matrix substrate 20)
On the active matrix substrate 20, m × n pixel portions P11, P12,... (Hereinafter, a plurality of pixel portions may be collectively referred to as a pixel portion P) are arranged in a matrix of m rows × n columns. Has been. Here, m and n are integers of 2 or more. Each of the m × n pixel portions P is an intersection of the jth pixel row and the kth pixel column at integers j and k where 1 ≦ j ≦ m and 1 ≦ k ≦ n + 1. The pixel portion Pjk is arranged in the area to be processed.
　複数本の第１ゲート線Ｇａは、ｍ×ｎ個の画素部のｍ行の画素行にそれぞれ対応し、行方向に沿って互いに並行して延びるように、ｍ本設けられている。これらのｍ本の第１ゲート線Ｇａのそれぞれは、第ｊ行目に第１ゲート線Ｇａ(j)が配置されている。複数本の第２ゲート線Ｇｂは、ｍ×ｎ個の画素部のｍ行の画素行にそれぞれ対応し、行方向に沿って互いに並行して延びるように、ｍ本設けられている。これらのｍ本の第２ゲート線Ｇｂのそれぞれは、第ｊ行目に第２ゲート線Ｇｂ(j)が配置されている。そして、第ｊ行目の第１ゲート線Ｇａ(j)と第２ゲート線Ｇｂ(j)のそれぞれは、列方向に互いに離間するように配置されている。 The plurality of first gate lines Ga are provided so as to correspond to m pixel rows of the m × n pixel portions and to extend in parallel with each other in the row direction. Each of the m first gate lines Ga has the first gate line Ga (j) arranged in the j-th row. A plurality of second gate lines Gb are provided so as to respectively correspond to m pixel rows of the m × n pixel portions and to extend in parallel with each other along the row direction. Each of these m second gate lines Gb has the second gate line Gb (j) arranged in the j-th row. The first gate line Ga (j) and the second gate line Gb (j) in the j-th row are arranged so as to be separated from each other in the column direction.
　複数本のデータ線Ｄは、ｍ×ｎ個の画素部Ｐのｎ列の画素列を区画するように列方向に沿って互いに並行して延びるように、ｎ＋１本設けられている。これらのｎ＋１本のデータ線Ｄのそれぞれは、第ｋ列目にデータ線Ｄ(k)が配置されている。ｎ＋１本のデータ線Ｄは、正極性のデータ信号が印加されるものと負極性のデータ信号が印加されるものとを含み、正極性のデータ信号が印加されるデータ線と負極性のデータ信号が印加されるデータ線とが交互に並ぶように配置されている。 The n + 1 data lines D are provided so as to extend in parallel with each other along the column direction so as to partition n pixel columns of the m × n pixel portions P. Each of these n + 1 data lines D has a data line D (k) arranged in the k-th column. The n + 1 data lines D include a data line to which a positive data signal is applied and a data line to which a negative data signal is applied, and a data line to which a positive data signal is applied and a negative data signal. Are arranged so as to be alternately arranged with data lines to which is applied.
　　（画素部Ｐ）
　次に、図２を用いて各画素部Ｐの構成について説明する。各画素部Ｐは、液晶素子２１、第１のスイッチング素子である第１ＴＦＴ２２、第２のスイッチング素子である第２ＴＦＴ２３、及びメモリ用の蓄積コンデンサ２４を備える。第１ＴＦＴ２２、第２ＴＦＴは、それぞれ、半導体膜として酸化物半導体膜を備える。酸化物半導体膜としては、例えば、インジウムガリウム亜鉛複合酸化物（ＩＧＺＯ）等が挙げられる。 (Pixel part P)
Next, the configuration of each pixel portion P will be described with reference to FIG. Each pixel portion P includes a liquid crystal element 21, a first TFT 22 that is a first switching element, a second TFT 23 that is a second switching element, and a storage capacitor 24 for memory. Each of the first TFT 22 and the second TFT includes an oxide semiconductor film as a semiconductor film. Examples of the oxide semiconductor film include indium gallium zinc composite oxide (IGZO).
　液晶素子２１は、一方の端子が対向電極に接続されている。 The liquid crystal element 21 has one terminal connected to the counter electrode.
　蓄積コンデンサ２４は、一方の端子が第１ＴＦＴ２２及び第２ＴＦＴ２３の共通のソース２２Ｓ、２３Ｓに接続され、他方の端子が対向電極に接続されている。 The storage capacitor 24 has one terminal connected to the common sources 22S and 23S of the first TFT 22 and the second TFT 23, and the other terminal connected to the counter electrode.
　以下、１≦ｊ＜ｍ、１≦ｋ＜ｎである整数ｋ、ｎにおいて、第ｊ行目～第ｊ＋１行目の画素行と第ｋ列目～第ｋ＋１列目の画素列の交差する領域に位置する４個の画素部Ｐjk，Ｐj(k+1)，Ｐ(j+1)k，Ｐ(j+1)(k+1)における第１ＴＦＴ２２及び第２ＴＦＴ２３について詳細に説明する。 Hereinafter, in the integers k and n where 1 ≦ j <m and 1 ≦ k <n, the region where the pixel rows from the j-th row to the (j + 1) -th row intersect with the pixel columns from the k-th column to the (k + 1) -th column The first TFT 22 and the second TFT 23 in the four pixel portions Pjk, Pj (k + 1), P (j + 1) k, and P (j + 1) (k + 1) located in FIG.
　　（画素部Ｐjk）
　第１ＴＦＴ２２は、第１ゲート線Ｇａ(j)及び第２ゲート線Ｇｂ(j)の間に配置されている。第１ＴＦＴ２２は、第１ゲート線Ｇａ(j)に印加される制御信号に応答して第ｋ列目のデータ線Ｄ(k)と液晶素子２１（液晶素子ＣＬａ）との接続状態を切り替えられるように、ゲート２２Ｇが第ｊ行目の第１ゲート線Ｇａ(j)に接続され、ドレイン２２Ｄが第ｋ列目のデータ線Ｄ(k)に接続され、ソース２２Ｓが液晶素子２１の他方の端子に接続されている。 (Pixel part Pjk)
The first TFT 22 is disposed between the first gate line Ga (j) and the second gate line Gb (j). The first TFT 22 can switch the connection state between the data line D (k) in the kth column and the liquid crystal element 21 (liquid crystal element CLa) in response to a control signal applied to the first gate line Ga (j). The gate 22G is connected to the first gate line Ga (j) in the j-th row, the drain 22D is connected to the data line D (k) in the k-th column, and the source 22S is connected to the other terminal of the liquid crystal element 21. It is connected to the.
　第２ＴＦＴ２３は、第１ゲート線Ｇａ(j)及び第２ゲート線Ｇｂ(j)の間に配置されている。第２ＴＦＴ２３は、第２ゲート線Ｇｂ(j)に印加される制御信号に応答して第ｋ＋１列目のデータ線Ｄ(k+1)と液晶素子２１との接続状態を切り替えられるように、ゲート２３Ｇが第ｊ行目の第２ゲート線Ｇｂ(j)に接続され、ドレイン２３Ｄが第ｋ＋１列目のデータ線Ｄ(k+1)に接続され、ソース２３Ｓが液晶素子２１の他方の端子に接続されている。 The second TFT 23 is disposed between the first gate line Ga (j) and the second gate line Gb (j). The second TFT 23 has a gate so that the connection state between the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 can be switched in response to a control signal applied to the second gate line Gb (j). 23G is connected to the second gate line Gb (j) of the jth row, the drain 23D is connected to the data line D (k + 1) of the (k + 1) th column, and the source 23S is connected to the other terminal of the liquid crystal element 21. It is connected.
　　（画素部Ｐj(k+1)）
　第１ＴＦＴ２２は、第１ゲート線Ｇａ(j)に印加される制御信号に応答して第ｋ＋１列目のデータ線Ｄ(k+1)と液晶素子２１（液晶素子ＣＬｂ）との接続状態を切り替えられるように、ゲート２２Ｇが第ｊ行目の第１ゲート線Ｇａ(j)に接続され、ドレイン２２Ｄが第ｋ＋１列目のデータ線Ｄ(k+1)に接続され、ソース２２Ｓが液晶素子２１の他方の端子に接続されている。 (Pixel part Pj (k + 1))
The first TFT 22 switches the connection state between the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 (liquid crystal element CLb) in response to a control signal applied to the first gate line Ga (j). As shown, the gate 22G is connected to the first gate line Ga (j) in the jth row, the drain 22D is connected to the data line D (k + 1) in the (k + 1) th column, and the source 22S is connected to the liquid crystal element 21. Is connected to the other terminal.
　第２ＴＦＴ２３は、第２ゲート線Ｇｂ(j)に印加される制御信号に応答して第ｋ＋２列目のデータ線Ｄ(k+2)と液晶素子２１との接続状態を切り替えられるように、ゲート２３Ｇが第ｊ行目の第２ゲート線Ｇｂ(j)に接続され、ドレイン２３Ｄが第ｋ＋２列目のデータ線Ｄ(k+2)に接続され、ソース２３Ｓが液晶素子２１の他方の端子に接続されている。 The second TFT 23 has a gate so that the connection state between the data line D (k + 2) in the (k + 2) th column and the liquid crystal element 21 can be switched in response to a control signal applied to the second gate line Gb (j). 23G is connected to the second gate line Gb (j) of the jth row, the drain 23D is connected to the data line D (k + 2) of the (k + 2) th column, and the source 23S is connected to the other terminal of the liquid crystal element 21. It is connected.
　　（画素部Ｐ(j+1)k）
　第１ＴＦＴ２２は、第２ゲート線Ｇｂ(j+1)に印加される制御信号に応答して第ｋ列目のデータ線Ｄ(k)と液晶素子２１（液晶素子ＣＬｃ）との接続状態を切り替えられるように、ゲート２２Ｇが第ｊ＋１行目の第２ゲート線Ｇｂ(j+1)に接続され、ドレイン２２Ｄが第ｋ列目のデータ線Ｄ(k)に接続され、ソース２２Ｓが液晶素子２１の他方の端子に接続されている。 (Pixel part P (j + 1) k)
The first TFT 22 switches the connection state between the data line D (k) in the kth column and the liquid crystal element 21 (liquid crystal element CLc) in response to a control signal applied to the second gate line Gb (j + 1). As shown, the gate 22G is connected to the second gate line Gb (j + 1) in the (j + 1) th row, the drain 22D is connected to the data line D (k) in the kth column, and the source 22S is connected to the liquid crystal element 21. Is connected to the other terminal.
　第２ＴＦＴ２３は、第１ゲート線Ｇａ(j+1)に印加される制御信号に応答して第ｋ＋１列目のデータ線Ｄ(k+1)と液晶素子２１との接続状態を切り替えられるように、ゲート２３Ｇが第ｊ＋１行目の第１ゲート線Ｇａ(j+1)に接続され、ドレイン２３Ｄが第ｋ＋１列目のデータ線Ｄ(k+1)に接続され、ソース２３Ｓが液晶素子２１の他方の端子に接続されている。 The second TFT 23 can switch the connection state between the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 in response to a control signal applied to the first gate line Ga (j + 1). The gate 23G is connected to the first gate line Ga (j + 1) of the (j + 1) th row, the drain 23D is connected to the data line D (k + 1) of the (k + 1) th column, and the source 23S is connected to the liquid crystal element 21. Connected to the other terminal.
　　（画素部Ｐ(j+1)(k+1)）
　第１ＴＦＴ２２は、第２ゲート線Ｇｂ(j+1)に印加される制御信号に応答して第ｋ＋１列目のデータ線Ｄ(k+1)と液晶素子２１（液晶素子ＣＬｄ）との接続状態を切り替えられるように、ゲート２２Ｇが第ｊ＋１行目の第２ゲート線Ｇｂ(j+1)に接続され、ドレイン２２Ｄが第ｋ＋１列目のデータ線Ｄ(k+1)に接続され、ソース２２Ｓが液晶素子２１の他方の端子に接続されている。 (Pixel part P (j + 1) (k + 1))
The first TFT 22 is connected to the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 (liquid crystal element CLd) in response to a control signal applied to the second gate line Gb (j + 1). The gate 22G is connected to the second gate line Gb (j + 1) of the (j + 1) th row, the drain 22D is connected to the data line D (k + 1) of the (k + 1) th column, and the source 22S Is connected to the other terminal of the liquid crystal element 21.
　第２ＴＦＴ２３は、第１ゲート線Ｇａ(j+1)に印加される制御信号に応答して第ｋ＋２列目のデータ線Ｄ(k+2)と液晶素子２１との接続状態を切り替えられるように、ゲート２３Ｇが第ｊ＋１行目の第１ゲート線Ｇａ(j+1)に接続され、ドレイン２３Ｄが第ｋ＋２列目のデータ線Ｄ(k+2)に接続され、ソース２３Ｓが液晶素子２１の他方の端子に接続されている。 The second TFT 23 can switch the connection state between the liquid crystal element 21 and the data line D (k + 2) of the (k + 2) th column in response to a control signal applied to the first gate line Ga (j + 1). The gate 23G is connected to the first gate line Ga (j + 1) in the (j + 1) th row, the drain 23D is connected to the data line D (k + 2) in the (k + 2) th column, and the source 23S is connected to the liquid crystal element 21. Connected to the other terminal.
　　（動作）
　次に、図３を参照して、液晶表示装置１０の動作について説明する。ここでは、表示データとして全面点灯のデータが入力されるものとする。 (Operation)
Next, the operation of the liquid crystal display device 10 will be described with reference to FIG. Here, it is assumed that data for lighting all over is input as display data.
　ｎ＋１本のデータ線Ｄは、常に正極性のデータ信号が印加されるデータ線と、常に負極性のデータ信号が印加されるデータ線とが行方向に交互に並ぶように配置されている。つまり、データドライバ１５は、奇数である整数ｏ（１≦ｏ≦ｎ＋１）に対して第ｏ列目のデータ線Ｄ（ｏ）には常に正極性のデータ信号を印加しかつ偶数である整数ｅ（２≦ｅ≦ｎ＋１）に対して第ｅ列目のデータ線Ｄ（ｅ）には常に負極性のデータ信号を印加する、或いは、奇数である整数ｏ（１≦ｏ≦ｎ＋１）に対して第ｏ列目のデータ線Ｄ（ｏ）には常に負極性のデータ信号を印加しかつ偶数である整数ｅ（２≦ｅ≦ｎ＋１）に対して第ｅ列目のデータ線Ｄ（ｅ）には常に正極性のデータ信号を印加する。ここでは、図３に示すように、データ線Ｄ(k)，Ｄ(k+2)には常に正極性のデータ信号が印加され、データ線Ｄ(k+1)には常に負極性のデータ信号が印加されることとする。 The n + 1 data lines D are arranged such that data lines to which positive data signals are always applied and data lines to which negative data signals are always applied are alternately arranged in the row direction. That is, the data driver 15 always applies a positive data signal to the data line D (o) in the o-th column with respect to the odd integer o (1 ≦ o ≦ n + 1) and is an even integer e. A negative data signal is always applied to the data line D (e) of the e-th column with respect to (2 ≦ e ≦ n + 1), or for an integer o (1 ≦ o ≦ n + 1) which is an odd number. A negative-polarity data signal is always applied to the o-th data line D (o), and the even-numbered integer e (2 ≦ e ≦ n + 1) is applied to the e-th data line D (e). Always applies a positive data signal. Here, as shown in FIG. 3, a positive data signal is always applied to the data lines D (k) and D (k + 2), and a negative data signal is always applied to the data line D (k + 1). A signal is applied.
　　（第１の駆動期間）
　まず、時刻ｔ１から時刻ｔ３までの第１の駆動期間における動作について説明する。 (First driving period)
First, the operation in the first drive period from time t 1 to time t 3 will be described.
　はじめに、時刻ｔ１においてフレーム同期信号ＦＲＭがＨレベルになると、第１ゲートドライバ１３が第１ゲート線Ｇａ(j)を選択し、第１ゲート線Ｇａ(j)がＨレベルになる。これにより、画素部Ｐjkの第１ＴＦＴ２２に第１ゲートドライバ１３から制御信号が印加されてオンとなると共に、データドライバ１５からデータ線Ｄ(k)を介して正極性のデータ信号が送信される。従って、第１の駆動期間中、液晶素子ＣＬａには正の駆動電圧が印加されることとなる。 First , when the frame synchronization signal FRM becomes H level at time t1, the first gate driver 13 selects the first gate line Ga (j), and the first gate line Ga (j) becomes H level. Thereby, a control signal is applied to the first TFT 22 of the pixel portion Pjk from the first gate driver 13 to be turned on, and a positive data signal is transmitted from the data driver 15 through the data line D (k). Therefore, a positive drive voltage is applied to the liquid crystal element CLa during the first drive period.
　同様に、時刻ｔ１において第１ゲート線Ｇａ(j)がＨレベルになると、画素部Ｐj(k+1)の第１ＴＦＴ２２に第１ゲートドライバ１３から制御信号が印加されてオンとなると共に、データドライバ１５からデータ線Ｄ(k+1)を介して負極性のデータ信号が送信される。従って、第１の駆動期間中、液晶素子ＣＬｂには負の駆動電圧が印加されることとなる。 Similarly, with at time t 1 a first gate line Ga (j) is becomes H level, the control signal from the first gate driver 13 is turned on is applied to the 1TFT22 pixel portion Pj (k + 1), A negative data signal is transmitted from the data driver 15 via the data line D (k + 1). Therefore, a negative drive voltage is applied to the liquid crystal element CLb during the first drive period.
　その後、時刻ｔ２において第１ゲートドライバ１３が第１ゲート線Ｇａ(j+1)を選択すると、第１ゲート線Ｇａ(j+1)がＨレベルになる。これにより、画素部Ｐ(j+1)kの第２ＴＦＴ２３に第１ゲートドライバ１３から制御信号が印加されてオンとなると共に、データドライバ１５からデータ線Ｄ(k+1)を介して負極性のデータ信号が送信される。従って、第１の駆動期間中、液晶素子ＣＬｃには負の駆動電圧が印加されることとなる。 Then, at time t 2 when the first gate driver 13 selects the first gate line Ga (j + 1), the first gate line Ga (j + 1) becomes the H level. As a result, the control signal is applied to the second TFT 23 of the pixel portion P (j + 1) k from the first gate driver 13 to be turned on, and the negative polarity is transmitted from the data driver 15 via the data line D (k + 1). Data signals are transmitted. Therefore, a negative drive voltage is applied to the liquid crystal element CLc during the first drive period.
　同様に、時刻ｔ２において第１ゲート線Ｇａ(j+1)がＨレベルになると、画素部Ｐ(j+1)(k+1)の第２ＴＦＴ２３に第１ゲートドライバ１３から制御信号が印加されてオンとなると共に、データドライバ１５からデータ線Ｄ(k+2)を介して正極性のデータ信号が送信される。従って、第１の駆動期間中、液晶素子ＣＬｄには正の駆動電圧が印加されることとなる。 Similarly, when the first gate line Ga (j + 1) becomes the H level at time t 2, the pixel portion P (j + 1) (k + 1) control signal from the first gate driver 13 to the 2TFT23 is applied Then, the data driver 15 is turned on, and a positive data signal is transmitted from the data driver 15 via the data line D (k + 2). Therefore, a positive drive voltage is applied to the liquid crystal element CLd during the first drive period.
　時刻ｔ２以降も同様にして、第１ゲートドライバ１３が水平同期信号に基づいて順次第１ゲート線Ｇａを選択し、第１の駆動期間中、各液晶素子に正または負の駆動電圧がそれぞれ印加される。 Time t 2 following the similar manner in the subsequent stages, the first gate driver 13 selects the forward first following gate line Ga on the basis of the horizontal synchronizing signal, in a first drive period, positive or negative driving voltage to each liquid crystal element Applied.
　　（第２の駆動期間）
　次に、時刻ｔ３から時刻ｔ５までの第２の駆動期間における動作について説明する。 (Second driving period)
Next, the operation in the second drive period from time t 3 to time t 5 will be described.
　時刻ｔ３においてフレーム同期信号ＦＲＭがＨレベルになると、第２ゲートドライバ１４が第２ゲート線Ｇｂ(j)を選択し、第２ゲート線Ｇｂ(j)がＨレベルになる。これにより、画素部Ｐjkの第２ＴＦＴ２３に第２ゲートドライバ１４から制御信号が印加されてオンとなると共に、データドライバ１５からデータ線Ｄ(k+1)を介して負極性のデータ信号が送信される。従って、第２の駆動期間中、液晶素子ＣＬａには負の駆動電圧が印加されることとなる。 When the frame sync signal FRM becomes H level at time t 3, the second gate driver 14 selects the second gate line Gb to (j), the second gate line Gb (j) becomes the H level. As a result, a control signal is applied to the second TFT 23 of the pixel portion Pjk from the second gate driver 14 to turn it on, and a negative data signal is transmitted from the data driver 15 via the data line D (k + 1). The Therefore, a negative drive voltage is applied to the liquid crystal element CLa during the second drive period.
　同様に、時刻ｔ３において第２ゲート線Ｇｂ(j)がＨレベルになると、画素部Ｐj(k+1)の第２ＴＦＴ２３に第２ゲートドライバ１４から制御信号が印加されてオンとなると共に、データドライバ１５からデータ線Ｄ(k+2)を介して正極性のデータ信号が送信される。従って、第２の駆動期間中、液晶素子ＣＬｂには正の駆動電圧が印加されることとなる。 Similarly, when the second gate line Gb (j) becomes H level at time t 3 , a control signal is applied to the second TFT 23 of the pixel portion Pj (k + 1) from the second gate driver 14 and turned on. A positive data signal is transmitted from the data driver 15 via the data line D (k + 2). Therefore, a positive drive voltage is applied to the liquid crystal element CLb during the second drive period.
　その後、時刻ｔ４において第２ゲートドライバ１４が第２ゲート線Ｇｂ(j+1)を選択すると、第２ゲート線Ｇｂ(j+1)がＨレベルになる。これにより、画素部Ｐ(j+1)kの第１ＴＦＴ２２に第２ゲートドライバ１４から制御信号が印加されてオンとなると共に、データドライバ１５からデータ線Ｄ(k)を介して正極性のデータ信号が送信される。従って、第２の駆動期間中、液晶素子ＣＬｃには正の駆動電圧が印加されることとなる。 Thereafter, when the second gate driver 14 selects second gate line Gb the (j + 1) at time t 4, the second gate line Gb (j + 1) becomes the H level. As a result, a control signal is applied to the first TFT 22 of the pixel portion P (j + 1) k from the second gate driver 14 to turn it on, and positive data from the data driver 15 via the data line D (k). A signal is transmitted. Therefore, a positive drive voltage is applied to the liquid crystal element CLc during the second drive period.
　同様に、時刻ｔ４において第２ゲート線Ｇｂ(j+1)がＨレベルになると、画素部Ｐ(j+1)(k+1)の第１ＴＦＴ２２に第２ゲートドライバ１４から制御信号が印加されてオンとなると共に、データドライバ１５からデータ線Ｄ(k+1)を介して負極性のデータ信号が送信される。従って、第２の駆動期間中、液晶素子ＣＬｄには負の駆動電圧が印加されることとなる。 Similarly, when the second gate line Gb (j + 1) becomes the H level at time t 4, the pixel portion P (j + 1) (k + 1) control signal from the second gate driver 14 to the 1TFT22 is applied Then, the data driver 15 is turned on, and a negative data signal is transmitted from the data driver 15 via the data line D (k + 1). Therefore, a negative drive voltage is applied to the liquid crystal element CLd during the second drive period.
　時刻ｔ４以降も同様にして、第２ゲートドライバ１４が水平同期信号に基づいて順次第２ゲート線Ｇｂを選択し、第２の駆動期間中、各液晶素子に正または負の駆動電圧がそれぞれ印加される。 Time t 4 later are similarly the second gate driver 14 selects the forward order second gate line Gb based on a horizontal synchronizing signal, in a second drive period, positive or negative driving voltage to each liquid crystal element Applied.
　また、時刻ｔ５以降の駆動期間においては、上記説明した第１の駆動期間と第２の駆動期間の動作が順番に繰り返される。 In the after time t 5 of the drive period, the operation of the first drive period and second drive period described above are repeated in sequence.
　以上説明したように、データ線Ｄ(k)及びデータ線Ｄ(k+2)に常に正極性のデータ信号を印加し、データ線Ｄ(k+1)に常に負極性のデータ信号を印加することにより、第１の駆動期間においては、図４（ａ）に示すように、液晶素子ＣＬａ，ＣＬｂ，ＣＬｃ，及びＣＬｄにはそれぞれ正、負、負、及び正の駆動電圧が印加され、第２の駆動期間においては、図４（ｂ）に示すように、液晶素子ＣＬａ，ＣＬｂ，ＣＬｃ，及びＣＬｄにはそれぞれ負、正、正、及び負の駆動電圧が印加される。従って、各データ線Ｄへ印加するデータ信号の極性を反転させることなく、隣接する液晶素子同士で逆極性とすることができ、また、各液晶素子ＣＬａ，ＣＬｂ，ＣＬｃ，ＣＬｄにおいて印加される電圧の極性を１フレームごとに反転することができる。 As described above, a positive data signal is always applied to the data line D (k) and the data line D (k + 2), and a negative data signal is always applied to the data line D (k + 1). Thus, in the first drive period, as shown in FIG. 4A, positive, negative, negative, and positive drive voltages are applied to the liquid crystal elements CLa, CLb, CLc, and CLd, respectively. In the second drive period, as shown in FIG. 4B, negative, positive, positive, and negative drive voltages are applied to the liquid crystal elements CLa, CLb, CLc, and CLd, respectively. Therefore, the polarity of the data signal applied to each data line D can be reversed between adjacent liquid crystal elements without reversing the polarity, and the voltage applied to each liquid crystal element CLa, CLb, CLc, CLd. Can be inverted every frame.
　なお、上記実施形態では、第１ゲートドライバ１３、第２ゲートドライバ１４及びデータドライバ１５はアクティブマトリクス基板２０の外に設けられているとしたが、これらがアクティブマトリクス基板２０の周辺領域に形成されていてもよい。 In the above embodiment, the first gate driver 13, the second gate driver 14, and the data driver 15 are provided outside the active matrix substrate 20, but these are formed in the peripheral region of the active matrix substrate 20. It may be.
　　（実施形態１の効果）
　実施形態１によれば、各データ線Ｄに印加されるデータ信号の極性を充放電させて反転させることなく、常に正極性のデータ信号または負極性のデータ信号を送信することにより各液晶素子２１に印加される電圧の極性を反転することができるので、駆動電力の消費を抑制することができる。また、各データ線Ｄに印加されるデータ信号の極性を充放電させて反転させることなく各液晶素子２１に印加される電圧の極性を反転することができるので、安定な制御を高速で行うことが可能となる。 (Effect of Embodiment 1)
According to the first embodiment, each liquid crystal element 21 is transmitted by always transmitting a positive polarity data signal or a negative polarity data signal without charging and discharging the polarity of the data signal applied to each data line D. Since the polarity of the voltage applied to can be reversed, driving power consumption can be suppressed. In addition, since the polarity of the voltage applied to each liquid crystal element 21 can be inverted without charging and discharging the polarity of the data signal applied to each data line D, stable control can be performed at high speed. Is possible.
　さらに、実施形態１によれば第１ＴＦＴ２２と第２ＴＦＴ２３とが酸化物半導体膜を備えているので、高速書き込み駆動が可能となる。図５（ａ）～（ｃ）は、高速書き込み後に休止する駆動においてフリッカパターンを画面表示した場合の、書き込み時間とパネル表面輝度の関係を示す。図５（ａ）の各フレーム毎の書き込み時間をＡ［ｍｓｅｃ］として、図５（ｂ）は書き込み時間が２／３×Ａ［ｍｓｅｃ］、図５（ｃ）は書き込み時間が１／２×Ａ［ｍｓｅｃ］の場合を示す。図５より、各フレーム毎の書き込み時間が短くなるほど輝度の振幅が小さくなり、画面輝度のチラツキが低減されることが知られている。従って、高速で書き込みを行うことにより、画面の輝度変化を抑制することができると共に、書き込み休止期間のＴＦＴオフリークによる画素電位変化を低減することができる。そのため、フリッカによる表示の劣化をさらに抑制することができる。 Furthermore, according to the first embodiment, since the first TFT 22 and the second TFT 23 include the oxide semiconductor film, high-speed writing driving is possible. FIGS. 5A to 5C show the relationship between the writing time and the panel surface brightness when the flicker pattern is displayed on the screen in the drive that pauses after high-speed writing. The write time for each frame in FIG. 5A is A [msec], FIG. 5B is the write time 2/3 × A [msec], and FIG. 5C is the write time 1/2 ×. A case of A [msec] is shown. From FIG. 5, it is known that as the writing time for each frame becomes shorter, the luminance amplitude becomes smaller and the flickering of the screen luminance is reduced. Therefore, by performing writing at high speed, it is possible to suppress a change in luminance of the screen and to reduce a change in pixel potential due to TFT off-leak during the writing suspension period. Therefore, display deterioration due to flicker can be further suppressed.
　また、実施形態１によれば、１つの画素部Ｐに２つのＴＦＴ（第１ＴＦＴ２２及び第２ＴＦＴ２３）が設けられているが、１本のデータ線Ｄ（ここでは、例えば第ｋ＋１列目のデータ線Ｄ(k+1)）は、第ｋ列目の画素列に含まれる画素部Ｐjkの第２ＴＦＴ２３にデータ信号を与える一方で第ｋ＋１列目の画素列に含まれる画素部Ｐj(k+1)の第１ＴＦＴ２２にデータ信号を与えるように構成されている、或いは、第ｋ列目の画素列に含まれる画素部Ｐ(j+1)kの第１ＴＦＴ２２にデータ信号を与える一方で第ｋ＋１列目の画素列に含まれる画素部Ｐ(j+1)(k+1)の第２ＴＦＴ２３にデータ信号を与えるように構成されているので、隣接する画素列（第ｋ列目及び第ｋ＋１列目）を区画する各部分にデータ線Ｄが１本ずつ配置されていればよい。このため、第１ＴＦＴ２２及び第２ＴＦＴ２３を各々駆動するために１つの画素列あたり２本のデータ線を配置する必要が無く、アクティブマトリクス基板２０の開口率を大きく確保でき、その結果として、バックライトの消費電力を抑制することができる。 Further, according to the first embodiment, two TFTs (first TFT 22 and second TFT 23) are provided in one pixel portion P, but one data line D (here, for example, the data line in the (k + 1) th column) D (k + 1)) provides a data signal to the second TFT 23 of the pixel unit Pjk included in the kth pixel column, while the pixel unit Pj (k + 1) included in the k + 1th pixel column. The first TFT 22 is configured to provide a data signal, or a data signal is applied to the first TFT 22 of the pixel portion P (j + 1) k included in the kth pixel column, while the k + 1th column. Since the data signal is supplied to the second TFT 23 of the pixel portion P (j + 1) (k + 1) included in the pixel column, the adjacent pixel columns (the k-th column and the k + 1-th column) It is only necessary that one data line D is arranged in each part that divides the area. Therefore, it is not necessary to arrange two data lines per pixel column in order to drive each of the first TFT 22 and the second TFT 23, and the aperture ratio of the active matrix substrate 20 can be secured large. As a result, the backlight Power consumption can be suppressed.
　さらに、実施形態１によれば、ｎ＋１本のデータ線Ｄは、正極性のデータ信号が印加されるデータ線と負極性のデータ信号が印加されるデータ線が交互に並ぶように配置されているので、これらのデータ線Ｄを単一種類のデータドライバ１５で駆動することが可能であり、複数種類のデータドライバを設ける場合よりもデータドライバ１５の駆動のための消費電力を抑制することができる。また、複数種類のデータドライバを設ける場合よりも製造コストを低減することができる。さらに、複数種類のデータドライバを設ける場合よりも狭額縁化することができる。 Further, according to the first embodiment, the n + 1 data lines D are arranged such that data lines to which a positive data signal is applied and data lines to which a negative data signal is applied are alternately arranged. Therefore, it is possible to drive these data lines D with a single type of data driver 15, and power consumption for driving the data driver 15 can be suppressed as compared with the case where a plurality of types of data drivers are provided. . Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Furthermore, the frame can be narrower than when a plurality of types of data drivers are provided.
　実施形態１によれば、本発明のアクティブマトリクス基板２０は、第１ゲート線Ｇａ及び第２ゲート線Ｇｂは、アクティブマトリクス基板２０上において、列方向に交互に並ぶように配置されている。これにより、第１ゲート線Ｇａ(j+1)と第２ゲート線Ｇｂ(j)の一対が第ｊ行目の画素行と第ｊ＋１行目の画素行を列方向に区画するように配置されることとなる。第１の駆動期間では第１ゲート線Ｇａに制御信号が印加される一方で第２ゲート線Ｇｂには制御信号が印加されず、第２の駆動期間では第２ゲート線Ｇｂに制御信号が印加される一方で第１ゲート線Ｇａには制御信号が印加されない。つまり、第１ゲート線Ｇａ(j+1)と第２ゲート線Ｇｂ(j)には同一フレームに両ゲート線に対し制御信号が印加されることがないので、第１ゲート線Ｇａ(j+1)と第２ゲート線Ｇｂ(j)の一対が第ｊ行目の画素行と第ｊ＋１行目の画素行を列方向に区画するように配置されても、一対の第１ゲート線Ｇａ(j+1)と第２ゲート線Ｇｂ(j)間での寄生容量による駆動特性の劣化を抑制することができる。 According to the first embodiment, in the active matrix substrate 20 of the present invention, the first gate lines Ga and the second gate lines Gb are arranged on the active matrix substrate 20 so as to be alternately arranged in the column direction. Thus, a pair of the first gate line Ga (j + 1) and the second gate line Gb (j) is arranged so as to partition the pixel row of the jth row and the pixel row of the j + 1th row in the column direction. The Rukoto. In the first driving period, a control signal is applied to the first gate line Ga, while no control signal is applied to the second gate line Gb, and in the second driving period, a control signal is applied to the second gate line Gb. On the other hand, no control signal is applied to the first gate line Ga. That is, since no control signal is applied to the first gate line Ga (j + 1) and the second gate line Gb (j) for both gate lines in the same frame, the first gate line Ga (j + 1) and the second gate line Gb (j) are arranged so as to partition the j-th pixel row and the j + 1-th pixel row in the column direction, the pair of first gate lines Ga ( j + 1) and the second gate line Gb (j) can suppress the deterioration of drive characteristics due to parasitic capacitance.
　　　　　　　＜変形例＞
　実施形態１では、第１ゲート線Ｇａ及び第２ゲート線Ｇｂがアクティブマトリクス基板２０上において列方向に交互に並ぶように配置されているとしたが、図６に変形例として示すように、第１ゲート線Ｇａ及び第２ゲート線Ｇｂが交互に並ばないように配置されていてもよい。 <Modification>
In the first embodiment, the first gate lines Ga and the second gate lines Gb are arranged so as to be alternately arranged in the column direction on the active matrix substrate 20, but as shown in FIG. The first gate line Ga and the second gate line Gb may be arranged so as not to be arranged alternately.
　この場合、列方向に隣接する画素部Ｐjk、Ｐ(j+1)kにおいて、画素部Ｐjkの第２ＴＦＴ２３と画素部Ｐ(j+1)kの第１ＴＦＴ２２とが、２本の第２ゲート線Ｇｂ(j)，Ｇｂ(j+1)を挟んで両側に対向して配置される。また、列方向に隣接する画素部Ｐ(j-1)k、Ｐjkにおいては、画素部Ｐ(j-1)kの第２ＴＦＴ２３と画素部Ｐjkの第１ＴＦＴ２２とが、２本の第１ゲート線Ｇｂ(j-1)，Ｇｂ(j)を挟んで両側に対向して配置される。つまり、２本の第１ゲート線Ｇａまたは２本の第２ゲート線Ｇｂを介して第１ＴＦＴ２２と第２ＴＦＴ２３とが両側に対向して配置され、これにより、アクティブマトリクス基板２０の開口率を大きく確保することができる。 In this case, in the pixel portions Pjk and P (j + 1) k adjacent in the column direction, the second TFT 23 of the pixel portion Pjk and the first TFT 22 of the pixel portion P (j + 1) k are two second gate lines. They are arranged opposite to each other across Gb (j) and Gb (j + 1). In the pixel portions P (j−1) k and Pjk adjacent in the column direction, the second TFT 23 of the pixel portion P (j−1) k and the first TFT 22 of the pixel portion Pjk are two first gate lines. They are arranged opposite to each other across Gb (j-1) and Gb (j). That is, the first TFT 22 and the second TFT 23 are arranged opposite to each other via the two first gate lines Ga or the two second gate lines Gb, thereby ensuring a large aperture ratio of the active matrix substrate 20. can do.
　また、実施形態１では、ｎ＋１本のデータ線Ｄは、常に正極性のデータ信号が印加されるデータ線及び常に負極性のデータ信号が印加されるデータ線を含むとして説明したが、あるときは、特定のデータ線Ｄ（ここではデータ線Ｄ(k)とする）に正極性のデータ信号が印加され、また別のときには、データ線Ｄ(k)に負極性のデータ信号が印加されてもよい。或いは、複数フレーム毎に、特定のデータ線Ｄ(k)に対して印加される電圧の極性が反転しても構わない。この場合でも、１フレーム毎に各データ線に印加するデータ信号の極性を反転させることなくドット反転駆動を行うことができるので、上述したように、１フレームごとにデータ線に印加する電圧の極性を反転させる場合よりも消費電力を低減することが可能となる。 In the first embodiment, the n + 1 data lines D are described as including a data line to which a positive data signal is always applied and a data line to which a negative data signal is always applied. A positive data signal is applied to a specific data line D (here, data line D (k)), and in another case, a negative data signal is applied to the data line D (k). Good. Alternatively, the polarity of the voltage applied to the specific data line D (k) may be inverted every plural frames. Even in this case, since the dot inversion drive can be performed without inverting the polarity of the data signal applied to each data line for each frame, the polarity of the voltage applied to the data line for each frame as described above. The power consumption can be reduced as compared with the case of inversion.
　本発明は、アクティブマトリクス基板及び液晶表示装置について有用である。特に、本発明は、低周波数で駆動可能であって且つ画面輝度のチラツキ（フリッカ）による表示の劣化を抑制したアクティブマトリクス基板及び液晶表示装置について有用である。 The present invention is useful for an active matrix substrate and a liquid crystal display device. In particular, the present invention is useful for an active matrix substrate and a liquid crystal display device that can be driven at a low frequency and suppress display deterioration due to flickering of screen brightness.
Ｄ　　　　　データ線
Ｇａ　　　　第１ゲート線
Ｇｂ　　　　第２ゲート線
Ｐ　　　　　画素部
１０　　　　液晶表示装置
１３　　　　第１ゲートドライバ
１４　　　　第２ゲートドライバ
１５　　　　データドライバ
２０　　　　アクティブマトリクス基板
２１（ＣＬ）液晶素子
２２　　　　第１スイッチング素子（第１ＴＦＴ）
２３　　　　第２スイッチング素子（第２ＴＦＴ） D data line Ga first gate line Gb second gate line P pixel unit 10 liquid crystal display device 13 first gate driver 14 second gate driver 15 data driver 20 active matrix substrate 21 (CL) liquid crystal element 22 first switching element (first 1 TFT)
23 Second switching element (second TFT)

Claims (4)

  1. 　ｍ行ｎ列（ｍ，ｎは、２以上の整数）のマトリクス状に配列されたｍ×ｎ個の画素部と、
    　上記ｍ×ｎ個の画素部のｍ行の画素行にそれぞれ対応し、行方向に沿って互いに並行して延びると共に列方向に互いに離間するｍ本の第１のゲート線及びｍ本の第２のゲート線と、
    　正極性のデータ信号が印加されるデータ線及び負極性のデータ信号が印加されるデータ線を含み、上記ｍ×ｎ個の画素部のｎ列の画素列を区画するように列方向に沿って互いに並行して延びると共に該正極性のデータ信号が印加されるデータ線と該負極性のデータ信号が印加されるデータ線とが行方向に交互に並ぶように配置されるｎ＋１本のデータ線と、
    を備え、
    　上記ｍ×ｎ個の画素部のうち第ｋ列目（１≦ｋ≦ｎ）の画素列に含まれるｍ個の画素部の各々は、
    　　液晶素子と、
    　　上記画素部に対応する第１及び第２ゲート線の間に配置され、該第１及び第２のゲート線のうち一方に印加される制御信号に応答して、第ｋ列目のデータ線と上記液晶素子との接続状態を切り替える第１のスイッチング素子と、
    　　上記画素部に対応する第１及び第２ゲート線の間に配置され、該第１及び第２のゲート線のうち他方に印加される制御信号に応答して、第ｋ＋１列目のデータ線と上記液晶素子との接続状態を切り替える第２のスイッチング素子と、
    を含むことを特徴とするアクティブマトリクス基板。     m × n pixel units arranged in a matrix of m rows and n columns (m and n are integers of 2 or more);
    The m first gate lines and the m second gate lines respectively corresponding to the m pixel rows of the m × n pixel portions extend in parallel with each other in the row direction and are spaced apart from each other in the column direction. The gate line,
    Including a data line to which a positive data signal is applied and a data line to which a negative data signal is applied, along the column direction so as to partition n pixel columns of the m × n pixel units. N + 1 data lines that extend in parallel with each other and are arranged so that the data lines to which the positive polarity data signal is applied and the data lines to which the negative polarity data signal is applied are alternately arranged in the row direction; ,
    With
    Of the m × n pixel units, each of the m pixel units included in the kth column (1 ≦ k ≦ n) pixel column is
    A liquid crystal element;
    In response to a control signal disposed between the first and second gate lines corresponding to the pixel portion and applied to one of the first and second gate lines, the kth data line and A first switching element that switches a connection state with the liquid crystal element;
    In response to a control signal disposed between the first and second gate lines corresponding to the pixel portion and applied to the other of the first and second gate lines, the (k + 1) th column data line and A second switching element that switches a connection state with the liquid crystal element;
    An active matrix substrate comprising:
  2. 　請求項１において、
    　上記第１のゲート線と上記第２のゲート線とが列方向において交互に並ぶように配置される
    ことを特徴とするアクティブマトリクス基板。     In claim 1,
    An active matrix substrate, wherein the first gate lines and the second gate lines are alternately arranged in a column direction.
  3. 　請求項１または２において、
    　上記第１スイッチング素子及び上記第２スイッチング素子のそれぞれは酸化物半導体膜を備えた薄膜トランジスタである
    ことを特徴とするアクティブマトリクス基板。     In claim 1 or 2,
    An active matrix substrate, wherein each of the first switching element and the second switching element is a thin film transistor including an oxide semiconductor film.
  4. 　請求項１～３のいずれか１項に記載のアクティブマトリクス基板と、
    　行方向において正極性のデータ信号の印加の対象となるデータ線と負極性のデータ信号の印加の対象となるデータ線とが交互に並ぶように、各データ信号を上記ｎ＋１本のデータ線にそれぞれ印加するデータドライバと、
    　第１の駆動期間では、上記ｍ本の第１のゲート線のいずれか１本に上記第１のスイッチング素子に送信する制御信号を印加し、第２の駆動期間では、上記ｍ本の第１のゲート線のいずれにも制御信号を印加しない第１のゲートドライバと、
    　上記第１の駆動期間では、上記ｍ本の第２のゲート線のいずれにも制御信号を印加せず、上記第２の駆動期間では、上記ｍ本の第２のゲート線のいずれか１本に上記第２のスイッチング素子に送信する制御信号を印加する第２のゲートドライバと、
    を備えることを特徴とする液晶表示装置。     The active matrix substrate according to any one of claims 1 to 3,
    In the row direction, the data signals are applied to the n + 1 data lines so that the data lines to be applied with the positive data signal and the data lines to be applied with the negative data signal are alternately arranged in the row direction. A data driver to be applied;
    In the first driving period, a control signal to be transmitted to the first switching element is applied to any one of the m first gate lines. In the second driving period, the m first gate lines are applied. A first gate driver that does not apply a control signal to any of the gate lines;
    In the first driving period, no control signal is applied to any of the m second gate lines, and in the second driving period, any one of the m second gate lines. A second gate driver for applying a control signal to be transmitted to the second switching element;
    A liquid crystal display device comprising:
PCT/JP2012/002296 2011-04-05 2012-04-02 Active matrix substrate and liquid crystal display device WO2012137472A1 (en)

Applications Claiming Priority (2)

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JP2011-083959 2011-04-05
JP2011083959 2011-04-05

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113409718A (en) * 2021-05-27 2021-09-17 惠科股份有限公司 Display panel and display device
CN114333726A (en) * 2021-12-29 2022-04-12 惠科股份有限公司 Display panel and display device
JP7529758B2 (en) 2020-03-19 2024-08-06 京東方科技集團股▲ふん▼有限公司 Display substrate and display device

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JP2006139288A (en) * 2004-11-12 2006-06-01 Samsung Electronics Co Ltd Display apparatus and driving method thereof
JP2007121767A (en) * 2005-10-28 2007-05-17 Nec Lcd Technologies Ltd Liquid crystal display device
JP2010135780A (en) * 2008-11-07 2010-06-17 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method thereof

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JP2006139288A (en) * 2004-11-12 2006-06-01 Samsung Electronics Co Ltd Display apparatus and driving method thereof
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JP2010135780A (en) * 2008-11-07 2010-06-17 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method thereof

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Publication number Priority date Publication date Assignee Title
JP7529758B2 (en) 2020-03-19 2024-08-06 京東方科技集團股▲ふん▼有限公司 Display substrate and display device
CN113409718A (en) * 2021-05-27 2021-09-17 惠科股份有限公司 Display panel and display device
CN113409718B (en) * 2021-05-27 2022-02-18 惠科股份有限公司 Display panel and display device
CN114333726A (en) * 2021-12-29 2022-04-12 惠科股份有限公司 Display panel and display device

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