WO2012134846A2 - Système, procédé et appareil pour décoder un code de convolution qui se mord la queue - Google Patents

Système, procédé et appareil pour décoder un code de convolution qui se mord la queue Download PDF

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Publication number
WO2012134846A2
WO2012134846A2 PCT/US2012/029588 US2012029588W WO2012134846A2 WO 2012134846 A2 WO2012134846 A2 WO 2012134846A2 US 2012029588 W US2012029588 W US 2012029588W WO 2012134846 A2 WO2012134846 A2 WO 2012134846A2
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WIPO (PCT)
Prior art keywords
stage
state
trellis
sets
decoder
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PCT/US2012/029588
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English (en)
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WO2012134846A3 (fr
Inventor
Tzahl WEISMAN
Tom Harel
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Intel Corporation
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Application filed by Intel Corporation filed Critical Intel Corporation
Priority to EP20120764606 priority Critical patent/EP2692063A4/fr
Priority to CN201280015779.3A priority patent/CN103444086B/zh
Publication of WO2012134846A2 publication Critical patent/WO2012134846A2/fr
Publication of WO2012134846A3 publication Critical patent/WO2012134846A3/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/413—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors tail biting Viterbi decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3972—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using sliding window techniques or parallel windows
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6511—Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0059—Convolutional codes

Definitions

  • Convolutional codes are typically used for wireless data transfer. Often convolutional codes are used in applications such as mobile communications, digital video, radio, and satellite communications, among other applications. Digital
  • a convolutional code is a code that begins and ends with the same state.
  • a circular Viterbi technique with extra bits may be used.
  • the extra bits facilitate the convergence of a trellis.
  • a trellis is a diagram or graph that may be used to decode a convolutional code. After a length of the trellis plus the extra bits is determined, a state having a best metric may be identified and used as a starting point for a traceback operation.
  • the traceback operation may output an estimated number of message bits. For instance, in some cases as many as one hundred extra bits or more are used.
  • this traditional approach suffers from performance loss and a large overhead leading to relatively poor results for shorter message lengths.
  • a WAVA technique processes a tail biting trellis iteratively by exploring an initial state of a transmitted sequence though continuous Viterbi decoding and improving the decoding decision with iterations. Path metrics are used to derive a sufficient condition for the decision to be optimal. While the WAVA algorithm approaches maximum likelihood performance, several iterations matching a length of a trellis are required along with complicated stopping conditions. As a result, a WAVA algorithm is complex and has an inefficient processing time.
  • WAV A wrapped around Viterbi algorithm
  • FIG. 1 illustrates an embodiment of a communications system.
  • FIG. 2 illustrates an embodiment of a logic flow for the system of FIG. 1.
  • FIG. 3 illustrates an embodiment of a three overlapping sets for an exemplary trellis of tail biting convolutional code.
  • FIG. 4 illustrates an embodiment of a trellis with the beginning and ending states.
  • FIG. 5 illustrates an embodiment of a computing architecture.
  • Various embodiments are generally directed to wireless communications systems. Some embodiments are particularly directed to one or more enhanced decoding techniques to decode a convolutional code for a wireless communications system, such as a tail biting convolutional code, among others.
  • Current techniques using the Viterbi algorithm for decoding a convolutional tail biting code often have a relatively large iteration length. The long iteration length hampers actual implementation for larger messages and thus leads to non-optimal algorithms that use an unnecessary number of extra bits. Further, these algorithms suffer from considerable performance loss as well as a large relative overhead when shorter messages are involved.
  • a convolution code may encode a bitstream using forward error correction.
  • a plurality of sets for a trellis of a convolutional code may be determined.
  • a trellis is a type of diagram used to decode a convolutional code.
  • a trellis may be divided into multiple overlapping sets.
  • each set may include a first stage and a second stage of the trellis and each set may overlap with at least one other set.
  • Path metrics may be determined for each state in a set when the first stage and the second stage have a same state.
  • Path metrics may be a summary of the branches or path used in the trellis from the first stage to the second stage.
  • the path metrics may be compared to determine a state with a minimum path metric.
  • a minimum path metric may be an optimal path from a first stage to a second stage.
  • Bits may be output from the state with a minimum path metric.
  • decoding the convolutional code may reach near optimal performance efficiency for a convolutional code with a shorter message length. As a result, embodiments can improve affordability, scalability, modularity, extendibility, or interoperability for an operator, device or network.
  • FIG. 1 illustrates a block diagram for a system 100.
  • the system 100 may comprise a communications system 100.
  • the system 100 shown in FIG. 1 has a limited number of elements in a certain topology, it may be appreciated that the system 100 may include more or less elements in alternate topologies as desired for a given implementation.
  • the communications system 100 may comprise, or form part of a wired communications system, a wireless communications system, or a combination of both.
  • the communications system 100 may include one or more devices arranged to communicate information over one or more types of wired communication links.
  • Examples of a wired communication link may include, without limitation, a wire, cable, bus, printed circuit board (PCB), Ethernet connection, peer-to- peer (P2P) connection, backplane, switch fabric, semiconductor material, twisted-pair wire, co-axial cable, fiber optic connection, and so forth.
  • the communications system 100 also may include one or more devices arranged to communicate information over one or more types of wireless communication links, such as wireless shared media 150.
  • Examples of a wireless communication link may include, without limitation, a radio channel, infrared channel, radio-frequency (RF) channel, Wireless Fidelity (WiFi) channel, a portion of the RF spectrum, and/or one or more licensed or license-free frequency bands.
  • the wireless devices may include one more wireless interfaces and/or components for wireless communication, such as one or more transmitters, receivers, transmitter/receivers ("transceivers"), radios, chipsets, amplifiers, filters, control logic, network interface cards (NICs), antennas, antenna arrays, and so forth.
  • an antenna may include, without limitation, an internal antenna, an omni-directional antenna, a monopole antenna, a dipole antenna, an end fed antenna, a circularly polarized antenna, a micro-strip antenna, a diversity antenna, a dual antenna, an antenna array, and so forth.
  • certain devices may include antenna arrays of multiple antennas to implement various adaptive antenna techniques and spatial diversity techniques.
  • the communications system 100 may communicate information in accordance with one or more standards as promulgated by a standards organization.
  • the communications system 100 may comprise or be implemented as a mobile broadband communications system. Examples of mobile broadband
  • the communications systems include, without limitation, systems compliant with various Institute of Electrical and Electronics Engineers (IEEE) standards, such as the IEEE 802.11 standards for Wireless Local Area Networks (WLANs) and variants, the IEEE 802.16 standards for Wireless Metropolitan Area Networks (WMANs) and variants, and the IEEE 802.20 or Mobile Broadband Wireless Access (MBWA) standards and variants, among others.
  • IEEE Institute of Electrical and Electronics Engineers
  • the communications system 100 may be implemented in accordance with the Worldwide Interoperability for Microwave Access (WiMAX) or WiMAX II standard.
  • WiMAX is a wireless broadband technology based on the IEEE 802.16 standard of which IEEE 802.16-2004 and the 802.16e amendment (802.16e-2005) are Physical (PHY) layer specifications.
  • WiMAX II is an advanced Fourth Generation (4G) system based on the IEEE 802.16j and IEEE 802.16m proposed standards for International Mobile Telecommunications (IMT) Advanced 4G series of standards. The embodiments are not limited in this context.
  • the communications system 100 may communicate, manage, or process information in accordance with one or more protocols.
  • a protocol may comprise a set of predefined rules or instructions for managing communication among devices.
  • the communications system 100 may employ one or more protocols such as a beam forming protocol, medium access control (MAC) protocol, Physical Layer Convergence Protocol (PLCP), Simple Network Management Protocol (SNMP), Asynchronous Transfer Mode (ATM) protocol, Frame Relay protocol, Systems Network Architecture (SNA) protocol, Transport Control Protocol (TCP), Internet Protocol (IP), TCP/IP, X.25, Hypertext Transfer Protocol (HTTP), User Datagram
  • MAC medium access control
  • PLCP Physical Layer Convergence Protocol
  • SNMP Simple Network Management Protocol
  • ATM Asynchronous Transfer Mode
  • Frame Relay protocol Frame Relay protocol
  • SNA Systems Network Architecture
  • TCP Internet Protocol
  • IP Internet Protocol
  • TCP/IP Transmission Control Protocol
  • HTTP Hypertext Transfer Protocol
  • UDP User Datagram Protocol
  • CBP contention-based period
  • CBP distributed contention-based period
  • the communications system 100 also may be arranged to operate in accordance with standards and/or protocols for media processing. The embodiments are not limited in this context.
  • the communication system 100 may have one or more devices 110, 120.
  • a device 110, 120 generally may comprise any physical or logical entity for communicating information in communications system 100.
  • a device 110, 120 may be implemented as hardware, software, or any combination thereof, as desired for a given set of design parameters or performance constraints.
  • FIG. 1 may show a limited number of devices by way of example, it can be appreciated that more or less devices may be employed for a given implementation.
  • a device 110, 120 may be a computer-implemented system having one or more software applications and/or components.
  • a device 110, 120 may comprise, or be implemented as, a computer system, a computing device, a computer sub-system, a computer, an appliance, a workstation, a terminal, a server, a personal computer (PC), a laptop, an ultra-laptop, a handheld computer, a personal digital assistant (PDA), a smart phone, a tablet computer, a gaming device, a set top box (STB), a television, a digital television, a telephone, a mobile telephone, a cellular telephone, a handset, a wireless access point, a base station (BS), a subscriber station (SS), a mobile subscriber center (MSC), a radio network controller (R C), a microprocessor, an integrated circuit such as an application specific integrated circuit (ASIC), a
  • ASIC application specific integrated circuit
  • PLD programmable logic device
  • processor such as general purpose processor, a digital signal processor (DSP) and/or a network processor
  • interface an input/output (I/O) device (e.g., keyboard, mouse, display, printer), a router, a hub, a gateway, a bridge, a switch, a circuit, a logic gate, a register, a semiconductor device, a chip, a transistor, or any other device, machine, tool, equipment, component, or combination thereof.
  • I/O input/output
  • a device 110, 120 may comprise, or be implemented as, software, a software module, an application, a program, a subroutine, an instruction set, computing code, words, values, symbols or combination thereof.
  • a device 110, 120 may be implemented according to a predefined computer language, manner or syntax, for instructing a processor to perform a certain function. Examples of a computer language may include C, C++, Java, BASIC, Perl, Matlab, Pascal, Visual BASIC, assembly language, machine code, micro-code for a network processor, and so forth.
  • a device 110, 120 may execute processing operations or logic for the system 100 using a processing component 130.
  • the processing component 130 may comprise various hardware elements, software elements, or a combination of both.
  • hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth.
  • Examples of software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation.
  • the device 110 may communicate with other devices, such as, but not limited to, device 120, over a communications media 150 using communications signals via the communications component 140.
  • communications media 150 includes wired communications media and wireless communications media.
  • wired communications media 150 may include a wire, cable, metal leads, printed circuit boards (PCB), backplanes, switch fabrics, semiconductor material, twistedpair wire, co-axial cable, fiber optics, a propagated signal, and so forth.
  • Examples of wireless communications media may include acoustic, radio-frequency (RF) spectrum, infrared and other wireless media.
  • RF radio-frequency
  • the devices 110, 120 of communications system 100 may be arranged to communicate one or more types of information, such as media information and control information.
  • Media information generally may refer to any data representing content meant for a user, such as image information, video information, graphical information, audio information, voice information, textual information, numerical information, alphanumeric symbols, character symbols, and so forth.
  • Control information generally may refer to any data representing commands, instructions or control words meant for an automated system. For example, control information may be used to route media information through a system, or instruct a device to process the media information in a certain manner.
  • the media and control information may be communicated from and to a number of different devices or networks.
  • the device 1 10 may execute communications operations or logic using
  • the communications component 140 may implement any well-known communications techniques and protocols, such as techniques suitable for use with packet-switched networks (e.g., public networks such as the Internet, private networks such as an enterprise intranet, and so forth), circuit-switched networks (e.g., the public switched telephone network), or a combination of packet-switched networks and circuit-switched networks (with suitable gateways and translators).
  • the communications component 140 may include various types of standard communication elements, such as one or more communications interfaces, network interfaces, network interface cards (NIC), radios, wireless transmitters/receivers (transceivers), wired and/or wireless communication media, physical connectors, and so forth.
  • the communications components 140 may comprise, or be implemented as, software, a software module, an application, a program, a subroutine, instructions, an instruction set, computing code, words, values, symbols or combination thereof.
  • the instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like.
  • the instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a processor to perform a certain function.
  • the instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language, such as C, C++, Java, BASIC, Perl, Matlab, Pascal, Visual BASIC, assembly language, machine code, and so forth. The embodiments are not limited in this context.
  • the software may be executed by any suitable processor and memory unit.
  • the communications component 140 may include a receiver 142.
  • a receiver 142 may be arranged to receive voice information and/or data
  • the receiver 142 may receive voice information and/or data information over one or more assigned frequency bands of a wireless communication channel.
  • a receiver 142 may receive signals from another device via the communications media 150.
  • Signals may be transmitted over communications media 150, such as, but not limited to, Wimax, LTE, CDMA, WiFi, and 3G and 4G technologies.
  • Signals may be encoded or decoded in order to protect the signal from noise resulting from adjacent channel signals.
  • Convolution codes may be used to protect data bits in the signals from noise.
  • a convolution code may encode data bits using forward error correction. By encoding the signals using a convolution code, a signal-to-noise ratio (SNR) may be decreased.
  • SNR signal-to-noise ratio
  • a receiver 142 may include a processor 144.
  • a processor 144 may be a baseband processor.
  • a receiver 142 may be implemented as a communications component 140 using any suitable processor 144 or logic device, such as a modem processor or baseband processor, for example.
  • a processor 144 may include or implement a decoder 146.
  • a decoder 146 may receive encoded data from a transmitting device, such as the device 120.
  • the device 120 may encode the data to protect information from interference during transmission.
  • the decoder 146 may decode the encoded data or information received by the receiver 142.
  • the decoder 146 may include a reconfigurable Add-Compare-
  • ACS Alternate Control
  • a reconfigurable ACS decoder may support a Viterbi algorithm decoder, a Bahl-Cocke- Jelinek-Raviv (BCJR) decoder and/or a low-density parity-check (LDPC) decoder.
  • BCJR Bahl-Cocke- Jelinek-Raviv
  • LDPC low-density parity-check
  • the decoder 146 may be used to decode convolutional code 148.
  • decode convolutional code 148 In an
  • the receiver 142 may use a decoder 146 to decode convolutional code 148.
  • Convolutional code 148 may be implemented as forward error correcting code
  • the decoder may decrease the SNR.
  • the convolutional code 148 may be decoded using a trellis diagram.
  • An example of a trellis diagram is provided in FIG. 4.
  • the decoder 146 may decode convolutional code 148 by determining a plurality of sets for a trellis.
  • a trellis may be divided into multiple overlapping sets.
  • each set may include a plurality of stages of the trellis. Each set may have a different beginning stage and ending stage as each set may capture a different part of the trellis.
  • a path metric may be determined when a state is tail biting.
  • Path metrics may be a summary of the branches or path used in the trellis from a first stage to a second stage. The path metrics may be compared to determine a state with a minimum path metric. Bits from the state of the minimum path metric may be output.
  • a processor 144 may include, or have access to, memory 145.
  • Memory 145 may comprise any machine -readable media. Memory 145 may be implemented using any machine-readable or computer-readable media capable of storing data, including both volatile and non- volatile memory.
  • memory 145 may include read-only memory (ROM), random-access memory (RAM), dynamic RAM (DRAM), Double-Data-Rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, polymer memory such as ferroelectric polymer memory, ovonic memory, phase change or ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic or optical cards, or any other type of media suitable for storing information.
  • ROM read-only memory
  • RAM random-access memory
  • DRAM dynamic RAM
  • DDRAM Double-Data-Rate DRAM
  • SDRAM synchronous DRAM
  • SRAM static RAM
  • PROM programmable ROM
  • EPROM erasable programmable ROM
  • EEPROM electrically erasable programmable ROM
  • flash memory polymer memory such as ferroelectric poly
  • memory 145 may be included on the same integrated circuit or die as processor 144, such as in a system-on-a-chip (SoC) implementation. Additionally or alternatively, some portion or all of memory 145 may be disposed on another integrated circuit or other medium, for example a hard disk drive that is external to the integrated circuit of processor 144. The embodiments are not limited in this context.
  • a memory 145 may be used to store parts of the convolutional code 148.
  • the convolutional code 148 may be decoded using a trellis 149 diagram.
  • the memory 145 may store the beginning and ending stages of a trellis 149 of the
  • the memory 145 may store path metrics for different states of the trellis 149.
  • FIG. 2 illustrates one embodiment of a logic flow 200 for decoding a tail biting convolutional code.
  • the logic flow 200 may be representative of some or all of the operations executed by one or more embodiments described herein.
  • the logic flow 200 may begin with a message received via a receiver.
  • the message may be decoded via a decoder.
  • the logic flow 200 may determine a plurality of sets for a trellis of a convolutional code at block 202.
  • a trellis is a diagram which may be used to decode a convolutional code.
  • a plurality of sets for a trellis of a convolutional code in the message may be determined.
  • Each trellis may include a number of stages.
  • a set may be a grouping of stages in a trellis.
  • a first set may begin at stage 0 and end at a second stage of the trellis.
  • Each set may begin at a first stage and end at a second stage.
  • Each set may have a different beginning stage and ending stage.
  • N may be a length of the trellis in a set, where N represents any positive integer.
  • the length of each set may be N.
  • N may be the length a transmitted message received by the decoder 146.
  • the number of stages N may be 64.
  • the number of stages N may be 50 or less.
  • the number of stages N may be 24.
  • the number of stages N may range from 5 to 100.
  • any length of convolutional code may be used.
  • decoding the tail biting convolutional code may have a maximum likelihood performance when the length of the message is short. In an embodiment, the convolutional code may have a maximum likelihood performance when the number of stages Nof the decoded trellis is 50 or less. The embodiments are not limited to the examples described.
  • each set may overlap with at least one other set. As the sets overlap, each set may begin after a number of stages have passed. In an embodiment, each set may start the same number of stages after a previous set begins. Overlapping sets, as opposed to contiguous sets, may reduce the total number of scanned stages. Overlapping sets may increase the efficiency and the maximum likelihood performance of the decoding.
  • FIG. 3 illustrates an embodiment of a three overlapping sets for an exemplary trellis 300 of a tail biting convolutional code.
  • embodiments may calculate path metrics for the trellis using multiple overlapping sets.
  • a trellis 300 may be divided into three sets.
  • a trellis may be length N plus EB, where N is the number of stages in a set and EB are the extra bits.
  • the length of each set may be N.
  • N may be the length a transmitted message received by the decoder 146.
  • the trellis may have N+EB+ 1 stages .
  • a first set 310 of the trellis 300 may be determined.
  • a first set may be a zero set as the set may begin at stage 0.
  • a first set may begin or have a first stage at stage 0 and end or have a second stage at stage N, where N is the length of the trellis in a set.
  • the trellis may continue cyclically until EB/2, where EB are the extra bits.
  • EB/2 may be the number of stages that pass since the trellis began.
  • the extra bits EB for a decoding procedure may be 48.
  • the extra bits EB for a decoding procedure may be 24. The embodiments are not limited to these examples.
  • the decoder may determine a second set 320 of the trellis 300.
  • a second set 320 may begin at a first stage and end at a second stage.
  • the second stage of the second set may be N stages from the first stage of the second set.
  • the first stage of the second set may be located between the first stage of the first set and the second stage of the first set.
  • the first stage of the second set may begin EB/2 stages after the first stage of the first set.
  • the second set 320 may have a first stage at stage EB/2 and have a second stage at stage EB/2 + N.
  • the first stage of the second set may be located between 0 and N so that the first and second sets overlap.
  • the decoder may determine a third set 330 of the trellis.
  • the third set may begin at a first stage.
  • the first stage of the third set may be stage EB.
  • the third set may end at a second stage.
  • the second stage of the third set may be stage EB+N.
  • the first stage of the third set may be located between EB/2 and EB/2+N so that the second and third sets overlap.
  • each set may have the same number of stages or length N.
  • Each set may include N+l trellis stages.
  • the stages of a trellis may be composed by circular processing.
  • the sets may be determined in parallel as the sets overlap.
  • the logic flow 200 may determine path metrics for each state in a set where a first stage and a second stage have a same state at block 204.
  • Path metrics may be a summary of the branches or path used in the trellis 300 from a beginning or first stage to a last or second stage of a set.
  • a decoder may determine path metrics for each state in a set when a state of a first stage equals a state of a second stage.
  • the decoder 146 may determine the path metrics sequentially.
  • the convolutional code 148 may determine the state at the beginning or first stage.
  • the state for the last or second stage may be compared with the state at the beginning or first stage.
  • the decoder 146 may compare the state of the first stage with the stage of the second stage to determine if the states are the same. If the states are the same, then the state is tail biting and the decoder 146 may determine the path metrics for the state.
  • the decoder 146 may use an algorithm to determine whether a state of the code is tail biting.
  • the algorithm may include a
  • RootState J [s] vector for each set where s may be the state.
  • the state s may be one of 64 possible states of the convolutional code.
  • there may be three sets with RootState J [s] , ⁇ z ' 0, 1, 2 ⁇ vectors.
  • Each vector may hold the state of the corresponding root or first state for the set.
  • a root state may be the state that can be reached by tracing back from a second or last state of the set to the beginning of the set.
  • the RootState _i vectors may be updated for each state s at the following stages:
  • RootState _0[s] may be updated at stages 0 to N-l .
  • RootState 1 [s] may be updated at states EB/2 to N+EB/2-1.
  • RootState _2[s] may be updated at stages EB to N+EB-l .
  • two more memory arrays may store the state metrics vector at stages EB/2 and EB in order to calculate the path metrics for the tail biting states in the second and third sets.
  • FIG. 4 illustrates an embodiment of a trellis with the beginning and ending states.
  • FIG. 4 depicts a trellis 400 divided into three sets 410, 420 and 430. As shown in FIG. 4, Nmay equal eight. Each set 410, 420 and 430 may include eight stages. The first set 410 has stage 0 through stage 7. FIG. 4 depicts four states. In FIG. 4, extra bits EB equals four, so the second set may 420 begin at stage 2 and the third set 430 may begin at stage 4.
  • path metrics may be determined for each state in a given set. It may be determined which states are tail biting, e.g., which states begin and end at the same state.
  • the root state vectors for each of the sets may determine a first or root state corresponding to the last or second state.
  • the decoder 146 may update the root state vectors or N-path metrics for each state s. At the end of a set, each vector may determine which states are tail biting states. A vector may identify a tail biting state when the first or root state is the same as the second or last state of a set.
  • the N -path metrics, or relative metrics may be recorded for a path where the state of the first stage and the state of the last state in the set are equal.
  • the N -path metric of a given state may be the difference between the state's metric in the last stage and the state's metric in the first stage, e.g., N stages before.
  • M(s,ri) may represent an accumulated metric for stage n and state s.
  • a first set 410 may be the zero set.
  • the N-path metrics may be Metric(s,N-l) - Metric0,0).
  • M (0,0) may have a first or root state of 0 and a second or last state of 0.
  • M(l,0) may have a first state of state 1 , but not have a second state of state 1.
  • M (2,0) may have a first state of state 2, but not have a second state of state 2.
  • M (3,0) may have a first state of state 3, but not have a second state of state 3.
  • M (0,0) may have a first or root state of 0 and a second or last state of 0.
  • M(l,0) may have a first state of state 1 , but not have a second state of state 1.
  • M (2,0) may have a first state of state 2, but not have a second state of state 2.
  • only state 0 may have a second state that is the same as the first state.
  • only state 0 may have a first or root state and a second or last state of 0.
  • only set_0[s] may equal 0.
  • State 0 may be the only tail biting convolutional code in the first set.
  • the only path metric for the first set 410 may be path metric 412 M (0,7)- M (0,0).
  • the decoder 146 may cycle the trellis 400 for another EB/2 steps and may record the N-path metrics at Metric s, N+EB/2 -1) - Metric S, EB/2) of the second set 420.
  • M (0,2) may have a first or root state of state 0, but not have a second or last state of state 0.
  • M ( ⁇ ,2) may have a first state of state 1, but not have a second state of state 1.
  • M (2,2) may have a first state of state 2, but not have a second state of state 2.
  • M (3,2) may have a first state of state 3, but not have a second state of state 3.
  • the decoder 146 may compare the first state to the second state 420 for all states in the second set 420 of the trellis. Looking at the second set 420 in FIG. 4, no states may have a first state and a second state in the same state. The second set may have no states that begin and end in the same state. As the second set 420 has no tail biting states, no path metrics may be determined.
  • the trellis 400 may cycle for another EB steps and may record the N-path metrics at Metric S, EB) - Metric (S, N+EB -1) of the third set 430.
  • M(0,4) may have a first or root state of state 0 and a second or last state of state 0.
  • M(l ,4) may have a first state of state 1 , but not have a second state of state 1.
  • M(2,4) may have a first state of state 2 and a second state of state 2.
  • M(2>,4) may have a first state of state 3 and a second state of state 3.
  • the decoder 146 may compare the first state to the second state for all states in the third set 430 of the trellis 400.
  • states 0, 2 and 3 all may have a second or last state that equals the first or root state. In other words, states 0, 2 and 3 all may have states that begin and end at the same state. Accordingly, path metric 432 (0,1 1)- (0,4) may be determined for state 0. Path metric 434 (2, l 1)- (2,4) may be determined for state 2. Path metric 436 (3, l 1)- (3,4) may be determined for state 3.
  • the logic flow 200 may compare the path metrics to determine a state with a minimum path metric at block 206.
  • the best path metric of a tail biting state among the three sets 410, 420 and 430 may constitute a winner.
  • the best path metric may be the minimum path metric.
  • a minimum path metric may be an optimal path from a beginning or first stage to a last or second stage.
  • the minimum path metric may be optimal among all the tail biting path metrics among all the sets 410, 420 and 430.
  • the decoder 146 may compare convolutional code sets, 310, 320 and 330 to determine a tail biting winner 340.
  • a decoder may compare path metrics for each tail biting state in the first set 310, second set 320 and third set 330 to determine a state with a minimum path metric 340.
  • the decoder 146 may compare 440 the path metrics: (0,7)- (0.0), (0, 1 1)- (0,4), M(2, ⁇ 1)- (2,4), and (3,l 1)- (3,4).
  • the metrics may be compared 440. In other words, each metric may subtract the first or root state from the second or last state.
  • Each metric may include the same number of stages N.
  • the decoder 146 may compare the metrics of various sets 410, 420 and 430 to determine a winning path 450. In an embodiment, the winning path 450 may be the minimum path metric. Referring again to FIG.
  • the logic flow 200 may output bits from the state of the minimum path metric at block 208.
  • the embodiments are not limited to this example.
  • the bits may be output by tracing back from the state of the winning path.
  • the output bits may be traced back using the RootState_i[s] algorithm described above.
  • FIG. 5 illustrates an embodiment of an exemplary computing architecture 500 suitable for implementing various embodiments as previously described.
  • system and “component” are intended to refer to a computer- related entity, either hardware, a combination of hardware and software, software, or software in execution, examples of which are provided by the exemplary computing architecture 500.
  • a component can be, but is not limited to being, a process running on a processor, a processor, a hard disk drive, multiple storage drives (of optical and/or magnetic storage medium), an object, an executable, a thread of execution, a program, and/or a computer.
  • an application running on a server and the server can be a component.
  • One or more components can reside within a process and/or thread of execution, and a component can be localized on one computer and/or distributed between two or more computers. Further, components may be communicatively coupled to each other by various types of communications media to coordinate operations. The coordination may involve the uni-directional or bi-directional exchange of information. For instance, the components may communicate information in the form of signals communicated over the communications media. The information can be implemented as signals allocated to various signal lines. In such allocations, each message is a signal. Further embodiments, however, may alternatively employ data messages. Such data messages may be sent across various connections. Exemplary connections include parallel interfaces, serial interfaces, and bus interfaces.
  • the computing architecture 500 may comprise or be implemented as part of an electronic device.
  • an electronic device may include without limitation a mobile device, a personal digital assistant, a mobile computing device, a smart phone, a cellular telephone, a handset, a one-way pager, a two- way pager, a messaging device, a computer, a personal computer (PC), a desktop computer, a laptop computer, a notebook computer, a handheld computer, a tablet computer, a server, a server array or server farm, a web server, a network server, an Internet server, a work station, a mini-computer, a main frame computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, multiprocessor systems, processor-based systems, consumer electronics, programmable consumer electronics, television, digital television, set top box, wireless access point, base station, subscriber station, mobile subscriber center, radio network controller, router, hub, gateway, bridge, switch, machine, or combination thereof.
  • the embodiments are not limited in this context
  • the computing architecture 500 includes various common computing elements, such as one or more processors, co-processors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input/output (I/O) components, and so forth.
  • processors co-processors
  • memory units chipsets
  • controllers peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input/output (I/O) components, and so forth.
  • oscillators oscillators, timing devices, video cards, audio cards, multimedia input/output (I/O) components, and so forth.
  • the embodiments are not limited to implementation by the computing architecture 500.
  • the computing architecture 500 comprises a processing unit 504, a system memory 506 and a system bus 508.
  • the processing unit 504 can be any of various commercially available processors. Dual microprocessors and other
  • the system bus 508 provides an interface for system components including, but not limited to, the system memory 506 to the processing unit 504.
  • the system bus 508 can be any of several types of bus structure that may further interconnect to a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures.
  • the computing architecture 500 may comprise or implement various articles of manufacture.
  • An article of manufacture may comprise a computer-readable storage medium to store logic.
  • Examples of a computer-readable storage medium may include any tangible media capable of storing electronic data, including volatile memory or non- volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth.
  • Examples of logic may include executable computer program instructions implemented using any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like.
  • the system memory 506 may include various types of computer-readable storage media in the form of one or more higher speed memory units, such as read-only memory (ROM), random-access memory (RAM), dynamic RAM (DRAM), Double-Data-Rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable
  • ROM read-only memory
  • RAM random-access memory
  • DRAM dynamic RAM
  • DDRAM Double-Data-Rate DRAM
  • SDRAM synchronous DRAM
  • SRAM static RAM
  • PROM programmable ROM
  • EPROM erasable programmable ROM
  • system memory 506 can include non-volatile memory 510 and/or volatile memory 512.
  • a basic input/output system (BIOS) can be stored in the non-volatile memory 510.
  • the computer 502 may include various types of computer-readable storage media in the form of one or more lower speed memory units, including an internal hard disk drive (HDD) 514, a magnetic floppy disk drive (FDD) 516 to read from or write to a removable magnetic disk 518, and an optical disk drive 520 to read from or write to a removable optical disk 522 (e.g., a CD-ROM or DVD).
  • the HDD 514, FDD 516 and optical disk drive 520 can be connected to the system bus 508 by a HDD interface 524, an FDD interface 526 and an optical drive interface 528, respectively.
  • the HDD interface 524 for external drive implementations can include at least one or both of Universal Serial Bus (USB) and IEEE 1394 interface technologies.
  • the drives and associated computer-readable media provide volatile and/or nonvolatile storage of data, data structures, computer-executable instructions, and so forth.
  • a number of program modules can be stored in the drives and memory units 510, 512, including an operating system 530, one or more application programs 532, other program modules 534, and program data 536.
  • the one or more application programs 532, other program modules 534, and program data 536 can include, for example, the decoder 146.
  • a user can enter commands and information into the computer 502 through one or more wire/wireless input devices, for example, a keyboard 538 and a pointing device, such as a mouse 540.
  • Other input devices may include a microphone, an infra-red (IR) remote control, a joystick, a game pad, a stylus pen, touch screen, or the like.
  • IR infra-red
  • These and other input devices are often connected to the processing unit 504 through an input device interface 542 that is coupled to the system bus 508, but can be connected by other interfaces such as a parallel port, IEEE 1394 serial port, a game port, a USB port, an IR interface, and so forth.
  • a monitor 544 or other type of display device is also connected to the system bus 508 via an interface, such as a video adaptor 546.
  • a computer typically includes other peripheral output devices, such as speakers, printers, and so forth.
  • the computer 502 may operate in a networked environment using logical connections via wire and/or wireless communications to one or more remote computers, such as a remote computer 548.
  • the remote computer 548 can be a workstation, a server computer, a router, a personal computer, portable computer, microprocessor-based entertainment appliance, a peer device or other common network device, and typically includes many or all of the elements described relative to the computer 502, although, for purposes of brevity, only a memory/storage device 550 is illustrated.
  • the logical connections depicted include wire/wireless connectivity to a local area network (LAN) 552 and/or larger networks, for example, a wide area network (WAN) 554.
  • LAN and WAN networking environments are commonplace in offices and companies, and facilitate enterprise-wide computer networks, such as intranets, all of which may connect to a global communications network, for example, the Internet.
  • the computer 502 When used in a LAN networking environment, the computer 502 is connected to the LAN 552 through a wire and/or wireless communication network interface or adaptor 556.
  • the adaptor 556 can facilitate wire and/or wireless communications to the LAN 552, which may also include a wireless access point disposed thereon for communicating with the wireless functionality of the adaptor 556.
  • the computer 502 can include a modem 558, or is connected to a communications server on the WAN 554, or has other means for establishing communications over the WAN 554, such as by way of the Internet.
  • the modem 558 which can be internal or external and a wire and/or wireless device, connects to the system bus 508 via the input device interface 542.
  • program modules depicted relative to the computer 502, or portions thereof can be stored in the remote memory/storage device 550. It will be appreciated that the network connections shown are exemplary and other means of establishing a
  • the computer 502 is operable to communicate with wire and wireless devices or entities using the IEEE 802 family of standards, such as wireless devices operatively disposed in wireless communication (e.g., IEEE 802.11 over-the-air modulation techniques) with, for example, a printer, scanner, desktop and/or portable computer, personal digital assistant (PDA), communications satellite, any piece of equipment or location associated with a wirelessly detectable tag (e.g., a kiosk, news stand, restroom), and telephone.
  • wireless communication e.g., IEEE 802.11 over-the-air modulation techniques
  • PDA personal digital assistant
  • Wi-Fi networks use radio technologies called IEEE 802.1 lx (a, b, g, n, etc.) to provide secure, reliable, fast wireless connectivity.
  • IEEE 802.1 lx a, b, g, n, etc.
  • a Wi-Fi network can be used to connect computers to each other, to the Internet, and to wire networks (which use IEEE 802.3 -related media and functions).
  • connection along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, some embodiments may be described using the terms “connected” and/or “coupled” to indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co- operate or interact with each other.

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Abstract

La présente invention concerne des techniques pour décoder un code de convolution qui se mord la queue. On peut déterminer une pluralité d'ensembles pour un treillis. Chaque ensemble peut comporter un premier étage et un second étage du treillis. On peut déterminer des métriques de chemin pour chaque état dans un ensemble lorsque le premier étage et le second étage ont un même état. On peut comparer les métriques de chemin afin de déterminer un état avec une métrique de chemin minimale. On peut délivrer en sortie des bits de l'état avec la métrique de chemin minimale. D'autres modes de réalisation sont décrits et revendiqués.
PCT/US2012/029588 2011-03-29 2012-03-18 Système, procédé et appareil pour décoder un code de convolution qui se mord la queue WO2012134846A2 (fr)

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CN201280015779.3A CN103444086B (zh) 2011-03-29 2012-03-18 用于咬尾卷积码解码的系统、方法和设备

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WO2012163135A1 (fr) * 2011-05-27 2012-12-06 上海无线通信研究中心 Procédé de décodage de canal et décodeur
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WO2012134846A3 (fr) 2012-11-22
CN103444086A (zh) 2013-12-11

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