WO2012132206A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
WO2012132206A1
WO2012132206A1 PCT/JP2012/001160 JP2012001160W WO2012132206A1 WO 2012132206 A1 WO2012132206 A1 WO 2012132206A1 JP 2012001160 W JP2012001160 W JP 2012001160W WO 2012132206 A1 WO2012132206 A1 WO 2012132206A1
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WIPO (PCT)
Prior art keywords
groove
insulating layer
semiconductor device
wiring
barrier metal
Prior art date
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PCT/JP2012/001160
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French (fr)
Japanese (ja)
Inventor
典明 小田
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ルネサスエレクトロニクス株式会社
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Publication of WO2012132206A1 publication Critical patent/WO2012132206A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • Patent Document 1 (US Pat. No. 6,800,180) describes that the following steps are provided as a manufacturing method for depositing a material such as a barrier metal layer on the bottom of a connection hole. First, a first material such as a barrier metal layer is sputtered on a semiconductor substrate. Next, a first bias voltage is applied to the substrate, and at the same time, the material around the contact hole is removed to form a facet on the upper portion of the recess. Next, a second bias voltage is applied to the substrate, and at the same time, a first material is sputter-deposited on the bottom of the recess. Thus, the coverage of the first material in the connection hole is a better.
  • Patent Document 2 Japanese Patent Laid-Open No. 2007-227709 describes a method for manufacturing a semiconductor integrated circuit device as described below. First, connection holes and wiring grooves are formed, and a barrier metal layer is formed on the side walls and bottom surface of the connection holes and wiring grooves. Next, the barrier metal layer at the bottom of the connection hole is removed, and a part of the embedded wiring below the connection hole is dug. Next, a tantalum film is deposited on the interlayer insulating film including the wiring trench and the connection hole by a sputtering method under the condition that the directivity is improved in the depth direction. In this way, the thickness of the barrier metal layer at the bottom of the wiring trench is increased, and the bottom of the connection hole is again covered with the barrier metal layer. Thereby, it is said that the reliability of the connection characteristic in the connection part of the copper wiring between the lower layer embedded wiring and the upper layer embedded wiring can be improved.
  • Patent Document 3 Japanese Patent Laid-Open No. 2004-342702 describes the following semiconductor device.
  • the underlayer is provided on the substrate.
  • the first insulating layer is provided so as to cover the underlying layer.
  • the taper portion is provided along the bottom end portion of the first recess extending from the surface of the first insulating layer to the base layer.
  • the taper portion has a taper surface toward the center of the bottom portion.
  • the barrier metal layer is provided so as to cover the side surface and the bottom portion of the first recess that is not covered by the tapered surface and the tapered portion.
  • the first conductor portion is provided so as to fill the first recess with a metal containing copper. Thereby, it is said that Cu migration in the wiring including the contact can be prevented.
  • Patent Document 4 Japanese Patent Laid-Open No. 2001-176968 describes the following semiconductor integrated circuit device.
  • the insulating film of the semiconductor integrated circuit device, the connection hole and the wiring grooves are formed.
  • a barrier conductive film (barrier metal layer) and a seed film are formed inside the connection hole and the wiring groove.
  • the connection hole is formed such that the bottom portion has a narrower forward taper than the upper portion.
  • the wiring groove is formed so that the side wall is perpendicular to the bottom of the wiring groove. Further, the side walls of the upper layer and the lower layer are formed so as to be continuous without being stepped. Thereby, it is said that the barrier property of the barrier conductive film (barrier metal layer) can be secured and the embedding property of the conductive film can be improved.
  • a semiconductor substrate A first insulating layer formed on the semiconductor substrate; A first groove formed in the first insulating layer and having a bottom surface and a side surface; A first barrier metal layer provided so as to be in contact with the bottom surface and the side surface of the first groove portion; A first wiring provided inside the first groove,
  • the first groove portion includes a first inclined portion that is inclined in a depth direction of the first groove portion at a portion of the bottom surface that is in contact with the side surface of the first groove portion.
  • a method for manufacturing a semiconductor device is provided.
  • the first groove portion has a first inclined portion that is inclined in the depth direction of the first groove portion at a portion of the bottom surface that contacts the side surface of the first groove portion.
  • the first barrier metal layer is formed on the bottom surface and the side surface of the first groove portion, particles that recoil at the first inclined portion and adhere to the side surface of the first groove portion increase.
  • the first barrier metal layer is formed with good coverage on the side surface of the first groove.
  • the electromigration of the wiring material in the fine multilayer wiring can be suppressed.
  • FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to a first embodiment. It is a figure for demonstrating the relationship between the taper angle of the inclination part in 1st Embodiment, and an electromigration lifetime. It is a sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment. It is a sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment. It is a sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment. It is sectional drawing for demonstrating the effect of 1st Embodiment. It is a figure which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a sectional view for explaining a method for manufacturing a semiconductor device according to a second embodiment.
  • FIG. 1 is a diagram illustrating a configuration of the semiconductor device according to the first embodiment.
  • FIG. 1A is a top view showing the configuration of the semiconductor device 10.
  • FIG. 1B is a cross-sectional view taken along the line AA ′ showing the configuration of the semiconductor device 10.
  • FIG. 1C is a cross-sectional view taken along line BB ′ showing the configuration of the semiconductor device 10.
  • the semiconductor device 10 has the following configuration.
  • first insulating layer a semiconductor substrate (silicon substrate 100), a first insulating layer (first via forming insulating layer 220 and first wiring forming insulating layer 230) formed on the semiconductor substrate (silicon substrate 100), and A first groove portion 240 formed on the first wiring formation insulating layer 230 and having a bottom surface and a side surface; a first barrier metal layer 242 provided in contact with the bottom surface and the side surface of the first groove portion 240; and the first groove portion 240. And a first wiring 250 provided therein.
  • the first groove portion 240 has a first inclined portion 246 that is inclined in the depth direction of the first groove portion 240 at a portion of the bottom surface that is in contact with the side surface of the first groove portion 240. Details will be described below.
  • the semiconductor substrate is, for example, the silicon substrate 100.
  • a first barrier metal layer 242 is provided inside the first wiring formation insulating layer 230 in the first insulating layer so as to be in contact with the side surface in a plan view.
  • a first wiring 250 is provided inside the first barrier metal layer 242.
  • a first insulating layer (a first via forming insulating layer 220 and a first wiring forming insulating layer 230) is provided on the silicon substrate 100.
  • a semiconductor element such as an FET (Field Effect Transistor) is formed on the silicon substrate 100.
  • the first insulating layer has, for example, a first via forming insulating layer 220 and a first wiring forming insulating layer 230, which are formed on the silicon substrate 100 in this order.
  • a contact (not shown) is provided on the first via formation insulating layer 220 in a region not shown.
  • a first wiring 250 to be described later is connected to the semiconductor element through this contact, for example.
  • the first via forming insulating layer 220 and the first wiring forming insulating layer 230 may be formed of the same material. At this time, an interface may not be formed between the first via formation insulating layer 220 and the first wiring formation insulating layer 230.
  • the first via forming insulating layer 220 and the first wiring forming insulating layer 230 may be formed from different materials. Further, each of the first via forming insulating layer 220 and the first wiring forming insulating layer 230 may be formed of a plurality of layers.
  • the relative dielectric constant of the first insulating layer (the first via forming insulating layer 220 and the first wiring forming insulating layer 230) is, for example, 2.6 or less. As a result, the inter-wiring capacitance can be reduced, so that the impedance of the entire semiconductor device 10 can be reduced.
  • the relative dielectric constant of at least the first via forming insulating layer 220 of the first insulating layer is 2.6 or less.
  • the first insulating layer (the first via forming insulating layer 220 and the first wiring forming insulating layer 230) is, for example, a porous film. With such a porous film, it is possible to lower the dielectric constant.
  • Examples of the first insulating layer include a porous SiO film and a porous SiOC film.
  • the layer thicknesses of the first via forming insulating layer 220 and the first wiring forming insulating layer 230 are 50 nm or more and 200 nm or less, respectively.
  • a first groove 240 is formed in the first wiring formation insulating layer 230 in the first insulating layer.
  • the first groove portion 240 is an opening provided in the first wiring formation insulating layer 230 in the first insulating layer and for forming the first wiring 250 by embedding a conductor therein.
  • the first groove portion 240 is provided with a first barrier metal layer 242 so as to be in contact with the bottom surface and the side surface thereof.
  • the first barrier metal layer 242 has good adhesion to the first insulating layer (the first via forming insulating layer 220 and the first wiring forming insulating layer 230).
  • the first barrier metal layer 242 has a function of protecting the material of the first wiring 250 from migration.
  • the first barrier metal layer 242 includes, for example, Ta, Ti, or Ru. Specifically, the first barrier metal layer 242 is, for example, Ta, Ti, or Ru. Furthermore, a nitride such as TaN, TiN, or RuN may be used.
  • the first barrier metal layer 242 may be formed of a plurality of layers. Specifically, the first barrier metal layer 242 has a two-layer structure of TaN / Ta from the side in contact with the first wiring formation insulating layer 230, for example.
  • the thickness of the first barrier metal layer 242 on the bottom surface of the first groove portion 240 described later is, for example, 5 nm or more and 30 nm or less. By being within the above range, it is possible to have a function of enhancing the above-described adhesion and a function of suppressing migration. In addition, when the 1st barrier metal layer 242 consists of multiple layers, it is preferable that each layer is the range of the said thickness.
  • a first wiring 250 is provided inside the first groove portion 240. At this time, the first wiring 250 is surrounded by the first barrier metal layer 242 on the bottom and side surfaces. Thereby, the electromigration of the material of the 1st wiring 250 can be suppressed.
  • the first wiring 250 includes, for example, Cu as a main material.
  • Cu is a material that easily causes electromigration.
  • electromigration can be suppressed by having the 1st inclination part 246 mentioned later.
  • the thickness of the first wiring 250 is, for example, 100nm or 800nm or less.
  • the 1st groove part 240 has the 1st inclination part 246 which inclines in the depth direction of the 1st groove part 240 in the part which contact
  • the “side surface of the first groove portion 240” means not only the side surface in the direction in which the first wiring 250 extends (the AA ′ line direction in FIG. 1A) but also the width direction of the first wiring 250. It includes a side surface (in the BB ′ line direction in FIG. 1A).
  • the direction in which the first wiring 250 extends means the longitudinal direction of the first wiring 250.
  • the bottom surface in contact with the side surface of the first groove portion 240 may not only be inclined in the direction along the side surface but also may be partially inclined.
  • the first inclined portion 246 is formed in the first groove portion 240.
  • the first barrier metal layer 242 is formed on the bottom surface and the side surface of the first groove portion 240, particles that recoil at the first inclined portion 246 and adhere to the side surface of the first groove portion 240 are formed. Become more. Therefore, the first barrier metal layer 242 with good coverage is formed on the side surface of the first groove portion 240. Details of the effect according to the first embodiment will be described later.
  • the first inclined portion 246 is formed in the vicinity of the first groove portion 240.
  • the “vicinity from the side surface of the first groove portion 240” in which the first inclined portion 246 is formed means that particles that have rebounded from the first inclined portion 246 in the first barrier metal layer forming step described later. It means a range close to the extent of reaching the side surface of one groove portion 240. Therefore, a portion parallel to the surface of the silicon substrate 100 may be formed on the bottom surface of the first groove portion 240.
  • the length of the first inclined portion 246 from the side surface of the first groove portion 240 is not less than 1 ⁇ 2 times the thickness of the first wiring 250. More preferably not more than 3 times half the thickness of the first wiring 250.
  • the side surface of the first groove portion 240 is perpendicular to the bottom surface of the first groove portion 240 in the region where the first inclined portion 246 is not formed.
  • the side surfaces of the first groove 240 are also perpendicular to the bottom surfaces of the silicon substrate 100 and the first insulating layer (the first via forming insulating layer 220 and the first wiring forming insulating layer 230).
  • the angle ⁇ formed by the first inclined portion 246 and the side surface is an acute angle.
  • the first barrier metal layer 242 is formed.
  • Layer 242 may be etched with plasma.
  • the first barrier metal layer 242 on the side surface of the first groove portion 240 is formed thicker than the thickness of the first barrier metal layer 242 on the bottom surface of the first groove portion 240.
  • the side surface of the first groove portion 240 is largely uneven due to the holes in the first wiring formation insulating layer 230. For this reason, the coverage of the first barrier metal layer 242 is deteriorated on the side surface of the first groove portion 240. Therefore, electromigration due to the material of the first wiring 250 is likely to occur particularly from the side surface of the first groove 240.
  • the first barrier metal layer 242 on the side surface of the first groove portion 240 is formed thick as described above, electromigration from the side surface of the first groove portion 240 can be reliably suppressed.
  • the first inclined portion 246 is also formed in the vicinity of the side surface of the first wiring 250 in the width direction (the BB ′ line direction in FIG. 1A). . That is, the first inclined portion 246 is formed on the side surfaces on both sides of the first groove portion 240. As a result, even if the wiring below the first wiring 250 extends in the width direction of the first wiring 250 (direction perpendicular to the first wiring 250), electromigration can be suppressed.
  • FIG. 2A is a diagram showing the relationship between the taper angle of the inclined portion and the electromigration lifetime in the first embodiment.
  • the taper angle of the first inclined portion 246 ( ⁇ in FIG. 2B) refers to an angle formed by the bottom surface of the first inclined portion 246 and the side surface of the first groove portion 240.
  • the horizontal axis represents the value obtained by subtracting the taper angle ⁇ from 90 degrees.
  • the angle formed by the first inclined portion 246 and the side surface of the first groove portion 240 is not less than 40 degrees and not more than 65 degrees. This will be described in detail.
  • FIG. 2 (a) a sample having a configuration as shown in FIG. 2 (b) was used.
  • the sample shown in FIG. 2B has the same configuration as that shown in FIG.
  • an etching stopper layer 310, a second via formation insulating layer 320, and a second wiring formation insulation layer 330 were further stacked in this order.
  • the second via forming insulating layer 320 and the second wiring forming insulating layer 330 correspond to the second insulating layer in the second embodiment to be described later.
  • the second via forming insulating layer 320 and the second wiring forming insulating layer 330 are provided with a connection hole (not shown) and a second groove (not shown).
  • a second barrier metal layer is provided on the bottom surface and side surfaces of the connection hole and the second groove. Furthermore, a second wiring 350 is provided inside the connection hole and the second groove portion. Note that the first wiring 250 pitch between the second wiring 350 was set to 140 nm.
  • the first via forming insulating layer 220 and the second via forming insulating layer 320 are porous SiOC films.
  • the first wiring formation insulating layer 230 and the second wiring formation insulation layer 330 are porous SiO films.
  • the first wiring 250 and the second wiring 350 are made of Cu.
  • Electromigration lifetime (EM Lifetime) was evaluated by applying a current density of 1 MA / cm 2 at a temperature of 300 ° C.
  • the electromigration lifetime in FIG. 2A indicates the time until the electrical resistance of 50% of the sample increases by 5% by the accelerated test described above.
  • the electromigration lifetime is increased by decreasing the taper angle ⁇ (increasing 90 ° ⁇ ).
  • the taper angle ⁇ is greater than 40 degrees and equal to or less than 65 degrees.
  • the first barrier metal layer 242 having particularly good coverage is formed on the side surface of the first groove portion 240, and the electromigration of the wiring material can be more reliably suppressed. Conceivable.
  • the angle (taper angle ⁇ ) formed by the first inclined portion 246 and the side surface of the first groove portion 240 in the first embodiment is preferably 40 degrees or more and 65 degrees or less.
  • the taper angle ⁇ is smaller than 40 degrees, the Cu burying property in the first groove 240 is deteriorated.
  • the taper angle ⁇ is in the above range, the first barrier metal layer 242 having particularly good coverage is formed on the side surface of the first groove portion 240. Thus, it is possible to suppress the electromigration of more reliably wiring material.
  • taper angle ⁇ may be within the range of the angle described above at the portion where the first inclined portion 246 is in contact with the side surface of the first groove portion 240.
  • first inclined portion 246 may be gradually parallel to the bottom surface of the first groove portion 240 where the first inclined portion 246 is not formed from the side in contact with the side surface of the first groove portion 240.
  • grains of a 1st barrier metal layer can be rebounded from the various directions of the 1st inclination part 246, and can be made to adhere to the side surface of the 1st groove part 240.
  • FIGS. 3 to 5 are cross-sectional views for explaining the method for manufacturing the semiconductor device according to the first embodiment.
  • the manufacturing method of the semiconductor device 10 according to the first embodiment includes the following steps. First, a first insulating layer is formed on a semiconductor substrate (silicon substrate 100). Next, the first groove portion 240 is formed in the first insulating layer (the first via forming insulating layer 220 and the first wiring forming insulating layer 230), and the first groove portion is formed in a portion of the bottom surface that contacts the side surface of the first groove portion 240.
  • the first inclined portion 246 is formed to be inclined in the depth direction of 240 (first groove forming step).
  • the first barrier metal layer 242 is formed on the bottom and side surfaces of the first groove portion 240 (first barrier metal layer forming step).
  • the first wiring 250 is formed by embedding a metal in the first groove portion 240. Details will be described below.
  • a silicon substrate 100 on which a semiconductor element (not shown) such as an FET is formed is prepared as a semiconductor substrate.
  • a first via formation insulating layer 220 is formed on the silicon substrate 100.
  • the first via forming insulating layer 220 is formed by, for example, CVD (Chemical Vapor Deposition).
  • a resist film (not shown) is applied on the first via formation insulating layer 220.
  • exposure and development are performed.
  • a resist film pattern having an opening is formed in a portion where a contact hole (not shown) connected to the semiconductor element is to be formed.
  • the first via formation insulating layer 220 in the opening of the resist film is removed by RIE (Reactive Ion Etching).
  • the resist film is ashed.
  • a barrier metal layer (not shown) and a seed layer (not shown) are sequentially formed on the first via formation insulating layer 220 and in the contact hole.
  • a metal is embedded in the contact hole by plating.
  • the first wiring formation insulating layer 230 is planarized by CMP (Chemical Mechanical Polishing). In this manner, a contact (not shown) connected to the semiconductor element is formed in the first via formation insulating layer 220.
  • a first wiring formed insulating layer 230 As shown in FIG. 3 (a), first, a first wiring formed insulating layer 230. At this time, the first wiring formation insulating layer 230 is formed by, for example, CVD. Then, on the first wiring formation insulating layer 230 is coated with a resist film (not shown). Next, exposure and development are performed. Thus, a resist film pattern having an opening in a portion where the first groove 240 is formed is formed. Then, by RIE, to remove the first wiring forming insulating layer 230 in the opening portion of the resist film. Next, the resist film is ashed. Hereinafter, this process is referred to as “first groove forming process”.
  • the bias voltage on the silicon substrate 100 side is adjusted to control the plasma to concentrate near the side surface of the first groove 240.
  • the 1st inclination part 246 is formed in the part which touches the side surface of the 1st groove part 240 among the bottom surfaces so that it may incline in the depth direction of the 1st groove part 240.
  • the first groove forming step etching is performed using a gas containing CF 3 I or CF 4 .
  • etching is performed using a gas containing CF 3 I or CF 4 .
  • the first wiring portion insulating layer 230 can be easily etched to form the first groove portion 240.
  • the first inclined portion 246 is formed so that it is deeper than the bottom surface of the first wiring formation insulating layer 230 and deep enough to reach the first via formation insulating layer 220 formed earlier.
  • a protective layer (not shown) for protecting the surface in the CMP process may be formed on the first wiring formation insulating layer 230.
  • a first barrier metal layer 242 is formed on the bottom and side surfaces of the first groove 240. At this time, a film is also formed on the first wiring formation insulating layer 230, but is omitted in FIG.
  • the first barrier metal layer 242 is formed by sputtering, for example.
  • TaN is formed by sputtering.
  • the first inclined portion 246 when the first inclined portion 246 is not provided, it is difficult to form a film on the side surface of the first groove portion 240 installed perpendicular to the surface of the sputtering target. In such a case, the thickness of the first barrier metal layer 242 formed on the side surface of the first groove 240 is thin.
  • the first barrier metal layer 242 can be formed on the side surface of the first groove portion with good coverage even at the stage of film formation.
  • the first barrier metal layer 242 is formed as follows. An etching process of the barrier metal layer 242 is performed. In this etching process, reverse sputtering, RIE, or the like is used.
  • the silicon substrate 100 of FIG. 3B is placed on the stage in the parallel plate type etching apparatus.
  • a high voltage is applied between the electrodes to generate plasma, and the surface of the silicon substrate 100 is irradiated with gas ions 500.
  • the gas ions 500 are, for example, Ar + ions.
  • the gas ions 500 are caused to collide toward the silicon substrate 100 side (arrows in FIG. 4A).
  • the first barrier metal layer 242 is sputtered to disperse some particles of the first barrier metal layer 242 on the bottom surface of the first groove portion 240 (V-shaped arrow in FIG. 4A). As a result, some particles of the first barrier metal layer 242 are attached to the side surface of the first groove portion 240.
  • the thickness (t 2 ) of the first barrier metal layer 242 on the side surface of the first groove 240 is set to the thickness (t 1 ) of the first barrier metal layer 242 on the bottom surface of the first groove 240. It is formed to be thicker. That is, the first barrier metal layer 242 is formed so that t 2 > t 1 .
  • the above thickness can be achieved by adjusting the etching time, the applied voltage, and the like.
  • first barrier metal layer 242 may be further formed after FIG.
  • first barrier metal layer 242 is TaN
  • Ta may be further formed after the etching step. Accordingly, a TaN / Ta double-layer structure may be formed from the side in contact with the first wiring formation insulating layer 230 as the first barrier metal layer 242.
  • the first barrier metal layer forming step is performed.
  • a first seed layer 244 is formed on the bottom and side surfaces of the first groove 240 so as to be in contact with the first barrier metal layer 242.
  • the first seed layer 244 for example, Cu is formed by sputtering.
  • the thickness of the first seed layer 244 is, for example, not less than 5 nm and not more than 50 nm.
  • the first seed layer 244 is used as a power feeding layer, and metal is embedded in the first groove portion 240 by electroplating. Next, excess metal is removed by CMP. In this way, the first wiring 250 is formed.
  • the semiconductor device 10 according to the first embodiment can be obtained.
  • FIG. 6 (a) is a cross-sectional view of a semiconductor device 10 according to the first embodiment.
  • a sample according to the first embodiment of FIG. 6A and a sample of a comparative example having the same configuration except that the first inclined portion 246 is not provided were prepared.
  • FIG. 6B shows a cross-sectional view of a comparative example that does not have the first inclined portion 246 for the portion C of FIG.
  • FIG.6 (c) has shown sectional drawing of 1st Embodiment about the C section of Fig.6 (a).
  • the C part is a side surface of the first groove part 240 formed in the first wiring formation insulating layer 230.
  • 6B and 6C show a case where the side surface of the first groove portion does not have a smooth surface, such as when the first wiring formation insulating layer 230 is a porous film, for example. ing.
  • the first barrier metal layer 242 cannot be formed on the unevenness on the side surface of the first groove portion 240 with good coverage. Therefore, a portion that is not covered with the first barrier metal layer 242 is generated due to the unevenness of the side surface of the first groove portion 240. In such a case, when the first wiring 250 is formed by plating, a portion where the first wiring 250 directly contacts the first wiring formation insulating layer 230 is generated.
  • the first wiring 250 that is in direct contact with the first wiring formation insulating layer 230 without using the first barrier metal layer 242 has low adhesion to the first wiring formation insulating layer 230. For this reason, electromigration occurs from the portion where the first wiring 250 is in direct contact with the first wiring formation insulating layer 230 due to the electron flow generated when a bias is applied to the first wiring 250.
  • the first barrier metal layer 242 is formed on the side surface of the first groove 240 with good coverage.
  • the first groove portion 240 is inclined in the depth direction of the first groove portion 240 at the portion of the bottom surface that contacts the side surface of the first groove portion 240.
  • One inclined portion 246 is provided.
  • the number of particles that recoil at the first inclined portion 246 and adhere to the side surface of the first groove portion 240 increases. In this way, the first barrier metal layer 242 can be formed on the side surface of the first groove portion 240 with good coverage.
  • the first wiring provided in the first groove is surrounded by the first barrier metal layer. Further, there is no portion where the first wiring 250 is in direct contact with the first wiring formation insulating layer 230.
  • the first wiring 250 is in close contact with the first wiring formation insulating layer 230 via the first barrier metal layer 242. Thereby, electromigration due to the material of the first wiring 250 does not occur due to an electron flow generated when a bias is applied to the first wiring 250.
  • the surroundings are protected by the first barrier metal layer even in a high temperature and high humidity environment. Thereby, the electromigration deterioration of the first wiring 250 is not accelerated by the moisture that has propagated through the first wiring formation insulating layer 230 and the like.
  • the electromigration of the wiring material in the fine multilayer wiring can be suppressed.
  • the case where the contact and the first groove 240 are formed by the single damascene method has been described.
  • the dual damascene method may be used.
  • FIG. 7 is a diagram illustrating a configuration of a semiconductor device according to the second embodiment.
  • the second embodiment is the same as the first embodiment except for the following points.
  • a second insulating layer (second via forming insulating layer 320 and second wiring forming insulating layer 330) is provided on the first wiring forming insulating layer 230. Further, in the second insulating layer, the second via forming insulating layer 320 is provided with a connection hole 322.
  • the second groove 340 having a bottom surface and a side surface is formed in the second wiring formation insulating layer 330 in the second insulating layer and is connected to the connection hole 322.
  • the second barrier metal layer 342 is provided so as to be in contact with the bottom surface and the side surface of the connection hole 322 and the second groove portion 340.
  • the second wiring 350 is provided inside the connection hole 322 and the second groove portion 340 and is connected to the first wiring 250 through the connection hole 322.
  • the second groove portion 340 has a second inclined portion 346 that is inclined in the depth direction of the second groove portion 340 at a portion in contact with the side surface of the second groove portion 340 in the bottom surface. Further, the second inclined portion 346 includes a part of the upper surface of the connection hole 322. Details will be described below.
  • the second insulating layer (the second via forming insulating layer 320 and the second wiring forming insulating layer 330), the second barrier metal layer 342, and the second wiring 350, which will be described below, are respectively the first insulating layer (the first via layer).
  • the formation insulating layer 220 and the first wiring formation insulating layer 230), the first barrier metal layer 242, and the first wiring 250 can be formed of the same material. Thereby, it is possible to suppress the occurrence of an event that causes Cu atoms to move due to a current during circuit operation, resulting in disconnection or an increase in resistance.
  • “suppressing the occurrence of an event” means that the time until a certain increase in resistance is increased. That is, the life of the semiconductor device 10 is extended.
  • the second insulating layer (the second via forming insulating layer 320 and the second wiring forming insulating layer 330), the second barrier metal layer 342, and the second wiring 350 are not limited to the above-described configuration.
  • the second insulating layer (the second via forming insulating layer 320 and the second wiring forming insulating layer 330), the second barrier metal layer 342, and the second wiring 350 are each composed of the first insulating layer (first via forming insulating layer).
  • the layer 220 and the first wiring formation insulating layer 230), the first barrier metal layer 242, and the first wiring 250 may be formed of a different material.
  • an etching stopper layer 310 is provided on the first wiring formation insulating layer 230.
  • the etching can be stopped by the etching stopper layer 310 when the position for opening the connection hole 322 described later is shifted.
  • Etching stopper layer 310 is composed of a layer having an etch selectivity in RIE.
  • the etching stopper layer 310 is, for example, SiN.
  • a second insulating layer (second via forming insulating layer 320 and second wiring forming insulating layer 330) is provided on the first wiring forming insulating layer 230.
  • the second insulating layer includes, for example, a second via forming insulating layer 320 and a second wiring forming insulating layer 330, and is formed on the first wiring forming insulating layer 230 in this order.
  • the second via forming insulating layer 320 and the second wiring forming insulating layer 330 may be formed of the same material. At this time, an interface may not be formed between the second via formation insulating layer 320 and the second wiring formation insulating layer 330.
  • the second via forming insulating layer 320 and the second wiring forming insulating layer 330 may be formed from different materials. Further, each of the second via formation insulating layer 320 and the second wiring formation insulating layer 330 may be formed of a plurality of layers.
  • the second via forming insulating layer 320 is provided with a connection hole 322.
  • the connection hole 322 is a hole provided in the second via forming insulating layer 320 in the second insulating layer, and the first wiring 250 and the second wiring 350 are embedded by embedding metal therein. Is connected.
  • the second groove 340 is formed in the second wiring formation insulating layer 330 in the second insulating layer, and is connected to the connection hole 322. As will be described later, the second groove 340 has the same shape as the first groove 240.
  • the second barrier metal layer 342 is provided so as to be in contact with the bottom surface and the side surface of the connection hole 322 and the second groove 340.
  • the second barrier metal layer 342 has the same function as the first barrier metal layer 242.
  • the second wiring 350 is provided inside the connection hole 322 and the second groove portion 340 and is connected to the first wiring 250 through the connection hole 322.
  • the second groove portion 340 has a second inclined portion 346 that is inclined in the depth direction of the second groove portion 340 in a portion of the bottom surface in contact with the side surface of the second groove portion 340.
  • the second groove 340 may be the same shape as the first groove 240.
  • the second inclined portion 346 can adjust the distance from the side surface of the second groove portion 340, the taper angle, and the like according to the height of the side surface of the second groove portion 340.
  • the second inclined portion 346 includes a portion of the upper surface of the connection hole 322.
  • the upper surface of the connection hole 322 is inclined in the same inclination direction of the second inclined portion 346 as the bottom surface in contact with the side surface of the second groove portion 340.
  • the upper surface of the opening of the connection hole 322 is wider than the surface in contact with the first wiring 250. Therefore, the current density in the upper part of the connection hole 322 can be reduced. That is, it is possible to electro-migration resistance of that portion is improved.
  • the second barrier metal layer 342 may be etched by plasma, as in the first embodiment.
  • the second barrier metal layer 342 on the side surface of the second groove 340 is formed thicker than the thickness of the second barrier metal layer 342 on the bottom surface of the second groove 340.
  • FIGS. 8 and 9 are cross-sectional views for explaining the semiconductor device manufacturing method according to the second embodiment.
  • the manufacturing method of the second embodiment is the same as the manufacturing method of the first embodiment except that the connection hole 322 is opened in the second via forming insulating layer 320. Details will be described below.
  • the etching stopper layer 310 is formed on the first wiring formation insulating layer 230 and the first wiring 250 that have been subjected to the CMP process.
  • the etching stopper layer 310 is formed by, for example, CVD.
  • a second via forming insulating layer 320 and a second wiring forming insulating layer 330 are sequentially stacked on the etching stopper layer 310.
  • the second via forming insulating layer 320 and the second wiring forming insulating layer 330 may be layers made of different materials.
  • a resist film (not shown) is applied on the second wiring formation insulating layer 330.
  • exposure and development are performed.
  • a resist film pattern having an opening in a portion where the second groove 340 is to be formed is formed.
  • RIE reactive ion etching
  • the bias voltage on the silicon substrate 100 side is adjusted so that the plasma is concentrated near the side surface of the second groove portion 340.
  • the second inclined portion 346 is formed so as to be inclined in the depth direction of the second groove portion 340 at a portion of the bottom surface that contacts the side surface of the second groove portion 340.
  • a resist film (not shown) is applied on the second wiring formation insulating layer 330 and the second groove 340.
  • exposure and development are performed.
  • a resist film pattern having an opening at a portion where the connection hole 322 is to be formed is formed.
  • the pattern of the resist film is formed so that the connection hole 322 is formed at a position overlapping the second inclined portion 346 in plan view.
  • RIE reactive ion etching
  • the second barrier metal layer 342 is formed on the bottom and side surfaces of the second groove 340 and the connection hole 322. At this time, a film is also formed on the first wiring formation insulating layer 230, but is omitted in FIG.
  • the first barrier metal layer 242 for example, is deposited by sputtering.
  • the second barrier metal layer 342 in the step of forming the second barrier metal layer 342, after the second barrier metal layer 342 is formed on the bottom and side surfaces of the second groove 340, the same as in the first embodiment. In addition, an etching process of the second barrier metal layer 342 is performed. Thereby, some particles of the second barrier metal layer 342 are attached to the side surface of the second groove 340.
  • connection hole 322 a part of the upper surface of the connection hole 322 is formed in the second inclined portion 346. For this reason, the upper surface of the connection hole 322 is widened toward the side surface of the second groove portion 340. Accordingly, some particles of the second barrier metal layer 342 scattered from the side surface of the connection hole 322 can be attached to the side surface of the second groove portion 340.
  • a second seed layer (not shown) is formed on the bottom and side surfaces of the second groove 340 and the connection hole 322 so as to be in contact with the second barrier metal layer 342.
  • metal is embedded in the second groove 340 and the connection hole 322 by electroplating.
  • excess metal is removed by CMP. In this way, the first wiring 250 is formed.
  • the semiconductor device 10 according to the first embodiment can be obtained.
  • the second inclined portion 346 includes a part of the upper surface of the connection hole 322.
  • the upper surface of the opening of the connection hole 322 is wider than the surface in contact with the first wiring 250. Therefore, it is possible to reduce the current density in the upper portion of the connection hole 322. That is, it is possible to improve the electromigration resistance of the part.
  • the upper surface of the connection hole 322 is widened toward the side surface of the second groove portion 340 as described above. Accordingly, some particles of the second barrier metal layer 342 scattered from the side surface of the connection hole 322 can be attached to the side surface of the second groove portion 340. Therefore, according to the second embodiment, electromigration can be further suppressed as compared with the first embodiment.
  • the second groove portion 340 includes the second inclined portion 346 has been described.
  • the second embodiment can be applied to a plurality of multilayer wiring structures.
  • the first via formation insulating layer 220 and the first wiring formation insulating layer 230 are, for example, a porous SiO film or a porous SiOC film has been described.
  • a non-porous (non-porous) SiOC film may be used.
  • the film forming method is not limited to the plasma CVD method, and can be formed by a CVD method, a coating method such as spin coating, or the like.

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Abstract

To suppress electromigration of a wiring material in fine multilayer wiring lines. This semiconductor device (10) is provided with: a semiconductor substrate (a silicon substrate (100)); first insulating layers (a first via-forming insulating layer (220) and a first wiring line-forming insulating layer (230)) that are formed on the semiconductor substrate (the silicon substrate (100)); a first groove (240) that is formed in the first wiring line-forming insulating layer (230) of the first insulating layers and has a bottom surface and a lateral surface; a first barrier metal layer (242) that is provided so as to be in contact with the bottom surface and the lateral surface of the first groove (240); and a first wiring line (250) that is provided within the first groove (240). In addition, the first groove (240) has a first inclined portion (246) in a part of the bottom surface, said part being in contact with the lateral surface of the first groove (240), and the first inclined portion (246) is inclined toward the depth direction of the first groove (240).

Description

半導体装置及び半導体装置の製造方法Semiconductor device and manufacturing method of semiconductor device
　本発明は、半導体装置及び半導体装置の製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
　多層配線構造の半導体装置において、配線を構成する材料のエレクトロマイグレーションを抑制することが望まれている。その対策として、様々な方法が提案されている。 In a semiconductor device having a multilayer wiring structure, it is desired to suppress electromigration of a material constituting the wiring. As a countermeasure, various methods have been proposed.
　特許文献１（米国特許第６８００１８０号明細書）には、接続孔の底にバリアメタル層などの材料を堆積するための製造方法として、以下のような工程を備えていると記載されている。まず、半導体基板上にバリアメタル層などの第１材料をスパッタする。次いで、基板に第１バイアス電圧を印加し、同時に、コンタクトホールの周囲の材料を除去して、リセスの上部にファセットを形成する。次いで、基板に第２バイアス電圧を印加して、同時に、リセスの底に第１材料をスパッタ成膜する。これにより、接続孔における第１材料のカバレッジが良くなるとされている。 Patent Document 1 (US Pat. No. 6,800,180) describes that the following steps are provided as a manufacturing method for depositing a material such as a barrier metal layer on the bottom of a connection hole. First, a first material such as a barrier metal layer is sputtered on a semiconductor substrate. Next, a first bias voltage is applied to the substrate, and at the same time, the material around the contact hole is removed to form a facet on the upper portion of the recess. Next, a second bias voltage is applied to the substrate, and at the same time, a first material is sputter-deposited on the bottom of the recess. Thus, the coverage of the first material in the connection hole is a better.
　また、特許文献２（特開２００７－２２７７０９号公報）には、下記のような半導体集積回路装置の製造方法が記載されている。まず、接続孔および配線溝を形成し、接続孔及び配線溝の側壁および底面にバリアメタル層を成膜する。次いで、接続孔の底部のバリアメタル層を除去し、さらに接続孔の下の埋め込み配線の一部を掘り込む。次いで、深さ方向に指向性を向上させた条件で、スパッタリング法にて配線溝および接続孔内を含む層間絶縁膜上にタンタル膜を堆積する。このようにして、配線溝の底部のバリアメタル層の膜厚を増加し、接続孔の底部を再びバリアメタル層で覆う。これにより、下層の埋め込み配線と上層の埋め込み配線との間における銅配線の接続部分での接続特性の信頼性を向上できるとされている。 Patent Document 2 (Japanese Patent Laid-Open No. 2007-227709) describes a method for manufacturing a semiconductor integrated circuit device as described below. First, connection holes and wiring grooves are formed, and a barrier metal layer is formed on the side walls and bottom surface of the connection holes and wiring grooves. Next, the barrier metal layer at the bottom of the connection hole is removed, and a part of the embedded wiring below the connection hole is dug. Next, a tantalum film is deposited on the interlayer insulating film including the wiring trench and the connection hole by a sputtering method under the condition that the directivity is improved in the depth direction. In this way, the thickness of the barrier metal layer at the bottom of the wiring trench is increased, and the bottom of the connection hole is again covered with the barrier metal layer. Thereby, it is said that the reliability of the connection characteristic in the connection part of the copper wiring between the lower layer embedded wiring and the upper layer embedded wiring can be improved.
　また、特許文献３（特開２００４－３４２７０２号公報）には、下記のような半導体装置が記載されている。下地層は、基板上に設けられている。また、第１絶縁層は、下地層を覆うように設けられている。テーパー部は、第１絶縁層の表面から下地層へ延びる第１凹部における底部の端部に沿って設けられている。ここで、テーパー部は、底部の中央に向かうテーパー面を有している。また、バリアメタル層は、テーパー面とテーパー部に覆われていない第１凹部の側面および底部を覆うように設けられている。第１導体部は、銅を含む金属によって、第１凹部を充填するように設けられている。これにより、コンタクトを含む配線におけるＣｕのマイグレーションを防止することができるとされている。 Further, Patent Document 3 (Japanese Patent Laid-Open No. 2004-342702) describes the following semiconductor device. The underlayer is provided on the substrate. The first insulating layer is provided so as to cover the underlying layer. The taper portion is provided along the bottom end portion of the first recess extending from the surface of the first insulating layer to the base layer. Here, the taper portion has a taper surface toward the center of the bottom portion. In addition, the barrier metal layer is provided so as to cover the side surface and the bottom portion of the first recess that is not covered by the tapered surface and the tapered portion. The first conductor portion is provided so as to fill the first recess with a metal containing copper. Thereby, it is said that Cu migration in the wiring including the contact can be prevented.
　また、特許文献４（特開２００１－１７６９６８号公報）には、下記のような半導体集積回路装置が記載されている。この半導体集積回路装置の絶縁膜には、接続孔および配線溝が形成されている。その接続孔および配線溝の内部には、バリア導電膜（バリアメタル層）およびシード膜を形成されている。ここで、接続孔は、底部が上部に比べて細い順テーパーとなるように形成されている。また、配線溝は、側壁が配線溝の底部に対して垂直になるように形成されている。また、上層、下層の側壁同士が階段状にならずに連続するように形成されている。これにより、バリア導電膜（バリアメタル層）のバリア性を確保し、導電性膜の埋め込み性を良くすることができるとされている。 Further, Patent Document 4 (Japanese Patent Laid-Open No. 2001-176968) describes the following semiconductor integrated circuit device. The insulating film of the semiconductor integrated circuit device, the connection hole and the wiring grooves are formed. A barrier conductive film (barrier metal layer) and a seed film are formed inside the connection hole and the wiring groove. Here, the connection hole is formed such that the bottom portion has a narrower forward taper than the upper portion. The wiring groove is formed so that the side wall is perpendicular to the bottom of the wiring groove. Further, the side walls of the upper layer and the lower layer are formed so as to be continuous without being stepped. Thereby, it is said that the barrier property of the barrier conductive film (barrier metal layer) can be secured and the embedding property of the conductive film can be improved.
米国特許第６８００１８０号明細書US Pat. No. 6,800,180 特開２００７－２２７７０９号公報JP 2007-227709 A 特開２００４－３４２７０２号公報JP 2004-342702 A 特開２００１－１７６９６８号公報JP 2001-176968 A
　近年では、半導体装置の集積化が進み、配線を接続する接続孔も微細化が進んでいる。このように微細化した多層配線の場合、上記した特許文献のなかでも特許文献１および特許文献４に記載の構造では、接続孔に十分な順テーパー角をつけられない。このような場合、特に溝部または接続孔の側面において、バリアメタル層のカバレッジ性が悪くなってしまう。この点に関して、発明者らは、特に溝部または接続孔の側面において、バリアメタル層のカバレッジ性が悪いことを原因として、配線材料のエレクトロマイグレーションが発生しやすいことを見出した（非特許文献１、非特許文献２）。したがって、上記した特許文献に記載の技術では、配線材料のエレクトロマイグレーションを抑制することができない可能性があった。 In recent years, integration of semiconductor devices has progressed, and connection holes for connecting wirings have also been miniaturized. In the case of such a miniaturized multilayer wiring, the structure described in Patent Document 1 and Patent Document 4 among the above-mentioned Patent Documents cannot provide a sufficient forward taper angle. In such a case, the coverage property of the barrier metal layer is deteriorated particularly on the side surface of the groove or the connection hole. In this regard, the inventors have found that electromigration of the wiring material is likely to occur due to the poor coverage of the barrier metal layer, particularly on the side surface of the groove or connection hole (Non-Patent Document 1, Non-patent document 2). Therefore, there is a possibility that the electromigration of the wiring material cannot be suppressed by the technique described in the above-described patent document.
　本発明によれば、
　半導体基板と、
　前記半導体基板上に形成された第１絶縁層と、
　前記第１絶縁層に形成され、底面と側面を有する第１溝部と、
　前記第１溝部の前記底面および前記側面と接するように設けられた第１バリアメタル層と、
　前記第１溝部の内部に設けられた第１配線と、
を備え、
　前記第１溝部は、前記底面のうち、前記第１溝部の前記側面と接する部分に前記第１溝部の深さ方向に傾斜している第１傾斜部を有する半導体装置が提供される。 According to the present invention,
A semiconductor substrate;
A first insulating layer formed on the semiconductor substrate;
A first groove formed in the first insulating layer and having a bottom surface and a side surface;
A first barrier metal layer provided so as to be in contact with the bottom surface and the side surface of the first groove portion;
A first wiring provided inside the first groove,
With
In the semiconductor device, the first groove portion includes a first inclined portion that is inclined in a depth direction of the first groove portion at a portion of the bottom surface that is in contact with the side surface of the first groove portion.
　また、本発明によれば、
　半導体基板上に第１絶縁層を形成する工程と、
　前記第１絶縁層に底面と側面を有する第１溝部を形成するとともに、前記底面のうち、前記第１溝部の前記側面と接する部分に前記第１溝部の深さ方向に傾斜させるように第１傾斜部を形成する第１溝部形成工程と、
　前記第１溝部の前記底面および前記側面に第１バリアメタル層を形成する第１バリアメタル層形成工程と、
　前記第１溝部内に金属を埋め込むことにより、第１配線を形成する工程と、
を備える半導体装置の製造方法が提供される。 Moreover, according to the present invention,
Forming a first insulating layer on the semiconductor substrate;
A first groove having a bottom surface and a side surface is formed in the first insulating layer, and a first portion of the bottom surface that is in contact with the side surface of the first groove portion is inclined in a depth direction of the first groove portion. A first groove forming step for forming an inclined portion;
A first barrier metal layer forming step of forming a first barrier metal layer on the bottom surface and the side surface of the first groove portion;
Forming a first wiring by embedding a metal in the first groove;
A method for manufacturing a semiconductor device is provided.
　本発明によれば、第１溝部は、底面のうち、第１溝部の側面と接する部分に第１溝部の深さ方向に傾斜している第１傾斜部を有している。このような第１溝部の底面および側面に第１バリアメタル層を形成するとき、第１傾斜部で反跳して、第１溝部の側面に付着する粒子が多くなる。このようにして、第１溝部の側面には、第１バリアメタル層がカバレッジ性良く形成されている。これにより、第１溝部内に設けられた第１配線は、第１バリアメタル層によって周囲が囲まれているため、エレクトロマイグレーションが起こりにくくなる。以上のように、微細な多層配線における配線材料のエレクトロマイグレーションを抑制することができる。 According to the present invention, the first groove portion has a first inclined portion that is inclined in the depth direction of the first groove portion at a portion of the bottom surface that contacts the side surface of the first groove portion. When the first barrier metal layer is formed on the bottom surface and the side surface of the first groove portion, particles that recoil at the first inclined portion and adhere to the side surface of the first groove portion increase. Thus, the first barrier metal layer is formed with good coverage on the side surface of the first groove. Thereby, since the periphery of the first wiring provided in the first groove is surrounded by the first barrier metal layer, electromigration hardly occurs. As described above, electromigration of the wiring material in fine multilayer wiring can be suppressed.
　本発明によれば、微細な多層配線における配線材料のエレクトロマイグレーションを抑制することができる。 According to the present invention, the electromigration of the wiring material in the fine multilayer wiring can be suppressed.
　上述した目的、およびその他の目的、特徴および利点は、以下に述べる好適な実施の形態、およびそれに付随する以下の図面によってさらに明らかになる。 The above-described object and other objects, features, and advantages will be further clarified by a preferred embodiment described below and the following drawings attached thereto.
第１の実施形態に係る半導体装置の構成を示す図である。1 is a diagram illustrating a configuration of a semiconductor device according to a first embodiment. 第１の実施形態における傾斜部のテーパー角とエレクトロマイグレーション寿命との関係を説明するための図である。It is a figure for demonstrating the relationship between the taper angle of the inclination part in 1st Embodiment, and an electromigration lifetime. 第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is a sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment. 第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is a sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment. 第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is a sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment. 第１の実施形態の効果を説明するための断面図である。It is sectional drawing for demonstrating the effect of 1st Embodiment. 第２の実施形態に係る半導体装置の構成を示す図である。It is a figure which shows the structure of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法を説明するための断面図である。It is a sectional view for explaining a method for manufacturing a semiconductor device according to a second embodiment.
　以下、本発明の実施の形態について、図面を用いて説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.
　（第１の実施形態）
　図１は、第１の実施形態に係る半導体装置の構成を示す図である。なお、図１（ａ）は、半導体装置１０の構成を示す上面図である。また、図１（ｂ）は、半導体装置１０の構成を示すＡ－Ａ'線断面図である。また、図１（ｃ）は、半導体装置１０の構成を示すＢ－Ｂ'線断面図である。この半導体装置１０は、以下のような構成を備えている。半導体基板（シリコン基板１００）と、半導体基板（シリコン基板１００）上に形成された第１絶縁層（第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０）と、第１絶縁層のうち、第１配線形成絶縁層２３０に形成され、底面と側面を有する第１溝部２４０と、第１溝部２４０の底面および側面と接するように設けられた第１バリアメタル層２４２と、第１溝部２４０内に設けられた第１配線２５０と、を備えている。また、第１溝部２４０は、底面のうち、第１溝部２４０の側面と接する部分に第１溝部２４０の深さ方向に傾斜している第１傾斜部２４６を有している。以下、詳細を説明する。 (First embodiment)
FIG. 1 is a diagram illustrating a configuration of the semiconductor device according to the first embodiment. FIG. 1A is a top view showing the configuration of the semiconductor device 10. FIG. 1B is a cross-sectional view taken along the line AA ′ showing the configuration of the semiconductor device 10. FIG. 1C is a cross-sectional view taken along line BB ′ showing the configuration of the semiconductor device 10. The semiconductor device 10 has the following configuration. Of the first insulating layer, a semiconductor substrate (silicon substrate 100), a first insulating layer (first via forming insulating layer 220 and first wiring forming insulating layer 230) formed on the semiconductor substrate (silicon substrate 100), and A first groove portion 240 formed on the first wiring formation insulating layer 230 and having a bottom surface and a side surface; a first barrier metal layer 242 provided in contact with the bottom surface and the side surface of the first groove portion 240; and the first groove portion 240. And a first wiring 250 provided therein. In addition, the first groove portion 240 has a first inclined portion 246 that is inclined in the depth direction of the first groove portion 240 at a portion of the bottom surface that is in contact with the side surface of the first groove portion 240. Details will be described below.
　本実施形態では、半導体基板としては、たとえば、シリコン基板１００である。 In the present embodiment, the semiconductor substrate is, for example, the silicon substrate 100.
　図１（ａ）のように、平面視において、第１絶縁層のうち、第１配線形成絶縁層２３０の内部には、側面に接するように第１バリアメタル層２４２が設けられている。また、第１バリアメタル層２４２の内側には、第１配線２５０が設けられている。 As shown in FIG. 1A, a first barrier metal layer 242 is provided inside the first wiring formation insulating layer 230 in the first insulating layer so as to be in contact with the side surface in a plan view. A first wiring 250 is provided inside the first barrier metal layer 242.
　また、図１（ｂ）のように、シリコン基板１００上には、第１絶縁層（第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０）が設けられている。ここで、シリコン基板１００には、たとえば、ＦＥＴ（Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）などの半導体素子（不図示）が形成されている。また、第１絶縁層は、たとえば、第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０を有しており、シリコン基板１００上にこの順で形成されている。また、図示されていない領域には、第１ビア形成絶縁層２２０にコンタクト（不図示）が設けられている。後述する第１配線２５０は、たとえば、このコンタクトを介して、半導体素子に接続されている。 Further, as shown in FIG. 1B, a first insulating layer (a first via forming insulating layer 220 and a first wiring forming insulating layer 230) is provided on the silicon substrate 100. Here, on the silicon substrate 100, for example, a semiconductor element (not shown) such as an FET (Field Effect Transistor) is formed. The first insulating layer has, for example, a first via forming insulating layer 220 and a first wiring forming insulating layer 230, which are formed on the silicon substrate 100 in this order. Further, a contact (not shown) is provided on the first via formation insulating layer 220 in a region not shown. A first wiring 250 to be described later is connected to the semiconductor element through this contact, for example.
　ここで、第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０は、同一の材料から形成されていてもよい。このとき、第１ビア形成絶縁層２２０と第１配線形成絶縁層２３０との間に界面が形成されていなくてもよい。または、第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０は、異なる材料から形成されていてもよい。さらに、第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０は、それぞれ、複数層から形成されていてもよい。 Here, the first via forming insulating layer 220 and the first wiring forming insulating layer 230 may be formed of the same material. At this time, an interface may not be formed between the first via formation insulating layer 220 and the first wiring formation insulating layer 230. Alternatively, the first via forming insulating layer 220 and the first wiring forming insulating layer 230 may be formed from different materials. Further, each of the first via forming insulating layer 220 and the first wiring forming insulating layer 230 may be formed of a plurality of layers.
　第１絶縁層（第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０）の比誘電率は、たとえば、２．６以下である。これにより、配線間容量を減らすことができるので、半導体装置１０の全体としてのインピーダンスを下げることができる。ここで、第１絶縁層のうち、少なくとも第１ビア形成絶縁層２２０の比誘電率が２．６以下であることが好ましい。 The relative dielectric constant of the first insulating layer (the first via forming insulating layer 220 and the first wiring forming insulating layer 230) is, for example, 2.6 or less. As a result, the inter-wiring capacitance can be reduced, so that the impedance of the entire semiconductor device 10 can be reduced. Here, it is preferable that the relative dielectric constant of at least the first via forming insulating layer 220 of the first insulating layer is 2.6 or less.
　また、第１絶縁層（第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０）は、たとえば、ポーラス膜である。このようなポーラス膜にすることにより、比誘電率を低くすることができる。ここで、第１絶縁層のうち、少なくとも第１ビア形成絶縁層２２０がポーラス膜であることが好ましい。 The first insulating layer (the first via forming insulating layer 220 and the first wiring forming insulating layer 230) is, for example, a porous film. With such a porous film, it is possible to lower the dielectric constant. Here, it is preferable that at least the first via forming insulating layer 220 of the first insulating layer is a porous film.
　第１絶縁層（第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０）としては、たとえば、ポーラスＳｉＯ膜、ポーラスＳｉＯＣ膜などである。また、第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０の層厚は、それぞれ５０ｎｍ以上２００ｎｍ以下である。 Examples of the first insulating layer (the first via forming insulating layer 220 and the first wiring forming insulating layer 230) include a porous SiO film and a porous SiOC film. The layer thicknesses of the first via forming insulating layer 220 and the first wiring forming insulating layer 230 are 50 nm or more and 200 nm or less, respectively.
　図１（ｂ）のように、第１絶縁層のうち、第１配線形成絶縁層２３０には、第１溝部２４０が形成されている。ここで、第１溝部２４０とは、第１絶縁層のうち、第１配線形成絶縁層２３０に設けられ、内部に導電体を埋め込むことにより第１配線２５０を形成するための開口部のことをいう。 As shown in FIG. 1B, a first groove 240 is formed in the first wiring formation insulating layer 230 in the first insulating layer. Here, the first groove portion 240 is an opening provided in the first wiring formation insulating layer 230 in the first insulating layer and for forming the first wiring 250 by embedding a conductor therein. Say.
　また、第１溝部２４０には、その底面および側面と接するように、第１バリアメタル層２４２が設けられている。ここで、第１バリアメタル層２４２は、第１絶縁層（第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０）との密着性が良い。また、第１バリアメタル層２４２は、第１配線２５０の材料をマイグレーションさせないように保護する機能を有している。 Further, the first groove portion 240 is provided with a first barrier metal layer 242 so as to be in contact with the bottom surface and the side surface thereof. Here, the first barrier metal layer 242 has good adhesion to the first insulating layer (the first via forming insulating layer 220 and the first wiring forming insulating layer 230). The first barrier metal layer 242 has a function of protecting the material of the first wiring 250 from migration.
　第１バリアメタル層２４２としては、たとえば、Ｔａ、ＴｉまたはＲｕを含んでいる。具体的には、第１バリアメタル層２４２としては、たとえば、Ｔａ、ＴｉまたはＲｕである。さらに、ＴａＮ、ＴｉＮまたはＲｕＮなどの窒化物であってもよい。 The first barrier metal layer 242 includes, for example, Ta, Ti, or Ru. Specifically, the first barrier metal layer 242 is, for example, Ta, Ti, or Ru. Furthermore, a nitride such as TaN, TiN, or RuN may be used.
　また、第１バリアメタル層２４２は、複数層で形成されていてもよい。具体的には、第１バリアメタル層２４２としては、たとえば、第１配線形成絶縁層２３０と接する側からＴａＮ／Ｔａとする二層構造である。 Further, the first barrier metal layer 242 may be formed of a plurality of layers. Specifically, the first barrier metal layer 242 has a two-layer structure of TaN / Ta from the side in contact with the first wiring formation insulating layer 230, for example.
　後述する第１溝部２４０の底面における第１バリアメタル層２４２の厚さは、たとえば、５ｎｍ以上３０ｎｍ以下である。上記範囲内であることにより、上記した密着性を強化する機能や、マイグレーションを抑止する機能を有することができる。なお、第１バリアメタル層２４２が複数層からなる場合は、それぞれの層が上記厚さの範囲であることが好ましい。 The thickness of the first barrier metal layer 242 on the bottom surface of the first groove portion 240 described later is, for example, 5 nm or more and 30 nm or less. By being within the above range, it is possible to have a function of enhancing the above-described adhesion and a function of suppressing migration. In addition, when the 1st barrier metal layer 242 consists of multiple layers, it is preferable that each layer is the range of the said thickness.
　また、第１溝部２４０の内部には、第１配線２５０が設けられている。このとき、第１配線２５０は、底面および側面を第１バリアメタル層２４２によって囲まれている。これにより、第１配線２５０の材料のエレクトロマイグレーションを抑制することができる。 In addition, a first wiring 250 is provided inside the first groove portion 240. At this time, the first wiring 250 is surrounded by the first barrier metal layer 242 on the bottom and side surfaces. Thereby, the electromigration of the material of the 1st wiring 250 can be suppressed.
　第１配線２５０としては、たとえば、Ｃｕを主材料として含んでいる。Ｃｕはエレクトロマイグレーションを生じやすい材料である。なお、後述する第１傾斜部２４６を有することで、エレクトロマイグレーションを抑制することができる。 The first wiring 250 includes, for example, Cu as a main material. Cu is a material that easily causes electromigration. In addition, electromigration can be suppressed by having the 1st inclination part 246 mentioned later.
　また、第１配線２５０の厚さは、たとえば、１００ｎｍ以上８００ｎｍ以下である。 The thickness of the first wiring 250 is, for example, 100nm or 800nm or less.
　ここで、第１溝部２４０は、底面のうち、第１溝部２４０の側面と接する部分に第１溝部２４０の深さ方向に傾斜している第１傾斜部２４６を有している。ここで、「第１溝部２４０の側面」とは、第１配線２５０が延伸する方向（図１（ａ）中のＡ－Ａ'線方向）の側面だけでなく、第１配線２５０の幅方向（図１（ａ）中のＢ－Ｂ'線方向）の側面を含む。なお、第１配線２５０が延伸する方向とは、第１配線２５０の長手方向のことを意味する。また、第１溝部２４０の側面と接する底面は、側面に沿った方向に全体が傾斜している場合だけでなく、その一部が傾斜している場合でもよい。 Here, the 1st groove part 240 has the 1st inclination part 246 which inclines in the depth direction of the 1st groove part 240 in the part which contact | connects the side surface of the 1st groove part 240 among the bottom faces. Here, the “side surface of the first groove portion 240” means not only the side surface in the direction in which the first wiring 250 extends (the AA ′ line direction in FIG. 1A) but also the width direction of the first wiring 250. It includes a side surface (in the BB ′ line direction in FIG. 1A). Note that the direction in which the first wiring 250 extends means the longitudinal direction of the first wiring 250. Further, the bottom surface in contact with the side surface of the first groove portion 240 may not only be inclined in the direction along the side surface but also may be partially inclined.
　このように、第１溝部２４０には、第１傾斜部２４６が形成されている。後述するように、このような第１溝部２４０の底面および側面に第１バリアメタル層２４２を形成するとき、第１傾斜部２４６で反跳して、第１溝部２４０の側面に付着する粒子が多くなる。したがって、第１溝部２４０の側面には、カバレッジ性のよい第１バリアメタル層２４２が形成されている。第１の実施形態に係る効果については、詳細を後述する。 Thus, the first inclined portion 246 is formed in the first groove portion 240. As will be described later, when the first barrier metal layer 242 is formed on the bottom surface and the side surface of the first groove portion 240, particles that recoil at the first inclined portion 246 and adhere to the side surface of the first groove portion 240 are formed. Become more. Therefore, the first barrier metal layer 242 with good coverage is formed on the side surface of the first groove portion 240. Details of the effect according to the first embodiment will be described later.
　また、図１（ｂ）のように、第１傾斜部２４６は、第１溝部２４０の近傍において形成されている。ここで、第１傾斜部２４６が形成されている「第１溝部２４０の側面から近傍」とは、後述する第１バリアメタル層の形成工程において、第１傾斜部２４６から反跳した粒子が第１溝部２４０の側面に届く程度に近い範囲のことをいう。したがって、第１溝部２４０の底面には、シリコン基板１００の表面と平行になる部分が形成されていてもよい。 Further, as shown in FIG. 1B, the first inclined portion 246 is formed in the vicinity of the first groove portion 240. Here, the “vicinity from the side surface of the first groove portion 240” in which the first inclined portion 246 is formed means that particles that have rebounded from the first inclined portion 246 in the first barrier metal layer forming step described later. It means a range close to the extent of reaching the side surface of one groove portion 240. Therefore, a portion parallel to the surface of the silicon substrate 100 may be formed on the bottom surface of the first groove portion 240.
　ここで、第１溝部２４０の側面からの第１傾斜部２４６の長さは、第１配線２５０の厚さの１／２倍以上である。より好ましくは、第１配線２５０の厚さの１／２倍以上３倍以下である。これにより、後述する第１バリアメタル層の形成工程において、第１傾斜部２４６から反跳した粒子を第１溝部２４０の側面の全体にわたって、付着させることができる。したがって、第１溝部２４０の側面の下部から上部まで、第１バリアメタル層２４２のカバレッジ性を良くすることができる。なお、ここでいう「第１配線２５０の厚さ」は、第１溝部２４０の深さから第１バリアメタル層２４２の厚さを引いた値と等しい。 Here, the length of the first inclined portion 246 from the side surface of the first groove portion 240 is not less than ½ times the thickness of the first wiring 250. More preferably not more than 3 times half the thickness of the first wiring 250. Thereby, in the formation process of the 1st barrier metal layer mentioned later, the particle | grains which bounced from the 1st inclination part 246 can be made to adhere over the whole side surface of the 1st groove part 240. FIG. Therefore, the coverage of the first barrier metal layer 242 can be improved from the lower part to the upper part of the side surface of the first groove part 240. The “thickness of the first wiring 250” here is equal to a value obtained by subtracting the thickness of the first barrier metal layer 242 from the depth of the first groove portion 240.
　また、図１（ｂ）のように第１溝部２４０の側面は、第１傾斜部２４６が形成されていない領域の第１溝部２４０の底面に対して垂直である。また、第１溝部２４０側面は、シリコン基板１００、第１絶縁層（第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０）の底面に対しても垂直である。これにより、平面視で第１配線２５０の占める範囲を狭くすることができる。このとき、第１傾斜部２４６と側面とのなす角θは鋭角となっている。 Further, as shown in FIG. 1B, the side surface of the first groove portion 240 is perpendicular to the bottom surface of the first groove portion 240 in the region where the first inclined portion 246 is not formed. The side surfaces of the first groove 240 are also perpendicular to the bottom surfaces of the silicon substrate 100 and the first insulating layer (the first via forming insulating layer 220 and the first wiring forming insulating layer 230). Thus, it is possible to narrow the range occupied by the first wiring 250 in plan view. At this time, the angle θ formed by the first inclined portion 246 and the side surface is an acute angle.
　ここで、後述するように、製造工程のうち、第１溝部２４０の底面および側面に第１バリアメタル層２４２を形成する工程において、第１バリアメタル層２４２を成膜した後に、第１バリアメタル層２４２をプラズマでエッチングしてもよい。この工程により、第１溝部２４０の側面における第１バリアメタル層２４２は、第１溝部２４０の底面における第１バリアメタル層２４２の厚さよりも厚く形成されている。これにより、第１溝部２４０の側面からのエレクトロマイグレーションを顕著に抑制することができる。 Here, as will be described later, in the process of forming the first barrier metal layer 242 on the bottom and side surfaces of the first groove 240 in the manufacturing process, after the first barrier metal layer 242 is formed, the first barrier metal layer 242 is formed. Layer 242 may be etched with plasma. By this step, the first barrier metal layer 242 on the side surface of the first groove portion 240 is formed thicker than the thickness of the first barrier metal layer 242 on the bottom surface of the first groove portion 240. Thereby, the electromigration from the side surface of the 1st groove part 240 can be suppressed notably.
　ここで、第１配線形成絶縁層２３０がポーラス膜である場合、第１配線形成絶縁層２３０中の空孔によって、第１溝部２４０の側面は凹凸が大きい。このため、第１溝部２４０の側面において、第１バリアメタル層２４２のカバレッジ性は悪くなる。したがって、第１配線２５０の材料によるエレクトロマイグレーションは、特に第１溝部２４０の側面から発生しやすい。 Here, when the first wiring formation insulating layer 230 is a porous film, the side surface of the first groove portion 240 is largely uneven due to the holes in the first wiring formation insulating layer 230. For this reason, the coverage of the first barrier metal layer 242 is deteriorated on the side surface of the first groove portion 240. Therefore, electromigration due to the material of the first wiring 250 is likely to occur particularly from the side surface of the first groove 240.
　このような場合、第１溝部２４０の側面における第１バリアメタル層２４２が上記のように厚く形成されていることにより、確実に第１溝部２４０の側面からのエレクトロマイグレーションを抑制することができる。 In such a case, since the first barrier metal layer 242 on the side surface of the first groove portion 240 is formed thick as described above, electromigration from the side surface of the first groove portion 240 can be reliably suppressed.
　また、図１（ｃ）のように、第１配線２５０の幅方向（図１（ａ）中のＢ－Ｂ'線方向）の側面の近傍においても、第１傾斜部２４６が形成されている。すなわち、第１溝部２４０の両側の側面において、第１傾斜部２４６が形成されている。これにより、第１配線２５０よりも下層の配線が、第１配線２５０の幅方向（第１配線２５０と垂直の方向）に延伸していても、エレクトロマイグレーションを抑制することができる。 Further, as shown in FIG. 1C, the first inclined portion 246 is also formed in the vicinity of the side surface of the first wiring 250 in the width direction (the BB ′ line direction in FIG. 1A). . That is, the first inclined portion 246 is formed on the side surfaces on both sides of the first groove portion 240. As a result, even if the wiring below the first wiring 250 extends in the width direction of the first wiring 250 (direction perpendicular to the first wiring 250), electromigration can be suppressed.
　次に、図２を用いて、第１傾斜部２４６のテーパー角θについて説明する。図２（ａ）は、第１の実施形態における傾斜部のテーパー角とエレクトロマイグレーション寿命との関係を示した図である。ここで、第１傾斜部２４６のテーパー角（図２（ｂ）中のθ）とは、第１傾斜部２４６の底面と、第１溝部２４０の側面とのなす角度のことをいう。なお、図２（ａ）では、９０度からテーパー角θを引いた値を横軸としている。 Next, with reference to FIG. 2, it will be described taper angle θ of the first inclined portion 246. FIG. 2A is a diagram showing the relationship between the taper angle of the inclined portion and the electromigration lifetime in the first embodiment. Here, the taper angle of the first inclined portion 246 (θ in FIG. 2B) refers to an angle formed by the bottom surface of the first inclined portion 246 and the side surface of the first groove portion 240. In FIG. 2A, the horizontal axis represents the value obtained by subtracting the taper angle θ from 90 degrees.
　ここで、第１傾斜部２４６と第１溝部２４０の側面とのなす角度は、４０度以上６５度以下である。これについて、詳細を説明する。 Here, the angle formed by the first inclined portion 246 and the side surface of the first groove portion 240 is not less than 40 degrees and not more than 65 degrees. This will be described in detail.
　図２（ａ）の測定には、図２（ｂ）のような構成を有するサンプルを用いた。図２（ｂ）のサンプルは、図１に示されている部分と同じ構成とした。図１の第１配線形成絶縁層２３０上に、さらに、エッチングストッパー層３１０、第２ビア形成絶縁層３２０および第２配線形成絶縁層３３０の順で積層した。なお、第２ビア形成絶縁層３２０および第２配線形成絶縁層３３０は、後述する第２の実施形態における第２絶縁層に相当する。また、第２ビア形成絶縁層３２０および第２配線形成絶縁層３３０には、接続孔（不図示）および第２溝部（不図示）が設けられている。また、その接続孔および第２溝部の底面および側面には、第２バリアメタル層が設けられている。さらに、接続孔および第２溝部の内部には、第２配線３５０が設けられている。なお、第１配線２５０と第２配線３５０とのピッチは、１４０ｎｍとした。第１ビア形成絶縁層２２０および第２ビア形成絶縁層３２０は、ポーラスＳｉＯＣ膜とした。第１配線形成絶縁層２３０および第２配線形成絶縁層３３０は、ポーラスＳｉＯ膜とした。また、第１配線２５０と第２配線３５０は、Ｃｕとした。 In the measurement of FIG. 2 (a), a sample having a configuration as shown in FIG. 2 (b) was used. The sample shown in FIG. 2B has the same configuration as that shown in FIG. On the first wiring formation insulating layer 230 of FIG. 1, an etching stopper layer 310, a second via formation insulating layer 320, and a second wiring formation insulation layer 330 were further stacked in this order. The second via forming insulating layer 320 and the second wiring forming insulating layer 330 correspond to the second insulating layer in the second embodiment to be described later. The second via forming insulating layer 320 and the second wiring forming insulating layer 330 are provided with a connection hole (not shown) and a second groove (not shown). A second barrier metal layer is provided on the bottom surface and side surfaces of the connection hole and the second groove. Furthermore, a second wiring 350 is provided inside the connection hole and the second groove portion. Note that the first wiring 250 pitch between the second wiring 350 was set to 140 nm. The first via forming insulating layer 220 and the second via forming insulating layer 320 are porous SiOC films. The first wiring formation insulating layer 230 and the second wiring formation insulation layer 330 are porous SiO films. The first wiring 250 and the second wiring 350 are made of Cu.
　以上のような構成を有するサンプルのうち、第１傾斜部２４６のテーパー角θが異なる５つのサンプルを用意して、下記のような加速試験を行った。図２（ｂ）中の実線矢印は、これらのサンプルに印加したバイアスの方向を示している。温度３００℃のもとで、電流密度１ＭＡ／ｃｍ２の電流を印加して、エレクトロマイグレーション寿命（ＥＭ　Ｌｉｆｅｔｉｍｅ）を評価した。図２（ａ）のエレクトロマイグレーション寿命とは、上記した加速試験によって、サンプルのうち５０％の電気抵抗が５％増加するまでの時間を示している。 Among the samples having the above configuration, five samples having different taper angles θ of the first inclined portions 246 were prepared, and the following acceleration test was performed. The solid arrow in FIG. 2B indicates the direction of the bias applied to these samples. Electromigration lifetime (EM Lifetime) was evaluated by applying a current density of 1 MA / cm 2 at a temperature of 300 ° C. The electromigration lifetime in FIG. 2A indicates the time until the electrical resistance of 50% of the sample increases by 5% by the accelerated test described above.
　図２（ａ）のように、テーパー角θを小さくしていく（９０°－θを大きくしていく）ことにより、エレクトロマイグレーション寿命が長くなることが分かる。とりわけ、９０°－θの値が２５度以上５０度未満であるときに、エレクトロマイグレーション寿命が顕著に長くなっている。すなわち、テーパー角θは４０度より大きく６５度以下である。 As shown in FIG. 2A, it can be seen that the electromigration lifetime is increased by decreasing the taper angle θ (increasing 90 ° −θ). In particular, when the value of 90 ° −θ is 25 degrees or more and less than 50 degrees, the electromigration lifetime is remarkably increased. That is, the taper angle θ is greater than 40 degrees and equal to or less than 65 degrees.
　テーパー角θが上記範囲であることにより、第１溝部２４０の側面には、特にカバレッジ性のよい第１バリアメタル層２４２が形成され、より確実に配線材料のエレクトロマイグレーションを抑制することができたと考えられる。 When the taper angle θ is in the above range, the first barrier metal layer 242 having particularly good coverage is formed on the side surface of the first groove portion 240, and the electromigration of the wiring material can be more reliably suppressed. Conceivable.
　以上のように、第１の実施形態における第１傾斜部２４６と第１溝部２４０の側面とのなす角度（テーパ角θ）は、４０度以上６５度以下であることが好ましい。テーパー角θが４０度より小さい場合は、第１溝部２４０へのＣｕの埋め込み性が悪くなってしまう。一方、テーパー角θが上記範囲であることにより、第１溝部２４０の側面には、特にカバレッジ性のよい第１バリアメタル層２４２が形成される。これにより、より確実に配線材料のエレクトロマイグレーションを抑制することができる。 As described above, the angle (taper angle θ) formed by the first inclined portion 246 and the side surface of the first groove portion 240 in the first embodiment is preferably 40 degrees or more and 65 degrees or less. When the taper angle θ is smaller than 40 degrees, the Cu burying property in the first groove 240 is deteriorated. On the other hand, when the taper angle θ is in the above range, the first barrier metal layer 242 having particularly good coverage is formed on the side surface of the first groove portion 240. Thus, it is possible to suppress the electromigration of more reliably wiring material.
　なお、テーパー角θは、第１傾斜部２４６が第１溝部２４０の側面と接する部分で上記した角度の範囲内であればよい。 Note that the taper angle θ may be within the range of the angle described above at the portion where the first inclined portion 246 is in contact with the side surface of the first groove portion 240.
　また、第１傾斜部２４６は、第１傾斜部２４６が形成されていない第１溝部２４０の底面に対して、第１溝部２４０の側面と接する側から徐々に平行になっていてもよい。これにより、後述する第１バリアメタル層の形成工程において、第１バリアメタル層の粒子を第１傾斜部２４６の様々な方向から反跳させて、第１溝部２４０の側面に付着させることができる。 Further, the first inclined portion 246 may be gradually parallel to the bottom surface of the first groove portion 240 where the first inclined portion 246 is not formed from the side in contact with the side surface of the first groove portion 240. Thereby, in the formation process of the 1st barrier metal layer mentioned later, the particle | grains of a 1st barrier metal layer can be rebounded from the various directions of the 1st inclination part 246, and can be made to adhere to the side surface of the 1st groove part 240. FIG. .
　次に、図３～図５を用いて、第１の実施形態に係る半導体装置の製造方法を説明する。図３～図５は、第１の実施形態に係る半導体装置の製造方法を説明するための断面図である。第１の実施形態に係る半導体装置１０の製造方法は、以下の工程を備えている。まず、半導体基板（シリコン基板１００）上に第１絶縁層を形成する。次いで、第１絶縁層（第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０）に第１溝部２４０を形成するとともに、底面のうち、第１溝部２４０の側面と接する部分に第１溝部２４０の深さ方向に傾斜させるように第１傾斜部２４６を形成する（第１溝部形成工程）。次いで、第１溝部２４０の底面および側面に第１バリアメタル層２４２を形成する（第１バリアメタル層形成工程）。次いで、第１溝部２４０内に金属を埋め込むことにより、第１配線２５０を形成する。以下、詳細を説明する。 Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 3 to 5 are cross-sectional views for explaining the method for manufacturing the semiconductor device according to the first embodiment. The manufacturing method of the semiconductor device 10 according to the first embodiment includes the following steps. First, a first insulating layer is formed on a semiconductor substrate (silicon substrate 100). Next, the first groove portion 240 is formed in the first insulating layer (the first via forming insulating layer 220 and the first wiring forming insulating layer 230), and the first groove portion is formed in a portion of the bottom surface that contacts the side surface of the first groove portion 240. The first inclined portion 246 is formed to be inclined in the depth direction of 240 (first groove forming step). Next, the first barrier metal layer 242 is formed on the bottom and side surfaces of the first groove portion 240 (first barrier metal layer forming step). Next, the first wiring 250 is formed by embedding a metal in the first groove portion 240. Details will be described below.
　まず、半導体基板として、ＦＥＴなどの半導体素子（不図示）が形成されたシリコン基板１００を準備する。次いで、シリコン基板１００上に、第１ビア形成絶縁層２２０を形成する。このとき、第１ビア形成絶縁層２２０を、たとえば、ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）により成膜する。 First, a silicon substrate 100 on which a semiconductor element (not shown) such as an FET is formed is prepared as a semiconductor substrate. Next, a first via formation insulating layer 220 is formed on the silicon substrate 100. At this time, the first via forming insulating layer 220 is formed by, for example, CVD (Chemical Vapor Deposition).
　次いで、第１ビア形成絶縁層２２０上に、レジスト膜（不図示）を塗布する。次いで、露光および現像を行う。これにより、半導体素子に接続するコンタクトホール（不図示）を形成する部分に開口部を有するレジスト膜のパターンを形成する。次いで、ＲＩＥ（Ｒｅａｃｔｉｖｅ　Ｉｏｎ　Ｅｔｃｈｉｎｇ）により、レジスト膜の開口部における第１ビア形成絶縁層２２０を除去する。次いで、レジスト膜をアッシングする。次いで、第１ビア形成絶縁層２２０上およびコンタクトホール内に、バリアメタル層（不図示）、シード層（不図示）を順に成膜する。次いで、メッキ法によりコンタクトホールに金属を埋め込む。次いで、ＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）により、第１配線形成絶縁層２３０上を平坦化する。このようにして、第１ビア形成絶縁層２２０に、半導体素子と接続するコンタクト（不図示）を形成する。 Next, a resist film (not shown) is applied on the first via formation insulating layer 220. Next, exposure and development are performed. Thus, a resist film pattern having an opening is formed in a portion where a contact hole (not shown) connected to the semiconductor element is to be formed. Next, the first via formation insulating layer 220 in the opening of the resist film is removed by RIE (Reactive Ion Etching). Next, the resist film is ashed. Next, a barrier metal layer (not shown) and a seed layer (not shown) are sequentially formed on the first via formation insulating layer 220 and in the contact hole. Next, a metal is embedded in the contact hole by plating. Next, the first wiring formation insulating layer 230 is planarized by CMP (Chemical Mechanical Polishing). In this manner, a contact (not shown) connected to the semiconductor element is formed in the first via formation insulating layer 220.
　図３（ａ）のように、まず、第１配線形成絶縁層２３０を形成する。このとき、第１配線形成絶縁層２３０を、たとえば、ＣＶＤにより成膜する。次いで、第１配線形成絶縁層２３０上に、レジスト膜（不図示）を塗布する。次いで、露光および現像を行う。これにより、第１溝部２４０を形成する部分に開口部を有するレジスト膜のパターンを形成する。次いで、ＲＩＥにより、レジスト膜の開口部における第１配線形成絶縁層２３０を除去する。次いで、レジスト膜をアッシングする。以降、この工程を「第１溝部形成工程」とする。 As shown in FIG. 3 (a), first, a first wiring formed insulating layer 230. At this time, the first wiring formation insulating layer 230 is formed by, for example, CVD. Then, on the first wiring formation insulating layer 230 is coated with a resist film (not shown). Next, exposure and development are performed. Thus, a resist film pattern having an opening in a portion where the first groove 240 is formed is formed. Then, by RIE, to remove the first wiring forming insulating layer 230 in the opening portion of the resist film. Next, the resist film is ashed. Hereinafter, this process is referred to as “first groove forming process”.
　第１溝部形成工程において、ＲＩＥを行う際、シリコン基板１００側のバイアス電圧を調整することにより、第１溝部２４０の側面付近にプラズマが集中するように制御する。これにより、底面のうち、第１溝部２４０の側面と接する部分に第１溝部２４０の深さ方向に傾斜させるように第１傾斜部２４６を形成する。 In the first groove forming step, when performing RIE, the bias voltage on the silicon substrate 100 side is adjusted to control the plasma to concentrate near the side surface of the first groove 240. Thereby, the 1st inclination part 246 is formed in the part which touches the side surface of the 1st groove part 240 among the bottom surfaces so that it may incline in the depth direction of the 1st groove part 240. FIG.
　また、第１溝部形成工程において、ＣＦ３ＩまたはＣＦ４を含むガスを用いてエッチングを行う。これにより、容易に第１配線形成絶縁層２３０をエッチングして、第１溝部２４０を形成することができる。 In the first groove forming step, etching is performed using a gas containing CF 3 I or CF 4 . As a result, the first wiring portion insulating layer 230 can be easily etched to form the first groove portion 240.
　このとき、第１傾斜部２４６が形成されることによって、第１配線形成絶縁層２３０の底面よりも深く、先に形成した第１ビア形成絶縁層２２０まで到達する程度に深く形成されている。 At this time, the first inclined portion 246 is formed so that it is deeper than the bottom surface of the first wiring formation insulating layer 230 and deep enough to reach the first via formation insulating layer 220 formed earlier.
　なお、第１配線形成絶縁層２３０上に、ＣＭＰ工程で表面を保護するための保護層（不図示）を形成しておいてもよい。 A protective layer (not shown) for protecting the surface in the CMP process may be formed on the first wiring formation insulating layer 230.
　次いで、図３（ｂ）のように、第１溝部２４０の底面および側面に、第１バリアメタル層２４２を形成する。このとき、第１配線形成絶縁層２３０上にも成膜されるが、図３（ｂ）では省略している。ここで、第１バリアメタル層２４２を、たとえば、スパッタ法により成膜する。第１バリアメタル層２４２として、たとえば、ＴａＮをスパッタ成膜する。 Next, as shown in FIG. 3B, a first barrier metal layer 242 is formed on the bottom and side surfaces of the first groove 240. At this time, a film is also formed on the first wiring formation insulating layer 230, but is omitted in FIG. Here, the first barrier metal layer 242 is formed by sputtering, for example. As the first barrier metal layer 242, for example, TaN is formed by sputtering.
　ここで、第１傾斜部２４６を有していない場合では、スパッタのターゲットの面に対して垂直に設置される第１溝部２４０の側面には成膜されにくい。このような場合では、第１溝部２４０の側面に成膜される第１バリアメタル層２４２の厚さは薄くなる。一方、第１の実施形態では、このスパッタ成膜工程においても、第１傾斜部２４６で反跳して、第１溝部２４０の側面に付着する粒子が多くなる。したがって、この成膜する段階でも、第１溝部の側面に、第１バリアメタル層２４２をカバレッジ性良く形成することができる。 Here, when the first inclined portion 246 is not provided, it is difficult to form a film on the side surface of the first groove portion 240 installed perpendicular to the surface of the sputtering target. In such a case, the thickness of the first barrier metal layer 242 formed on the side surface of the first groove 240 is thin. On the other hand, in the first embodiment, also in this sputter film forming step, the number of particles that recoil at the first inclined portion 246 and adhere to the side surface of the first groove portion 240 increases. Therefore, the first barrier metal layer 242 can be formed on the side surface of the first groove portion with good coverage even at the stage of film formation.
　次いで、図４（ａ）のように、第１バリアメタル層２４２の形成工程において、第１溝部２４０の底面および側面に第１バリアメタル層２４２を成膜した後、下記のように、第１バリアメタル層２４２のエッチング工程を行う。なお、このエッチング工程は、逆スパッタ、ＲＩＥなどが用いられる。 Next, as shown in FIG. 4A, in the step of forming the first barrier metal layer 242, after forming the first barrier metal layer 242 on the bottom and side surfaces of the first groove 240, the first barrier metal layer 242 is formed as follows. An etching process of the barrier metal layer 242 is performed. In this etching process, reverse sputtering, RIE, or the like is used.
　まず、平行平板型のエッチング装置内のステージに、図３（ｂ）のシリコン基板１００を載置する。次いで、電極間に高電圧を印加し、プラズマを発生させ、ガスイオン５００をシリコン基板１００の表面に照射する。このガスイオン５００は、たとえばＡｒ＋イオンである。このとき、ガスイオン５００を、シリコン基板１００側に向かって衝突させる（図４（ａ）中の矢印）。次いで、第１バリアメタル層２４２をスパッタリングして、第１溝部２４０の底面における第１バリアメタル層２４２の一部の粒子を飛散させる（図４（ａ）中のＶ字矢印）。これにより、第１バリアメタル層２４２の一部の粒子を、第１溝部２４０の側面に付着させる。 First, the silicon substrate 100 of FIG. 3B is placed on the stage in the parallel plate type etching apparatus. Next, a high voltage is applied between the electrodes to generate plasma, and the surface of the silicon substrate 100 is irradiated with gas ions 500. The gas ions 500 are, for example, Ar + ions. At this time, the gas ions 500 are caused to collide toward the silicon substrate 100 side (arrows in FIG. 4A). Next, the first barrier metal layer 242 is sputtered to disperse some particles of the first barrier metal layer 242 on the bottom surface of the first groove portion 240 (V-shaped arrow in FIG. 4A). As a result, some particles of the first barrier metal layer 242 are attached to the side surface of the first groove portion 240.
　このようにして、第１バリアメタル層２４２をプラズマでエッチングすることにより、第１溝部２４０の底面における第１バリアメタル層２４２の一部を第１溝部２４０の側面に付着させる。 In this way, by etching the first barrier metal layer 242 with plasma, a part of the first barrier metal layer 242 on the bottom surface of the first groove 240 is attached to the side surface of the first groove 240.
　ここで、上記エッチング工程において、第１溝部２４０の側面における第１バリアメタル層２４２の厚さ（ｔ２）を、第１溝部２４０の底面における第１バリアメタル層２４２の厚さ（ｔ１）よりも厚くなるように形成する。すなわち、ｔ２＞ｔ１となるように、第１バリアメタル層２４２を形成する。エッチング工程において、たとえば、エッチング時間、印加電圧などを調整するにより、上記厚さとなるようにすることができる。 Here, in the etching step, the thickness (t 2 ) of the first barrier metal layer 242 on the side surface of the first groove 240 is set to the thickness (t 1 ) of the first barrier metal layer 242 on the bottom surface of the first groove 240. It is formed to be thicker. That is, the first barrier metal layer 242 is formed so that t 2 > t 1 . In the etching step, for example, the above thickness can be achieved by adjusting the etching time, the applied voltage, and the like.
　なお、図４（ａ）の後に、さらに、第１バリアメタル層２４２を形成してもよい。たとえば、先の第１バリアメタル層２４２がＴａＮであった場合には、上記エッチング工程の後に、さらにＴａを成膜してもよい。これにより、第１バリアメタル層２４２として、第１配線形成絶縁層２３０と接する側からＴａＮ／Ｔａの二層構造を形成してもよい。 Note that the first barrier metal layer 242 may be further formed after FIG. For example, when the first barrier metal layer 242 is TaN, Ta may be further formed after the etching step. Accordingly, a TaN / Ta double-layer structure may be formed from the side in contact with the first wiring formation insulating layer 230 as the first barrier metal layer 242.
　以上のように、第１バリアメタル層形成工程が行われる。 As described above, the first barrier metal layer forming step is performed.
　次いで、図５（ａ）のように、第１溝部２４０の底面および側面に、第１バリアメタル層２４２と接するように第１シード層２４４を形成する。第１シード層２４４として、たとえば、Ｃｕをスパッタ成膜する。第１シード層２４４の厚さは、たとえば、５ｎｍ以上５０ｎｍ以下である。 Next, as shown in FIG. 5A, a first seed layer 244 is formed on the bottom and side surfaces of the first groove 240 so as to be in contact with the first barrier metal layer 242. As the first seed layer 244, for example, Cu is formed by sputtering. The thickness of the first seed layer 244 is, for example, not less than 5 nm and not more than 50 nm.
　次いで、図５（ｂ）のように、第１シード層２４４を給電層として、電界メッキにより、第１溝部２４０の内部に金属を埋め込む。次いで、ＣＭＰにより、余分な金属を除去する。このようにして、第１配線２５０を形成する。 Next, as shown in FIG. 5B, the first seed layer 244 is used as a power feeding layer, and metal is embedded in the first groove portion 240 by electroplating. Next, excess metal is removed by CMP. In this way, the first wiring 250 is formed.
　以上により、第１の実施形態に係る半導体装置１０を得ることができる。 Thus, the semiconductor device 10 according to the first embodiment can be obtained.
　次に、図６を用いて、比較例と対比しながら、第１の実施形態の効果について説明する。図６（ａ）は、第１の実施形態に係る半導体装置１０の断面図である。図６（ａ）の第１の実施形態に係るサンプルと、第１傾斜部２４６を有していない点を除いて同様の構成を有する比較例のサンプルを用意した。図６（ｂ）は、図６（ａ）のＣ部について、第１傾斜部２４６を有していない比較例の断面図を示している。一方、図６（ｃ）は、図６（ａ）のＣ部について、第１の実施形態の断面図を示している。 Next, the effects of the first embodiment will be described using FIG. 6 in comparison with the comparative example. 6 (a) is a cross-sectional view of a semiconductor device 10 according to the first embodiment. A sample according to the first embodiment of FIG. 6A and a sample of a comparative example having the same configuration except that the first inclined portion 246 is not provided were prepared. FIG. 6B shows a cross-sectional view of a comparative example that does not have the first inclined portion 246 for the portion C of FIG. On the other hand, FIG.6 (c) has shown sectional drawing of 1st Embodiment about the C section of Fig.6 (a).
　図６（ａ）のように、Ｃ部は、第１配線形成絶縁層２３０に形成された第１溝部２４０の側面である。図６（ｂ）、図６（ｃ）は、たとえば、第１配線形成絶縁層２３０がポーラス膜であった場合などのように、第１溝部の側面が平滑な表面をしていない場合を示している。 As shown in FIG. 6A, the C part is a side surface of the first groove part 240 formed in the first wiring formation insulating layer 230. 6B and 6C show a case where the side surface of the first groove portion does not have a smooth surface, such as when the first wiring formation insulating layer 230 is a porous film, for example. ing.
　図６（ｂ）のように、第１傾斜部２４６を有していない比較例では、第１バリアメタル層２４２は、第１溝部２４０の側面の凹凸へカバレッジ良く成膜することができない。そのため、第１溝部２４０の側面の凹凸によって、第１バリアメタル層２４２で覆われていない部分が生じてしまう。このような場合、メッキによって第１配線２５０を形成すると、第１配線２５０が、直接、第１配線形成絶縁層２３０と接する部分が生じる。 As shown in FIG. 6B, in the comparative example that does not have the first inclined portion 246, the first barrier metal layer 242 cannot be formed on the unevenness on the side surface of the first groove portion 240 with good coverage. Therefore, a portion that is not covered with the first barrier metal layer 242 is generated due to the unevenness of the side surface of the first groove portion 240. In such a case, when the first wiring 250 is formed by plating, a portion where the first wiring 250 directly contacts the first wiring formation insulating layer 230 is generated.
　第１バリアメタル層２４２を介さず、第１配線形成絶縁層２３０と直接に接した第１配線２５０は、第１配線形成絶縁層２３０との密着性が弱い。このため、第１配線２５０にバイアスを印加した際に生じる電子流によって、第１配線２５０が、直接、第１配線形成絶縁層２３０と接する部分からエレクトロマイグレーションが発生してしまう。 The first wiring 250 that is in direct contact with the first wiring formation insulating layer 230 without using the first barrier metal layer 242 has low adhesion to the first wiring formation insulating layer 230. For this reason, electromigration occurs from the portion where the first wiring 250 is in direct contact with the first wiring formation insulating layer 230 due to the electron flow generated when a bias is applied to the first wiring 250.
　また、高温高湿環境下において、第１配線形成絶縁層２３０、または、その上下層との界面から水分が伝搬してくる。その場合においても、伝搬してきた水分によって、第１配線２５０の材料のエレクトロマイグレーションが起きやすくなってしまう。 In a high temperature and high humidity environment, moisture propagates from the first wiring formation insulating layer 230 or the interface with the upper and lower layers. Even in such a case, the electromigration of the material of the first wiring 250 easily occurs due to the propagated moisture.
　以上のように、比較例では、第１配線の材料によるエレクトロマイグレーションを抑制することができない可能性があった。 As described above, in the comparative example, there is a possibility that electromigration due to the material of the first wiring cannot be suppressed.
　一方、図６（ｂ）のように、第１の実施形態では、第１溝部２４０の側面には、第１バリアメタル層２４２がカバレッジ性良く形成されている。図６（ａ）のように、第１の実施形態では、第１溝部２４０は、底面のうち、第１溝部２４０の側面と接する部分に第１溝部２４０の深さ方向に傾斜している第１傾斜部２４６を有している。上述したように、第１バリアメタル層形成工程において、第１傾斜部２４６で反跳して、第１溝部２４０の側面に付着する粒子が多くなる。このようにして、第１溝部２４０の側面には、第１バリアメタル層２４２をカバレッジ性良く形成することができる。 On the other hand, as shown in FIG. 6B, in the first embodiment, the first barrier metal layer 242 is formed on the side surface of the first groove 240 with good coverage. As shown in FIG. 6A, in the first embodiment, the first groove portion 240 is inclined in the depth direction of the first groove portion 240 at the portion of the bottom surface that contacts the side surface of the first groove portion 240. One inclined portion 246 is provided. As described above, in the first barrier metal layer forming step, the number of particles that recoil at the first inclined portion 246 and adhere to the side surface of the first groove portion 240 increases. In this way, the first barrier metal layer 242 can be formed on the side surface of the first groove portion 240 with good coverage.
　これにより、第１溝部内に設けられた第１配線は、第１バリアメタル層によって周囲が囲まれている。また、第１配線２５０が、直接、第１配線形成絶縁層２３０と接する部分は生じていない。 Thereby, the first wiring provided in the first groove is surrounded by the first barrier metal layer. Further, there is no portion where the first wiring 250 is in direct contact with the first wiring formation insulating layer 230.
　このように、第１配線２５０は、第１バリアメタル層２４２を介して、第１配線形成絶縁層２３０と強く密着されている。これにより、第１配線２５０にバイアスを印加した際に生じる電子流によって、第１配線２５０の材料によるエレクトロマイグレーションが起こることがない。 As described above, the first wiring 250 is in close contact with the first wiring formation insulating layer 230 via the first barrier metal layer 242. Thereby, electromigration due to the material of the first wiring 250 does not occur due to an electron flow generated when a bias is applied to the first wiring 250.
　また、高温高湿環境下においても、第１バリアメタル層によって周囲が保護されている。これにより、第１配線形成絶縁層２３０等を伝搬してきた水分によって、第１配線２５０のエレクトロマイグレーション劣化が加速されることがない。 Also, the surroundings are protected by the first barrier metal layer even in a high temperature and high humidity environment. Thereby, the electromigration deterioration of the first wiring 250 is not accelerated by the moisture that has propagated through the first wiring formation insulating layer 230 and the like.
　したがって、第１の実施形態によれば、微細な多層配線における配線材料のエレクトロマイグレーションを抑制することができる。 Therefore, according to the first embodiment, the electromigration of the wiring material in the fine multilayer wiring can be suppressed.
　以上、第１の実施形態においては、シングルダマシン法によって、コンタクトおよび第１溝部２４０を形成する場合を説明したが、デュアルダマシン法であっても構わない。 As described above, in the first embodiment, the case where the contact and the first groove 240 are formed by the single damascene method has been described. However, the dual damascene method may be used.
　（第２の実施形態）
　図７は、第２の実施形態に係る半導体装置の構成を示す図である。第２の実施形態は、以下の点を除いて、第１の実施形態と同様である。第１配線形成絶縁層２３０上には、第２絶縁層（第２ビア形成絶縁層３２０および第２配線形成絶縁層３３０）が設けられている。また、第２絶縁層のうち、第２ビア形成絶縁層３２０には、接続孔３２２が設けられている。また、底面と側面とを有する第２溝部３４０は、第２絶縁層のうち、第２配線形成絶縁層３３０に形成されており、接続孔３２２と接続している。また、第２バリアメタル層３４２は、接続孔３２２および第２溝部３４０の底面および側面と接するように設けられている。また、第２配線３５０は、接続孔３２２および第２溝部３４０の内部に設けられており、接続孔３２２を介して第１配線２５０と接続している。このとき、第２溝部３４０は、底面のうち、第２溝部３４０の側面と接する部分に第２溝部３４０の深さ方向に傾斜している第２傾斜部３４６を有している。さらに、第２傾斜部３４６は、接続孔３２２の上面の一部を含んでいる。以下、詳細を説明する。 (Second Embodiment)
FIG. 7 is a diagram illustrating a configuration of a semiconductor device according to the second embodiment. The second embodiment is the same as the first embodiment except for the following points. A second insulating layer (second via forming insulating layer 320 and second wiring forming insulating layer 330) is provided on the first wiring forming insulating layer 230. Further, in the second insulating layer, the second via forming insulating layer 320 is provided with a connection hole 322. The second groove 340 having a bottom surface and a side surface is formed in the second wiring formation insulating layer 330 in the second insulating layer and is connected to the connection hole 322. The second barrier metal layer 342 is provided so as to be in contact with the bottom surface and the side surface of the connection hole 322 and the second groove portion 340. The second wiring 350 is provided inside the connection hole 322 and the second groove portion 340 and is connected to the first wiring 250 through the connection hole 322. At this time, the second groove portion 340 has a second inclined portion 346 that is inclined in the depth direction of the second groove portion 340 at a portion in contact with the side surface of the second groove portion 340 in the bottom surface. Further, the second inclined portion 346 includes a part of the upper surface of the connection hole 322. Details will be described below.
　以下で説明する、第２絶縁層（第２ビア形成絶縁層３２０並びに第２配線形成絶縁層３３０）、第２バリアメタル層３４２および第２配線３５０は、それぞれ、第１絶縁層（第１ビア形成絶縁層２２０並びに第１配線形成絶縁層２３０）、第１バリアメタル層２４２および第１配線２５０と同一の材料により形成することができる。これにより、回路動作時の電流によりＣｕ原子が移動して、断線や抵抗増加に至る事象の発生を抑制することができる。ここでいう「事象の発生を抑制する」とは、ある一定の抵抗増加等までに至る時間が長くなることを意味する。すなわち、半導体装置１０の寿命が延びることを意味する。 The second insulating layer (the second via forming insulating layer 320 and the second wiring forming insulating layer 330), the second barrier metal layer 342, and the second wiring 350, which will be described below, are respectively the first insulating layer (the first via layer). The formation insulating layer 220 and the first wiring formation insulating layer 230), the first barrier metal layer 242, and the first wiring 250 can be formed of the same material. Thereby, it is possible to suppress the occurrence of an event that causes Cu atoms to move due to a current during circuit operation, resulting in disconnection or an increase in resistance. Here, “suppressing the occurrence of an event” means that the time until a certain increase in resistance is increased. That is, the life of the semiconductor device 10 is extended.
　ただし、第２絶縁層（第２ビア形成絶縁層３２０並びに第２配線形成絶縁層３３０）、第２バリアメタル層３４２および第２配線３５０は、上記した構成に限られるものではない。逆に、第２絶縁層（第２ビア形成絶縁層３２０並びに第２配線形成絶縁層３３０）、第２バリアメタル層３４２および第２配線３５０は、それぞれ、第１絶縁層（第１ビア形成絶縁層２２０並びに第１配線形成絶縁層２３０）、第１バリアメタル層２４２および第１配線２５０と異なる材料で形成しても構わない。 However, the second insulating layer (the second via forming insulating layer 320 and the second wiring forming insulating layer 330), the second barrier metal layer 342, and the second wiring 350 are not limited to the above-described configuration. Conversely, the second insulating layer (the second via forming insulating layer 320 and the second wiring forming insulating layer 330), the second barrier metal layer 342, and the second wiring 350 are each composed of the first insulating layer (first via forming insulating layer). The layer 220 and the first wiring formation insulating layer 230), the first barrier metal layer 242, and the first wiring 250 may be formed of a different material.
　図７のように、第１配線形成絶縁層２３０上には、エッチングストッパー層３１０が設けられている。これにより、後述する接続孔３２２を開口する位置がずれた場合において、エッチングストッパー層３１０によってエッチングを止めることができる。エッチングストッパー層３１０は、ＲＩＥにおいてエッチング選択性を有する膜で構成されている。エッチングストッパー層３１０としては、たとえば、ＳｉＮである。 As shown in FIG. 7, an etching stopper layer 310 is provided on the first wiring formation insulating layer 230. Thus, the etching can be stopped by the etching stopper layer 310 when the position for opening the connection hole 322 described later is shifted. Etching stopper layer 310 is composed of a layer having an etch selectivity in RIE. The etching stopper layer 310 is, for example, SiN.
　さらに、第１配線形成絶縁層２３０上には、第２絶縁層（第２ビア形成絶縁層３２０および第２配線形成絶縁層３３０）が設けられている。第２絶縁層は、たとえば、第２ビア形成絶縁層３２０および第２配線形成絶縁層３３０を有しており、第１配線形成絶縁層２３０上にこの順で形成されている。 Furthermore, a second insulating layer (second via forming insulating layer 320 and second wiring forming insulating layer 330) is provided on the first wiring forming insulating layer 230. The second insulating layer includes, for example, a second via forming insulating layer 320 and a second wiring forming insulating layer 330, and is formed on the first wiring forming insulating layer 230 in this order.
　ここで、第２ビア形成絶縁層３２０および第２配線形成絶縁層３３０は、同一の材料から形成されていてもよい。このとき、第２ビア形成絶縁層３２０と第２配線形成絶縁層３３０との間に界面が形成されていなくてもよい。または、第２ビア形成絶縁層３２０および第２配線形成絶縁層３３０は、異なる材料から形成されていてもよい。さらに、第２ビア形成絶縁層３２０および第２配線形成絶縁層３３０は、それぞれ、複数層から形成されていてもよい。 Here, the second via forming insulating layer 320 and the second wiring forming insulating layer 330 may be formed of the same material. At this time, an interface may not be formed between the second via formation insulating layer 320 and the second wiring formation insulating layer 330. Alternatively, the second via forming insulating layer 320 and the second wiring forming insulating layer 330 may be formed from different materials. Further, each of the second via formation insulating layer 320 and the second wiring formation insulating layer 330 may be formed of a plurality of layers.
　また、第２絶縁層のうち、第２ビア形成絶縁層３２０には、接続孔３２２が設けられている。ここで、接続孔３２２は、第２絶縁層のうち、第２ビア形成絶縁層３２０に設けられた孔のことであり、内部に金属を埋め込むことにより、第１配線２５０と第２配線３５０とを接続している。 Of the second insulating layer, the second via forming insulating layer 320 is provided with a connection hole 322. Here, the connection hole 322 is a hole provided in the second via forming insulating layer 320 in the second insulating layer, and the first wiring 250 and the second wiring 350 are embedded by embedding metal therein. Is connected.
　また、第２溝部３４０は、第２絶縁層のうち、第２配線形成絶縁層３３０に形成されており、接続孔３２２と接続している。後述するように、この第２溝部３４０は、第１溝部２４０と同様の形状を有している。 Further, the second groove 340 is formed in the second wiring formation insulating layer 330 in the second insulating layer, and is connected to the connection hole 322. As will be described later, the second groove 340 has the same shape as the first groove 240.
　また、第２バリアメタル層３４２は、接続孔３２２および第２溝部３４０の底面および側面と接するように設けられている。ここで、第２バリアメタル層３４２は、第１バリアメタル層２４２と同様の機能を有している。 The second barrier metal layer 342 is provided so as to be in contact with the bottom surface and the side surface of the connection hole 322 and the second groove 340. Here, the second barrier metal layer 342 has the same function as the first barrier metal layer 242.
　また、第２配線３５０は、接続孔３２２および第２溝部３４０の内部に設けられており、接続孔３２２を介して第１配線２５０と接続している。 The second wiring 350 is provided inside the connection hole 322 and the second groove portion 340 and is connected to the first wiring 250 through the connection hole 322.
　このとき、第２溝部３４０は、底面のうち、第２溝部３４０の側面と接する部分に第２溝部３４０の深さ方向に傾斜している第２傾斜部３４６を有している。第２溝部３４０は、第１溝部２４０と同様の形状とすることができる。ただし、第２傾斜部３４６は、第２溝部３４０の側面の高さに応じて、第２溝部３４０の側面からの距離、テーパー角等を調整することができる。 At this time, the second groove portion 340 has a second inclined portion 346 that is inclined in the depth direction of the second groove portion 340 in a portion of the bottom surface in contact with the side surface of the second groove portion 340. The second groove 340 may be the same shape as the first groove 240. However, the second inclined portion 346 can adjust the distance from the side surface of the second groove portion 340, the taper angle, and the like according to the height of the side surface of the second groove portion 340.
　さらに、第２傾斜部３４６は、接続孔３２２の上面の一部を含んでいる。すなわち、接続孔３２２の上面は、第２溝部３４０の側面と接する底面と同じ第２傾斜部３４６の傾斜方向に傾斜している。これにより、接続孔３２２の開口の上面は、第１配線２５０と接する面よりも広くなっている。したがって、接続孔３２２の上部における電流密度を低下させることができる。すなわち、その部分のエレクトロマイグレーション耐性が向上させることができる。 Furthermore, the second inclined portion 346 includes a portion of the upper surface of the connection hole 322. In other words, the upper surface of the connection hole 322 is inclined in the same inclination direction of the second inclined portion 346 as the bottom surface in contact with the side surface of the second groove portion 340. Thereby, the upper surface of the opening of the connection hole 322 is wider than the surface in contact with the first wiring 250. Therefore, the current density in the upper part of the connection hole 322 can be reduced. That is, it is possible to electro-migration resistance of that portion is improved.
　ここで、後述するように、第１の実施形態と同様に、第２バリアメタル層３４２を成膜した後に、第２バリアメタル層３４２をプラズマでエッチングしてもよい。この工程により、第２溝部３４０の側面における第２バリアメタル層３４２は、第２溝部３４０の底面における第２バリアメタル層３４２の厚さよりも厚く形成されている。これにより、第２溝部３４０の側面からのエレクトロマイグレーションを顕著に抑制することができる。 Here, as described later, after the second barrier metal layer 342 is formed, the second barrier metal layer 342 may be etched by plasma, as in the first embodiment. By this step, the second barrier metal layer 342 on the side surface of the second groove 340 is formed thicker than the thickness of the second barrier metal layer 342 on the bottom surface of the second groove 340. Thereby, the electromigration from the side surface of the 2nd groove part 340 can be suppressed notably.
　次に、図８、図９を用いて、第２の実施形態に係る半導体装置の製造方法を説明する。図８、図９は、第２の実施形態に係る半導体装置の製造方法を説明するための断面図である。第２の実施形態の製造方法は、第２ビア形成絶縁層３２０に接続孔３２２を開口する点を除いて、第１の実施形態の製造方法と同様である。以下、詳細を説明する。 Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. 8 and 9 are cross-sectional views for explaining the semiconductor device manufacturing method according to the second embodiment. The manufacturing method of the second embodiment is the same as the manufacturing method of the first embodiment except that the connection hole 322 is opened in the second via forming insulating layer 320. Details will be described below.
　図８（ａ）のように、第１の実施形態と同様の半導体装置１０が形成されている。まず、ＣＭＰ処理された第１配線形成絶縁層２３０および第１配線２５０上に、エッチングストッパー層３１０を形成する。エッチングストッパー層３１０を、たとえば、ＣＶＤにより成膜する。 As shown in FIG. 8A, a semiconductor device 10 similar to that of the first embodiment is formed. First, the etching stopper layer 310 is formed on the first wiring formation insulating layer 230 and the first wiring 250 that have been subjected to the CMP process. The etching stopper layer 310 is formed by, for example, CVD.
　次いで、エッチングストッパー層３１０上に、第２ビア形成絶縁層３２０および第２配線形成絶縁層３３０を順に積層する。このとき、第２ビア形成絶縁層３２０と第２配線形成絶縁層３３０は、異なる材料からなる層であってもよい。 Next, a second via forming insulating layer 320 and a second wiring forming insulating layer 330 are sequentially stacked on the etching stopper layer 310. At this time, the second via forming insulating layer 320 and the second wiring forming insulating layer 330 may be layers made of different materials.
　次いで、図８（ｂ）のように、まず、第２配線形成絶縁層３３０上に、レジスト膜（不図示）を塗布する。次いで、露光および現像を行う。これにより、第２溝部３４０を形成する部分に開口部を有するレジスト膜のパターンを形成する。次いで、ＲＩＥにより、レジスト膜の開口部における第２配線形成絶縁層３３０を除去する。 Next, as shown in FIG. 8B, first, a resist film (not shown) is applied on the second wiring formation insulating layer 330. Next, exposure and development are performed. Thus, a resist film pattern having an opening in a portion where the second groove 340 is to be formed is formed. Then, by RIE, to remove the second wiring forming insulating layer 330 in the opening portion of the resist film.
　このとき、第１溝部形成工程と同様にして、ＲＩＥを行う際、シリコン基板１００側のバイアス電圧を調整することにより、第２溝部３４０の側面付近にプラズマが集中するように制御する。これにより、底面のうち、第２溝部３４０の側面と接する部分に第２溝部３４０の深さ方向に傾斜させるように第２傾斜部３４６を形成する。 At this time, similarly to the first groove portion forming step, when performing RIE, the bias voltage on the silicon substrate 100 side is adjusted so that the plasma is concentrated near the side surface of the second groove portion 340. Accordingly, the second inclined portion 346 is formed so as to be inclined in the depth direction of the second groove portion 340 at a portion of the bottom surface that contacts the side surface of the second groove portion 340.
　次いで、レジスト膜をアッシングする。このようにして、第２傾斜部３４６を有する第２溝部３４０を形成する。 Next, the resist film is ashed. In this manner, a second groove 340 having a second inclined portion 346.
　次いで、第２配線形成絶縁層３３０および第２溝部３４０上に、レジスト膜（不図示）を塗布する。次いで、露光および現像を行う。これにより、接続孔３２２を形成する部分に開口部を有するレジスト膜のパターンを形成する。ここでは、接続孔３２２は、平面視で第２傾斜部３４６と重なる位置に形成するように、レジスト膜のパターンを形成する。次いで、ＲＩＥにより、レジスト膜の開口部における第２ビア形成絶縁層３２０を除去する。次いで、レジスト膜をアッシングする。このようにして、接続孔３２２を形成する。 Next, a resist film (not shown) is applied on the second wiring formation insulating layer 330 and the second groove 340. Next, exposure and development are performed. As a result, a resist film pattern having an opening at a portion where the connection hole 322 is to be formed is formed. Here, the pattern of the resist film is formed so that the connection hole 322 is formed at a position overlapping the second inclined portion 346 in plan view. Then, by RIE, to remove the second via formation insulating layer 320 at the opening of the resist film. Next, the resist film is ashed. In this way, the connection hole 322 is formed.
　次いで、図９（ａ）のように、第２溝部３４０および接続孔３２２の底面および側面に、第２バリアメタル層３４２を形成する。このとき、第１配線形成絶縁層２３０上にも成膜されるが、図９（ａ）では省略している。ここで、第１バリアメタル層２４２を、たとえば、スパッタ法により成膜する。 Next, as shown in FIG. 9A, the second barrier metal layer 342 is formed on the bottom and side surfaces of the second groove 340 and the connection hole 322. At this time, a film is also formed on the first wiring formation insulating layer 230, but is omitted in FIG. Here, the first barrier metal layer 242, for example, is deposited by sputtering.
　次いで、図９（ａ）のように、第２バリアメタル層３４２の形成工程において、第２溝部３４０の底面および側面に第２バリアメタル層３４２を成膜した後、第１の実施形態と同様に、第２バリアメタル層３４２のエッチング工程を行う。これにより、第２バリアメタル層３４２の一部の粒子を、第２溝部３４０の側面に付着させる。 Next, as shown in FIG. 9A, in the step of forming the second barrier metal layer 342, after the second barrier metal layer 342 is formed on the bottom and side surfaces of the second groove 340, the same as in the first embodiment. In addition, an etching process of the second barrier metal layer 342 is performed. Thereby, some particles of the second barrier metal layer 342 are attached to the side surface of the second groove 340.
　このとき、接続孔３２２の上面の一部は、第２傾斜部３４６に形成されている。このため、接続孔３２２の上面は、第２溝部３４０の側面に向けて広くなっている。これにより、接続孔３２２の側面から飛散した第２バリアメタル層３４２の一部の粒子を、第２溝部３４０の側面に付着させることができる。 At this time, a part of the upper surface of the connection hole 322 is formed in the second inclined portion 346. For this reason, the upper surface of the connection hole 322 is widened toward the side surface of the second groove portion 340. Accordingly, some particles of the second barrier metal layer 342 scattered from the side surface of the connection hole 322 can be attached to the side surface of the second groove portion 340.
　次いで、図９（ｂ）のように、第２溝部３４０および接続孔３２２の底面および側面に、第２バリアメタル層３４２と接するように第２シード層（不図示）を形成する。次いで、第２シード層３４４を給電層として、電界メッキにより、第２溝部３４０および接続孔３２２の内部に金属を埋め込む。次いで、ＣＭＰにより、余分な金属を除去する。このようにして、第１配線２５０を形成する。 Next, as shown in FIG. 9B, a second seed layer (not shown) is formed on the bottom and side surfaces of the second groove 340 and the connection hole 322 so as to be in contact with the second barrier metal layer 342. Next, using the second seed layer 344 as a power feeding layer, metal is embedded in the second groove 340 and the connection hole 322 by electroplating. Next, excess metal is removed by CMP. In this way, the first wiring 250 is formed.
　以上により、第１の実施形態に係る半導体装置１０を得ることができる。 Thus, the semiconductor device 10 according to the first embodiment can be obtained.
　次に、第２の実施形態の効果について説明する。第２の実施形態によれば、第１の実施形態と同様の効果を得ることができる。さらに、第２の実施形態では、第２傾斜部３４６は、接続孔３２２の上面の一部を含んでいる。これにより、接続孔３２２の開口の上面は、第１配線２５０と接する面よりも広くなっている。したがって、接続孔３２２の上部における電流密度を低下させることができる。すなわち、その部分のエレクトロマイグレーション耐性を向上させることができる。 Next, the effect of the second embodiment will be described. According to the second embodiment, it is possible to achieve the same effects as in the first embodiment. Furthermore, in the second embodiment, the second inclined portion 346 includes a part of the upper surface of the connection hole 322. Thereby, the upper surface of the opening of the connection hole 322 is wider than the surface in contact with the first wiring 250. Therefore, it is possible to reduce the current density in the upper portion of the connection hole 322. That is, it is possible to improve the electromigration resistance of the part.
　これにより、第１溝部の底面および側面に第１バリアメタル層を形成するとき、上記のように、接続孔３２２の上面は、第２溝部３４０の側面に向けて広くなっている。これにより、接続孔３２２の側面から飛散した第２バリアメタル層３４２の一部の粒子を、第２溝部３４０の側面に付着させることができる。したがって、第２の実施形態によれば、第１の実施形態よりも、さらにエレクトロマイグレーションを抑制することができる。 Thus, when the first barrier metal layer is formed on the bottom surface and the side surface of the first groove portion, the upper surface of the connection hole 322 is widened toward the side surface of the second groove portion 340 as described above. Accordingly, some particles of the second barrier metal layer 342 scattered from the side surface of the connection hole 322 can be attached to the side surface of the second groove portion 340. Therefore, according to the second embodiment, electromigration can be further suppressed as compared with the first embodiment.
　以上、第２の実施形態において、第２溝部３４０において第２傾斜部３４６を有する場合を説明したが、さらに複数の多層配線構造においても適用することができる。 As described above, in the second embodiment, the case where the second groove portion 340 includes the second inclined portion 346 has been described. However, the second embodiment can be applied to a plurality of multilayer wiring structures.
　以上、第１、第２の実施形態において、第１ビア形成絶縁層２２０および第１配線形成絶縁層２３０としては、たとえば、ポーラスＳｉＯ膜、ポーラスＳｉＯＣ膜などである場合を説明したが、有機ポリマー系の膜や、ポーラスでない（空孔をもたない）ＳｉＯＣ膜であっても構わない。成膜方法に関しても、プラズマＣＶＤ法に限らず、ＣＶＤ法、スピンコートなどの塗布法等によって形成することができる。 As described above, in the first and second embodiments, the case where the first via formation insulating layer 220 and the first wiring formation insulating layer 230 are, for example, a porous SiO film or a porous SiOC film has been described. A non-porous (non-porous) SiOC film may be used. The film forming method is not limited to the plasma CVD method, and can be formed by a CVD method, a coating method such as spin coating, or the like.
　以上、図面を参照して本発明の実施形態について述べたが、これらは本発明の例示であり、上記以外の様々な構成を採用することもできる。 As described above, the embodiments of the present invention have been described with reference to the drawings. However, these are exemplifications of the present invention, and various configurations other than the above can be adopted.
　この出願は、２０１１年３月３１日に出願された日本出願特願２０１１－０７８９６０号を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2011-078960 filed on March 31, 2011, the entire disclosure of which is incorporated herein.

Claims (16)

  1. 　半導体基板と、
    　前記半導体基板上に形成された第１絶縁層と、
    　前記第１絶縁層に形成され、底面と側面を有する第１溝部と、
    　前記第１溝部の前記底面および前記側面と接するように設けられた第１バリアメタル層と、
    　前記第１溝部の内部に設けられた第１配線と、
    を備え、
    　前記第１溝部は、前記底面のうち、前記第１溝部の前記側面と接する部分に前記第１溝部の深さ方向に傾斜している第１傾斜部を有する半導体装置。     A semiconductor substrate;
    A first insulating layer formed on the semiconductor substrate;
    A first groove formed in the first insulating layer and having a bottom surface and a side surface;
    A first barrier metal layer provided in contact with the bottom surface and the side surface of the first groove portion;
    A first wiring provided inside the first groove,
    With
    The first groove portion includes a first inclined portion that is inclined in a depth direction of the first groove portion in a portion of the bottom surface that is in contact with the side surface of the first groove portion.
  2. 　請求項１に記載の半導体装置において、
    　前記第１溝部の前記側面からの前記第１傾斜部の長さは、前記第１配線の厚さの１／２倍以上である半導体装置。     The semiconductor device according to claim 1,
    The length of the said 1st inclination part from the said side surface of a said 1st groove part is a semiconductor device which is 1/2 times or more of the thickness of the said 1st wiring.
  3. 　請求項１または２に記載の半導体装置において、
    　前記第１溝部の前記側面における前記第１バリアメタル層の厚さは、前記第１溝部の前記底面における前記第１バリアメタル層の厚さよりも厚い半導体装置。     The semiconductor device according to claim 1 or 2,
    The thickness of the first barrier metal layer on the side surface of the first groove is greater than the thickness of the first barrier metal layer on the bottom surface of the first groove.
  4. 　請求項１～３のいずれか一項に記載の半導体装置において、
    　前記第１傾斜部と前記第１溝部の前記側面とのなす角度は、４０度以上６５度以下である半導体装置。     The semiconductor device according to any one of claims 1 to 3,
    An angle formed by the first inclined portion and the side surface of the first groove is a semiconductor device that is not less than 40 degrees and not more than 65 degrees.
  5. 　請求項１～４のいずれか一項に記載の半導体装置において、
    　前記第１溝部の前記側面は、前記第１傾斜部が形成されていない領域の前記第１溝部の前記底面に対して垂直である半導体装置。     The semiconductor device according to any one of claims 1 to 4,
    The semiconductor device, wherein the side surface of the first groove portion is perpendicular to the bottom surface of the first groove portion in a region where the first inclined portion is not formed.
  6. 　請求項１～５のいずれか一項に記載の半導体装置において、
    　前記第１傾斜部は、当該第１傾斜部が形成されていない前記第１溝部の前記底面に対して、前記第１溝部の側面と接する側から徐々に平行になっている半導体装置。     The semiconductor device according to any one of claims 1 to 5,
    The semiconductor device in which the first inclined portion is gradually parallel to the bottom surface of the first groove portion where the first inclined portion is not formed from the side in contact with the side surface of the first groove portion.
  7. 　請求項１～６のいずれか一項に記載の半導体装置において、
    　前記第１絶縁層の比誘電率は、２．６以下である半導体装置。     The semiconductor device according to any one of claims 1 to 6,
    A semiconductor device in which the first dielectric layer has a relative dielectric constant of 2.6 or less.
  8. 　請求項１～７のいずれか一項に記載の半導体装置において、
    　前記第１絶縁層は、ポーラス膜である半導体装置。     The semiconductor device according to any one of claims 1 to 7,
    The semiconductor device wherein the first insulating layer is a porous film.
  9. 　請求項１～８のいずれか一項に記載の半導体装置において、
    　前記第１配線は、Ｃｕを主材料として含む半導体装置。     The semiconductor device according to any one of claims 1 to 8,
    The first wiring is a semiconductor device containing Cu as a main material.
  10. 　請求項１～９のいずれか一項に記載の半導体装置において、
    　前記第１バリアメタル層は、Ｔａ、ＴｉまたはＲｕを含む半導体装置。     The semiconductor device according to any one of claims 1 to 9,
    The first barrier metal layer is a semiconductor device containing Ta, Ti, or Ru.
  11. 　請求項１～１０のいずれか一項に記載の半導体装置において、
    　前記第１絶縁層上に設けられた第２絶縁層と、
    　前記第２絶縁層に設けられた接続孔と、
    　前記第２絶縁層に形成され、前記接続孔と接続するとともに、底面と側面とを有する第２溝部と、
    　前記接続孔および前記第２溝部の前記底面および前記側面と接するように設けられた第２バリアメタル層と、
    　前記接続孔および前記第２溝部の内部に設けられ、前記接続孔を介して前記第１配線と接続する第２配線と、
    をさらに備え、
    　前記第２溝部は、前記底面のうち、前記第２溝部の前記側面と接する部分に前記第２溝部の深さ方向に傾斜している第２傾斜部を有し、
    　前記第２傾斜部は、前記接続孔の上面の一部を含む半導体装置。     The semiconductor device according to any one of claims 1 to 10,
    A second insulating layer provided on the first insulating layer;
    A connection hole provided in the second insulating layer;
    A second groove formed in the second insulating layer, connected to the connection hole, and having a bottom surface and a side surface;
    A second barrier metal layer provided so as to be in contact with the bottom surface and the side surface of the connection hole and the second groove portion;
    A second wiring provided inside the connection hole and the second groove, and connected to the first wiring through the connection hole;
    Further comprising
    The second groove portion includes a second inclined portion that is inclined in a depth direction of the second groove portion in a portion of the bottom surface that is in contact with the side surface of the second groove portion.
    The second inclined portion is a semiconductor device including a part of an upper surface of the connection hole.
  12. 　請求項１１に記載の半導体装置において、
    　前記第２溝部の前記側面における前記第２バリアメタル層の厚さは、前記第２溝部の前記底面における前記第２バリアメタル層の厚さよりも厚い半導体装置。     The semiconductor device according to claim 11,
    The thickness of the said 2nd barrier metal layer in the said side surface of the said 2nd groove part is a semiconductor device thicker than the thickness of the said 2nd barrier metal layer in the said bottom face of the said 2nd groove part.
  13. 　請求項１１または１２に記載の半導体装置において、
    　前記第２絶縁層、前記第２バリアメタル層および前記第２配線は、それぞれ、前記第１絶縁層前記第１バリアメタル層および前記第１配線と同一の材料により形成されている半導体装置。     The semiconductor device according to claim 11 or 12,
    The semiconductor device in which the second insulating layer, the second barrier metal layer, and the second wiring are formed of the same material as the first insulating layer, the first barrier metal layer, and the first wiring, respectively.
  14. 　半導体基板上に第１絶縁層を形成する工程と、
    　前記第１絶縁層に底面と側面を有する第１溝部を形成するとともに、前記底面のうち、前記第１溝部の前記側面と接する部分に前記第１溝部の深さ方向に傾斜させるように第１傾斜部を形成する第１溝部形成工程と、
    　前記第１溝部の前記底面および前記側面に第１バリアメタル層を形成する第１バリアメタル層形成工程と、
    　前記第１溝部内に金属を埋め込むことにより、第１配線を形成する工程と、
    を備える半導体装置の製造方法。     Forming a first insulating layer on the semiconductor substrate;
    A first groove having a bottom surface and a side surface is formed in the first insulating layer, and a first portion of the bottom surface that is in contact with the side surface of the first groove portion is inclined in a depth direction of the first groove portion. A first groove forming step for forming an inclined portion;
    A first barrier metal layer forming step of forming a first barrier metal layer on the bottom surface and the side surface of the first groove portion;
    Forming a first wiring by embedding a metal in the first groove;
    A method for manufacturing a semiconductor device comprising:
  15. 　請求項１４に記載の半導体装置の製造方法において、
    　前記第１バリアメタル層形成工程において、前記第１溝部の底面および側面に前記第１バリアメタル層を成膜した後、前記第１バリアメタル層をプラズマでエッチングすることにより、前記第１溝部の前記底面における前記第１バリアメタル層の一部を前記第１溝部の前記側面に付着させるエッチング工程を含む半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 14,
    In the first barrier metal layer forming step, after forming the first barrier metal layer on the bottom and side surfaces of the first groove, the first barrier metal layer is etched with plasma, thereby A method of manufacturing a semiconductor device, comprising: an etching step of attaching a part of the first barrier metal layer on the bottom surface to the side surface of the first groove portion.
  16. 　請求項１４または１５に記載の半導体装置の製造方法において、
    　前記第１溝部形成工程において、ＣＦ３ＩまたはＣＦ４を含むガスを用いてエッチングを行うことにより、前記第１溝部を形成する半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 14 or 15,
    A method of manufacturing a semiconductor device, wherein the first groove portion is formed by performing etching using a gas containing CF 3 I or CF 4 in the first groove portion forming step.
PCT/JP2012/001160 2011-03-31 2012-02-21 Semiconductor device and method for manufacturing semiconductor device WO2012132206A1 (en)

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