WO2012129878A1

WO2012129878A1 - Method and system for on-chip interconnection bus arbitration

Info

Publication number: WO2012129878A1
Application number: PCT/CN2011/078420
Authority: WO
Inventors: 刘凯; 李炜
Original assignee: 中兴通讯股份有限公司
Priority date: 2011-04-01
Filing date: 2011-08-15
Publication date: 2012-10-04
Also published as: CN102736997B; CN102736997A

Abstract

Disclosed in the invention are a method and a system for on-chip interconnection bus arbitration, a request of a peripheral can be buffered by them; a signal of arbitration response is initiated to the peripheral when the request of the peripheral can be responded or be buffered. The on-chip interconnection bus arbitration technology of the application can obtain continuously the signal of bus arbitration in the case of a request of single equipment therefore transmission efficiency of the bus is improved greatly.

Description

Arbitration method and system for on-chip interconnect bus

The present invention relates to the field of chips, and in particular to an arbitration method and system for an on-chip interconnect bus. Background technique

The internal bus interconnection of the chip is a key area of current chip research. With the continuous improvement of chip processing capability, processing frequency and processing functions, higher requirements are placed on the internal interconnect bus of the chip, and the chip interconnection is realized in the case of multi-device shared bus. The speed and efficiency of the bus.

In the case of inter-chip bus interconnection, multiple bus units are often required to access bus resources, thus forming an arbitration relationship for the on-chip bus. In general, in order to ensure that the unit that obtains arbitration can continuously transmit data, chip arbitration is often required. The bus request is initiated as soon as it is initiated (as shown in Figure 1), but this bus arbitration structure requires the bus request to arrive at the bus arbitration after the bus has been transmitted, and then sent to the requesting unit after the arbitration logic operation. This type of operation often consumes a large amount of delay, so the bus operating frequency is often not very high, which will greatly reduce the actual transmission efficiency of the bus.

Another common practice is to transfer the combined logic signal after arbitration to the bus (as shown in Figure 2). This can increase the transmission frequency of the bus, but the arbitration result cannot be immediately returned to the transmitting device, thus causing the transmission. The device waits, which causes the bus to fail to achieve continuous transmission and also reduces the actual transmission efficiency of the bus. Summary of the invention

In view of this, the main object of the present invention is to provide an arbitration method and system for an on-chip interconnect bus to continuously obtain a bus arbitration signal and improve the transmission efficiency of the bus.

In order to achieve the above object, the technical solution of the present invention is achieved as follows: An arbitration method for an on-chip interconnect bus, including:

The current peripheral request is buffered; an arbitration acknowledgement signal is sent to the peripheral when the peripheral request can be acknowledged or buffered.

The process of buffering the peripheral request includes:

The peripheral request is first sent to the normal transmission path, and a backup requested by the peripheral is sent to the sliding buffer skid buffer circuit; the appropriate path is selected from the normal transmission path and the skid buffer path, and the peripheral request is sent to a combinational logic circuit for bus arbitration decisions;

If the arbitration result is calculated, the normal path is gated; otherwise, the data of the skid buffer path is selected.

Wherein, under initial conditions, the value of the Skid buffer is empty, and when a transfer request is externally provided but not acknowledged, the next peripheral request is also sent to the skid buffer; when the skid buffer is full, And then initiating a new arbitration permission signal as an arbitration response signal to the peripheral;

Whenever the skid buffer has a buffered arbitration signal, when the peripheral obtains new arbitration permission, the request signal is first taken from the skid buffer.

The final arbitration enable signal as the arbitration acknowledge signal is the timing output; if the peripheral continues to obtain the low arbitration enable signal, the peripheral continues to obtain the arbitration enable signal.

Wherein, the final arbitration enable signal as the arbitration acknowledgement signal is the timing output; if the peripheral does not obtain the low level arbitration enable signal, it also checks whether the peripheral has a request currently, or has a request in the cache; if there is a request The request is processed first, and the arbitration permission signal is no longer sent to the peripheral.

An arbitration system for an on-chip interconnect bus, comprising a request buffer unit and an arbitration processing unit; wherein

The request cache unit is configured to cache a current peripheral request;

The arbitration processing unit is configured to: when the peripheral request can be answered or cached, An arbitration response signal is sent to the peripheral.

The request cache unit is configured to: when caching the current peripheral request:

The peripheral request is first sent to the normal transmission path, and a backup requested by the peripheral is sent to the skid buffer circuit; the appropriate path is selected from the normal transmission path and the skip buffer path, and the peripheral request is sent to the bus arbitration. In the combined logic circuit of the decision;

The initial value is that the value of the Skid buffer is empty. When a transmission request is externally provided but is not acknowledged, the request buffer unit is further configured to trigger the skid buffer to receive a next peripheral request.

The arbitration processing unit is configured to: after the skid buffer is full, no longer initiate a new arbitration permission signal as an arbitration response signal to the peripheral device.

The final arbitration enable signal as the arbitration acknowledge signal is the timing output; if the peripheral continues to obtain the low arbitration enable signal, the peripheral is also used to continuously obtain the arbitration enable signal.

Wherein, the final arbitration enable signal as the arbitration acknowledgement signal is a timing output; if the peripheral does not obtain the low level arbitration enable signal, the request buffer unit is further configured to check whether the peripheral has a request, or cache There is a request; if there is a request, the request is processed first, and the arbitration processing unit is no longer triggered to send an arbitration permission signal to the peripheral.

The arbitration technique of the on-chip interconnect bus of the present invention can continuously obtain the bus arbitration signal in the case of a single device request, thereby greatly improving the transmission efficiency of the bus. DRAWINGS

Figure la and Figure lb are schematic diagrams of the chip arbitration principle of the prior art;

2a and 2b are schematic diagrams showing the principle of chip arbitration in the prior art 2;

3a and 3b are schematic diagrams showing a bus arbitration structure and a chip arbitration principle according to an embodiment of the present invention; 4 is a schematic diagram showing the detailed structure of an arbitration circuit and a principle of chip arbitration according to an embodiment of the present invention; FIG. 5 is a schematic diagram of an arbitration process of an on-chip interconnect bus according to an embodiment of the present invention. detailed description

In practice, an interconnect bus arbitration circuit can be proposed, which is designed with a skid buffer circuit capable of buffering current peripheral requests, and in the case where peripheral requests can be acknowledged or cached, Initiate an arbitration response signal. This will ensure that the actual bus arbitration is not calculated before it can initiate an arbitration response signal to the peripheral, thereby ensuring the timeliness of the response of the arbitration signal and ensuring the efficiency of the bus arbitration response.

It should be noted that the buffer buffer used in bus arbitration can store deep bus requests. In addition, for the bus arbitration response signal design, the response signal will jointly determine the buffer state of the buffer unit and the combined logic arbitration signal of the bus to determine the bus acknowledge signal to be transmitted. Moreover, the bus arbitration acknowledgement signal is a sequential circuit design, that is, the signal is a register beat design, has a good timing characteristic, and can improve the overall operating frequency of the bus.

Referring to the overall frame structure of the arbitration architecture in Figure 3, the whole can be divided into the following parts: Skid buffer buffer logic, general combination logic arbitration circuit, arbitration response signal output circuit.

As shown in Figure 3, the peripheral request signal (with the request access address) is first sent to the circuit (normal transmission path), and a backup requested by the peripheral is sent to the skid buffer circuit, the multiplexer (mux) circuit. It is responsible for selecting an appropriate path from the normal transmission path and the skid buffer path to send the peripheral request signal to the combinational logic circuit of the bus arbitration decision. The skid buffer circuit refers to a differential flip flop (DFF) 1. The DFF is mainly used to implement the register function, and may also be replaced by a storage device other than the DFF.

If the arbitration result is calculated, the mux logic gates the normal path (the portion above DFF 1); otherwise, the data of the skid buffer path is selected. The combinatorial logic decision circuit is a general digital decider circuit, which can be designed as a polling, priority, etc. circuit as needed. The result of the combinational logic decision circuit is ORed with the state of the register in the current skid buffer to indicate whether it can be succeeded next time. The response signal is continuously sent, and the signal is sent to the peripheral unit after being beat.

The Skid buffer circuit is capable of buffering a deep peripheral request. Under the initial conditions, the value of the Skid buffer is empty. When there is a transfer request but is not acknowledged by the arbiter, the circuit will send the next peripheral request to the skid buffer. When the skid buffer is full, the arbitration circuit will ensure that no new arbitration enable signals are issued to the peripherals. Whenever the skid buffer has a buffered arbitration signal, when the peripheral obtains new arbitration permission, the peripheral request signal will be removed from the skid buffer.

The general combinational logic arbitration circuit can follow a plurality of arbitration priority algorithms, which are essentially combined logic circuits for returning an arbitration enable signal to a peripheral device under the beat clock according to the input signals of the plurality of bus peripherals.

The arbitration response output signal is shown in Figure 4. The final arbitration enable signal (gnt) is a timing output whose output is related to the combination logic arbitration output ( gnt_raw ) and whether there is still a peripheral request signal present. If the peripheral continues to receive the gnt_raw signal, indicating that the peripheral can continue to transmit, the peripheral can continue to obtain the arbitration enable signal. If the peripheral does not get the gnt_raw signal at this time, it needs to check whether the current peripheral has a request, or has a request in the cache. If there is a request, the request is processed first, and the arbitration permission signal is no longer sent to the peripheral.

As shown in Figure 3, at beat 1, the peripheral first sends the address al. Since the skid buffer is empty in the initial state, after the address al is sent, the peripheral continues to transmit the address a2 on the next clock cycle beat 2. Since the address al is not arbitrated at beat 1, the gnt signal is pulled low after the address a2 is sent, the address al is held in the skid buffer, and the address al is held on the output port. At beat 2, address al gets arbitration, then on beat 3, the gnt signal is pulled high again, at which point address a2 is output at beat 3.

It can be seen that if the peripheral can continuously obtain arbitration, its address can be transmitted continuously, which can ensure the maximum bus transmission efficiency, and the gnt signal is the register output, which greatly improves the running frequency of the bus.

It can be seen from the above description of the technology that the arbitration operation idea of the on-chip interconnect bus of the present invention can be expressed. The process shown in FIG. 5 is shown, and the process includes the following steps:

Step 510: Cache the current peripheral request.

Step 520: When the peripheral request can be acknowledged or buffered, an arbitration acknowledgement signal is sent to the peripheral.

In summary, the arbitration technique of the on-chip interconnect bus of the present invention can continuously obtain the bus arbitration signal in the case of a single device request, thereby greatly improving the transmission efficiency of the bus.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Claims

Claim

1. An arbitration method for an on-chip interconnect bus, comprising:

2. The method of claim 1, wherein the process of buffering the peripheral request comprises: the peripheral request being first sent to a normal transmission path, and a backup requested by the peripheral is sent to a sliding buffer skid buffer a circuit; selecting a suitable path from the normal transmission path and the skid buffer path, and sending the peripheral request to the combination logic circuit of the bus arbitration decision;

3. The method according to claim 2, wherein

Under initial conditions, the value of the Skid buffer is empty. When a transfer request is externally provided but is not acknowledged, the next peripheral request is also sent to the skid buffer; when the skid buffer is full, it is no longer The peripheral initiates a new arbitration enable signal as an arbitration response signal;

The method according to any one of claims 1 to 3, wherein the final arbitration permission signal as an arbitration response signal is a timing output;

If the peripheral continues to acquire a low arbitration enable signal, the peripheral continues to acquire the arbitration enable signal.

If the peripheral does not obtain a low-level arbitration enable signal, it also checks whether the current peripheral has a request, or has a request in the cache; if there is a request, the request is processed first, and the arbitration permission signal is no longer sent to the peripheral. .

6. An arbitration system for an on-chip interconnect bus, comprising a request buffer unit and an arbitration processing unit; wherein

The request cache unit is configured to cache a current peripheral request;

The arbitration processing unit is configured to initiate an arbitration response signal to the peripheral device when the peripheral request can be acknowledged or cached.

7. The system according to claim 6, wherein the request cache unit is configured to: when caching a current peripheral request:

8. The system according to claim 7, wherein

Under initial conditions, the value of the Skid buffer is empty. When a transmission request is externally provided but is not acknowledged, the request buffer unit is further configured to trigger the skid buffer to receive the next peripheral request;

The system according to any one of claims 6 to 8, wherein the final arbitration permission signal as an arbitration response signal is a timing output;

If the peripheral continues to acquire a low arbitration enable signal, the peripheral is also used to continuously obtain the arbitration enable signal.

10. The system according to any one of claims 6 to 8, wherein the final arbitration permission signal as an arbitration response signal is a timing output;

If the peripheral does not obtain a low level arbitration enable signal, the request cache unit is used It also checks whether the peripheral currently has a request, or has a request in the cache; if there is a request, the request is processed first, and the arbitration processing unit is no longer triggered to send an arbitration permission signal to the peripheral.