WO2012124420A1 - Light-emitting diode and method for manufacturing same - Google Patents

Light-emitting diode and method for manufacturing same Download PDF

Info

Publication number
WO2012124420A1
WO2012124420A1 PCT/JP2012/053348 JP2012053348W WO2012124420A1 WO 2012124420 A1 WO2012124420 A1 WO 2012124420A1 JP 2012053348 W JP2012053348 W JP 2012053348W WO 2012124420 A1 WO2012124420 A1 WO 2012124420A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
light emitting
emitting diode
mesa structure
light
Prior art date
Application number
PCT/JP2012/053348
Other languages
French (fr)
Japanese (ja)
Inventor
典孝 村木
範行 粟飯原
Original Assignee
昭和電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昭和電工株式会社 filed Critical 昭和電工株式会社
Priority to CN201280013022.0A priority Critical patent/CN103430332B/en
Publication of WO2012124420A1 publication Critical patent/WO2012124420A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Definitions

  • the present invention relates to a light emitting diode and a method for manufacturing the same.
  • This application claims priority based on Japanese Patent Application No. 2011-055833 filed in Japan on March 14, 2011 and Japanese Patent Application No. 2011-203449 filed in Japan on September 16, 2011. Is incorporated herein by reference.
  • a point light source type light emitting diode that extracts light generated in the light emitting layer from a part of the upper surface of the element is known.
  • this type of light emitting diode one having a current confinement structure for limiting a current-carrying region in a light emitting layer to a part of the surface is known (for example, Patent Document 1).
  • a light emitting diode having a current confinement structure a light emitting region is limited, and light is emitted from a light emitting hole provided immediately above the region, so that high light output is obtained and the emitted light is applied to an optical component or the like. It is possible to capture efficiently.
  • the resonator type light emitting diode (RCLED: Resonant-Cavity Light Emitting Diode) has antinodes of standing waves generated in the resonator composed of two mirrors arranged in the resonator.
  • a high-efficiency light-emitting element that is configured to be located in the light-emitting layer and that operates in LED mode without causing laser oscillation by setting the reflectance of the mirror on the light emission side to be lower than that of the mirror on the substrate side.
  • Resonator-type light-emitting diodes can respond faster than ordinary light-emitting diodes due to the effect of the resonator structure due to the narrow emission spectrum line width, high directivity of emitted light, and short carrier lifetime due to spontaneous emission. Because there is a feature such as, there is a suitable sensor.
  • the upper mirror layer and the active layer have a pillar structure in order to narrow the light emitting region in the direction parallel to the substrate, and the light extraction surface on the top surface of the pillar structure has an opening for light emission.
  • a configuration including a layer is known (for example, Patent Document 4).
  • FIG. 18 shows a resonator type light emitting diode having a lower mirror layer 132, an active layer 133, an upper mirror layer 134, and a contact layer 135 in this order on a substrate 131.
  • the layer 134 and the contact layer 135 are formed as a pillar structure 137, the pillar structure 137 and its periphery are covered with a protective film 138, an electrode film 139 is formed on the protective film 138, and the top surface 137a of the pillar structure 137 (light A resonator type light emitting diode in which an opening 139a for light emission is formed in the electrode film 139 on the extraction surface) is shown.
  • Reference numeral 140 denotes a back electrode.
  • the current confinement structure having a pillar structure as shown in FIG. 18 can be applied to a point light source type light emitting diode which is not a resonator type.
  • the side surface 137b of the pillar structure 137 is formed. Is formed perpendicularly or steeply to the substrate 131.
  • a protective film is formed on the side surface of the pillar structure by vapor deposition or sputtering, and then a metal (for example, Au) film for electrodes is formed by vapor deposition.
  • the protective film is formed on the vertical or steeply inclined side surface. It is not easy to form a film or a metal film for an electrode with a uniform film thickness, and there is a problem that it is likely to be a discontinuous film.
  • the electrode metal film When the protective film becomes a discontinuous film (symbol A in FIG. 18), the electrode metal film enters the discontinuous portion and comes into contact with the active layer or the like, causing a leak. In addition, when the electrode metal film becomes a discontinuous film (symbol B in FIG. 18), it causes a conduction failure.
  • the present invention has been made in view of the above circumstances, and a protective film and a light-emitting diode in which an electrode film formed thereon is formed with a uniform film thickness, and yield is reduced by reducing leakage and poor conduction.
  • An object of the present invention is to provide a method of manufacturing a light-emitting diode that can be manufactured at a lower cost than ever before.
  • a light emitting diode comprising a compound semiconductor layer including a reflective layer and an active layer on a substrate, having a flat portion on the top thereof, and a mesa structure portion having an inclined side surface and a top surface,
  • Each of the flat portion and the mesa structure portion is sequentially covered with a protective film and an electrode film, and the mesa structure portion includes at least a part of the active layer, and the inclined side surface Is formed by wet etching and has a horizontal cross-sectional area continuously reduced toward the top surface, and the protective film includes at least a part of the flat portion and the mesa structure portion.
  • An energization window that covers at least the inclined side surface and the peripheral region of the top surface of the mesa structure and exposes part of the surface of the compound semiconductor layer inside the peripheral region in plan view.
  • the above The polar layer is in direct contact with the surface of the compound semiconductor layer exposed from the energizing window, covers at least a part of the protective film formed on the flat portion, and emits light on the top surface of the mesa structure portion.
  • a light-emitting diode which is a continuous film formed to have an injection hole.
  • the “flat portion” is formed at the same time when the mesa structure portion is formed by wet etching of the compound semiconductor layer, and “flattening” is performed by wet etching. is there.
  • the light emitting layer included in the active layer is ((Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ⁇ X1 ⁇ 1, 0 ⁇ Y1 ⁇ 1), (Al X2 Ga 1-X2 ) As (0 ⁇ X2 ⁇ 1), (In X3 Ga 1-X3 ) As (0 ⁇ X3 ⁇ 1)), according to any one of (1) to (13), Light emitting diode.
  • the manufacturing method of the light emitting diode as described in (15) characterized by performing.
  • the flat portion and the mesa structure portion having the inclined side surface and the top surface are formed on the upper portion, and at least a part of the flat portion and the mesa structure portion is the protective film and the electrode.
  • the mesa structure portion is sequentially covered with a film, and the mesa structure portion includes at least a part of the active layer, and the protective film includes at least a portion of the flat portion, the inclined side surface of the mesa structure portion, and the mesa structure.
  • An energization window that covers at least the peripheral region of the top surface of the portion and exposes a part of the surface of the compound semiconductor layer inside the peripheral region in plan view, and the electrode layer is exposed from the energization window.
  • the protective film and the electrode film on it are easy to form on the side, a continuous film with a uniform film thickness is formed, so there is no leakage or poor conduction due to the discontinuous film, and stable and high-luminance emission Is secured.
  • Such an effect is achieved as long as a mesa structure portion having an inclined side surface formed by wet etching is provided, and is an effect obtained regardless of the laminated structure inside the light emitting diode and the configuration of the substrate.
  • the reflective layer is made of metal, the light emitted from the light emitting layer is reflected with a high reflectance, and high light output is possible.
  • the light emitting diode of the present invention it is possible to emit light with a narrow emission spectrum line width by adopting a configuration in which the reflective layer is a DBR reflective layer. Furthermore, by adopting a configuration in which the upper DBR reflective layer is provided on the side opposite to the substrate of the active layer, the emission spectral line width is narrow, the directivity of the emitted light is high, and high-speed response is possible.
  • the contact resistance of the ohmic electrode can be lowered and low voltage driving can be performed.
  • the mesa structure portion adopts a configuration including all of the active layer and part or all of the reflective layer, so that all light emission occurs in the mesa structure portion.
  • the light extraction efficiency is improved.
  • the mesa shape changes depending on the etching depth due to anisotropy in wet etching during manufacturing. Is suppressed, and the mesa area can be easily controlled, so that a highly accurate dimensional shape is obtained.
  • each inclined side surface of the mesa structure portion is formed offset with respect to the orientation flat of the substrate, the four sides constituting the rectangular mesa structure portion are formed.
  • the influence of the anisotropy due to the substrate orientation is mitigated, a uniform mesa shape / gradient is obtained.
  • the light emitting diode of the present invention by adopting a configuration in which the height of the mesa structure portion is 3 to 7 ⁇ m and the width of the inclined side surface in a plan view is 0.5 to 7 ⁇ m, Compared to the above, it is easy to form a protective film on the side and the electrode film on it, so a continuous film is formed with a uniform film thickness. Luminance emission is guaranteed.
  • the light emitting diode of the present invention by adopting a configuration in which the light emitting hole is circular or elliptical in plan view, it is easy to form a uniform contact region as compared with a structure having a corner such as a rectangle. Occurrence of current concentration and the like can be suppressed. Further, it is suitable for coupling to a fiber or the like on the light receiving side.
  • the light emitting diode of the present invention by adopting a configuration in which the diameter of the light emitting hole is 50 to 150 ⁇ m, the current density in the mesa structure is increased below 50 ⁇ m, and the output is saturated at a low current. On the other hand, if it exceeds 150 ⁇ m, it is difficult to spread the current to the entire mesa structure, so that the problem that the output is saturated is also avoided.
  • wire bonding is performed on a flat portion where a sufficient load (and ultrasonic wave) can be applied by adopting a configuration having a bonding wire in a portion on the flat portion of the electrode layer. Wire bonding with high bonding strength has been realized.
  • a mesa structure portion formed by wet-etching a compound semiconductor layer and having a horizontal cross-sectional area continuously reduced toward the top surface, and the mesa structure portion On the mesa structure portion and the flat portion so that the top surface of the mesa structure portion has a conduction window exposing a part of the surface of the compound semiconductor layer.
  • a step of forming a protective film; and a direct contact with the surface of the compound semiconductor layer exposed from the energization window; and at least a part of the protective film formed on the flat portion; and a top surface of the mesa structure portion The process of forming the electrode layer, which is a continuous film, so as to have a light exit hole at the top, has a high light output and can efficiently take out the emitted light into an optical component or the like And the vertical side Compared to the case, since it is easy to form the protective film and the electrode film thereon on the inclined slope, a continuous film with a uniform film thickness is formed, so there is no leakage or poor conduction due to the discontinuous film, A light-emitting diode in which stable and high-luminance light emission is ensured can be manufactured.
  • the side surface is formed vertically, but by forming the mesa structure portion by wet etching, the side surface can be formed with a gently inclined side surface. Further, by forming the mesa structure portion by wet etching, the formation time can be shortened as compared with the case where the pillar structure is formed by conventional dry etching.
  • FIG. 1 is a schematic cross-sectional view of a resonator type light emitting diode which is an example of a light emitting diode to which the present invention is applied.
  • FIG. 2 is a perspective view of a light emitting diode formed on a wafer including the light emitting diode shown in FIG.
  • a light emitting diode according to an embodiment to which the present invention is applied will be described in detail with reference to FIGS. 1 and 2.
  • a light-emitting diode 100 shown in FIG. 1 is a light-emitting diode having a compound semiconductor layer including a reflective layer 2 and an active layer 3 on a substrate 1, and a flat portion 6, an inclined side surface 7 a, and a top surface 7 b on the upper portion. And the mesa structure portion 7 having at least a part thereof covered with a protective film 8 and an electrode film 9 in order. At least a part of the active layer 3 is included, the inclined side surface 7a is formed by wet etching, and the cross-sectional area in the horizontal direction is continuously reduced toward the top surface 7b.
  • Compound A conductive window 8b exposing a part of the surface of the conductor layer is provided, and the electrode layer 9 is in direct contact with the surface of the compound semiconductor layer exposed from the conductive window 8b, and is a protective film formed on the flat portion 6 8 is a continuous film formed so as to cover at least a part of 8 and have a light exit hole 9b on the top surface 7b of the mesa structure 7, and the reflective layer 2 is a DBR reflective layer (lower DBR reflective layer).
  • the upper DBR reflective layer 4 is provided on the side of the active layer 3 opposite to the substrate 1, and the compound semiconductor layer has a contact layer 5 that contacts the electrode layer 9.
  • the mesa structure 7 of the resonator type light emitting diode of the present embodiment is rectangular in plan view, and the light emission hole 9b of the electrode layer 9 is circular in plan view.
  • the plan view of the mesa structure 7 is not limited to a rectangle, and the plan view of the light emission hole 9b is not limited to a circle.
  • a light leakage prevention film 16 for preventing light leakage from the side surface is provided on the electrode film of the mesa structure 7. Further, a back electrode 10 is provided on the lower surface side of the substrate 1.
  • streets (scheduled cutting lines) 21 are the lengths of the streets 21) for each light emitting diode. It can be manufactured by cutting along a direction centerline). That is, each light emitting diode can be cut by applying a laser, a blade, or the like to the portion of the street 21 along the dotted line 22.
  • the mesa structure portion 7 has a structure protruding upward with respect to the flat portion 6, and has an inclined side surface 7a and a top surface 7b as outer surfaces.
  • the inclined side surface 7 a is an electrode layer (front surface electrode) formed on the entire active layer 3, the upper DBR layer 4, and the inclined cross section of the contact layer 5 via a protective film.
  • the top surface 7b is composed of the surface of the portion 8d covering the central portion of the protective film 8 and the surface of the electrode layer 9 (portions 9ba, 9bb and 9d).
  • the inside of the mesa structure portion 7 of the present invention includes the contact layer 5, the upper DBR layer 4, and at least a part of the active layer 3.
  • the inside of the mesa structure portion 7 includes the contact layer 5, the upper DBR layer 4, and the entire active layer 3.
  • the mesa structure 7 may include only a part of the active layer 3, but it is preferable that the entire active layer 3 is included in the mesa structure 7. This is because all the light emitted from the active layer 3 is generated in the mesa structure, and the light extraction efficiency is improved. Further, a part of the lower DBR layer 2 may be included in the mesa structure portion 7.
  • the mesa structure 7 has an inclined side surface 7a formed by wet etching, and has a horizontal cross-sectional area that continuously decreases from the substrate 1 side to the top surface. Since the inclined side surface 7a is formed by wet etching, it is formed in a convex shape downward.
  • the height h of the mesa structure 7 is preferably 3 to 7 ⁇ m, and the width w of the inclined side surface 7a in plan view is preferably 0.5 to 7 ⁇ m. In this case, since the side surface of the mesa structure portion 7 is not vertical or steeply inclined but gently inclined, it is easy to form the protective film and the electrode metal film with a uniform film thickness, which is discontinuous.
  • the height h is an electrode that covers the portion 8ba of the protective film 8 from the surface of the electrode film 9 (portion 9c) formed through the protective film on the flat portion 6. This refers to the vertical distance (see FIG.
  • the width w is the lowest of the electrode film 9 (reference numeral 9a) on the inclined side surface connected to the edge from the edge of the electrode film 9 (reference numeral 9ba) covering the protective film 8 at the reference numeral 8ba.
  • the horizontal distance of the edge see FIG. 1).
  • FIG. 3 is an electron micrograph of a cross section in the vicinity of the mesa structure portion 7.
  • the layer configuration of the example shown in FIG. 3 is the same as that of the example described later except that the contact layer is made of Al 0.3 Ga 0.7 As and the layer thickness is 3 ⁇ m.
  • the mesa structure portion of the present invention is formed by wet etching, the horizontal cross-sectional area (or width or diameter) of the mesa structure portion increases from the top surface side to the substrate side (downward in the figure). ) To increase. With this shape, it can be determined that the mesa structure is formed not by dry etching but by wet etching. In the example shown in FIG. 3, the height h is 7 ⁇ m and the width w is 3.5 to 4.5 ⁇ m.
  • the mesa structure 7 is preferably rectangular in plan view.
  • the mesa shape can be prevented from changing depending on the etching depth due to the influence of anisotropy in wet etching during manufacturing, and the area of each surface of the mesa structure can be easily controlled, so a highly accurate dimensional shape can be obtained. It is.
  • the position of the mesa structure portion 7 in the light emitting diode is preferably shifted to one side in the long axis direction of the light emitting diode in order to reduce the size of the element. Since the flat portion 6 needs to have a size necessary for attaching a bonding wire (not shown), there is a limit to narrowing it, and by moving the mesa structure portion 7 to the other side, the flat portion 6 has a limit. This is because the range can be minimized and the device can be miniaturized.
  • the flat part 6 is a part arranged around the mesa structure part 7.
  • wire bonding is performed on a portion located on the flat portion of the electrode layer to which a sufficient load (and ultrasonic wave) can be applied, so that wire bonding with high bonding strength can be realized.
  • a protective film 8 and an electrode layer (front electrode layer) 9 are sequentially formed on the flat portion 6, and a bonding wire (not shown) is attached on the electrode layer 9.
  • the material disposed immediately below the protective film 8 of the flat portion 6 is determined by the internal configuration of the mesa structure portion 7.
  • the inside of the mesa structure portion 7 includes the contact layer 5, the upper DBR layer 4, and the entire active layer 3, and the lower DBR layer that is a layer immediately below the active layer 3. Therefore, the material disposed immediately below the protective film 8 of the flat portion 6 is the material of the uppermost surface of the lower DBR layer.
  • the protective film 8 includes a portion 8a that covers the inclined side surface 7a of the mesa structure portion 7 and a portion 8c that covers at least a portion of the flat portion 6 (a portion 8cc that covers the flat portion on the opposite side across the mesa structure portion 7). And a portion 8ba that covers the peripheral region 7ba of the top surface 7b of the mesa structure 7 and a portion 8d that covers the central portion of the top surface 7b, and is a contact layer inside the peripheral region 7ba in plan view. 5 has an energizing window 8b that exposes a part of the surface.
  • the energization window 8b of the present embodiment is a portion of the surface of the contact layer 5 on the top surface 7b of the mesa structure 7 that is located below the portion 8ba located below the peripheral region 7ba and the portion 8d covering the central portion. An area between two concentric circles with different diameters between and is exposed.
  • the first function of the protective film 8 is to arrange the surface electrode layer 9 and the back electrode 10 in the lower layer of the front electrode layer 9 in order to narrow the region where light emission occurs and the range from which light is extracted. It is to limit the region in which the current flows. That is, after forming the protective film 8, a front electrode layer is formed on the entire surface including the protective film 8, and then the front electrode layer is patterned. Even if the surface electrode layer is not removed, no current flows between the electrode 10 and the back electrode 10. An energization window 8b of the protective film 8 is formed where a current between the back electrode 10 is desired to flow.
  • the shape and position of the energization window 8b is the shape as shown in FIG. It is not limited to or position.
  • the second function of the protective film 8 is not an essential function while the first function is an essential function.
  • the protective film 8 shown in FIG. it is arranged on the surface of the contact layer 5 in the light emitting hole 9a of the surface electrode layer 9, so that light can be extracted through the protective film 8, and the surface of the contact layer 5 from which light is extracted is protected. That is.
  • the material of the protective film 8 a known material can be used as the insulating layer, but a silicon oxide film is preferable because it is easy to form a stable insulating film. In this embodiment, since light is extracted through the protective film 8 (8d), the protective film 8 needs to have translucency.
  • the film thickness of the protective film 8 is preferably 0.3 to 1 ⁇ m. This is because if the thickness is less than 0.3 ⁇ m, the insulation is not sufficient, and if it exceeds 1 ⁇ m, it takes too much time to form.
  • the electrode layer (front surface electrode layer) 9 is a portion that covers a portion 9 a that covers the inclined side surface 7 a of the protective film 8 and a portion 8 c that covers at least a part of the flat portion 6 of the protective film 8.
  • 9c, a portion 9ba of the protective film 8 that covers the portion 8ba that covers the peripheral region 7ba of the top surface 7b of the mesa structure portion 7, and a portion 9bb that embeds the current-carrying window 8b of the protective film 8 hereinafter referred to as “contact” as appropriate
  • a portion 9d that covers the outer peripheral edge portion of the portion 8d that covers the central portion of the top surface 7b of the protective film 8 on the top surface 7b of the mesa structure portion 7.
  • the first function of the electrode layer (front electrode layer) 9 is to pass a current between the electrode layer 10 and the back electrode 10, and the second function is to limit the range in which the emitted light is emitted.
  • the contact portion 9bb is responsible for the first function
  • the portion 9d covering the outer peripheral edge portion of the portion 8d covering the center portion is responsible for the second function.
  • a non-translucent protective film may be used so that the protective film bears it.
  • the electrode layer 9 may cover the entire protective film 8 of the flat portion 6 or may cover a part thereof, but it is preferable that the electrode layer 9 covers as wide a range as possible in order to properly attach the bonding wire. From the viewpoint of cost reduction, as shown in FIG. 2, it is preferable not to cover the electrode layer on the street 21 when cutting each light emitting diode.
  • this electrode layer 9 is in contact with the contact layer 5 only at the contact portion 9bb on the top surface 7b of the mesa structure portion 7, the electrode layer 9 and the back electrode 10 are located between the contact portion 9bb and the back electrode 10. Only current flows. Therefore, current concentrates in a range where the light emitting layer 13 overlaps with the light emission hole 9b in plan view, and light emission concentrates in that range, so that light can be extracted efficiently.
  • a known electrode material can be used as the material of the electrode layer 9, but AuBe / Au is most preferable because a good ohmic contact can be obtained.
  • the film thickness of the electrode layer 9 is preferably 0.5 to 2.0 ⁇ m. This is because it is difficult to obtain a uniform and good ohmic contact if the thickness is less than 0.5 ⁇ m, and the strength and thickness at the time of bonding are insufficient, and if it exceeds 2.0 ⁇ m, the cost is excessive.
  • a light leakage prevention film 16 that prevents light emitted from the active layer from leaking from the side surface of the mesa structure 7 to the outside of the device may be provided.
  • the material of the light leakage prevention film 16 a known reflective material can be used.
  • the same AuBe / Au as the electrode layer 9 may be used.
  • a protective film 8d (8) is formed under the light emitting hole 9b, and light is emitted from the light emitting hole 9b through the protective film 8d (8) on the top surface of the mesa structure portion 7. It is the structure to take out.
  • the shape of the light exit hole 9b is preferably circular or elliptical in plan view. Compared to a structure having a corner such as a rectangle, a uniform contact region can be easily formed, and current concentration at the corner can be suppressed. Moreover, it is because it is suitable for the coupling
  • the diameter of the light exit hole 9b is preferably 50 to 150 ⁇ m. If it is less than 50 ⁇ m, the current density at the emission part becomes high and the output is saturated at a low current. On the other hand, if it exceeds 150 ⁇ m, it is difficult to diffuse the current to the whole emission part, and the light emission efficiency with respect to the injection current decreases. It is.
  • a GaAs substrate can be used as the substrate 1, for example.
  • a commercially available single crystal substrate manufactured by a known manufacturing method can be used.
  • the surface on which the GaAs substrate is epitaxially grown is preferably smooth.
  • the surface orientation of the surface of the GaAs substrate is easily epi-grown, and from the (100) plane and (100) that are mass-produced, a substrate that is turned off within ⁇ 20 ° is preferable from the viewpoint of quality stability.
  • the range of the plane orientation of the GaAs substrate is more preferably 15 ° off ⁇ 5 ° from the (100) direction to the (0-1-1) direction.
  • the dislocation density of the GaAs substrate is preferably low in order to improve the crystallinity of the lower DBR layer 2, the active layer 3, and the upper DBR layer 4. Specifically, for example, 10,000 pieces cm ⁇ 2 or less, preferably 1,000 pieces cm ⁇ 2 or less are suitable.
  • the GaAs substrate may be n-type or p-type.
  • the carrier concentration of the GaAs substrate can be appropriately selected from desired electrical conductivity and element structure.
  • the carrier concentration is preferably in the range of 1 ⁇ 10 17 to 5 ⁇ 10 18 cm ⁇ 3 .
  • the carrier concentration is preferably in the range of 2 ⁇ 10 18 to 5 ⁇ 10 19 cm ⁇ 3 .
  • the thickness of the GaAs substrate has an appropriate range depending on the size of the substrate. If the thickness of the GaAs substrate is less than the appropriate range, the compound semiconductor layer may be broken during the manufacturing process. On the other hand, if the thickness of the GaAs substrate is thicker than an appropriate range, the material cost increases. Therefore, when the substrate size of the GaAs substrate is large, for example, when the diameter is 75 mm, a thickness of 250 to 500 ⁇ m is desirable to prevent cracking during handling. Similarly, when the diameter is 50 mm, a thickness of 200 to 400 ⁇ m is desirable, and when the diameter is 100 mm, a thickness of 350 to 600 ⁇ m is desirable.
  • the warpage of the compound semiconductor layer caused by the active layer 3 can be reduced by increasing the thickness of the substrate according to the substrate size of the GaAs substrate.
  • the temperature distribution during epitaxial growth becomes uniform, so that the in-plane wavelength distribution of the active layer 3 can be reduced.
  • the shape of the GaAs substrate is not particularly limited to a circle, and there is no problem even if it is a rectangle or the like.
  • known functional layers can be added as appropriate.
  • a known layer structure such as a current diffusion layer for planarly diffusing the element driving current over the entire light emitting portion, or a current blocking layer or a current constricting layer for limiting the area through which the element driving current flows is used. Can be provided.
  • the reflective layer (lower DBR layer) and compound semiconductor layer formed on the substrate 1 are configured by sequentially laminating a lower DBR layer 2, an active layer 3, and an upper DBR layer 4.
  • a DBR (Distributed Bragg Reflector) layer is composed of two types of layers having a film thickness of ⁇ / (4n) ( ⁇ : wavelength of light to be reflected in vacuum, n: refractive index of layer material) and different refractive indexes. It consists of a multilayer film laminated alternately. When the difference between the two types of refractive indexes is large, a high reflectance can be obtained with a multilayer film having a relatively small number of layers. Instead of being reflected on a certain surface as in a normal reflective film, the multilayer film as a whole is characterized in that reflection occurs based on the light interference phenomenon.
  • the material of the DBR layer is preferably transparent with respect to the emission wavelength, and is preferably selected so as to be a combination that increases the difference in refractive index between the two types of materials constituting the DBR layer.
  • the lower DBR layer 2 is preferably formed by alternately stacking 10 to 50 pairs of two kinds of layers having different refractive indexes. This is because when the number is 10 pairs or less, the reflectance is too low, so that it does not contribute to an increase in output, and even when the number is 50 pairs or more, the increase in reflectance is small.
  • a combination of AlGaInP having different compositions is preferable because it does not contain As that easily causes crystal defects, and GaInP and AlInP have the largest refractive index difference among them, so that the number of reflective layers can be reduced and the composition can be switched. Is also preferable because it is simple. Moreover, AlGaAs has an advantage that a large difference in refractive index is easily obtained.
  • the upper DBR layer 4 can also have the same layer structure as the lower DBR layer 2, but has a lower reflectance than the lower DBR layer 2 because it is necessary to emit light through the upper DBR layer 4.
  • an active layer 3 is sandwiched between an upper DBR layer 4 having a low reflectance and a lower DBR layer 2 having a high reflectance, and light emitted from the active layer 3 is interposed between the upper DBR layer 4 and the lower DBR layer 2.
  • the active layer 3 includes a lower clad layer 11, a lower guide layer 12, a light emitting layer 13, an upper guide layer 14, and an upper clad layer 15 which are sequentially laminated. That is, the active layer 3 includes a lower clad layer 11 disposed opposite to the lower side and the upper side of the light emitting layer 13 in order to “confine” the carrier and the light emission that cause radiative recombination in the light emitting layer 13.
  • a so-called double hetero (English abbreviation: DH) structure including the lower guide layer 12, the upper guide layer 14, and the upper cladding layer 15 is preferable in order to obtain high-intensity light emission.
  • the light emitting layer 13 can form a quantum well structure in order to control the light emission wavelength of a light emitting diode (LED). That is, the light emitting layer 13 can have a multilayer structure (laminated structure) of the well layer 17 and the barrier layer 18 having a barrier layer (also referred to as a barrier layer) 18 at both ends.
  • a barrier layer also referred to as a barrier layer
  • the thickness of the light emitting layer 13 is preferably in the range of 0.02 to 2 ⁇ m.
  • the conductivity type of the light emitting layer 13 is not particularly limited, and any of undoped, p-type and n-type can be selected. In order to increase the light emission efficiency, it is desirable that the crystallinity be undoped or the carrier concentration be less than 3 ⁇ 10 17 cm ⁇ 3 .
  • a known well layer material can be used.
  • AlGaAs, InGaAs, or AlGaInP can be used.
  • the layer thickness of the well layer 17 is preferably in the range of 3 to 30 nm. More preferably, it is in the range of 3 to 10 nm.
  • the material of the barrier layer 18 it is preferable to select a material suitable for the material of the well layer 17. In order to prevent the absorption in the barrier layer 18 and increase the light emission efficiency, it is preferable that the composition has a band gap larger than that of the well layer 17.
  • AlGaAs or InGaAs is used as the material of the well layer 17
  • AlGaAs or AlGaInP is preferable as the material of the barrier layer 18.
  • AlGaInP is used as the material of the barrier layer 18, it does not contain As which tends to create defects, so that it has high crystallinity and contributes to high output.
  • Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ⁇ X1 ⁇ 1, 0 ⁇ Y1 ⁇ 1) is used as the material of the well layer 17, the Al composition is higher than the material of the barrier layer 18 ( Al X4 Ga 1-X4 ) Y1 In 1-Y1 P (0 ⁇ X4 ⁇ 1, 0 ⁇ Y1 ⁇ 1, X1 ⁇ X4) or well layer (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ⁇ AlGaAs whose band gap energy is larger than X1 ⁇ 1, 0 ⁇ Y1 ⁇ 1) can be used.
  • the layer thickness of the barrier layer 18 is preferably equal to or greater than the layer thickness of the well layer 17.
  • the number of pairs in which the well layers 17 and the barrier layers 18 are alternately stacked is not particularly limited, but is preferably 2 or more and 40 or less. . That is, the active layer 11 preferably includes 2 to 40 well layers 17. Here, as a preferable range of the luminous efficiency of the active layer 11, it is preferable that the well layer 17 has five or more layers. On the other hand, since the well layer 17 and the barrier layer 18 have a low carrier concentration, the forward voltage (V F ) increases when the number of pairs is increased. For this reason, it is preferable that it is 40 pairs or less, and it is more preferable that it is 20 pairs or less.
  • the lower guide layer 12 and the upper guide layer 14 are provided on the lower surface and the upper surface of the light emitting layer 13, respectively, as shown in FIG. Specifically, the lower guide layer 12 is provided on the lower surface of the light emitting layer 13, and the upper guide layer 14 is provided on the upper surface of the light emitting layer 13.
  • the material of the lower guide layer 12 and the upper guide layer 14 a known compound semiconductor material can be used, and it is preferable to select a material suitable for the material of the light emitting layer 13.
  • a material suitable for the material of the light emitting layer 13 For example, AlGaAs or AlGaInP can be used.
  • the material of the lower guide layer 12 and the upper guide layer 14 is preferably AlGaAs or AlGaInP.
  • AlGaInP is used as the material of the lower guide layer 12 and the upper guide layer 14, since it does not contain As which tends to form defects, the crystallinity is high and contributes to high output.
  • Al composition is higher than the material of the guide layer 14 ( Al X4 Ga 1-X4 ) Y1 In 1-Y1 P (0 ⁇ X4 ⁇ 1, 0 ⁇ Y1 ⁇ 1, X1 ⁇ X4) or well layer (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ⁇ AlGaAs whose band gap energy is larger than X1 ⁇ 1, 0 ⁇ Y1 ⁇ 1) can be used.
  • the lower guide layer 12 and the upper guide layer 14 are provided to reduce the propagation of defects between the lower clad layer 11 and the upper clad layer 15 and the active layer 11, respectively.
  • the layer thickness of the lower guide layer 12 and the upper guide layer 14 is preferably 10 nm or more, and more preferably 20 nm to 100 nm.
  • the conductivity types of the lower guide layer 12 and the upper guide layer 14 are not particularly limited, and any of undoped, p-type, and n-type can be selected. In order to increase the light emission efficiency, it is desirable that the crystallinity be undoped or the carrier concentration be less than 3 ⁇ 10 17 cm ⁇ 3 .
  • the lower cladding layer 11 and the upper cladding layer 15 are provided on the lower surface of the lower guide layer 12 and the upper surface of the upper guide layer 14, respectively, as shown in FIG.
  • a known compound semiconductor material can be used as the material of the lower cladding layer 11 and the upper cladding layer 15, and it is preferable to select a material suitable for the material of the light emitting layer 13.
  • a material suitable for the material of the light emitting layer 13 For example, AlGaAs or AlGaInP can be used.
  • the material of the lower cladding layer 11 and the upper cladding layer 15 is preferably AlGaAs or AlGaInP.
  • AlGaInP is used as the material of the lower clad layer 11 and the upper clad layer 15, it does not contain As which easily creates defects, so that the crystallinity is high and contributes to high output.
  • Al composition is higher than the material of the cladding layer 15 ( Al X4 Ga 1-X4 ) Y1 In 1-Y1 P (0 ⁇ X4 ⁇ 1, 0 ⁇ Y1 ⁇ 1, X1 ⁇ X4) or well layer (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ⁇ AlGaAs whose band gap energy is larger than X1 ⁇ 1, 0 ⁇ Y1 ⁇ 1) can be used.
  • the lower cladding layer 11 and the upper cladding layer 15 are configured to have different polarities.
  • the carrier concentration and thickness of the lower clad layer 11 and the upper clad layer 15 can be in a known suitable range, and the conditions are preferably optimized so that the light emission efficiency of the active layer 11 is increased.
  • the lower and upper clad layers need not be provided. Further, by controlling the composition of the lower clad layer 11 and the upper clad layer 15, the warpage of the compound semiconductor layer 20 can be reduced.
  • the contact layer 5 is provided in order to reduce the contact resistance with the electrode.
  • the material of the contact layer 5 is preferably a material having a band gap larger than that of the light emitting layer 13.
  • the lower limit value of the carrier concentration of the contact layer 5 is preferably 5 ⁇ 10 17 cm ⁇ 3 or more and more preferably 1 ⁇ 10 18 cm ⁇ 3 or more in order to reduce the contact resistance with the electrode.
  • the upper limit value of the carrier concentration is desirably 2 ⁇ 10 19 cm ⁇ 3 or less at which the crystallinity is likely to decrease.
  • the thickness of the contact layer 5 is preferably 0.05 ⁇ m or more.
  • the upper limit value of the thickness of the contact layer 5 is not particularly limited, but is desirably 10 ⁇ m or less in order to make the cost for epitaxial growth within an appropriate range.
  • the light-emitting diode of the present invention can be incorporated into electronic devices such as lamps, backlights, mobile phones, displays, various panels, computers, game machines, lighting, etc., and machinery such as automobiles incorporating such electronic devices. it can.
  • FIG. 5 is a schematic cross-sectional view showing another example of a resonator type light emitting diode which is an example of a light emitting diode to which the present invention is applied.
  • a protective film is formed under the light emitting hole, and light is extracted from the light emitting hole through the protective film on the top surface of the mesa structure portion.
  • the protective film is not provided under the light emitting hole, and light is directly extracted from the light emitting hole 9b without the protective film.
  • the protective film 28 includes at least a part 28 c of the flat portion 6, the inclined side surface 7 a of the mesa structure portion 7, and the top of the mesa structure portion 7.
  • the electrode 7 has a flat portion 6 through the protective film 28, covering the peripheral area 7 ba of the surface 7 b and having a conduction window 28 b exposing the surface of the contact layer 5 inside the peripheral area 7 ba in plan view.
  • the protective film 28 of the second embodiment includes a portion 28 a that covers the inclined side surface 7 a of the mesa structure portion 7 and a portion 28 c that covers at least a part of the flat portion 6 (the mesa structure portion 7. And a portion 28ba covering the peripheral region 7ba of the top surface 7b of the mesa structure 7 and a contact layer inside the peripheral region 7ba in plan view. 5 has an energizing window 28b that exposes the surface of 5. That is, the energization window 28 b exposes the surface of the contact layer 5 other than the portion located below the peripheral region 7 ba on the top surface 7 b of the mesa structure 7.
  • An electrode layer (front electrode layer) 9 is formed on the protective film 8, and the protective film 8 is formed in a portion where no current flows between the electrode layer 9 and the back electrode 10.
  • the electrode layer (front surface electrode layer) 29 of the second embodiment includes a portion 29 a that covers a portion 28 a that covers the inclined side surface 7 a of the protective film 28, and a protective film 28.
  • the top surface 7b of the structure portion 7 includes a portion 29bb that covers the contact layer 5 so as to open the light emission hole 29b beyond the portion 28ba of the protective film 28.
  • the portion 29bb has both the first function and the second function.
  • the light-emitting diode according to the third embodiment to which the present invention is applied differs from the light-emitting diode according to the first embodiment in that there is no upper DBR reflection layer and a current diffusion layer is provided instead.
  • FIG. 6 is a schematic cross-sectional view of an example of a light emitting diode 300 according to the third embodiment. As shown in FIG. 6, the light emitting diode 300 has a configuration in which a current diffusion layer 40 is provided on the active layer 3.
  • the material of the current diffusion layer 40 for example, AlGaAs or the like can be used as the material of the current diffusion layer 40.
  • the thickness of the current diffusion layer 40 is preferably 0.1 ⁇ m or more and 10 ⁇ m or less. If the thickness is less than 0.1 ⁇ m, the current diffusion effect is insufficient, and if it exceeds 10 ⁇ m, the cost for epitaxial growth is too large for the effect.
  • the light-emitting diode according to the fourth embodiment to which the present invention is applied has no upper DBR reflective layer as compared with the light-emitting diode according to the first embodiment, and includes a reflective layer made of metal instead of the lower DBR reflective layer.
  • a difference is that a conductive substrate of a metal substrate or a substrate made of silicon, germanium or the like is provided as a substrate.
  • the upper clad layer may have a current diffusion function of the current diffusion layer 40 in the third embodiment.
  • the light emitting diode 400 is a light emitting diode including a reflective layer 52 made of a metal, a GaP layer 53, an active layer 54, and a contact layer 5 in this order on a conductive substrate 51. Further, a back electrode 56 is provided on the lower surface side of the conductive substrate 51.
  • the reflective layer 52 made of metal is preferably a metal having a reflectance of 90% or more with respect to the emission wavelength.
  • a metal having a reflectance of 90% or more with respect to the emission wavelength For example, gold (Au), silver (Ag), copper (Cu), aluminum (Al), or these Or an AgPdCu alloy (APC).
  • the active layer 54 includes an upper clad layer 63a, a light emitting layer 64, and a lower clad layer 63b.
  • the upper clad layer also has a current spreading function of the current spreading layer 40 in the third embodiment.
  • the thickness of the upper clad 63a is preferably 0.1 ⁇ m or more and 10 ⁇ m or less. If the thickness is less than 0.1 ⁇ m, the current diffusion effect is insufficient, and if it exceeds 10 ⁇ m, the cost for epitaxial growth is too large for the effect.
  • the GaP layer 53 has a low contact resistance and can be electrically connected to both the reflective layer 52 made of metal and the active layer 54 made of a compound semiconductor. Any material having such a function is not limited to GaP, but (Al x Ga (1-x) ) (1-y) In y P, (Al x Ga (1-x) ) (1-y) In y As or the like can be used.
  • the thickness of the GaP layer 53 is preferably 1 ⁇ m or more and 5 ⁇ m or less. This is because if the thickness is less than 1 ⁇ m, the light emission output decreases due to the stress at the bonding interface, and if it exceeds 5 ⁇ m, the cost for the epitaxial growth is too large for the effect.
  • metal Si, Ge, GaP, GaInP, SiC, or the like can be used.
  • Si substrates and Ge substrates are advantageous in that they are inexpensive and have excellent moisture resistance.
  • GaP, GaInP, and SiC substrates have the advantage that they have a thermal expansion coefficient close to that of the light emitting portion, excellent moisture resistance, and good thermal conductivity.
  • the metal substrate is excellent from the viewpoints of cost, mechanical strength, and heat dissipation, and, as will be described later, by having a structure in which a plurality of metal layers (metal plates) are laminated, the thermal expansion coefficient of the entire metal substrate is increased. There is an advantage that it can be adjusted.
  • a structure in which a plurality of metal layers (metal plates) are stacked can be employed.
  • metal layers metal plates
  • the number of layers of the second metal layer is preferably an odd number in total.
  • the first metal layer made of a material having a thermal expansion coefficient larger than that of the compound semiconductor layer 3. Since the thermal expansion coefficient of the metal substrate as a whole is close to the thermal expansion coefficient of the compound semiconductor layer, it is possible to suppress warping and cracking of the metal substrate when the compound semiconductor layer and the metal substrate are joined, and the light emitting diode This is because the production yield can be improved.
  • the first metal layer may be made of a material having a smaller thermal expansion coefficient than that of the compound semiconductor layer 2.
  • the thermal expansion coefficient of the metal substrate as a whole is close to the thermal expansion coefficient of the compound semiconductor layer, it is possible to suppress warping and cracking of the metal substrate when joining the compound semiconductor layer and the metal substrate, and the production yield of light emitting diodes It is because it can improve. From the above viewpoint, any of the two types of metal layers may be the first metal layer or the second metal layer.
  • a preferred example is a metal substrate composed of three layers of Cu / Mo / Cu. From the above viewpoint, the same effect can be obtained with a metal substrate composed of three layers of Mo / Cu / Mo, but the metal substrate composed of three layers of Cu / Mo / Cu is a Cu layer that has high mechanical strength and is easy to process Mo. Therefore, there is an advantage that processing such as cutting is easier than a metal substrate composed of three layers of Mo / Cu / Mo.
  • the thermal expansion coefficient of the entire metal substrate is, for example, 6.1 ppm / K for a three-layer metal substrate of Cu (30 ⁇ m) / Mo (25 ⁇ m) / Cu (30 ⁇ m), and Mo (25 ⁇ m) / Cu (70 ⁇ m). In the case of a metal substrate composed of three layers of / Mo (25 ⁇ m), it is 5.7 ppm / K.
  • the metal layer constituting the metal substrate is preferably made of a material having high thermal conductivity. This is because the heat dissipation of the metal substrate can be increased, the light emitting diode can emit light with high brightness, and the life of the light emitting diode can be extended.
  • thermo conductivity 420 W / m ⁇ K
  • alloys thereof are preferably used.
  • the metal layers are made of a material having a thermal expansion coefficient substantially equal to that of the compound semiconductor layer.
  • the material of the metal layer is preferably a material having a thermal expansion coefficient that is within ⁇ 1.5 ppm / K of the thermal expansion coefficient of the compound semiconductor layer.
  • the thermal conductivity of the entire metal substrate is, for example, 250 W / m ⁇ K for a three-layer metal substrate of Cu (30 ⁇ m) / Mo (25 ⁇ m) / Cu (30 ⁇ m), and Mo (25 ⁇ m) / Cu (70 ⁇ m) / In the case of a metal substrate composed of three layers of Mo (25 ⁇ m), it is 220 W / m ⁇ K.
  • the material for the metal protective film is preferably made of a metal containing at least one of chromium, nickel, chemically stable platinum, and gold having excellent adhesion.
  • the metal protective film is optimally composed of a layer combining nickel having good adhesion and gold having excellent chemical resistance.
  • the thickness of the metal protective film is not particularly limited, but in the range of 0.2 to 5 ⁇ m, preferably 0.5 to 3 ⁇ m, from the balance between resistance to the etching solution and cost. In the case of expensive gold, the thickness is desirably 2 ⁇ m or less.
  • FIG. 8 is a schematic cross-sectional view showing one step of a method for manufacturing a light emitting diode.
  • FIG. 9 is a schematic sectional view showing one process after FIG.
  • the compound semiconductor layer 20 shown in FIG. 8 is produced.
  • the compound semiconductor layer 20 is produced by sequentially laminating the lower DBR layer 2, the active layer 3, the upper DBR layer 4, and the contact layer 5 on the substrate 1.
  • a buffer layer may be provided between the substrate 1 and the lower DBR layer 2.
  • the buffer layer is provided in order to reduce the propagation of defects between the substrate 1 and the constituent layers of the active layer 3. For this reason, the buffer layer is not necessarily required if the quality of the substrate and the epitaxial growth conditions are selected.
  • the material of the buffer layer is preferably the same as that of the substrate to be epitaxially grown.
  • As the buffer layer a multilayer film made of a material different from that of the substrate can be used in order to reduce the propagation of defects.
  • the thickness of the buffer layer is preferably 0.1 ⁇ m or more, and more preferably 0.2 ⁇ m or more.
  • a known growth method such as a molecular beam epitaxial method (MBE) or a low pressure metal organic chemical vapor deposition method (MOCVD method) can be applied.
  • MBE molecular beam epitaxial method
  • MOCVD method low pressure metal organic chemical vapor deposition method
  • the substrate 1 used for the epitaxial growth of the compound semiconductor layer is subjected to a pretreatment such as a cleaning process or a heat treatment before the growth to remove surface contamination or a natural oxide film.
  • a pretreatment such as a cleaning process or a heat treatment before the growth to remove surface contamination or a natural oxide film.
  • Each layer constituting the compound semiconductor layer can be laminated by setting a substrate 1 having a diameter of 50 to 150 mm in an MOCVD apparatus and simultaneously epitaxially growing the substrate 1.
  • the MOCVD apparatus a commercially available large-sized apparatus such as a self-revolving type or a high-speed rotating type can
  • examples of the group III constituent element include trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga), and trimethylindium ((CH 3 ) 3 In) can be used.
  • a Mg doping material for example, biscyclopentadienyl magnesium (bis- (C 5 H 5 ) 2 Mg) or the like can be used.
  • a Si doping material for example, disilane (Si 2 H 6 ) or the like can be used.
  • phosphine (PH 3 ), arsine (AsH 3 ), or the like can be used as a raw material for the group V constituent element.
  • the carrier concentration, layer thickness, and temperature conditions of each layer can be selected as appropriate.
  • the compound semiconductor layer produced in this way has a good surface state with few crystal defects despite having the active layer 3.
  • the compound semiconductor layer 20 may be subjected to surface processing such as polishing corresponding to the element structure.
  • the back electrode 10 is formed on the back surface of the substrate 1.
  • the back electrode 10 of the n-type ohmic electrode is formed by sequentially stacking, for example, Au and AuGe by vapor deposition.
  • a compound semiconductor layer other than the mesa structure part that is, a contact layer, an upper DBR layer, and at least a part of the active layer
  • the contact layer, the upper DBR layer, the active layer, and at least part of the lower DBR layer are wet-etched.
  • a photoresist is deposited on the contact layer which is the uppermost layer of the compound semiconductor layer, and a resist pattern 23 having an opening 23a other than the mesa structure is formed by photolithography.
  • the size of the mesa-type structure portion scheduled to be formed is larger than the top surface of the “mesa-type structure portion” by about 10 ⁇ m above, below, left and right of each side.
  • the contact layer, the upper DBR layer, and the active layer other than the mesa structure portion, or the contact layer, the upper DBR layer, and the active layer And at least part of the lower DBR layer is removed by etching.
  • the etching removal can be performed with a wet etching time of 30 to 120 seconds. Thereafter, the resist is removed.
  • the plan view shape of the mesa structure portion is determined by the shape of the opening 23 a of the resist pattern 23.
  • An opening 23 a having a shape corresponding to a desired shape in plan view is formed in the resist pattern 23.
  • the depth of etching that is, to which layer of the compound semiconductor layer is removed by etching depends on the type of etchant and the etching time.
  • the etching depth (corresponding to “h” in FIG. 1) is substantially proportional to the etching time (sec), but the increasing rate of the etching width increases as the etching time increases. That is, as shown in FIG. 3, it is formed so that the increasing rate of the horizontal sectional area (or width or diameter) of the mesa structure portion increases as the depth increases (as it goes downward in the drawing).
  • This etching shape is different from the etching shape by dry etching. Therefore, it can be determined from the shape of the inclined slope of the mesa structure portion whether the mesa structure portion is formed by dry etching or wet etching.
  • a material for the protective film 8 is formed on the entire surface. Specifically, for example, SiO 2 is formed on the entire surface by sputtering.
  • FIG. 11 shows a plan view of the vicinity of the energization window 8 b of the protective film 8. Thereafter, the resist is removed.
  • the front electrode layer 9 is formed. That is, the front electrode layer 9 having the light emission holes 9 b is formed on the protective film 8 and on the contact layer 5 exposed from the energization window 8 b of the protective film 8. Specifically, a photoresist is deposited on the entire surface, and an electrode film including a portion corresponding to the light emission hole 9b by photolithography and a cut portion (street) between a plurality of light emitting diodes on the wafer substrate is unnecessary. A resist pattern having openings other than the portions is formed. Next, an electrode layer material is deposited.
  • the deposited metal tends to wrap around in order to deposit the electrode layer material on the inclined side surface of the mesa structure.
  • Vapor deposition is performed using a type of vapor deposition apparatus. Thereafter, the resist is removed.
  • the shape of the light emission hole 9b is determined by the shape of the opening of the resist pattern (not shown). A resist pattern having the opening shape corresponding to the shape of the desired light emission hole 9b is formed.
  • the light emitting diodes on the wafer substrate are separated into individual pieces. Specifically, for example, the street portion is cut by a dicing saw or a laser and cut into individual light emitting diodes on the wafer substrate.
  • the light emitting diode (second embodiment) of the present invention is different from the light emitting diode (first embodiment) only in the arrangement of the protective film and the electrode, and the manufacturing method thereof is the light emitting diode (first embodiment). It can carry out similarly to the manufacturing method of.
  • the manufacturing method of the light emitting diode (third embodiment) of the present invention is different from the manufacturing method of the light emitting diode (first embodiment) in the formation process of the compound semiconductor layer on the substrate 1 and the lower DBR layer. 2 and the active layer 3 are stacked, and then the current diffusion layer 40 is stacked on the active layer 3. The rest can be performed in the same manner as in the method of manufacturing the light emitting diode (first embodiment).
  • FIG. 12A to FIG. 12C are schematic cross-sectional views of a part of the metal substrate for explaining the manufacturing process of the metal substrate.
  • a first metal layer (first metal plate) 51b having a thermal expansion coefficient larger than the material of the active layer
  • a second metal layer (second metal) having a thermal expansion coefficient smaller than the material of the active layer. Plate) 51a, and hot-pressed to form.
  • first metal layers 51b and one substantially flat plate-like second metal layer 51a are prepared.
  • Cu having a thickness of 10 ⁇ m is used as the first metal layer 51b
  • Mo having a thickness of 75 ⁇ m is used as the second metal layer 51a.
  • the second metal layer 51a is inserted between the two first metal layers 51b, and these layers are stacked.
  • the first metal layer 51b is Cu
  • the second metal layer 51a is Mo
  • a metal substrate 1 having three layers is formed.
  • the metal substrate 51 has a thermal expansion coefficient of 5.7 ppm / K and a thermal conductivity of 220 W / m ⁇ K.
  • a metal protective film 51c that covers the entire surface of the metal substrate 1, that is, the upper surface, the lower surface, and the side surfaces is formed.
  • the side surface covered by the metal protective film is the outer peripheral side surface of the metal substrate (plate). Therefore, when the side surface of the metal substrate 51 of each light-emitting diode after separation is covered with the metal protective film 51c, a step of covering the side surface with the metal protective film is performed separately.
  • FIG. 12C shows a part of the metal substrate (plate) that is not on the outer peripheral end side, and the metal protective film on the outer peripheral side surface does not appear in the figure.
  • a known film forming method can be used for the metal protective film, but a plating method capable of forming a film on the entire surface including the side surface is most preferable.
  • nickel is then plated with gold, and the metal substrate 51 in which the upper surface, side surfaces, and lower surface of the metal substrate are covered with the nickel film and the gold film (metal protective film) can be produced.
  • the plating material is not particularly limited, and known materials such as copper, silver, nickel, chromium, platinum, and gold can be applied. However, a layer that combines nickel having good adhesion and gold having excellent chemical resistance is optimal.
  • known techniques and chemicals can be used as the plating method.
  • An electroless plating method that does not require an electrode is simple and desirable.
  • a plurality of epitaxial layers are grown on one surface 61 a of a semiconductor substrate (growth substrate) 61 to form an epitaxial stacked body 80 including an active layer 54.
  • the semiconductor substrate 61 is a substrate for forming the epitaxial stacked body 80, and is, for example, a Si-doped n-type GaAs single crystal substrate in which one surface 61a is inclined by 15 ° from the (100) plane.
  • a gallium arsenide (GaAs) single crystal substrate can be used as a substrate on which the epitaxial laminated body 80 is formed.
  • a metal organic chemical vapor deposition (MOCVD) method As a method for forming the active layer 54, a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, a liquid phase epitaxial (Liquid Phase EpiLex) method, or the like. Can be used.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • Liquid Phase EpiLex Liquid Phase EpiLex
  • Each layer is epitaxially grown using Note that biscyclopentadienyl magnesium ((C 5 H 5 ) 2 Mg) is used as a Mg doping material. Further, disilane (Si 2 H 6 ) is used as a Si doping raw material. Further, phosphine (PH 3 ) or arsine (AsH 3 ) is used as a raw material for the group V constituent element.
  • the p-type GaP layer 53 is grown at 750 ° C., for example, and the other epitaxial growth layers are grown at 730 ° C., for example.
  • a buffer layer 62 a made of n-type GaAs doped with Si is formed on one surface 61 a of the growth substrate 61.
  • the buffer layer 62a for example, n-type GaAs doped with Si is used, the carrier concentration is 2 ⁇ 10 18 cm ⁇ 3 , and the layer thickness is 0.2 ⁇ m.
  • the etching stop layer 62b is formed on the buffer layer 62a.
  • the etching stop layer 62b is a layer for preventing the cladding layer and the light emitting layer from being etched when the semiconductor substrate is etched away.
  • the contact layer 5 made of, for example, Si-doped n-type Al x Ga 1-x As (0.1 ⁇ X ⁇ 0.3) is formed on the etching stop layer 62b.
  • a clad layer 63 a made of n-type (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P doped with Si is formed on the contact layer 5.
  • a light emitting layer 64 having a laminated structure of three pairs of a well layer / barrier layer made of Al 0.17 Ga 0.83 As / Al 0.3 Ga 0.7 As is formed on the cladding layer 63a. Form a film.
  • a p-type GaP layer 53 doped with Mg is formed on the cladding layer 63b.
  • the affixing surface is adjusted (that is, mirror-finished.
  • the surface roughness is 0.2 nm or less).
  • a guide layer may be provided between the clad layer and the light emitting layer.
  • a reflective layer 52 made of, for example, Au is formed on the p-type GaP layer 53.
  • a barrier layer (not shown) and / or a bonding layer (not shown) may be formed on the reflective layer 52.
  • the barrier layer can suppress the metal contained in the metal substrate from diffusing and reacting with the reflective layer 52.
  • a material for the barrier layer nickel, titanium, platinum, chromium, tantalum, tungsten, molybdenum, or the like can be used.
  • the barrier layer can improve the performance of the barrier by a combination of two or more kinds of metals, for example, a combination of platinum and titanium. Even if a barrier layer is not provided, the bonding layer can have the same function as the barrier layer by adding these materials to the bonding layer.
  • the bonding layer is a layer for bonding the compound semiconductor layer 10 including the active layer 54 to the metal substrate 1 with good adhesion.
  • an Au-based eutectic metal that is chemically stable and has a low melting point is used.
  • the Au-based eutectic metal include eutectic compositions of alloys such as AuGe, AuSn, AuSi, and AuIn.
  • the semiconductor substrate 61 on which the epitaxial laminated body 80, the reflective layer 6 and the like are formed, and the metal substrate 51 formed in the metal substrate manufacturing process are carried into a decompression device, and the bonding is performed. It arrange
  • a load of 500 kg is applied to bond the bonding surfaces of the bonding layers. And the bonding surface 51A of the metal substrate 51 are bonded to form a bonded structure 90.
  • the semiconductor substrate 61 and the buffer layer 62a are selectively removed from the bonded structure 90 with an ammonia-based etchant.
  • the metal substrate of the present invention is covered with the metal protective film and has high resistance to the etchant, the quality of the metal substrate is prevented from being deteriorated.
  • the etching stop layer 62b is selectively removed with a hydrochloric acid-based etchant. Since the metal substrate of the present invention is covered with a metal protective film and has high resistance to an etchant, the metal substrate is prevented from being deteriorated in quality.
  • a back electrode 56 is formed on the back surface of the metal substrate 51.
  • An etchant used for wet etching is not limited, but an ammonia-based etchant (for example, a mixed solution of ammonia / hydrogen peroxide solution) is suitable for an As-based compound semiconductor material such as AlGaAs, and P such as AlGaInP.
  • An iodine-based etchant (for example, potassium iodide / ammonia) is suitable for a compound semiconductor material, a phosphoric acid / hydrogen peroxide mixture is suitable for an AlGaAs system, and a bromomethanol mixture is suitable for a P-system. Yes.
  • a phosphoric acid mixed solution may be used in a structure formed only of an As system
  • an ammonia mixed solution may be used in an As system structure portion
  • an iodine mixed solution may be used in a P system structure portion in a structure in which an As / P system is mixed.
  • the compound semiconductor layer as described above that is, in the case of the uppermost AlGaAs contact layer 5, the AlGaInP clad layer 63a, the AlGaAs light emitting layer 64, the AlGaInP clad layer 63b, and the GaP layer 53
  • etchants having high etching rates for the As-based contact layer 5 and the light-emitting layer 64 and the other P-based layers.
  • iodine-based etchant for example, an etchant in which iodine (I), potassium iodide (KI), pure water (H 2 O), and ammonia water (NH 4 OH) are mixed can be used.
  • ammonia-based etchant for example, an ammonia / hydrogen peroxide mixed solution (NH 4 OH: H 2 O 2 : H 2 O) can be used.
  • the contact layer 5 made of AlGaAs in the portion other than the mesa structure portion is removed by etching using an ammonia-based etchant.
  • the cladding layer 55 made of AlGaInP which is the next layer, functions as an etching stop layer, so that it is not necessary to strictly control the etching time, but for example, the thickness of the contact layer 5 is 0.05 ⁇ m. If so, etching may be performed for about 10 seconds.
  • the cladding layer 55 made of AlGaInP other than the mesa structure is removed by etching using an iodine-based etchant.
  • the etching rate is 0 when an etchant mixed at a ratio of 500 cc of iodine (I), 100 g of potassium iodide (KI), 2000 cc of pure water (H 2 O) and 90 cc of aqueous ammonia hydroxide (NH 4 OH) is used. It was 72 ⁇ m / min.
  • the thickness of the cladding layer 55 If the thickness is about 4 ⁇ m, etching may be performed for about 6 minutes.
  • the light emitting layer 64 made of AlGaAs other than the mesa structure is removed by etching using an ammonia-based etchant. Also in this etching, the cladding layer 63b made of AlGaInP, which is the next layer, functions as an etching stop layer, so that it is not necessary to strictly control the etching time, but the thickness of the light emitting layer 64 is about 0.25 ⁇ m. Then, the etching may be performed for about 40 seconds.
  • the cladding layer 63b made of AlGaInP other than the mesa structure portion is etched away using an iodine-based etchant.
  • an iodine-based etchant it is necessary to stop the etching up to the GaP layer 53.
  • the etching time needs to be 4 minutes or less.
  • the subsequent protective film forming process, the street and contact layer protective film removing process, and the front electrode layer forming process are performed in the same manner as in the method of manufacturing the light emitting diode (first embodiment). be able to.
  • the light emitting diodes on the wafer substrate are singulated by performing etching and laser cutting in order. Specifically, after forming a resist pattern having an opening in a street portion, the compound semiconductor layer and the reflective layer on the street are removed by etching, and then the metal substrate is laser-cut to complete singulation. Selection of the layer to be etched is not limited to the above case, such as etching only the compound semiconductor layer or laser cutting after etching the metal protective layer in addition to the compound semiconductor layer and the reflective layer.
  • a metal protective film may be formed on the side surfaces of the cut metal substrate of the separated light emitting diodes under the same conditions as the conditions for forming the upper and lower metal protective films.
  • a light-emitting diode lamp in which a light-emitting diode chip was mounted on a substrate was prepared for characteristic evaluation.
  • Example 1 The light-emitting diode of Example 1 is an example of the light-emitting diode of the first embodiment.
  • an epitaxial wafer was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of n-type GaAs single crystal doped with Si.
  • the GaAs substrate had a (100) plane as a growth plane and a carrier concentration of 2 ⁇ 10 18 cm ⁇ 3 .
  • the layer thickness of the GaAs substrate was about 250 ⁇ m.
  • the compound semiconductor layer is an n-type buffer layer made of GaAs doped with Si, and 40 pairs of repeating structures of Al 0.9 Ga 0.1 As and Al 0.1 Ga 0.9 As doped with Si.
  • n-type lower DBR reflective layer n-type lower clad layer made of Si-doped Al 0.4 Ga 0.6 As, lower guide layer made of Al 0.25 Ga 0.75 As, GaAs / Al 0. Well layer / barrier layer composed of three pairs of 15 Ga 0.85 As, upper guide layer composed of Al 0.25 Ga 0.75 As, p-type composed of C 0.4 doped Al 0.4 Ga 0.6 As Upper clad layer, p-type upper DBR reflective layer having 5 pairs of repetitive structures of C-doped Al 0.9 Ga 0.1 As and Al 0.1 Ga 0.9 As, C-doped p-type Al 0 .1 Ga 0.9 It is a contact layer made of As.
  • a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 50 mm and a thickness of 250 ⁇ m by using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer.
  • MOCVD apparatus metal organic chemical vapor deposition apparatus method
  • trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga) and trimethylindium ((CH 3 ) 3 In) are used as the raw materials for the group III constituent elements did.
  • tetrabromomethane (CBr 4 ) was used as a doping material for C.
  • disilane (Si 2 H 6 ) was used as a Si doping material.
  • phosphine (PH 3 ) and arsine (AsH 3 ) were used as raw materials for the group V constituent elements.
  • the growth temperature of each layer was 700 ° C.
  • the buffer layer made of GaAs has a carrier concentration of about 2 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
  • Lower DBR reflection layer and the carrier concentration of about 1 ⁇ 10 18 cm -3, and Al 0.9 Ga 0.1 As that were about 54nm thickness, a carrier concentration of about 1 ⁇ 10 18 cm -3, layer thickness 40 pairs of Al 0.1 Ga 0.9 As having a thickness of about 51 nm were alternately laminated.
  • the lower cladding layer had a carrier concentration of about 1 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 54 nm.
  • the lower guide layer was undoped and had a thickness of about 50 nm.
  • the well layer was undoped GaAs having a thickness of about 7 nm
  • the barrier layer was undoped Al 7 .5 Ga 0.85 As having a thickness of about 7 nm.
  • Three pairs of well layers and barrier layers were alternately laminated.
  • the upper guide layer was undoped and had a thickness of about 50 nm.
  • the upper cladding layer had a carrier concentration of about 1 ⁇ 10 18 cm ⁇ 3 and a layer thickness of 54 nm.
  • the contact layer made of Al 0.1 Ga 0.9 As had a carrier concentration of about 3 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 250 nm.
  • an n-type ohmic electrode was formed on the back surface of the substrate by vacuum deposition so that the thickness of AuGe and Ni alloy was 0.5 ⁇ m, Pt was 0.2 ⁇ m, and Au was 1 ⁇ m. .
  • wet etching was performed for 60 seconds to form a mesa structure portion and a flat portion.
  • the contact layer, the upper DBR reflection layer, and the active layer are all removed, and a mesa shape having a rectangular shape in plan view with a top surface size of 190 ⁇ m ⁇ 190 ⁇ m, a height h of 7 ⁇ m, and a width w of 5 ⁇ m.
  • a structure part (excluding a protective film and an electrode film) was formed.
  • a protective film made of SiO 2 was formed to a thickness of about 0.5 ⁇ m. Then, after patterning with a resist (AZ5200NJ (manufactured by Clariant)), using a buffered hydrofluoric acid, a concentric circular opening (outer diameter dout: 166 ⁇ m, inner diameter din: 154 ⁇ m) (see FIG. 11) and street Part openings were formed.
  • a resist AZ5200NJ (manufactured by Clariant)
  • a concentric circular opening (outer diameter dout: 166 ⁇ m, inner diameter din: 154 ⁇ m) (see FIG. 11) and street Part openings were formed.
  • a front surface electrode film
  • a resist AZ5200NJ (manufactured by Clariant)
  • AuBe 1.2 ⁇ m of Au and 0.15 ⁇ m of AuBe are sequentially deposited and circularly viewed in plan view by lift-off.
  • a front surface electrode p-type ohmic electrode having a light emission hole 9b (diameter: 150 ⁇ m) and having a long side of 350 ⁇ m and a short side of 250 ⁇ m was formed.
  • heat treatment was performed at 450 ° C. for 10 minutes to form an alloy, and low resistance p-type and n-type ohmic electrodes were formed.
  • the light leakage prevention film 16 was formed.
  • a resist AZ5200NJ (manufactured by Clariant)
  • Ti 0.5 ⁇ m and Au 0.17 ⁇ m are sequentially deposited, and lift-off is performed.
  • the light leakage prevention film 16 was formed.
  • the compound semiconductor layer side was cut at a street portion using a dicing saw to form a chip.
  • the crushing layer and dirt by dicing were removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to produce the light emitting diode of the example.
  • This light-emitting diode lamp was manufactured by supporting (mounting) a mount with a die bonder, wire-bonding a p-type ohmic electrode and a p-electrode terminal with a gold wire, and sealing with a general epoxy resin.
  • All of the 100 light-emitting diode lamps produced have the same characteristics, leak (short circuit) when the protective film becomes discontinuous, and the electrode metal film becomes discontinuous. There was no defect that was thought to be due to poor energization.
  • FIG. 16 is a graph showing the measurement result of the light spectrum (see the schematic diagram on the right side of the graph) immediately above the light emitting diode.
  • the vertical axis represents light intensity
  • the horizontal axis represents wavelength.
  • the line width of the emission spectrum was narrow (high monochromaticity), and the half width (HWHM) was 6.3 nm.
  • FIG. 17 is a graph showing the measurement results of the directivity of the emitted light (see the schematic diagram on the right side of the graph).
  • the circumference from “ ⁇ 1” to “1” on the horizontal axis in the graph represents 13000 as the light intensity (Int.). Therefore, for example, when the intensity of light is 6500 in a certain direction, a graph is drawn on the circumference leading from “ ⁇ 0.5” to “0.5” on the horizontal axis in that direction. Further, for example, in the light emitting diode of the example, there is a graph on a circumference (not shown) leading from about “ ⁇ 0.9” to “0.9” in the direction of ⁇ 10 ° from directly above (90 °).
  • the light intensity is about 90% of 13000 in that range.
  • the light emitting diode of the example had high intensity (about 70% or more of 13000) in a range of about ⁇ 15 ° from directly above the light emitting hole, and showed high directivity.
  • Example 2 The light emitting diode of Example 2 is an example of the light emitting diode of the fourth embodiment (when a metal substrate is used).
  • a 75 ⁇ m thick Mo layer (foil, plate) is sandwiched between two 10 ⁇ m thick Cu layers (foil, plate) and thermocompression bonded to a 95 ⁇ m thick metal plate plate (before cutting into individual pieces). Formed. The upper and lower surfaces of the metal plate plate were polished to make the upper surface a glossy surface, and then washed with an organic solvent to remove dirt.
  • a 2 ⁇ m Ni layer and a 1 ⁇ m Au layer are sequentially formed on the entire surface of the metal plate plate as a metal protective film by electroless plating to produce a metal substrate (metal substrate before cutting into individual pieces) 51. did.
  • an epitaxial wafer having an emission wavelength of 730 nm was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of n-type GaAs single crystal doped with Si.
  • the GaAs substrate the plane inclined by 15 ° from the (100) plane in the (0-1-1) direction was used as the growth plane, and the carrier concentration was set to 2 ⁇ 10 18 cm ⁇ 3 .
  • the layer thickness of the GaAs substrate was about 0.5 ⁇ m.
  • an n-type buffer layer 62a made of GaAs doped with Si
  • an etching stop layer 62b made of Si-doped (Al 0.5 Ga 0.5 ) 0.5 In 0.5 P
  • Si-doped the n-type contact layer 5 made of Al0.3GaAs of doped Si (Al 0.7 Ga 0.3) 0.5 in consisting 0.5 P n-type upper cladding layer 63a, Al 0.4 Ga
  • An upper guide layer made of 0.6 As, a well layer / barrier layer 64 made of a pair of Al 0.17 Ga 0.83 As / Al 0.3 Ga 0.7 As, and Al 0.4 Ga 0.6 As
  • a lower guide layer Mg-doped (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P p-type lower cladding layer 63b, (Al 0.5 Ga 0.5 ) 0.5 In 0.
  • a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 50 mm and a thickness of 250 ⁇ m by using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer.
  • MOCVD apparatus metal organic chemical vapor deposition apparatus method
  • trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga) and trimethylindium ((CH 3 ) 3 In) are used as the raw materials for the group III constituent elements did.
  • biscyclopentadienyl magnesium bis- (C 5 H 5 ) 2 Mg
  • disilane (Si 2 H 6 ) was used as a Si doping material.
  • phosphine (PH 3 ) and arsine (AsH 3 ) were used as raw materials for the group V constituent elements.
  • the growth temperature of each layer the p-type GaP layer was grown at 750 ° C. The other layers were grown at 700 ° C.
  • the buffer layer made of GaAs has a carrier concentration of about 2 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
  • the etching stop layer had a carrier concentration of 2 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
  • the contact layer had a carrier concentration of about 2 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.05 ⁇ m.
  • the upper cladding layer had a carrier concentration of about 1 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 3.0 ⁇ m.
  • the well layer was undoped Al 0.17 Ga 0.83 As with a thickness of about 7 nm, and the barrier layer was undoped Al 0.3 Ga 0.7 As with a thickness of about 19 nm.
  • the lower guide layer was undoped and had a thickness of about 50 nm.
  • the lower cladding layer had a carrier concentration of about 8 ⁇ 10 17 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
  • the intermediate layer had a carrier concentration of about 8 ⁇ 10 17 cm ⁇ 3 and a layer thickness of about 0.05 ⁇ m.
  • the GaP layer had a carrier concentration of about 3 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 3.5 ⁇ m.
  • the GaP layer was polished up to a depth of about 1 ⁇ m from the surface and mirror-finished. By this mirror finishing, the roughness of the surface of the current diffusion layer was set to 0.18 nm.
  • a reflective layer made of Au was formed to a thickness of 0.7 ⁇ m on the GaP layer. Further, a Ti layer having a thickness of 0.5 ⁇ m was formed as a barrier layer on the reflective layer, and an AuGe layer having a thickness of 1.0 ⁇ m was formed as a bonding layer on the barrier layer.
  • a structure in which a compound semiconductor layer, a reflective layer, and the like are formed on a GaAs substrate and a metal substrate are arranged so as to face each other and carried into a decompression device, and heated at 400 ° C., They were joined with a load of 500 kg to form a joined structure.
  • the GaAs substrate which is a growth substrate for the compound semiconductor layer, and the buffer layer were selectively removed from the bonded structure with an ammonia-based etchant, and the etching stop layer was selectively removed with a hydrochloric acid-based etchant.
  • wet etching is performed for 40 seconds, and the upper guide layer in a portion other than the mesa structure portion, The light emitting layer 64 and the lower guide layer were removed.
  • wet etching was performed for 50 seconds using the iodine-based etchant to remove the lower clad layer 63b other than the mesa structure. A mesa structure was thus formed.
  • a protective film made of SiO 2 was formed to a thickness of about 0.5 ⁇ m. Thereafter, after forming a resist pattern, an opening (see FIG. 11) having a concentric circular shape (outer diameter dout: 166 ⁇ m, inner diameter din: 154 ⁇ m) and a street portion opening were formed using buffered hydrofluoric acid.
  • a front surface electrode (film)
  • vacuum deposition is performed so that the thickness of AuGe and Ni alloy is 0.5 ⁇ m, Pt is 0.2 ⁇ m, and Au is 1 ⁇ m.
  • a front surface electrode (n-type ohmic electrode) having a long side of 350 ⁇ m and a short side of 250 ⁇ m having a light emission hole 9b having a circular shape (diameter: 150 ⁇ m) in plan view was formed by lift-off. Thereafter, heat treatment was performed at 450 ° C. for 10 minutes to form an alloy, and a low-resistance n-type ohmic electrode was formed.
  • This light-emitting diode lamp was manufactured by supporting (mounting) a mount with a die bonder, wire-bonding a p-type ohmic electrode and a p-electrode terminal with a gold wire, and sealing with a general epoxy resin.
  • All of the 100 light-emitting diode lamps produced have the same characteristics, leak (short circuit) when the protective film becomes discontinuous, and the electrode metal film becomes discontinuous. There was no defect that was thought to be due to poor energization.
  • a light-emitting diode having a wavelength of 850 nm having a structure in which a thick film is grown and a substrate is removed by a liquid phase epitaxial method is shown.
  • An AlGaAs layer was grown on a GaAs substrate using a slide boat type growth apparatus.
  • a p-type GaAs substrate was set in a substrate storage groove of a slide boat type growth apparatus, and Ga metal, GaAs polycrystal, metal Al, and a dopant were put in a crucible prepared for growth of each layer.
  • the growing layer has a four-layer structure of a transparent thick film layer (first p-type layer), a lower clad layer (p-type clad layer), an active layer, and an upper clad layer (n-type clad layer). did.
  • a slide boat type growth apparatus in which these raw materials are set is set in a quartz reaction tube, heated to 950 ° C. in a hydrogen stream, dissolved, and then the ambient temperature is lowered to 910 ° C. After pressing and bringing into contact with the raw material solution (melt), the temperature is lowered at a rate of 0.5 ° C./min. After reaching the predetermined temperature, the operation of repeatedly touching each raw material solution after pressing the slider is repeated repeatedly. Specifically, after contact with the melt, the ambient temperature was lowered to 703 ° C. to grow the n-clad layer, and then the slider was pushed to separate the raw material solution from the wafer to complete the epitaxial growth.
  • the epitaxial substrate was taken out, the surface of the n-type GaAlAs cladding layer was protected, and the p-type GaAs substrate was selectively removed with an ammonia-hydrogen peroxide etchant. Thereafter, gold electrodes were formed on both sides of the epitaxial wafer, and a surface electrode in which a wire bonding pad having a diameter of 100 ⁇ m was arranged at the center was formed using an electrode mask having a long side of 350 ⁇ m. On the back electrode, ohmic electrodes having a diameter of 20 ⁇ m were formed at intervals of 80 ⁇ m. Thereafter, separation and etching were performed by dicing, so that a 350 ⁇ m square light-emitting diode in which the n-type AlGaAs layer was on the surface side was produced.
  • the line width of the emission spectrum was wide, and the half width (HWHM) was 42 nm.
  • the present invention can be applied to a light emitting diode and a manufacturing method thereof.

Abstract

Provided is a light-emitting diode having a protective film and an electrode film thereabove formed to a uniform thickness, and a method for manufacturing the light-emitting diode. The light-emitting diode has, on an upper part, a flat portion and a mesa-structure unit having a sloped side surface and a top surface. At least some of each of the flat portion and the mesa-structure portion is covered by the protective film and the electrode film in the stated order. The sloped side surface is formed by wet etching, and the horizontal sectional area is formed continuously smaller toward the top surface. The protective film covers the sloped side surface, a peripheral region of the top surface, and at least some of the flat portion; and has an electrification window through which a portion of the front surface of a compound semiconductor layer is exposed within the peripheral region as seen from above. An electrode layer is a continuous film making direct contact with the front surface of the compound semiconductor layer exposed through the electrification window, and covering at least some of the protective film formed on the flat portion, the electrode layer formed so that a light emission hole is provided in the top surface of the mesa-structure portion.

Description

発光ダイオード及びその製造方法Light emitting diode and manufacturing method thereof
　本発明は、発光ダイオード及びその製造方法に関するものである。
本願は、２０１１年３月１４日に日本に出願された特願２０１１－０５５８３３号、および２０１１年９月１６日に日本に出願された特願２０１１－２０３４４９号に基づき優先権を主張し、それらの内容をここに援用する。 The present invention relates to a light emitting diode and a method for manufacturing the same.
This application claims priority based on Japanese Patent Application No. 2011-055833 filed in Japan on March 14, 2011 and Japanese Patent Application No. 2011-203449 filed in Japan on September 16, 2011. Is incorporated herein by reference.
　発光層で発生した光を素子上面の一部から取り出す点光源型の発光ダイオードが知られている。この型の発光ダイオードにおいて、発光層における通電領域をその面内の一部に制限するための電流狭窄構造を有するものが知られている（例えば、特許文献１）。電流狭窄構造を有する発光ダイオードでは、発光領域が限定され、その領域の真上に設けられた光射出孔から光を射出させるため、高い光出力が得られると共に射出させた光を光学部品等に効率良く取り込むことが可能である。 A point light source type light emitting diode that extracts light generated in the light emitting layer from a part of the upper surface of the element is known. As this type of light emitting diode, one having a current confinement structure for limiting a current-carrying region in a light emitting layer to a part of the surface is known (for example, Patent Document 1). In a light emitting diode having a current confinement structure, a light emitting region is limited, and light is emitted from a light emitting hole provided immediately above the region, so that high light output is obtained and the emitted light is applied to an optical component or the like. It is possible to capture efficiently.
　点光源型の発光ダイオードのうち特に、共振器型発光ダイオード（ＲＣＬＥＤ：Resonant-Cavity Light Emitting Diode）は、２つのミラーからなる共振器内で発生する定在波の腹が共振器内に配置した発光層に位置するように構成すると共に、光出射側のミラーの反射率を基板側のミラーの反射率よりも低く設定することによりレーザ発振させないでＬＥＤモードで動作する、高効率の発光素子である（特許文献２，３）。共振器型発光ダイオードは通常の発光ダイオードと比較して、共振器構造の効果によって、発光スペクトル線幅が狭い、出射光の指向性が高い、自然放出によるキャリア寿命が短いため高速応答が可能である、等の特徴があるため、センサなどに適している。 Among the point light source type light emitting diodes, in particular, the resonator type light emitting diode (RCLED: Resonant-Cavity Light Emitting Diode) has antinodes of standing waves generated in the resonator composed of two mirrors arranged in the resonator. A high-efficiency light-emitting element that is configured to be located in the light-emitting layer and that operates in LED mode without causing laser oscillation by setting the reflectance of the mirror on the light emission side to be lower than that of the mirror on the substrate side. Yes (Patent Documents 2 and 3). Resonator-type light-emitting diodes can respond faster than ordinary light-emitting diodes due to the effect of the resonator structure due to the narrow emission spectrum line width, high directivity of emitted light, and short carrier lifetime due to spontaneous emission. Because there is a feature such as, there is a suitable sensor.
　共振器型発光ダイオードにおいて、基板に平行な方向において発光領域を狭くするために上部ミラー層及び活性層等をピラー構造とし、そのピラー構造の頂面の光取り出し面に光出射用の開口を有する層を備えた構成が知られている（例えば、特許文献４）。
　図１８は、基板１３１上に、下部ミラー層１３２と、活性層１３３と、上部ミラー層１３４と、コンタクト層１３５とを順に備えた共振器型発光ダイオードであって、活性層１３３と、上部ミラー層１３４と、コンタクト層１３５とをピラー構造１３７とし、ピラー構造１３７及びその周囲を保護膜１３８で被覆し、その保護膜１３８上に電極膜１３９を形成し、ピラー構造１３７の頂面１３７ａ（光取り出し面）において電極膜１３９に光出射用の開口１３９ａを形成した共振器型発光ダイオードを示す。符号１４０は裏面電極である。 In the resonator type light emitting diode, the upper mirror layer and the active layer have a pillar structure in order to narrow the light emitting region in the direction parallel to the substrate, and the light extraction surface on the top surface of the pillar structure has an opening for light emission. A configuration including a layer is known (for example, Patent Document 4).
FIG. 18 shows a resonator type light emitting diode having a lower mirror layer 132, an active layer 133, an upper mirror layer 134, and a contact layer 135 in this order on a substrate 131. The active layer 133, the upper mirror The layer 134 and the contact layer 135 are formed as a pillar structure 137, the pillar structure 137 and its periphery are covered with a protective film 138, an electrode film 139 is formed on the protective film 138, and the top surface 137a of the pillar structure 137 (light A resonator type light emitting diode in which an opening 139a for light emission is formed in the electrode film 139 on the extraction surface) is shown. Reference numeral 140 denotes a back electrode.
　図１８で示したようなピラー構造の電流狭窄構造は、共振器型ではない点光源型の発光ダイオードにおいても適用が可能である。 The current confinement structure having a pillar structure as shown in FIG. 18 can be applied to a point light source type light emitting diode which is not a resonator type.
特開２００５－３１８４２号公報JP 2005-31842 A 特開２００２－７６４３３号公報JP 2002-76433 A 特開２００７－２９９９４９号公報JP 2007-299949 A 特開平９－２８３８６２号公報JP-A-9-283862
　上記ピラー構造を形成する際、活性層等を成膜した後の、ピラー構造以外の部分の除去を異方性のドライエッチングによって実施するため、図１８に示すように、ピラー構造１３７の側面１３７ｂは基板１３１に対して垂直あるいは急傾斜に形成されてしまう。このピラー構造の側面には通常、蒸着法やスパッタ法によって保護膜が形成された後、蒸着法によって電極用金属（例えば、Ａｕ）膜を形成するが、この垂直あるいは急傾斜の側面に、保護膜や電極用金属膜を一様な膜厚で形成するのは容易ではなく、不連続な膜になりやすいという問題がある。保護膜が不連続な膜になった場合（図１８中の符号Ａ）には、その不連続部分に電極用金属膜が入り込んで活性層等に接触してリークの原因になる。また、電極用金属膜が不連続な膜になった場合（図１８中の符号Ｂ）には、通電不良の原因になる。 When the pillar structure is formed, in order to remove portions other than the pillar structure after forming the active layer and the like by anisotropic dry etching, as shown in FIG. 18, the side surface 137b of the pillar structure 137 is formed. Is formed perpendicularly or steeply to the substrate 131. Usually, a protective film is formed on the side surface of the pillar structure by vapor deposition or sputtering, and then a metal (for example, Au) film for electrodes is formed by vapor deposition. The protective film is formed on the vertical or steeply inclined side surface. It is not easy to form a film or a metal film for an electrode with a uniform film thickness, and there is a problem that it is likely to be a discontinuous film. When the protective film becomes a discontinuous film (symbol A in FIG. 18), the electrode metal film enters the discontinuous portion and comes into contact with the active layer or the like, causing a leak. In addition, when the electrode metal film becomes a discontinuous film (symbol B in FIG. 18), it causes a conduction failure.
　また、ピラー構造以外の部分の除去をドライエッチングで行うと、高価な装置が必要となり、エッチング時間も長くかかるという問題もある。 In addition, if the portion other than the pillar structure is removed by dry etching, there is a problem that an expensive apparatus is required and it takes a long etching time.
　本発明は、上記事情を鑑みてなされたものであり、保護膜及びその上に形成された電極膜が均一な膜厚で形成された発光ダイオード、及び、リークや通電不良を低減して歩留まりが向上すると共に従来より低コストで製造可能な発光ダイオードの製造方法を提供することを目的とする。 The present invention has been made in view of the above circumstances, and a protective film and a light-emitting diode in which an electrode film formed thereon is formed with a uniform film thickness, and yield is reduced by reducing leakage and poor conduction. An object of the present invention is to provide a method of manufacturing a light-emitting diode that can be manufactured at a lower cost than ever before.
　本発明は、以下の手段を提供する。
（１）基板上に反射層と活性層を含む化合物半導体層とを備えた発光ダイオードであって、その上部に平坦部と、傾斜側面及び頂面を有するメサ型構造部とを有し、前記平坦部及び前記メサ型構造部はそれぞれ、少なくとも一部は保護膜、電極膜によって順に覆われてなり、前記メサ型構造部は少なくとも前記活性層の一部を含むものであって、前記傾斜側面はウェットエッチングによって形成されてなると共に前記頂面に向かって水平方向の断面積が連続的に小さく形成されてなり、前記保護膜は、前記平坦部の少なくとも一部と、前記メサ型構造部の前記傾斜側面と、前記メサ型構造部の前記頂面の周縁領域とを少なくとも覆うとともに、平面視して前記周縁領域の内側に前記化合物半導体層の表面の一部を露出する通電窓を有し、前記電極層は、前記通電窓から露出された化合物半導体層の表面に直接接触すると共に、前記平坦部上に形成された保護膜の一部を少なくとも覆い、前記メサ型構造部の頂面上に光射出孔を有するように形成された連続膜である、ことを特徴とする発光ダイオード。
　なお、本発明で「平坦部」とは、化合物半導体層をウェットエッチングしてメサ型構造部を形成したときに同時に形成されるものであって、“平坦”化はウェットエッチングで行ったものである。
（２）前記反射層がＤＢＲ反射層であることを特徴とする（１）に記載の発光ダイオード。
（３）前記活性層の基板と反対側に上部ＤＢＲ反射層を備えることを特徴とする（２）に記載の発光ダイオード。
（４）前記反射層が金属からなることを特徴とする（１）に記載の発光ダイオード。
（５）前記化合物半導体層が、前記電極層に接触するコンタクト層を有することを特徴とする（１）～（４）のいずれか一つに記載の発光ダイオード。
（６）前記メサ型構造部が前記活性層のすべてと、前記反射層の一部または全部を含むことを特徴とする請求項１～５のいずれか一項に記載の発光ダイオード。
（７）前記メサ型構造部は平面視して矩形であることを特徴とする（１）～（６）のいずれか一つに記載の発光ダイオード。
（８）前記メサ型構造部の各傾斜側面は前記基板のオリエンテーションフラットに対してオフセットして形成されていることを特徴とする（７）に記載の発光ダイオード。
（９）前記メサ型構造部の高さが３～７μｍであって、平面視した前記傾斜側面の幅が０．５～７μｍであることを特徴とする（１）～（８）のいずれか一つに記載の発光ダイオード。
（１０）前記光射出孔は平面視して円形又は楕円であることを特徴とする（１）～（９）のいずれか一つに記載の発光ダイオード。
（１１）前記光射出孔の径が５０～１５０μｍであることを特徴とする（１０）に記載の発光ダイオード。
（１２）前記電極層の前記平坦部上の部分にボンディングワイヤを有することを特徴とする（１）～（１１）のいずれか一つに記載の発光ダイオード。
（１３）前記活性層に含まれる発光層が多重量子井戸からなることを特徴とする（１）～（１２）のいずれか一つに記載の発光ダイオード。
（１４）前記活性層に含まれる発光層が（（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）、（ＡｌＸ２Ｇａ１－Ｘ２）Ａｓ（０≦Ｘ２≦１）、（ＩｎＸ３Ｇａ１－Ｘ３）Ａｓ（０≦Ｘ３≦１））のいずれかからなることを特徴とする（１）～（１３）のいずれか一つに記載の発光ダイオード。
（１５）基板上に、反射層と活性層を含む化合物半導体層とを形成する工程と、前記化合物半導体層をウェットエッチングして、頂面に向かって水平方向の断面積が連続的に小さく形成されてなるメサ型構造部と該メサ型構造部の周囲に配置する平坦部とを形成する工程と、前記メサ型構造部の頂面に、前記化合物半導体層の表面の一部を露出する通電窓を有するように、前記メサ型構造部及び平坦部上に保護膜を形成する工程と、前記通電窓から露出された化合物半導体層の表面に直接接触すると共に、前記平坦部上に形成された保護膜の一部を少なくとも覆い、前記メサ型構造部の頂面上に光射出孔を有するように、連続膜である電極層を形成する工程と、を有することを特徴とする発光ダイオードの製造方法。　
（１６）前記ウェットエッチングを、リン酸／過酸化水素水混合液、アンモニア／過酸化水素水混合液、ブロムメタノール混合液、ヨウ化カリウム／アンモニアの群から選択される少なくとも1種以上を用いて行うことを特徴とする（１５）に記載の発光ダイオードの製造方法。 The present invention provides the following means.
(1) A light emitting diode comprising a compound semiconductor layer including a reflective layer and an active layer on a substrate, having a flat portion on the top thereof, and a mesa structure portion having an inclined side surface and a top surface, Each of the flat portion and the mesa structure portion is sequentially covered with a protective film and an electrode film, and the mesa structure portion includes at least a part of the active layer, and the inclined side surface Is formed by wet etching and has a horizontal cross-sectional area continuously reduced toward the top surface, and the protective film includes at least a part of the flat portion and the mesa structure portion. An energization window that covers at least the inclined side surface and the peripheral region of the top surface of the mesa structure and exposes part of the surface of the compound semiconductor layer inside the peripheral region in plan view. The above The polar layer is in direct contact with the surface of the compound semiconductor layer exposed from the energizing window, covers at least a part of the protective film formed on the flat portion, and emits light on the top surface of the mesa structure portion. A light-emitting diode, which is a continuous film formed to have an injection hole.
In the present invention, the “flat portion” is formed at the same time when the mesa structure portion is formed by wet etching of the compound semiconductor layer, and “flattening” is performed by wet etching. is there.
(2) The light emitting diode according to (1), wherein the reflective layer is a DBR reflective layer.
(3) The light-emitting diode according to (2), further comprising an upper DBR reflective layer on the side opposite to the substrate of the active layer.
(4) The light-emitting diode according to (1), wherein the reflective layer is made of metal.
(5) The light-emitting diode according to any one of (1) to (4), wherein the compound semiconductor layer has a contact layer in contact with the electrode layer.
(6) The light emitting diode according to any one of (1) to (5), wherein the mesa structure portion includes all of the active layer and a part or all of the reflective layer.
(7) The light emitting diode according to any one of (1) to (6), wherein the mesa structure portion is rectangular in a plan view.
(8) Each light emitting diode according to (7), wherein each inclined side surface of the mesa structure portion is formed offset with respect to the orientation flat of the substrate.
(9) Any of (1) to (8), wherein the height of the mesa structure portion is 3 to 7 μm, and the width of the inclined side surface in plan view is 0.5 to 7 μm. The light emitting diode according to one.
(10) The light emitting diode according to any one of (1) to (9), wherein the light emission hole is circular or elliptical in plan view.
(11) The light-emitting diode according to (10), wherein the diameter of the light emission hole is 50 to 150 μm.
(12) The light-emitting diode according to any one of (1) to (11), wherein a bonding wire is provided on a portion of the electrode layer on the flat portion.
(13) The light-emitting diode according to any one of (1) to (12), wherein the light-emitting layer included in the active layer is formed of a multiple quantum well.
(14) The light emitting layer included in the active layer is ((Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1), (Al X2 Ga 1-X2 ) As (0 ≦ X2 ≦ 1), (In X3 Ga 1-X3 ) As (0 ≦ X3 ≦ 1)), according to any one of (1) to (13), Light emitting diode.
(15) Forming a compound semiconductor layer including a reflective layer and an active layer on a substrate, and wet etching the compound semiconductor layer to form a horizontal cross-sectional area continuously smaller toward the top surface Forming a mesa structure portion formed and a flat portion disposed around the mesa structure portion, and energizing to expose a part of the surface of the compound semiconductor layer on the top surface of the mesa structure portion A step of forming a protective film on the mesa structure portion and the flat portion so as to have a window; and a direct contact with the surface of the compound semiconductor layer exposed from the energization window; and a step formed on the flat portion. A step of forming an electrode layer that is a continuous film so as to cover at least a part of the protective film and have a light emission hole on the top surface of the mesa structure. Method.
(16) The wet etching is performed using at least one selected from the group consisting of a phosphoric acid / hydrogen peroxide mixture, an ammonia / hydrogen peroxide mixture, a bromomethanol mixture, and potassium iodide / ammonia. The manufacturing method of the light emitting diode as described in (15) characterized by performing.
　本発明の発光ダイオードによれば、その上部に平坦部と、傾斜側面及び頂面を有するメサ型構造部とを有し、平坦部及びメサ型構造部はそれぞれ、少なくとも一部は保護膜、電極膜によって順に覆われてなり、メサ型構造部は少なくとも活性層の一部を含むものであって、保護膜は、平坦部の少なくとも一部と、メサ型構造部の傾斜側面と、メサ型構造部の前記頂面の周縁領域とを少なくとも覆うとともに、平面視して前記周縁領域の内側に化合物半導体層の表面の一部を露出する通電窓を有し、電極層は、通電窓から露出された化合物半導体層の表面に直接接触すると共に、平坦部上に形成された保護膜の一部を少なくとも覆い、メサ型構造部の頂面上に光射出孔を有するように形成された連続膜である構成を採用したので、高い光出力が得られると共に射出させた光を光学部品等に効率良く取り込むことが可能である。
　また、メサ型構造部の傾斜側面はウェットエッチングによって形成されてなると共に頂面に向かって水平方向の断面積が連続的に小さく形成されてなる構成を採用したので、垂直側面の場合に比べて側面に保護膜及びその上の電極膜を形成しやすいために均一な膜厚で連続な膜が形成されるため、不連続な膜に起因したリークや通電不良がなく、安定で高輝度の発光が担保されている。かかる効果は、ウェットエッチングによって形成されてなる傾斜側面を有するメサ型構造部を備えていれば奏する効果であり、発光ダイオードの内部の積層構造や基板の構成によらずに得られる効果である。 According to the light emitting diode of the present invention, the flat portion and the mesa structure portion having the inclined side surface and the top surface are formed on the upper portion, and at least a part of the flat portion and the mesa structure portion is the protective film and the electrode. The mesa structure portion is sequentially covered with a film, and the mesa structure portion includes at least a part of the active layer, and the protective film includes at least a portion of the flat portion, the inclined side surface of the mesa structure portion, and the mesa structure. An energization window that covers at least the peripheral region of the top surface of the portion and exposes a part of the surface of the compound semiconductor layer inside the peripheral region in plan view, and the electrode layer is exposed from the energization window. A continuous film formed so as to be in direct contact with the surface of the compound semiconductor layer and to cover at least a part of the protective film formed on the flat portion and to have a light emission hole on the top surface of the mesa structure portion. Since a certain configuration is adopted, high light output is achieved. It is possible to incorporate efficiently such as an optical light is emitted piece with be.
In addition, since the inclined side surface of the mesa structure is formed by wet etching and the cross-sectional area in the horizontal direction is continuously reduced toward the top surface, the configuration is adopted compared to the case of the vertical side surface. Since the protective film and the electrode film on it are easy to form on the side, a continuous film with a uniform film thickness is formed, so there is no leakage or poor conduction due to the discontinuous film, and stable and high-luminance emission Is secured. Such an effect is achieved as long as a mesa structure portion having an inclined side surface formed by wet etching is provided, and is an effect obtained regardless of the laminated structure inside the light emitting diode and the configuration of the substrate.
　本発明の発光ダイオードによれば、反射層が金属からなる構成を採用することにより、発光層で発光した光を高い反射率で反射して高い光出力が可能となる。 According to the light emitting diode of the present invention, by adopting a configuration in which the reflective layer is made of metal, the light emitted from the light emitting layer is reflected with a high reflectance, and high light output is possible.
　本発明の発光ダイオードによれば、反射層がＤＢＲ反射層である構成を採用することにより、発光スペクトル線幅が狭い発光が可能となる。また、さらに、活性層の基板と反対側に上部ＤＢＲ反射層を備える構成を採用することにより、発光スペクトル線幅が狭く、出射光の指向性が高く、高速応答が可能となる。 According to the light emitting diode of the present invention, it is possible to emit light with a narrow emission spectrum line width by adopting a configuration in which the reflective layer is a DBR reflective layer. Furthermore, by adopting a configuration in which the upper DBR reflective layer is provided on the side opposite to the substrate of the active layer, the emission spectral line width is narrow, the directivity of the emitted light is high, and high-speed response is possible.
　本発明の発光ダイオードによれば、化合物半導体層が電極層に接触するコンタクト層を有する構成を採用することにより、オーミック電極の接触抵抗を下げて低電圧駆動が可能となる。 According to the light emitting diode of the present invention, by adopting a configuration in which the compound semiconductor layer has a contact layer in contact with the electrode layer, the contact resistance of the ohmic electrode can be lowered and low voltage driving can be performed.
　本発明の発光ダイオードによれば、メサ型構造部は活性層のすべてと、反射層の一部または全部を含む構成を採用することにより、発光は全て、メサ型構造部内で生ずることになり、光取り出し効率が向上する。 According to the light emitting diode of the present invention, the mesa structure portion adopts a configuration including all of the active layer and part or all of the reflective layer, so that all light emission occurs in the mesa structure portion. The light extraction efficiency is improved.
　本発明の発光ダイオードによれば、メサ型構造部を平面視して矩形である構成を採用することにより、製造時のウェットエッチングにおける異方性の影響によりエッチング深さによりメサ形状が変化することが抑制され、メサ部面積の制御が容易なので、高精度の寸法形状が得られている。 According to the light emitting diode of the present invention, by adopting a rectangular configuration when the mesa structure is viewed in plan, the mesa shape changes depending on the etching depth due to anisotropy in wet etching during manufacturing. Is suppressed, and the mesa area can be easily controlled, so that a highly accurate dimensional shape is obtained.
　本発明の発光ダイオードによれば、メサ型構造部の各傾斜側面が基板のオリエンテーションフラットに対してオフセットして形成されている構成を採用することにより、矩形メサ型構造部を構成する4辺に対し基板方位による異方性の影響が緩和されているため、均等なメサ形状・勾配が得られている。 According to the light emitting diode of the present invention, by adopting a configuration in which each inclined side surface of the mesa structure portion is formed offset with respect to the orientation flat of the substrate, the four sides constituting the rectangular mesa structure portion are formed. On the other hand, since the influence of the anisotropy due to the substrate orientation is mitigated, a uniform mesa shape / gradient is obtained.
　本発明の発光ダイオードによれば、メサ型構造部の高さが３～７μｍであって、平面視した傾斜側面の幅が０．５～７μｍである構成を採用することにより、垂直側面の場合に比べて側面に保護膜及びその上の電極膜を形成しやすいために均一な膜厚で連続な膜が形成されるため、不連続な膜に起因したリークや通電不良がなく、安定で高輝度の発光が担保されている。 According to the light emitting diode of the present invention, by adopting a configuration in which the height of the mesa structure portion is 3 to 7 μm and the width of the inclined side surface in a plan view is 0.5 to 7 μm, Compared to the above, it is easy to form a protective film on the side and the electrode film on it, so a continuous film is formed with a uniform film thickness. Luminance emission is guaranteed.
　本発明の発光ダイオードによれば、光射出孔が平面視して円形又は楕円である構成を採用することにより、矩形等の角を持つ構造に比べ均一なコンタクト領域を形成しやすく、角部での電流集中等の発生を抑制できる。また、受光側でのファイバー等への結合に適している。 According to the light emitting diode of the present invention, by adopting a configuration in which the light emitting hole is circular or elliptical in plan view, it is easy to form a uniform contact region as compared with a structure having a corner such as a rectangle. Occurrence of current concentration and the like can be suppressed. Further, it is suitable for coupling to a fiber or the like on the light receiving side.
　本発明の発光ダイオードによれば、光射出孔の径が５０～１５０μｍである構成を採用することにより、５０μm未満ではメサ型構造部での電流密度が高くなり、低電流で出力が飽和してしまう一方、１５０μmを超えるとメサ型構造部全体への電流拡散が困難であるため、やはり出力は飽和するという問題が回避されている。 According to the light emitting diode of the present invention, by adopting a configuration in which the diameter of the light emitting hole is 50 to 150 μm, the current density in the mesa structure is increased below 50 μm, and the output is saturated at a low current. On the other hand, if it exceeds 150 μm, it is difficult to spread the current to the entire mesa structure, so that the problem that the output is saturated is also avoided.
　本発明の発光ダイオードによれば、電極層の平坦部上の部分にボンディングワイヤを有する構成を採用することにより、十分な荷重（及び超音波）をかけられる平坦部にワイヤボンディングがなされているので、接合強度の強いワイヤボンディングが実現されている。 According to the light emitting diode of the present invention, wire bonding is performed on a flat portion where a sufficient load (and ultrasonic wave) can be applied by adopting a configuration having a bonding wire in a portion on the flat portion of the electrode layer. Wire bonding with high bonding strength has been realized.
　本発明の発光ダイオードの製造方法によれば、化合物半導体層をウェットエッチングして、頂面に向かって水平方向の断面積が連続的に小さく形成されてなるメサ型構造部と該メサ型構造部の周囲に配置する平坦部とを形成する工程と、メサ型構造部の頂面に、化合物半導体層の表面の一部を露出する通電窓を有するように、メサ型構造部及び平坦部上に保護膜を形成する工程と、通電窓から露出された化合物半導体層の表面に直接接触すると共に、前記平坦部上に形成された保護膜の一部を少なくとも覆い、メサ型構造部の頂面上に光射出孔を有するように、連続膜である電極層を形成する工程と、を有する構成を採用したので、高い光出力を有すると共に射出させた光を光学部品等に効率良く取り込むことが可能であると共に、垂直側面の場合に比べて傾斜斜面に保護膜及びその上の電極膜を形成しやすいために均一な膜厚で連続な膜が形成されるため、不連続な膜に起因したリークや通電不良がなく、安定で高輝度の発光が担保された発光ダイオードを製造することができる。従来の異方性のドライエッチングによりピラー構造を形成すると側面が垂直に形成されるが、ウェットエッチングによりメサ型構造部を形成することにより、側面を緩やかな傾斜の側面を形成することができる。また、ウェットエッチングによりメサ型構造部を形成することにより、従来のドライエッチングによってピラー構造を形成する場合に比べて形成時間が短縮することができる。 According to the method for manufacturing a light emitting diode of the present invention, a mesa structure portion formed by wet-etching a compound semiconductor layer and having a horizontal cross-sectional area continuously reduced toward the top surface, and the mesa structure portion On the mesa structure portion and the flat portion so that the top surface of the mesa structure portion has a conduction window exposing a part of the surface of the compound semiconductor layer. A step of forming a protective film; and a direct contact with the surface of the compound semiconductor layer exposed from the energization window; and at least a part of the protective film formed on the flat portion; and a top surface of the mesa structure portion The process of forming the electrode layer, which is a continuous film, so as to have a light exit hole at the top, has a high light output and can efficiently take out the emitted light into an optical component or the like And the vertical side Compared to the case, since it is easy to form the protective film and the electrode film thereon on the inclined slope, a continuous film with a uniform film thickness is formed, so there is no leakage or poor conduction due to the discontinuous film, A light-emitting diode in which stable and high-luminance light emission is ensured can be manufactured. When the pillar structure is formed by conventional anisotropic dry etching, the side surface is formed vertically, but by forming the mesa structure portion by wet etching, the side surface can be formed with a gently inclined side surface. Further, by forming the mesa structure portion by wet etching, the formation time can be shortened as compared with the case where the pillar structure is formed by conventional dry etching.
本発明の第１の実施形態である発光ダイオードの断面摸式図である。It is a cross-sectional model drawing of the light emitting diode which is the 1st Embodiment of this invention. 本発明の第１の実施形態である発光ダイオードの斜視図である。It is a perspective view of the light emitting diode which is the 1st Embodiment of this invention. 本発明の第１の実施形態である発光ダイオードの傾斜斜面の断面を示す電子顕微鏡写真である。It is an electron micrograph which shows the cross section of the inclined slope of the light emitting diode which is the 1st Embodiment of this invention. 本発明の第１の実施形態である発光ダイオードの活性層の断面摸式図である。It is a cross-sectional schematic diagram of the active layer of the light emitting diode which is the 1st Embodiment of this invention. 本発明の第２の実施形態である発光ダイオードの断面摸式図である。It is a cross-sectional schematic diagram of the light emitting diode which is the 2nd Embodiment of this invention. 本発明の第３の実施形態である発光ダイオードの断面摸式図である。It is a cross-sectional schematic diagram of the light emitting diode which is the 3rd Embodiment of this invention. 本発明の第４の実施形態である発光ダイオードの断面摸式図である。It is a cross-sectional schematic diagram of the light emitting diode which is the 4th Embodiment of this invention. 本発明の第１の実施形態の発光ダイオードの製造方法を説明するための断面摸式図である。It is a cross-sectional model diagram for demonstrating the manufacturing method of the light emitting diode of the 1st Embodiment of this invention. 本発明の第１の実施形態の発光ダイオードの製造方法を説明するための断面摸式図である。It is a cross-sectional model diagram for demonstrating the manufacturing method of the light emitting diode of the 1st Embodiment of this invention. ウェットエッチングのエッチング時間に対する深さ及び幅の関係を示すグラフである。It is a graph which shows the relationship of the depth and width with respect to the etching time of wet etching. 本発明の第１の実施形態の発光ダイオードの製造方法を説明するための断面摸式図である。It is a cross-sectional model diagram for demonstrating the manufacturing method of the light emitting diode of the 1st Embodiment of this invention. 本発明の第４の実施形態の発光ダイオードに用いる金属基板の製造工程の一例を示す工程断面図である。It is process sectional drawing which shows an example of the manufacturing process of the metal substrate used for the light emitting diode of the 4th Embodiment of this invention. 本発明の第４の実施形態の発光ダイオードの製造方法の一例を示す工程断面図である。It is process sectional drawing which shows an example of the manufacturing method of the light emitting diode of the 4th Embodiment of this invention. 本発明の第４の実施形態の発光ダイオードの製造方法の一例を示す工程断面図である。It is process sectional drawing which shows an example of the manufacturing method of the light emitting diode of the 4th Embodiment of this invention. 本発明の第４の実施形態の発光ダイオードの製造方法の一例を示す工程断面図である。It is process sectional drawing which shows an example of the manufacturing method of the light emitting diode of the 4th Embodiment of this invention. 発光ダイオードの直上における光スペクトルの測定結果を示すグラフである。It is a graph which shows the measurement result of the optical spectrum immediately above a light emitting diode. 発光した光の指向性の測定結果を示すグラフである。It is a graph which shows the measurement result of the directivity of emitted light. 従来の発光ダイオードの断面図である。It is sectional drawing of the conventional light emitting diode.
　以下、本発明を適用した発光ダイオード及びその製造方法について、図を用いてその構成を説明する。なお、以下の説明で用いる図面は、特徴をわかりやすくするために便宜上特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率などは実際と同じであるとは限らない。また、以下の説明において例示される材料、寸法等は一例であって、本発明はそれらに限定されるものではなく、その要旨を変更しない範囲で適宜変更して実施することが可能である。
　なお、本発明の効果を損ねない範囲で以下に記載していない層を備えてもよい。 Hereinafter, a configuration of a light emitting diode to which the present invention is applied and a method for manufacturing the same will be described with reference to the drawings. Note that the drawings used in the following description may show the features that are enlarged for convenience in order to make the features easier to understand, and the dimensional ratios of the respective components are not necessarily the same as the actual ones. . In addition, the materials, dimensions, and the like exemplified in the following description are examples, and the present invention is not limited to them, and can be appropriately changed and implemented without changing the gist thereof.
In addition, you may provide the layer which is not described below in the range which does not impair the effect of this invention.
〔発光ダイオード（第１の実施形態）〕
　図１に、本発明を適用した発光ダイオードの一例である共振器型発光ダイオードの断面模式図である。図２は、図１で示した発光ダイオードを含むウェハ上に形成された発光ダイオードの斜視図である。
　以下に、図１及び図２を参照して、本発明を適用した一実施形態の発光ダイオードについて詳細に説明する。 [Light-Emitting Diode (First Embodiment)]
FIG. 1 is a schematic cross-sectional view of a resonator type light emitting diode which is an example of a light emitting diode to which the present invention is applied. FIG. 2 is a perspective view of a light emitting diode formed on a wafer including the light emitting diode shown in FIG.
Hereinafter, a light emitting diode according to an embodiment to which the present invention is applied will be described in detail with reference to FIGS. 1 and 2.
　図１に示す発光ダイオード１００は、基板１上に反射層２と活性層３を含む化合物半導体層とを備えた発光ダイオードであって、その上部に平坦部６と、傾斜側面７ａ及び頂面７ｂを外面として有するメサ型構造部７とを有し、平坦部６及びメサ型構造部７はそれぞれ、少なくとも一部は保護膜８、電極膜９によって順に覆われてなり、メサ型構造部７は少なくとも活性層３の一部を含むものであって、傾斜側面７ａはウェットエッチングによって形成されてなると共に頂面７ｂに向かって水平方向の断面積が連続的に小さく形成されてなり、保護膜８は、平坦部６の少なくとも一部と、メサ型構造部７の傾斜側面７ａと、メサ型構造部７の頂面７ｂの周縁領域７ｂａとを少なくとも覆うとともに、平面視して周縁領域７ｂａの内側に化合物半導体層の表面の一部を露出する通電窓８ｂを有し、電極層９は、通電窓８ｂから露出された化合物半導体層の表面に直接接触すると共に、平坦部６上に形成された保護膜８の一部を少なくとも覆い、メサ型構造部７の頂面７ｂ上に光射出孔９ｂを有するように形成された連続膜であって、反射層２はＤＢＲ反射層（下部ＤＢＲ反射層）であり、活性層３の基板１と反対側に上部ＤＢＲ反射層４に備え、化合物半導体層は電極層９に接触するコンタクト層５を有するものである。
　本実施形態の共振器型発光ダイオードのメサ型構造部７は、平面視して矩形であり、電極層９の光射出孔９ｂは平面視して円形である。メサ型構造部７の平面視は矩形に限定されず、また、光射出孔９ｂの平面視も円形に限定されない。
　メサ型構造部７の電極膜上に、側面からの光の漏れを防止するための光漏れ防止膜１６を備えている。
　また、基板１の下面側には裏面電極１０を備えている。 A light-emitting diode 100 shown in FIG. 1 is a light-emitting diode having a compound semiconductor layer including a reflective layer 2 and an active layer 3 on a substrate 1, and a flat portion 6, an inclined side surface 7 a, and a top surface 7 b on the upper portion. And the mesa structure portion 7 having at least a part thereof covered with a protective film 8 and an electrode film 9 in order. At least a part of the active layer 3 is included, the inclined side surface 7a is formed by wet etching, and the cross-sectional area in the horizontal direction is continuously reduced toward the top surface 7b. Covers at least a part of the flat portion 6, the inclined side surface 7 a of the mesa structure portion 7, and the peripheral region 7 ba of the top surface 7 b of the mesa structure portion 7, and the inside of the peripheral region 7 ba in plan view. Compound A conductive window 8b exposing a part of the surface of the conductor layer is provided, and the electrode layer 9 is in direct contact with the surface of the compound semiconductor layer exposed from the conductive window 8b, and is a protective film formed on the flat portion 6 8 is a continuous film formed so as to cover at least a part of 8 and have a light exit hole 9b on the top surface 7b of the mesa structure 7, and the reflective layer 2 is a DBR reflective layer (lower DBR reflective layer). In addition, the upper DBR reflective layer 4 is provided on the side of the active layer 3 opposite to the substrate 1, and the compound semiconductor layer has a contact layer 5 that contacts the electrode layer 9.
The mesa structure 7 of the resonator type light emitting diode of the present embodiment is rectangular in plan view, and the light emission hole 9b of the electrode layer 9 is circular in plan view. The plan view of the mesa structure 7 is not limited to a rectangle, and the plan view of the light emission hole 9b is not limited to a circle.
A light leakage prevention film 16 for preventing light leakage from the side surface is provided on the electrode film of the mesa structure 7.
Further, a back electrode 10 is provided on the lower surface side of the substrate 1.
　本発明の発光ダイオードは、図２に示すように、ウェハ状の基板上に多数の発光ダイオード１００を作製した後、各発光ダイオードごとにストリート（切断予定ライン）２１（点線２２はストリート２１の長手方向の中心線）に沿って切断することにより製造することができる。すなわち、点線２２に沿ってストリート２１の部分にレーザーやブレード等を当てることにより、各発光ダイオードごとに切断することができる。 As shown in FIG. 2, in the light emitting diode of the present invention, after a large number of light emitting diodes 100 are formed on a wafer-like substrate, streets (scheduled cutting lines) 21 (dotted lines 22 are the lengths of the streets 21) for each light emitting diode. It can be manufactured by cutting along a direction centerline). That is, each light emitting diode can be cut by applying a laser, a blade, or the like to the portion of the street 21 along the dotted line 22.
　メサ型構造部７は、平坦部６に対して上方に突出した構造であり、傾斜側面７ａと頂面７ｂとを外面として有する。図１で示した例の場合、傾斜側面７ａは、活性層３の全層、上部ＤＢＲ層４及びコンタクト層５の傾斜断面上に保護膜を介して形成された電極層(おもて面電極層)９の表面からなり、頂面７ｂは、保護膜８の中央部分を覆う部分８ｄの表面と、電極層９（符号９ｂａ、９ｂｂ及び９ｄの部分）の表面とからなる。 The mesa structure portion 7 has a structure protruding upward with respect to the flat portion 6, and has an inclined side surface 7a and a top surface 7b as outer surfaces. In the case of the example shown in FIG. 1, the inclined side surface 7 a is an electrode layer (front surface electrode) formed on the entire active layer 3, the upper DBR layer 4, and the inclined cross section of the contact layer 5 via a protective film. The top surface 7b is composed of the surface of the portion 8d covering the central portion of the protective film 8 and the surface of the electrode layer 9 (portions 9ba, 9bb and 9d).
　また、本発明のメサ型構造部７の内部は、コンタクト層５と、上部ＤＢＲ層４と、活性層３の少なくとも一部とを含む。
　図１で示した例の場合、メサ型構造部７の内部は、コンタクト層５と、上部ＤＢＲ層４と、活性層３の全層とを含む。メサ型構造部７の内部には、活性層３の一部だけを含んでもよいが、活性層３の全層がメサ型構造部７の内部に含まれるのが好ましい。活性層３で発光した光を全てメサ型構造部内で生ずることになり、光取り出し効率が向上するからである。また、メサ型構造部７の内部に下部ＤＢＲ層２の一部を含んでもよい。 Further, the inside of the mesa structure portion 7 of the present invention includes the contact layer 5, the upper DBR layer 4, and at least a part of the active layer 3.
In the case of the example shown in FIG. 1, the inside of the mesa structure portion 7 includes the contact layer 5, the upper DBR layer 4, and the entire active layer 3. The mesa structure 7 may include only a part of the active layer 3, but it is preferable that the entire active layer 3 is included in the mesa structure 7. This is because all the light emitted from the active layer 3 is generated in the mesa structure, and the light extraction efficiency is improved. Further, a part of the lower DBR layer 2 may be included in the mesa structure portion 7.
　また、メサ型構造部７は、その傾斜側面７ａはウェットエッチングによって形成されてなると共に、基板１側から頂面に向かって水平方向の断面積が連続的に小さく形成されてなる。傾斜側面７ａはウェットエッチングによって形成されたものなので、下に凸状に形成されてなる。メサ型構造部７の高さｈは３～７μｍであって、平面視した傾斜側面７ａの幅ｗが０．５～７μｍであるのが好ましい。この場合、メサ型構造部７の側面が垂直若しくは急傾斜でなく、緩やかな傾斜であるために、保護膜や電極用金属膜を一様な膜厚で形成するのが容易となり、不連続な膜になるおそれがなく、そのため、不連続な膜に起因したリークや通電不良がなく、安定で高輝度の発光が担保されるからである。
　また、高さが７μｍを超えるまでウェットエッチングを行うと、傾斜側面がオーバーハング形状（逆テーパ状）になりやすくなるので好ましくない。オーバーハング形状（逆テーパ状）では保護膜や電極膜を均一な膜厚で不連続箇所なく形成することが垂直側面の場合よりもさらに困難になる。
　なお、本明細書において、高さｈとは、平坦部６上の保護膜を介して形成された電極膜９（符号９ｃの部分）の表面から、保護膜８の符号８ｂａの部分を覆う電極膜９（符号９ｂａの部分）の表面までの垂直方向の距離（図１参照）をいう。また、幅ｗとは、保護膜８の符号８ｂａの部分を覆う電極膜９（符号９ｂａの部分）のエッジからそのエッジにつながった傾斜側面の電極膜９（符号９ａの部分）の最下のエッジの水平方向の距離（図１参照）をいう。 In addition, the mesa structure 7 has an inclined side surface 7a formed by wet etching, and has a horizontal cross-sectional area that continuously decreases from the substrate 1 side to the top surface. Since the inclined side surface 7a is formed by wet etching, it is formed in a convex shape downward. The height h of the mesa structure 7 is preferably 3 to 7 μm, and the width w of the inclined side surface 7a in plan view is preferably 0.5 to 7 μm. In this case, since the side surface of the mesa structure portion 7 is not vertical or steeply inclined but gently inclined, it is easy to form the protective film and the electrode metal film with a uniform film thickness, which is discontinuous. This is because there is no possibility of forming a film, and therefore there is no leakage or poor conduction due to the discontinuous film, and stable and high-luminance emission is ensured.
Further, it is not preferable to perform wet etching until the height exceeds 7 μm because the inclined side surface tends to be in an overhang shape (reverse taper shape). In the overhang shape (reverse taper shape), it becomes more difficult to form the protective film and the electrode film with a uniform film thickness without discontinuous portions than in the case of the vertical side surface.
In the present specification, the height h is an electrode that covers the portion 8ba of the protective film 8 from the surface of the electrode film 9 (portion 9c) formed through the protective film on the flat portion 6. This refers to the vertical distance (see FIG. 1) to the surface of the film 9 (portion 9ba). The width w is the lowest of the electrode film 9 (reference numeral 9a) on the inclined side surface connected to the edge from the edge of the electrode film 9 (reference numeral 9ba) covering the protective film 8 at the reference numeral 8ba. The horizontal distance of the edge (see FIG. 1).
　図３は、メサ型構造部７近傍の断面の電子顕微鏡写真である。
　図３で示した例の層構成は、コンタクト層がＡｌ０．３Ｇａ０．７Ａｓからなり、層厚が３μｍである点以外は、後述する実施例と同様な構成である。 FIG. 3 is an electron micrograph of a cross section in the vicinity of the mesa structure portion 7.
The layer configuration of the example shown in FIG. 3 is the same as that of the example described later except that the contact layer is made of Al 0.3 Ga 0.7 As and the layer thickness is 3 μm.
　本発明のメサ型構造部はウェットエッチングによって形成されてなるので、その頂面側から基板側へ行くほど（図で下方に行くほど）、メサ型構造部の水平断面積（又は、幅もしくは径）の増大率が大きくなるように形成されている。この形状によってメサ型構造部がドライエッチングではなく、ウェットエッチングによって形成されたものであることを判別することができる。
　図３で示した例では、高さｈは７μｍであり、幅ｗは３．５～４．５μｍであった。 Since the mesa structure portion of the present invention is formed by wet etching, the horizontal cross-sectional area (or width or diameter) of the mesa structure portion increases from the top surface side to the substrate side (downward in the figure). ) To increase. With this shape, it can be determined that the mesa structure is formed not by dry etching but by wet etching.
In the example shown in FIG. 3, the height h is 7 μm and the width w is 3.5 to 4.5 μm.
　メサ型構造部７は、平面視して矩形であるのが好ましい。製造時のウェットエッチングにおける異方性の影響でエッチング深さによりメサ形状が変化することが抑制され、メサ型構造部の各面の面積の制御が容易なので、高精度の寸法形状が得られるからである。 The mesa structure 7 is preferably rectangular in plan view. The mesa shape can be prevented from changing depending on the etching depth due to the influence of anisotropy in wet etching during manufacturing, and the area of each surface of the mesa structure can be easily controlled, so a highly accurate dimensional shape can be obtained. It is.
　発光ダイオードにおけるメサ型構造部７の位置は、図1及び図２に示すように、素子の小型化のためには発光ダイオードの長軸方向の一方に片寄っているのが好ましい。平坦部６はボンディングワイヤ（図示せず）を取り付けるのに要する広さが必要であるため、狭くするのには限界があり、メサ型構造部７をもう一方に寄せることにより、平坦部６の範囲を最小化でき、素子の小型化を図ることができるからである。 As shown in FIGS. 1 and 2, the position of the mesa structure portion 7 in the light emitting diode is preferably shifted to one side in the long axis direction of the light emitting diode in order to reduce the size of the element. Since the flat portion 6 needs to have a size necessary for attaching a bonding wire (not shown), there is a limit to narrowing it, and by moving the mesa structure portion 7 to the other side, the flat portion 6 has a limit. This is because the range can be minimized and the device can be miniaturized.
　平坦部６は、メサ型構造部７の周囲に配置する部分である。本発明では、十分な荷重（及び超音波）をかけることが可能な電極層の平坦部に位置する部分にワイヤボンディングがなされるので、接合強度の強いワイヤボンディングが実現できる。 The flat part 6 is a part arranged around the mesa structure part 7. In the present invention, wire bonding is performed on a portion located on the flat portion of the electrode layer to which a sufficient load (and ultrasonic wave) can be applied, so that wire bonding with high bonding strength can be realized.
　平坦部６の上には、保護膜８、電極層(おもて面電極層)９が順に形成されており、電極層９の上にはボンディングワイヤ（図示せず）が取り付けられる。平坦部６の保護膜８の直下に配置する材料は、メサ型構造部７の内部の構成により決まる。図１で示した例の場合、メサ型構造部７の内部はコンタクト層５と、上部ＤＢＲ層４と、活性層３の全層とを含み、活性層３の直下の層である下部ＤＢＲ層の最上面が平坦部６の保護膜８の直下に配置するので、平坦部６の保護膜８の直下に配置する材料は下部ＤＢＲ層の最上面の材料である。 A protective film 8 and an electrode layer (front electrode layer) 9 are sequentially formed on the flat portion 6, and a bonding wire (not shown) is attached on the electrode layer 9. The material disposed immediately below the protective film 8 of the flat portion 6 is determined by the internal configuration of the mesa structure portion 7. In the case of the example shown in FIG. 1, the inside of the mesa structure portion 7 includes the contact layer 5, the upper DBR layer 4, and the entire active layer 3, and the lower DBR layer that is a layer immediately below the active layer 3. Therefore, the material disposed immediately below the protective film 8 of the flat portion 6 is the material of the uppermost surface of the lower DBR layer.
　保護膜８は、メサ型構造部７の傾斜側面７ａを覆う部分８ａと、平坦部６の少なくとも一部を覆う部分８ｃ（メサ型構造部７を挟んで反対側の平坦部を覆う部分８ｃｃも含む）と、メサ型構造部７の頂面７ｂの周縁領域７ｂａを覆う部分８ｂａと、前記頂面７ｂの中央部分を覆う部分８ｄとからなり、平面視して周縁領域７ｂａの内側にコンタクト層５の表面の一部を露出する通電窓８ｂを有する。
　本実施形態の通電窓８ｂは、メサ型構造部７の頂面７ｂにおいてコンタクト層５の表面のうち、周縁領域７ｂａの下に位置する部分８ｂａと中央部分を覆う部分８ｄの下に位置する部分との間の径の異なる２つの同心円間の領域を露出する。 The protective film 8 includes a portion 8a that covers the inclined side surface 7a of the mesa structure portion 7 and a portion 8c that covers at least a portion of the flat portion 6 (a portion 8cc that covers the flat portion on the opposite side across the mesa structure portion 7). And a portion 8ba that covers the peripheral region 7ba of the top surface 7b of the mesa structure 7 and a portion 8d that covers the central portion of the top surface 7b, and is a contact layer inside the peripheral region 7ba in plan view. 5 has an energizing window 8b that exposes a part of the surface.
The energization window 8b of the present embodiment is a portion of the surface of the contact layer 5 on the top surface 7b of the mesa structure 7 that is located below the portion 8ba located below the peripheral region 7ba and the portion 8d covering the central portion. An area between two concentric circles with different diameters between and is exposed.
　保護膜８の第1の機能は発光が生じる領域及び光を取り出す範囲を狭くするために、おもて面電極層９の下層に配置しておもて面電極層９と裏面電極１０との間の電流が流れる領域を制限することである。すなわち、保護膜８を形成した後、保護膜８を含む全面におもて面電極層を形成し、その後、おもて面電極層をパターニングするが、保護膜８を形成した部分についてはおもて面電極層を除去しなくても裏面電極１０との間に電流が流れることはない。裏面電極１０との間の電流を流したいところに保護膜８の通電窓８ｂを形成する。
　従って、第１の機能を持たせるように、メサ型構造部７の頂面７ｂの一部に通電窓８ｂを形成する構成であれば、通電窓８ｂの形状や位置は図１のような形状や位置に限定されない。 The first function of the protective film 8 is to arrange the surface electrode layer 9 and the back electrode 10 in the lower layer of the front electrode layer 9 in order to narrow the region where light emission occurs and the range from which light is extracted. It is to limit the region in which the current flows. That is, after forming the protective film 8, a front electrode layer is formed on the entire surface including the protective film 8, and then the front electrode layer is patterned. Even if the surface electrode layer is not removed, no current flows between the electrode 10 and the back electrode 10. An energization window 8b of the protective film 8 is formed where a current between the back electrode 10 is desired to flow.
Therefore, if the energization window 8b is formed on a part of the top surface 7b of the mesa structure 7 so as to have the first function, the shape and position of the energization window 8b is the shape as shown in FIG. It is not limited to or position.
　保護膜８の第２の機能は、第1の機能は必須の機能であるのに対して必須の機能ではないが、図１に示す保護膜８の場合、第２の機能として、平面視しておもて面電極層９の光射出孔９ａ内のコンタクト層５の表面に配置して、保護膜８越しに光を取り出すことができ、かつ、光を取り出すコンタクト層５の表面を保護することである。
　なお、後述する第２の実施形態では、光射出孔の下に保護膜を有さず、保護膜を介さずに光射出孔９ｂから直接、光を取り出す構成であり、第２の機能を有さない。 The second function of the protective film 8 is not an essential function while the first function is an essential function. In the case of the protective film 8 shown in FIG. In addition, it is arranged on the surface of the contact layer 5 in the light emitting hole 9a of the surface electrode layer 9, so that light can be extracted through the protective film 8, and the surface of the contact layer 5 from which light is extracted is protected. That is.
In the second embodiment to be described later, there is no protective film under the light emitting hole, and the light is directly extracted from the light emitting hole 9b without the protective film, and the second function is provided. No.
　保護膜８の材料としては絶縁層として公知のものを用いることができるが、安定した絶縁膜の形成が容易であることから、シリコン酸化膜が好ましい。
　なお、本実施形態では、この保護膜８（８ｄ）越しに光を取り出すので、保護膜８は透光性を有する必要がある。 As the material of the protective film 8, a known material can be used as the insulating layer, but a silicon oxide film is preferable because it is easy to form a stable insulating film.
In this embodiment, since light is extracted through the protective film 8 (8d), the protective film 8 needs to have translucency.
　また、保護膜８の膜厚は、０．３～１μｍが好ましい。０．３μｍ未満では絶縁が十分ではないからであり、１μｍを超えると形成するのに時間がかかり過ぎるからである。 The film thickness of the protective film 8 is preferably 0.3 to 1 μm. This is because if the thickness is less than 0.3 μm, the insulation is not sufficient, and if it exceeds 1 μm, it takes too much time to form.
　電極層(おもて面電極層)９は、保護膜８のうち傾斜側面７ａを覆う部分８ａを覆う部分９ａと、保護膜８のうち平坦部６の少なくとも一部を覆う部分８ｃを覆う部分９ｃと、保護膜８のうちメサ型構造部７の頂面７ｂの周縁領域７ｂａを覆う部分８ｂａの部分を覆う部分９ｂａと、保護膜８の通電窓８ｂを埋め込む部分９ｂｂ（以下適宜、「コンタクト部分」という）と、メサ型構造部７の頂面７ｂにおいて保護膜８のうち頂面７ｂの中央部分を覆う部分８ｄの外周縁部を覆う部分９ｄとからなる。 The electrode layer (front surface electrode layer) 9 is a portion that covers a portion 9 a that covers the inclined side surface 7 a of the protective film 8 and a portion 8 c that covers at least a part of the flat portion 6 of the protective film 8. 9c, a portion 9ba of the protective film 8 that covers the portion 8ba that covers the peripheral region 7ba of the top surface 7b of the mesa structure portion 7, and a portion 9bb that embeds the current-carrying window 8b of the protective film 8 (hereinafter referred to as “contact” as appropriate) And a portion 9d that covers the outer peripheral edge portion of the portion 8d that covers the central portion of the top surface 7b of the protective film 8 on the top surface 7b of the mesa structure portion 7.
　電極層(おもて面電極層)９の第1の機能は裏面電極１０との間に電流を流すことであり、第２の機能は発光した光が射出される範囲を制限することである。図１で示した例の場合、第1の機能はコンタクト部分９ｂｂが担い、第２の機能は中央部分を覆う部分８ｄの外周縁部を覆う部分９ｄが担っている。
　第２の機能については非透光性の保護膜を用いることにより、その保護膜に担わせる構成でもよい。 The first function of the electrode layer (front electrode layer) 9 is to pass a current between the electrode layer 10 and the back electrode 10, and the second function is to limit the range in which the emitted light is emitted. . In the case of the example shown in FIG. 1, the contact portion 9bb is responsible for the first function, and the portion 9d covering the outer peripheral edge portion of the portion 8d covering the center portion is responsible for the second function.
For the second function, a non-translucent protective film may be used so that the protective film bears it.
　電極層９は平坦部６の保護膜８全体を覆っていてもよいし、その一部を覆っても構わないが、ボンディングワイヤが適切に取り付けるためにはできるだけ広範囲を覆っているのが好ましい。コスト低減の観点から、図２に示すように、各発光ダイオードごとに切断する際のストリート２１には電極層を覆わないのが好ましい。 The electrode layer 9 may cover the entire protective film 8 of the flat portion 6 or may cover a part thereof, but it is preferable that the electrode layer 9 covers as wide a range as possible in order to properly attach the bonding wire. From the viewpoint of cost reduction, as shown in FIG. 2, it is preferable not to cover the electrode layer on the street 21 when cutting each light emitting diode.
　この電極層９はメサ型構造部７の頂面７ｂにおいてコンタクト部分９ｂｂでしかコンタクト層５に接触していないので、電極層９と裏面電極１０とは、コンタクト部９ｂｂと裏面電極１０との間でしか電流が流れない。そのため、発光層１３において平面視して光射出孔９ｂと重なる範囲に電流が集中し、その範囲に発光が集中するため、効率的に光を取り出すことができる。 Since this electrode layer 9 is in contact with the contact layer 5 only at the contact portion 9bb on the top surface 7b of the mesa structure portion 7, the electrode layer 9 and the back electrode 10 are located between the contact portion 9bb and the back electrode 10. Only current flows. Therefore, current concentrates in a range where the light emitting layer 13 overlaps with the light emission hole 9b in plan view, and light emission concentrates in that range, so that light can be extracted efficiently.
　電極層９の材料としては公知の電極材料を用いることができるが、良好なオーミックコンタクトが得られることから、ＡｕＢｅ／Ａｕが最も好ましい。
　また、電極層９の膜厚は、０．５～２．０μｍが好ましい。０．５μｍ未満では均一かつ良好なオーミックコンタクトを得ることが困難な上、ボンディング時の強度、厚みが不十分だからであり、２．０μｍを超えるとコストがかかり過ぎるからである。 A known electrode material can be used as the material of the electrode layer 9, but AuBe / Au is most preferable because a good ohmic contact can be obtained.
The film thickness of the electrode layer 9 is preferably 0.5 to 2.0 μm. This is because it is difficult to obtain a uniform and good ohmic contact if the thickness is less than 0.5 μm, and the strength and thickness at the time of bonding are insufficient, and if it exceeds 2.0 μm, the cost is excessive.
　図１に示すように、活性層で発光した光がメサ型構造部７の側面から素子外に漏れることを防止する光漏れ防止膜１６を備えてもよい。 As shown in FIG. 1, a light leakage prevention film 16 that prevents light emitted from the active layer from leaking from the side surface of the mesa structure 7 to the outside of the device may be provided.
　光漏れ防止膜１６の材料としては公知の反射材料を用いることができる。電極層９と同じＡｕＢｅ／Ａｕでもよい。 As the material of the light leakage prevention film 16, a known reflective material can be used. The same AuBe / Au as the electrode layer 9 may be used.
　本実施形態においては、光射出孔９ｂの下に保護膜８ｄ（８）が形成されており、メサ型構造部７の頂面において保護膜８ｄ（８）を介して光射出孔９ｂから光を取り出す構成である。 In the present embodiment, a protective film 8d (8) is formed under the light emitting hole 9b, and light is emitted from the light emitting hole 9b through the protective film 8d (8) on the top surface of the mesa structure portion 7. It is the structure to take out.
　光射出孔９ｂの形状は、平面視して円形又は楕円であるのが好ましい。矩形等の角を持つ構造に比べ均一なコンタクト領域を形成しやすく、角部での電流集中等の発生を抑制できる。また、受光側でのファイバー等への結合に適しているからである。 The shape of the light exit hole 9b is preferably circular or elliptical in plan view. Compared to a structure having a corner such as a rectangle, a uniform contact region can be easily formed, and current concentration at the corner can be suppressed. Moreover, it is because it is suitable for the coupling | bonding to the fiber etc. in the light-receiving side.
　光射出孔９ｂの径は、５０～１５０μｍであるのが好ましい。５０μm未満では射出部での電流密度が高くなり、低電流で出力が飽和してしまう一方、１５０μmを超えると射出部全体への電流拡散が困難であるため、注入電流に対する発光効率が低下するからである。 The diameter of the light exit hole 9b is preferably 50 to 150 μm. If it is less than 50 μm, the current density at the emission part becomes high and the output is saturated at a low current. On the other hand, if it exceeds 150 μm, it is difficult to diffuse the current to the whole emission part, and the light emission efficiency with respect to the injection current decreases. It is.
　基板１としては、例えば、ＧａＡｓ基板を用いることができる。 As the substrate 1, for example, a GaAs substrate can be used.
　ＧａＡｓ基板を用いる場合は、公知の製法で作製された市販品の単結晶基板を使用できる。ＧａＡｓ基板のエピタキシャル成長させる表面は、平滑であることが望ましい。ＧａＡｓ基板の表面の面方位は、エピ成長しやすく、量産されている（１００）面および（１００）から、±２０°以内にオフした基板が、品質の安定性の面からのぞましい。さらに、ＧａＡｓ基板の面方位の範囲が、（１００）方向から（０－１－１）方向に１５°オフ±５°であることがより好ましい。 When using a GaAs substrate, a commercially available single crystal substrate manufactured by a known manufacturing method can be used. The surface on which the GaAs substrate is epitaxially grown is preferably smooth. The surface orientation of the surface of the GaAs substrate is easily epi-grown, and from the (100) plane and (100) that are mass-produced, a substrate that is turned off within ± 20 ° is preferable from the viewpoint of quality stability. Furthermore, the range of the plane orientation of the GaAs substrate is more preferably 15 ° off ± 5 ° from the (100) direction to the (0-1-1) direction.
　ＧａＡｓ基板の転位密度は、下部ＤＢＲ層２、活性層３及び上部ＤＢＲ層４の結晶性を良くするために低い方が望ましい。具体的には、例えば、１０，０００個ｃｍ－２以下、望ましくは、１，０００個ｃｍ－２以下であることが好適である。 The dislocation density of the GaAs substrate is preferably low in order to improve the crystallinity of the lower DBR layer 2, the active layer 3, and the upper DBR layer 4. Specifically, for example, 10,000 pieces cm −2 or less, preferably 1,000 pieces cm −2 or less are suitable.
　ＧａＡｓ基板は、ｎ型であってもｐ型であってもよい。ＧａＡｓ基板のキャリア濃度は、所望の電気伝導度と素子構造から、適宜選択することができる。例えば、ＧａＡｓ基板がＳｉドープのｎ型である場合には、キャリア濃度が１×１０１７～５×１０１８ｃｍ－３の範囲であることが好ましい。これに対して、ＧａＡｓ基板がＺｎをドープしたｐ型の場合には、キャリア濃度２×１０１８～５×１０１９ｃｍ－３の範囲であることが好ましい。 The GaAs substrate may be n-type or p-type. The carrier concentration of the GaAs substrate can be appropriately selected from desired electrical conductivity and element structure. For example, when the GaAs substrate is Si-doped n-type, the carrier concentration is preferably in the range of 1 × 10 17 to 5 × 10 18 cm −3 . In contrast, when the GaAs substrate is p-type doped with Zn, the carrier concentration is preferably in the range of 2 × 10 18 to 5 × 10 19 cm −3 .
　ＧａＡｓ基板の厚さは、基板のサイズに応じて適切な範囲がある。ＧａＡｓ基板の厚さが適切な範囲よりも薄いと、化合物半導体層の製造プロセス中に割れてしまうおそれがある。一方、ＧａＡｓ基板の厚さが適切な範囲よりも厚いと材料コストが増加することになる。このため、ＧａＡｓ基板の基板サイズが大きい場合、例えば、直径７５ｍｍの場合には、ハンドリング時の割れを防止するために２５０～５００μｍの厚さが望ましい。同様に、直径５０ｍｍの場合は、２００～４００μｍの厚さが望ましく、直径１００ｍｍの場合は、３５０～６００μｍの厚さが望ましい。 The thickness of the GaAs substrate has an appropriate range depending on the size of the substrate. If the thickness of the GaAs substrate is less than the appropriate range, the compound semiconductor layer may be broken during the manufacturing process. On the other hand, if the thickness of the GaAs substrate is thicker than an appropriate range, the material cost increases. Therefore, when the substrate size of the GaAs substrate is large, for example, when the diameter is 75 mm, a thickness of 250 to 500 μm is desirable to prevent cracking during handling. Similarly, when the diameter is 50 mm, a thickness of 200 to 400 μm is desirable, and when the diameter is 100 mm, a thickness of 350 to 600 μm is desirable.
　このように、ＧａＡｓ基板の基板サイズに応じて基板の厚さを厚くすることにより、活性層３に起因する化合物半導体層の反りを低減することができる。これにより、エピタキシャル成長中の温度分布が均一となることため、活性層３の面内の波長分布を小さくすることができる。なお、ＧａＡｓ基板の形状は、特に円形に限定されず、矩形等であっても問題ない。 As described above, the warpage of the compound semiconductor layer caused by the active layer 3 can be reduced by increasing the thickness of the substrate according to the substrate size of the GaAs substrate. As a result, the temperature distribution during epitaxial growth becomes uniform, so that the in-plane wavelength distribution of the active layer 3 can be reduced. The shape of the GaAs substrate is not particularly limited to a circle, and there is no problem even if it is a rectangle or the like.
　反射層（下部ＤＢＲ層２）及び化合物半導体層（活性層３、上部ＤＢＲ層４、コンタクト層５）の構造には、公知の機能層を適時加えることができる。例えば、素子駆動電流を発光部の全般に平面的に拡散させるための電流拡散層、逆に素子駆動電流の通流する領域を制限するための電流阻止層や電流狭窄層など公知の層構造を設けることができる。 In the structure of the reflective layer (lower DBR layer 2) and the compound semiconductor layer (active layer 3, upper DBR layer 4, contact layer 5), known functional layers can be added as appropriate. For example, a known layer structure such as a current diffusion layer for planarly diffusing the element driving current over the entire light emitting portion, or a current blocking layer or a current constricting layer for limiting the area through which the element driving current flows is used. Can be provided.
　基板１上に形成される反射層（下部ＤＢＲ層）及び化合物半導体層は、下部ＤＢＲ層２、活性層３及び上部ＤＢＲ層４が順次積層されて構成されている。 The reflective layer (lower DBR layer) and compound semiconductor layer formed on the substrate 1 are configured by sequentially laminating a lower DBR layer 2, an active layer 3, and an upper DBR layer 4.
　ＤＢＲ（Distributed Bragg Reflector）層は、λ／（４ｎ）の膜厚で（λ：反射すべき光の真空中での波長、ｎ：層材料の屈折率）、屈折率が異なる２種類の層を交互に積層した多層膜からなるものである。反射率は２種類の屈折率の差が大きいと、比較的少ない層数の多層膜で高反射率が得られる。通常の反射膜のようにある面で反射されるのでなく、多層膜の全体として光の干渉現象に基づき反射が起きることが特徴である。
　ＤＢＲ層の材料は発光波長に対して透明であることが好ましく、又、ＤＢＲ層を構成する２種類の材料の屈折率の差が大きくなる組み合わせとなるよう選択されるのが好ましい。 A DBR (Distributed Bragg Reflector) layer is composed of two types of layers having a film thickness of λ / (4n) (λ: wavelength of light to be reflected in vacuum, n: refractive index of layer material) and different refractive indexes. It consists of a multilayer film laminated alternately. When the difference between the two types of refractive indexes is large, a high reflectance can be obtained with a multilayer film having a relatively small number of layers. Instead of being reflected on a certain surface as in a normal reflective film, the multilayer film as a whole is characterized in that reflection occurs based on the light interference phenomenon.
The material of the DBR layer is preferably transparent with respect to the emission wavelength, and is preferably selected so as to be a combination that increases the difference in refractive index between the two types of materials constituting the DBR layer.
　下部ＤＢＲ層２は、屈折率の異なる２種類の層が交互に１０～５０対積層されてなるのが好ましい。１０対以下である場合は反射率が低すぎるために出力の増大に寄与せず、５０対以上にしてもさらなる反射率の増大は小さいからである。
　下部ＤＢＲ層２を構成する屈折率の異なる２種類の層は、組成の異なる２種類の（ＡｌＸｈＧａ１－Ｘｈ）Ｙ３Ｉｎ１－Ｙ３Ｐ（０＜Ｘｈ≦１、Ｙ３＝０．５）、（ＡｌＸｌＧａ１－Ｘｌ）Ｙ３Ｉｎ１－Ｙ３Ｐ；０≦Ｘｌ＜１、Ｙ３＝０．５）の対であり、両者のＡｌの組成差ΔＸ＝ｘh－ｘｌが０．５より大きいか又は等しくなる組み合わせか、又は、ＧａＩｎＰとＡｌＩｎＰの組み合わせか、又は、組成の異なる２種類のＡｌｘｌＧａ１－ｘｌＡｓ（０．１≦ｘｌ≦１）、ＡｌｘｈＧａ１－ｘｈＡｓ（０．１≦ｘｈ≦１）の対であり、両者の組成差ΔＸ＝ｘｈ－ｘｌが０．５より大きいか等しくなる組み合わせかのいずれかから選択されるのが効率よく高い反射率が得られることから望ましい。
　組成の異なるＡｌＧａＩｎＰの組み合わせは、結晶欠陥を生じやすいＡｓを含まないので好ましく、ＧａＩｎＰとＡｌＩｎＰはその中で屈折率差を最も大きくとれるので、反射層の数を少なくすることができ、組成の切り替えも単純であるので好ましい。また、ＡｌＧａＡｓは、大きな屈折率差をとりやすいという利点がある。 The lower DBR layer 2 is preferably formed by alternately stacking 10 to 50 pairs of two kinds of layers having different refractive indexes. This is because when the number is 10 pairs or less, the reflectance is too low, so that it does not contribute to an increase in output, and even when the number is 50 pairs or more, the increase in reflectance is small.
The two types of layers having different refractive indexes constituting the lower DBR layer 2 are two types of (Al Xh Ga 1-Xh ) Y3 In 1-Y3 P (0 <Xh ≦ 1, Y3 = 0.5) having different compositions. , (Al Xl Ga 1-Xl ) Y3 In 1-Y3 P; 0 ≦ Xl <1, Y3 = 0.5), and the Al composition difference ΔX = xh−xl is greater than 0.5 Or a combination of GaInP and AlInP, or two types of Al xl Ga 1-xl As (0.1 ≦ xl ≦ 1), Al xh Ga 1-xh As (0 ..Ltoreq.xh.ltoreq.1), and a high reflectivity can be obtained efficiently if the composition difference between them is selected from any combination in which .DELTA.X = xh-xl is greater than or equal to 0.5. Is desirable.
A combination of AlGaInP having different compositions is preferable because it does not contain As that easily causes crystal defects, and GaInP and AlInP have the largest refractive index difference among them, so that the number of reflective layers can be reduced and the composition can be switched. Is also preferable because it is simple. Moreover, AlGaAs has an advantage that a large difference in refractive index is easily obtained.
　上部ＤＢＲ層４も、下部ＤＢＲ層２と同様の層構造を用いることができるが、上部ＤＢＲ層４を透過させて光を射出する必要があるので、下部ＤＢＲ層２よりも反射率が低くなるように構成する。具体的には、下部ＤＢＲ層２と同じ材料からなる場合、下部ＤＢＲ層２よりも層数が少なくなるように、屈折率の異なる２種類の層が交互に３～１０対積層されてなるのが好ましい。２対以下である場合は反射率が低すぎるために出力の増大に寄与せず、１１対以上にすると上部ＤＢＲ層４を透過する光量が低下しすぎるからである。 The upper DBR layer 4 can also have the same layer structure as the lower DBR layer 2, but has a lower reflectance than the lower DBR layer 2 because it is necessary to emit light through the upper DBR layer 4. Configure as follows. Specifically, when the same material as that of the lower DBR layer 2 is used, 3 to 10 pairs of two kinds of layers having different refractive indexes are alternately stacked so that the number of layers is smaller than that of the lower DBR layer 2. Is preferred. This is because when the number of pairs is two or less, the reflectance is too low to contribute to an increase in output, and when the number is eleven or more, the amount of light transmitted through the upper DBR layer 4 is too low.
　本発明の発光ダイオードは、活性層３を低反射率の上部ＤＢＲ層４と高反射率の下部ＤＢＲ層２で挟み、活性層３で発光した光が上部ＤＢＲ層４と下部ＤＢＲ層２と間で共振して定在波の腹が発光層に位置させる構成をとることにより、レーザ発振させないで、従来の発光ダイオードよりも指向性が高く、高効率の発光ダイオードとなっている。 In the light emitting diode of the present invention, an active layer 3 is sandwiched between an upper DBR layer 4 having a low reflectance and a lower DBR layer 2 having a high reflectance, and light emitted from the active layer 3 is interposed between the upper DBR layer 4 and the lower DBR layer 2. By adopting a configuration in which the antinodes of the standing waves are located in the light emitting layer, the laser light is not oscillated, and the light emitting diode has higher directivity and higher efficiency than the conventional light emitting diode.
　図４に示すように、活性層３は、下部クラッド層１１、下部ガイド層１２、発光層１３、上部ガイド層１４、上部クラッド層１５が順次積層されて構成されている。すなわち、活性層３は、放射再結合をもたらすキャリア（担体；ｃａｒｒｉｅｒ）及び発光を発光層１３に「閉じ込める」ために、発光層１３の下側及び上側に対峙して配置した下部クラッド層１１、下部ガイド層１２、及び上部ガイド層１４、上部クラッド層１５を含む、所謂、ダブルヘテロ（英略称：ＤＨ）構造とすることが高強度の発光を得る上で好ましい。 As shown in FIG. 4, the active layer 3 includes a lower clad layer 11, a lower guide layer 12, a light emitting layer 13, an upper guide layer 14, and an upper clad layer 15 which are sequentially laminated. That is, the active layer 3 includes a lower clad layer 11 disposed opposite to the lower side and the upper side of the light emitting layer 13 in order to “confine” the carrier and the light emission that cause radiative recombination in the light emitting layer 13. A so-called double hetero (English abbreviation: DH) structure including the lower guide layer 12, the upper guide layer 14, and the upper cladding layer 15 is preferable in order to obtain high-intensity light emission.
　図４に示すように、発光層１３は、発光ダイオード（ＬＥＤ）の発光波長を制御するため、量子井戸構造を構成することができる。すなわち、発光層１３は、バリア層（障壁層ともいう）１８を両端に有する、井戸層１７とバリア層１８との多層構造（積層構造）とすることができる。 As shown in FIG. 4, the light emitting layer 13 can form a quantum well structure in order to control the light emission wavelength of a light emitting diode (LED). That is, the light emitting layer 13 can have a multilayer structure (laminated structure) of the well layer 17 and the barrier layer 18 having a barrier layer (also referred to as a barrier layer) 18 at both ends.
　発光層１３の層厚は、０．０２～２μｍの範囲であることが好ましい。発光層１３の伝導型は特に限定されるものではなく、アンドープ、ｐ型及びｎ型のいずれも選択することができる。発光効率を高めるには、結晶性が良好なアンドープ又は３×１０１７ｃｍ－３未満のキャリア濃度とすることが望ましい。 The thickness of the light emitting layer 13 is preferably in the range of 0.02 to 2 μm. The conductivity type of the light emitting layer 13 is not particularly limited, and any of undoped, p-type and n-type can be selected. In order to increase the light emission efficiency, it is desirable that the crystallinity be undoped or the carrier concentration be less than 3 × 10 17 cm −3 .
　井戸層１７の材料としては公知の井戸層材料を用いることができる。例えば、ＡｌＧａＡｓ、ＩｎＧａＡｓ、ＡｌＧａＩｎＰを用いることができる。 As the material of the well layer 17, a known well layer material can be used. For example, AlGaAs, InGaAs, or AlGaInP can be used.
　井戸層１７の層厚は、３～３０ｎｍの範囲が好適である。より好ましくは、３～１０ｎｍの範囲である。 The layer thickness of the well layer 17 is preferably in the range of 3 to 30 nm. More preferably, it is in the range of 3 to 10 nm.
　バリア層１８の材料としては、井戸層１７の材料に対して適した材料を選択するのが好ましい。バリア層１８での吸収を防止して発光効率を高めるため、井戸層１７よりもバンドギャップが大きくなる組成とするのが好ましい。 As the material of the barrier layer 18, it is preferable to select a material suitable for the material of the well layer 17. In order to prevent the absorption in the barrier layer 18 and increase the light emission efficiency, it is preferable that the composition has a band gap larger than that of the well layer 17.
　例えば、井戸層１７の材料としてＡｌＧａＡｓ又はＩｎＧａＡｓを用いた場合にはバリア層１８の材料としてＡｌＧａＡｓやＡｌＧａＩｎＰが好ましい。バリア層１８の材料としてＡｌＧａＩｎＰを用いた場合、欠陥を作りやすいＡｓを含まないので結晶性が高く、高出力に寄与する。
　井戸層１７の材料として（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）を用いた場合、バリア層１８の材料としてよりＡｌ組成の高い（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ４≦１，０＜Ｙ１≦１，Ｘ１＜Ｘ４）または井戸層（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）よりバンドギャップエネルギーが大きくなるＡｌＧａＡｓを用いることができる。 For example, when AlGaAs or InGaAs is used as the material of the well layer 17, AlGaAs or AlGaInP is preferable as the material of the barrier layer 18. When AlGaInP is used as the material of the barrier layer 18, it does not contain As which tends to create defects, so that it has high crystallinity and contributes to high output.
When (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1) is used as the material of the well layer 17, the Al composition is higher than the material of the barrier layer 18 ( Al X4 Ga 1-X4 ) Y1 In 1-Y1 P (0 ≦ X4 ≦ 1, 0 <Y1 ≦ 1, X1 <X4) or well layer (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ AlGaAs whose band gap energy is larger than X1 ≦ 1, 0 <Y1 ≦ 1) can be used.
　バリア層１８の層厚は、井戸層１７の層厚と等しいか又は井戸層１７の層厚より厚いのが好ましい。トンネル効果が生じる層厚範囲で十分に厚くすることにより、トンネル効果による井戸層間への広がりが抑制されてキャリアの閉じ込め効果が増大し、電子と正孔の発光再結合確率が大きくなり、発光出力の向上を図ることができる。 The layer thickness of the barrier layer 18 is preferably equal to or greater than the layer thickness of the well layer 17. By sufficiently thickening the layer thickness range in which the tunnel effect occurs, spreading between the well layers due to the tunnel effect is suppressed, the carrier confinement effect is increased, the probability of recombination of electrons and holes is increased, and the light emission output Can be improved.
　井戸層１７とバリア層１８との多層構造において、井戸層１７とバリア層１８とを交互に積層する対の数は特に限定されるものではないが、２対以上４０対以下であることが好ましい。すなわち、活性層１１には、井戸層１７が２～４０層含まれていることが好ましい。ここで、活性層１１の発光効率が好適な範囲としては、井戸層１７が５層以上であることが好ましい。一方、井戸層１７及びバリア層１８は、キャリア濃度が低いため、多くの対にすると順方向電圧（ＶＦ）が増大してしまう。このため、４０対以下であることが好ましく、２０対以下であることがより好ましい。 In the multilayer structure of the well layer 17 and the barrier layer 18, the number of pairs in which the well layers 17 and the barrier layers 18 are alternately stacked is not particularly limited, but is preferably 2 or more and 40 or less. . That is, the active layer 11 preferably includes 2 to 40 well layers 17. Here, as a preferable range of the luminous efficiency of the active layer 11, it is preferable that the well layer 17 has five or more layers. On the other hand, since the well layer 17 and the barrier layer 18 have a low carrier concentration, the forward voltage (V F ) increases when the number of pairs is increased. For this reason, it is preferable that it is 40 pairs or less, and it is more preferable that it is 20 pairs or less.
　下部ガイド層１２及び上部ガイド層１４は、図４に示すように、発光層１３の下面及び上面にそれぞれ設けられている。具体的には、発光層１３の下面に下部ガイド層１２が設けられ、発光層１３の上面に上部ガイド層１４が設けられている。 The lower guide layer 12 and the upper guide layer 14 are provided on the lower surface and the upper surface of the light emitting layer 13, respectively, as shown in FIG. Specifically, the lower guide layer 12 is provided on the lower surface of the light emitting layer 13, and the upper guide layer 14 is provided on the upper surface of the light emitting layer 13.
　下部ガイド層１２および上部ガイド層１４の材料としては、公知の化合物半導体材料を用いることができ、発光層１３の材料に対して適した材料を選択するのが好ましい。例えば、ＡｌＧａＡｓ、ＡｌＧａＩｎＰを用いることができる。 As the material of the lower guide layer 12 and the upper guide layer 14, a known compound semiconductor material can be used, and it is preferable to select a material suitable for the material of the light emitting layer 13. For example, AlGaAs or AlGaInP can be used.
　例えば、井戸層１７の材料としてＡｌＧａＡｓ又はＩｎＧａＡｓを用い、バリア層１８の材料としてＡｌＧａＡｓ又はＡｌＧａＩｎＰを用いた場合、下部ガイド層１２および上部ガイド層１４の材料としてはＡｌＧａＡｓ又はＡｌＧａＩｎＰが好ましい。下部ガイド層１２および上部ガイド層１４の材料としてＡｌＧａＩｎＰを用いた場合、欠陥を作りやすいＡｓを含まないので結晶性が高く、高出力に寄与する。
　井戸層１７の材料として（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）を用いた場合、ガイド層１４の材料としてよりＡｌ組成の高い（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ４≦１，０＜Ｙ１≦１，Ｘ１＜Ｘ４）または井戸層（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）よりバンドギャップエネルギーが大きくなるＡｌＧａＡｓを用いることができる。 For example, when AlGaAs or InGaAs is used as the material of the well layer 17 and AlGaAs or AlGaInP is used as the material of the barrier layer 18, the material of the lower guide layer 12 and the upper guide layer 14 is preferably AlGaAs or AlGaInP. When AlGaInP is used as the material of the lower guide layer 12 and the upper guide layer 14, since it does not contain As which tends to form defects, the crystallinity is high and contributes to high output.
When (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1) is used as the material of the well layer 17, the Al composition is higher than the material of the guide layer 14 ( Al X4 Ga 1-X4 ) Y1 In 1-Y1 P (0 ≦ X4 ≦ 1, 0 <Y1 ≦ 1, X1 <X4) or well layer (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ AlGaAs whose band gap energy is larger than X1 ≦ 1, 0 <Y1 ≦ 1) can be used.
　下部ガイド層１２及び上部ガイド層１４は、夫々、下部クラッド層１１及び上部クラッド層１５と活性層１１との欠陥の伝搬を低減するために設けられている。このため、下部ガイド層１２および上部ガイド層１４の層厚は１０ｎｍ以上が好ましく、２０ｎｍ～１００ｎｍがより好ましい。 The lower guide layer 12 and the upper guide layer 14 are provided to reduce the propagation of defects between the lower clad layer 11 and the upper clad layer 15 and the active layer 11, respectively. For this reason, the layer thickness of the lower guide layer 12 and the upper guide layer 14 is preferably 10 nm or more, and more preferably 20 nm to 100 nm.
　下部ガイド層１２及び上部ガイド層１４の伝導型は特に限定されるものではなく、アンドープ、ｐ型及びｎ型のいずれも選択することができる。発光効率を高めるには、結晶性が良好なアンドープ又は３×１０１７ｃｍ－３未満のキャリア濃度とすることが望ましい。 The conductivity types of the lower guide layer 12 and the upper guide layer 14 are not particularly limited, and any of undoped, p-type, and n-type can be selected. In order to increase the light emission efficiency, it is desirable that the crystallinity be undoped or the carrier concentration be less than 3 × 10 17 cm −3 .
　下部クラッド層１１及び上部クラッド層１５は、図４に示すように、下部ガイド層１２の下面及び上部ガイド層１４上面にそれぞれ設けられている。 The lower cladding layer 11 and the upper cladding layer 15 are provided on the lower surface of the lower guide layer 12 and the upper surface of the upper guide layer 14, respectively, as shown in FIG.
　下部クラッド層１１及び上部クラッド層１５の材料としては、公知の化合物半導体材料を用いることができ、発光層１３の材料に対して適した材料を選択するのが好ましい。例えば、ＡｌＧａＡｓ、ＡｌＧａＩｎＰを用いることができる。 A known compound semiconductor material can be used as the material of the lower cladding layer 11 and the upper cladding layer 15, and it is preferable to select a material suitable for the material of the light emitting layer 13. For example, AlGaAs or AlGaInP can be used.
　例えば、井戸層１７の材料としてＡｌＧａＡｓ又はＩｎＧａＡｓを用い、バリア層１８の材料としてＡｌＧａＡｓ又はＡｌＧａＩｎＰを用いた場合、下部クラッド層１１及び上部クラッド層１５の材料としてはＡｌＧａＡｓ又はＡｌＧａＩｎＰが好ましい。下部クラッド層１１及び上部クラッド層１５の材料としてＡｌＧａＩｎＰを用いた場合、欠陥を作りやすいＡｓを含まないので結晶性が高く、高出力に寄与する。
　井戸層１７の材料として（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）を用いた場合、クラッド層１５の材料としてよりＡｌ組成の高い（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ４≦１，０＜Ｙ１≦１，Ｘ１＜Ｘ４）または井戸層（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）よりバンドギャップエネルギーが大きくなるＡｌＧａＡｓを用いることができる。 For example, when AlGaAs or InGaAs is used as the material of the well layer 17 and AlGaAs or AlGaInP is used as the material of the barrier layer 18, the material of the lower cladding layer 11 and the upper cladding layer 15 is preferably AlGaAs or AlGaInP. When AlGaInP is used as the material of the lower clad layer 11 and the upper clad layer 15, it does not contain As which easily creates defects, so that the crystallinity is high and contributes to high output.
When (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1) is used as the material of the well layer 17, the Al composition is higher than the material of the cladding layer 15 ( Al X4 Ga 1-X4 ) Y1 In 1-Y1 P (0 ≦ X4 ≦ 1, 0 <Y1 ≦ 1, X1 <X4) or well layer (Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ AlGaAs whose band gap energy is larger than X1 ≦ 1, 0 <Y1 ≦ 1) can be used.
　下部クラッド層１１と上部クラッド層１５とは、極性が異なるように構成されている。
また、下部クラッド層１１及び上部クラッド層１５のキャリア濃度及び厚さは、公知の好適な範囲を用いることができ、活性層１１の発光効率が高まるように条件を最適化することが好ましい。なお、下部および上部クラッド層は設けなくてもよい。
　また、下部クラッド層１１及び上部クラッド層１５の組成を制御することによって、化合物半導体層２０の反りを低減させることができる。 The lower cladding layer 11 and the upper cladding layer 15 are configured to have different polarities.
The carrier concentration and thickness of the lower clad layer 11 and the upper clad layer 15 can be in a known suitable range, and the conditions are preferably optimized so that the light emission efficiency of the active layer 11 is increased. The lower and upper clad layers need not be provided.
Further, by controlling the composition of the lower clad layer 11 and the upper clad layer 15, the warpage of the compound semiconductor layer 20 can be reduced.
　コンタクト層５は、電極との接触抵抗を低下させるために設けられている。コンタクト層５の材料は、発光層１３よりバンドギャップの大きい材料であることが好ましい。また、コンタクト層５のキャリア濃度の下限値は、電極との接触抵抗を低下させるために５×１０１７ｃｍ－３以上であることが好ましく、１×１０１８ｃｍ－３以上がより好ましい。キャリア濃度の上限値は、結晶性の低下が起こりやすくなる２×１０１９ｃｍ－３以下が望ましい。コンタクト層５の厚さは、０．０５μｍ以上が好ましい。コンタクト層５の厚さの上限値は特に限定されないが、エピタキシャル成長に係るコストを適正範囲にするため、１０μｍ以下とすることが望ましい。 The contact layer 5 is provided in order to reduce the contact resistance with the electrode. The material of the contact layer 5 is preferably a material having a band gap larger than that of the light emitting layer 13. The lower limit value of the carrier concentration of the contact layer 5 is preferably 5 × 10 17 cm −3 or more and more preferably 1 × 10 18 cm −3 or more in order to reduce the contact resistance with the electrode. The upper limit value of the carrier concentration is desirably 2 × 10 19 cm −3 or less at which the crystallinity is likely to decrease. The thickness of the contact layer 5 is preferably 0.05 μm or more. The upper limit value of the thickness of the contact layer 5 is not particularly limited, but is desirably 10 μm or less in order to make the cost for epitaxial growth within an appropriate range.
　本発明の発光ダイオードは、ランプ、バックライト、携帯電話、ディスプレイ、各種パネル類、コンピュータ、ゲーム機、照明などの電子機器や、それらの電子機器を組み込んだ自動車などの機械装置等に組み込むことができる。 The light-emitting diode of the present invention can be incorporated into electronic devices such as lamps, backlights, mobile phones, displays, various panels, computers, game machines, lighting, etc., and machinery such as automobiles incorporating such electronic devices. it can.
〔発光ダイオード（第２の実施形態）〕
　図５に、本発明を適用した発光ダイオードの一例である共振器型発光ダイオードの他の例を示した断面模式図を示す。
　第1の実施形態においては、光射出孔の下に保護膜が形成されており、メサ型構造部の頂面において保護膜を介して光射出孔から光を取り出す構成であったが、第２の実施形態は、光射出孔の下に保護膜を有さず、保護膜を介さずに光射出孔９ｂから直接、光を取り出す構成である。
　すなわち、第２の実施形態に係る共振器型発光ダイオード２００では、保護膜２８は、平坦部６の少なくとも一部２８ｃと、メサ型構造部７の傾斜側面７ａと、メサ型構造部７の頂面７ｂの周縁領域７ｂａとを覆うとともに、平面視して周縁領域７ｂａの内側にコンタクト層５の表面を露出する通電窓２８ｂを有し、電極膜２９は、保護膜２８を介して平坦部６の少なくとも一部と、保護膜２８を介してメサ型構造部７の傾斜側面７ａと、保護膜２８を介してメサ型構造部７の頂面７ｂの周縁領域７ｂａとを覆い、さらに、メサ型構造部７の頂面において通電窓２８ｂから露出するコンタクト層５の表面の一部だけを覆ってコンタクト層５の表面の他の部分５ａを露出する光射出孔２９ｂを有する、ことを特徴とする。 [Light-Emitting Diode (Second Embodiment)]
FIG. 5 is a schematic cross-sectional view showing another example of a resonator type light emitting diode which is an example of a light emitting diode to which the present invention is applied.
In the first embodiment, a protective film is formed under the light emitting hole, and light is extracted from the light emitting hole through the protective film on the top surface of the mesa structure portion. In this embodiment, the protective film is not provided under the light emitting hole, and light is directly extracted from the light emitting hole 9b without the protective film.
That is, in the resonator type light emitting diode 200 according to the second embodiment, the protective film 28 includes at least a part 28 c of the flat portion 6, the inclined side surface 7 a of the mesa structure portion 7, and the top of the mesa structure portion 7. The electrode 7 has a flat portion 6 through the protective film 28, covering the peripheral area 7 ba of the surface 7 b and having a conduction window 28 b exposing the surface of the contact layer 5 inside the peripheral area 7 ba in plan view. At least a part thereof, the inclined side surface 7a of the mesa structure 7 through the protective film 28, and the peripheral region 7ba of the top surface 7b of the mesa structure 7 through the protective film 28. It has a light emission hole 29b which covers only a part of the surface of the contact layer 5 exposed from the energizing window 28b on the top surface of the structure portion 7 and exposes the other part 5a of the surface of the contact layer 5. .
　図５に示すように、第２の実施形態の保護膜２８は、メサ型構造部７の傾斜側面７ａを覆う部分２８ａと、平坦部６の少なくとも一部を覆う部分２８ｃ（メサ型構造部７を挟んで反対側の平坦部を覆う部分２８ｃｃも含む）と、メサ型構造部７の頂面７ｂの周縁領域７ｂａを覆う部分２８ｂａとからなり、平面視して周縁領域７ｂａの内側にコンタクト層５の表面を露出する通電窓２８ｂを有する。すなわち、通電窓２８ｂはメサ型構造部７の頂面７ｂにおいてコンタクト層５の表面のうち、周縁領域７ｂａの下に位置する部分以外を露出する。保護膜８の上に電極層(おもて面電極層)９を形成するが、この電極層９と裏面電極１０との間において電流を流さない部分に保護膜８を形成している。 As shown in FIG. 5, the protective film 28 of the second embodiment includes a portion 28 a that covers the inclined side surface 7 a of the mesa structure portion 7 and a portion 28 c that covers at least a part of the flat portion 6 (the mesa structure portion 7. And a portion 28ba covering the peripheral region 7ba of the top surface 7b of the mesa structure 7 and a contact layer inside the peripheral region 7ba in plan view. 5 has an energizing window 28b that exposes the surface of 5. That is, the energization window 28 b exposes the surface of the contact layer 5 other than the portion located below the peripheral region 7 ba on the top surface 7 b of the mesa structure 7. An electrode layer (front electrode layer) 9 is formed on the protective film 8, and the protective film 8 is formed in a portion where no current flows between the electrode layer 9 and the back electrode 10.
　また、図５に示すように、第２の実施形態の電極層(おもて面電極層)２９は、保護膜２８のうち傾斜側面７ａを覆う部分２８ａを覆う部分２９ａと、保護膜２８のうち平坦部６の少なくとも一部を覆う部分２８ｃを覆う部分２９ｃと、保護膜２８のうちメサ型構造部７の頂面７ｂの周縁領域７ｂａを覆う部分２８ｂａの部分を覆う部分２９ｂａと、メサ型構造部７の頂面７ｂにおいて保護膜２８のうち符号２８ｂａの部分を越えて光射出孔２９ｂを開口するようにコンタクト層５を覆う部分２９ｂｂとからなる。
　第２の実施形態の電極層(おもて面電極層)２９では、部分２９ｂｂが上記の第１の機能及び第２の機能の両方を担っている。 Further, as shown in FIG. 5, the electrode layer (front surface electrode layer) 29 of the second embodiment includes a portion 29 a that covers a portion 28 a that covers the inclined side surface 7 a of the protective film 28, and a protective film 28. Of these, a portion 29c covering a portion 28c covering at least a part of the flat portion 6, a portion 29ba covering a portion 28ba of the protective film 28 covering the peripheral region 7ba of the top surface 7b of the mesa structure portion 7, and a mesa type The top surface 7b of the structure portion 7 includes a portion 29bb that covers the contact layer 5 so as to open the light emission hole 29b beyond the portion 28ba of the protective film 28.
In the electrode layer (front electrode layer) 29 of the second embodiment, the portion 29bb has both the first function and the second function.
〔発光ダイオード（第３の実施形態）〕
　本発明を適用した第３の実施形態の発光ダイオードは、第１の実施形態の発光ダイオードと比較すると、上部ＤＢＲ反射層がなく、その替わりに電流拡散層を備えた点が異なる。 [Light Emitting Diode (Third Embodiment)]
The light-emitting diode according to the third embodiment to which the present invention is applied differs from the light-emitting diode according to the first embodiment in that there is no upper DBR reflection layer and a current diffusion layer is provided instead.
　図６に、第３の実施形態に係る発光ダイオード３００の一例の断面模式図を示す。
図６に示すように、発光ダイオード３００は、活性層３上に電流拡散層４０を備えた構成である。 FIG. 6 is a schematic cross-sectional view of an example of a light emitting diode 300 according to the third embodiment.
As shown in FIG. 6, the light emitting diode 300 has a configuration in which a current diffusion layer 40 is provided on the active layer 3.
　本実施形態では、電流拡散層４０の材料としては、例えば、ＡｌＧａＡｓ等を用いることができる。
　電流拡散層４０の厚さとしては、０．１μｍ以上１０μｍ以下であることが好ましい。
０．１μｍ未満では電流拡散効果が不十分だからであり、１０μｍを超えると効果に対しエピタキシャル成長に係わるコストが大きすぎるからである。 In the present embodiment, as the material of the current diffusion layer 40, for example, AlGaAs or the like can be used.
The thickness of the current diffusion layer 40 is preferably 0.1 μm or more and 10 μm or less.
If the thickness is less than 0.1 μm, the current diffusion effect is insufficient, and if it exceeds 10 μm, the cost for epitaxial growth is too large for the effect.
〔発光ダイオード（第４の実施形態）〕
　本発明を適用した第４の実施形態の発光ダイオードは、第１の実施形態の発光ダイオードと比較すると、上部ＤＢＲ反射層がなく、また、下部ＤＢＲ反射層に替えて金属からなる反射層を備えると共に、基板として金属基板やシリコンやゲルマニウム等からなる基板の導電性基板を備えた点が異なる。
　なお、本実施形態では、上部クラッド層が第３の実施形態における電流拡散層４０の電流拡散機能をも有する構成としてもよい。 [Light Emitting Diode (Fourth Embodiment)]
The light-emitting diode according to the fourth embodiment to which the present invention is applied has no upper DBR reflective layer as compared with the light-emitting diode according to the first embodiment, and includes a reflective layer made of metal instead of the lower DBR reflective layer. In addition, a difference is that a conductive substrate of a metal substrate or a substrate made of silicon, germanium or the like is provided as a substrate.
In the present embodiment, the upper clad layer may have a current diffusion function of the current diffusion layer 40 in the third embodiment.
　図７に、第４の実施形態に係る発光ダイオード４００の一例の断面模式図を示す。
　図７に示すように、発光ダイオード４００は、導電性基板５１上に金属からなる反射層５２、ＧａＰ層５３、活性層５４、コンタクト層５を順に備えた発光ダイオードである。
また、導電性基板５１の下面側には裏面電極５６を備えている。 In FIG. 7, the cross-sectional schematic diagram of an example of the light emitting diode 400 which concerns on 4th Embodiment is shown.
As shown in FIG. 7, the light emitting diode 400 is a light emitting diode including a reflective layer 52 made of a metal, a GaP layer 53, an active layer 54, and a contact layer 5 in this order on a conductive substrate 51.
Further, a back electrode 56 is provided on the lower surface side of the conductive substrate 51.
　金属からなる反射層５２としては、発光波長に対して９０％以上の反射率を有する金属が好ましく、例えば、金（Ａｕ）、銀（Ａｇ）、銅（Ｃｕ）、アルミニウム（Ａｌ）、又はこれらの合金やＡｇＰｄＣｕ合金（ＡＰＣ）により構成される。 The reflective layer 52 made of metal is preferably a metal having a reflectance of 90% or more with respect to the emission wavelength. For example, gold (Au), silver (Ag), copper (Cu), aluminum (Al), or these Or an AgPdCu alloy (APC).
　活性層５４は、上部クラッド層６３ａと、発光層６４と、下部クラッド層６３ｂとを含む構成であるが、上部クラッド層に、第３の実施形態における電流拡散層４０の電流拡散機能をも持たせる場合、上部クラッド６３ａの厚さとしては、０．１μｍ以上１０μｍ以下であることが好ましい。０．１μｍ未満では電流拡散効果が不十分だからであり、１０μｍを超えると効果に対しエピタキシャル成長に係わるコストが大きすぎるからである。 The active layer 54 includes an upper clad layer 63a, a light emitting layer 64, and a lower clad layer 63b. The upper clad layer also has a current spreading function of the current spreading layer 40 in the third embodiment. In this case, the thickness of the upper clad 63a is preferably 0.1 μm or more and 10 μm or less. If the thickness is less than 0.1 μm, the current diffusion effect is insufficient, and if it exceeds 10 μm, the cost for epitaxial growth is too large for the effect.
　ＧａＰ層５３は、金属からなる反射層５２と、化合物半導体からなる活性層５４の両方に対して接触抵抗を低く両者を電気的に接続することができる。かかる機能を有する材料であれば、ＧａＰに限らず、（ＡｌｘＧａ(１－ｘ)）（１－ｙ）ＩｎｙＰ、（ＡｌｘＧａ（１－ｘ））（１－ｙ）ＩｎｙＡｓ等を用いることができる。
　ＧａＰ層５３の厚さとしては、１μｍ以上５μｍ以下であることが好ましい。１μｍ未満では接合界面の応力により、発光出力が低下するからであり、５μｍを超えると効果に対しエピタキシャル成長に係わるコストが大きすぎるからである。 The GaP layer 53 has a low contact resistance and can be electrically connected to both the reflective layer 52 made of metal and the active layer 54 made of a compound semiconductor. Any material having such a function is not limited to GaP, but (Al x Ga (1-x) ) (1-y) In y P, (Al x Ga (1-x) ) (1-y) In y As or the like can be used.
The thickness of the GaP layer 53 is preferably 1 μm or more and 5 μm or less. This is because if the thickness is less than 1 μm, the light emission output decreases due to the stress at the bonding interface, and if it exceeds 5 μm, the cost for the epitaxial growth is too large for the effect.
　導電性基板５１の材料としては、金属、Ｓｉ、Ｇｅ、ＧａＰ、ＧａＩｎＰ、ＳｉＣ等を用いることができる。Ｓｉ基板、Ｇｅ基板は安価で耐湿性に優れているという利点がある。ＧａＰ、ＧａＩｎＰ、ＳｉＣ基板は、発光部と熱膨張係数が近く、耐湿性に優れ、熱伝導性が良いという利点がある。金属基板はコスト面、機械強度、放熱性の観点から優れており、また、後述するように、複数の金属層（金属板）を積層した構造とすることにより、金属基板全体として熱膨張係数を調整できるという利点がある。 As a material of the conductive substrate 51, metal, Si, Ge, GaP, GaInP, SiC, or the like can be used. Si substrates and Ge substrates are advantageous in that they are inexpensive and have excellent moisture resistance. GaP, GaInP, and SiC substrates have the advantage that they have a thermal expansion coefficient close to that of the light emitting portion, excellent moisture resistance, and good thermal conductivity. The metal substrate is excellent from the viewpoints of cost, mechanical strength, and heat dissipation, and, as will be described later, by having a structure in which a plurality of metal layers (metal plates) are laminated, the thermal expansion coefficient of the entire metal substrate is increased. There is an advantage that it can be adjusted.
　導電性基板５１として金属基板を用いる場合、複数の金属層（金属板）を積層した構造とすることができる。　
　複数の金属層（金属板）を積層した構造とする場合、２種類の金属層が交互に積層されてなるのが好ましく、特に、この２種類の金属層（例えば、これらを第1の金属層、第２の金属層という）の層数は合わせて奇数とするのが好ましい。 When a metal substrate is used as the conductive substrate 51, a structure in which a plurality of metal layers (metal plates) are stacked can be employed.
In the case of a structure in which a plurality of metal layers (metal plates) are laminated, it is preferable that two types of metal layers are alternately laminated, and in particular, these two types of metal layers (for example, the first metal layer). The number of layers of the second metal layer is preferably an odd number in total.
　例えば、第２の金属層を第1の金属層で挟んだ金属基板とした場合、金属基板の反りや割れの観点から、第２の金属層として化合物半導体層より熱膨張係数が小さい材料を用いるときは、第１の金属層、を化合物半導体層３より熱膨張係数が大きい材料からなるものを用いるのが好ましい。金属基板全体としての熱膨張係数が化合物半導体層の熱膨張係数に近いものとなるため、化合物半導体層と金属基板とを接合する際の金属基板の反りや割れを抑制することができ、発光ダイオードの製造歩留まりを向上させることができるからである。同様に、第２の金属層として化合物半導体層２より熱膨張係数が大きい材料を用いるときは、第１の金属層、を化合物半導体層２より熱膨張係数が小さい材料からなるものを用いるのが好ましい。金属基板全体としての熱膨張係数が化合物半導体層の熱膨張係数に近いものとなるため、化合物半導体層と金属基板とを接合する際の金属基板の反りや割れを抑制でき、発光ダイオードの製造歩留まりを向上できるからである。
　以上の観点からは、２種類の金属層はいずれが第１の金属層でも第２の金属層でも構わない。
　２種類の金属層としては、例えば、銀（熱膨張係数＝１８．９ｐｐｍ／Ｋ）、銅（熱膨張係数＝１６．５ｐｐｍ／Ｋ）、金（熱膨張係数＝１４．２ｐｐｍ／Ｋ）、アルミニウム（熱膨張係数＝２３．１ｐｐｍ／Ｋ）、ニッケル（熱膨張係数＝１３．４ｐｐｍ／Ｋ）およびこれらの合金のいずれかからなる金属層と、モリブデン（熱膨張係数＝５．１ｐｐｍ／Ｋ）、タングステン（熱膨張係数＝４．３ｐｐｍ／Ｋ）、クロム（熱膨張係数＝４．９ｐｐｍ／Ｋ）およびこれらの合金のいずれかからなる金属層との組み合わせを用いることができる。
　好適な例としては、Ｃｕ／Ｍｏ／Ｃｕの３層からなる金属基板があげられる。上記の観点ではＭｏ／Ｃｕ／Ｍｏの３層からなる金属基板でも同様な効果が得られるが、Ｃｕ／Ｍｏ／Ｃｕの３層からなる金属基板は、機械的強度が高いＭｏを加工しやすいＣｕで挟んだ構成なので、Ｍｏ／Ｃｕ／Ｍｏの３層からなる金属基板よりも切断等の加工が容易であるという利点がある。 For example, when a metal substrate having the second metal layer sandwiched between the first metal layers is used, a material having a smaller thermal expansion coefficient than the compound semiconductor layer is used as the second metal layer from the viewpoint of warping or cracking of the metal substrate. In some cases, it is preferable to use the first metal layer made of a material having a thermal expansion coefficient larger than that of the compound semiconductor layer 3. Since the thermal expansion coefficient of the metal substrate as a whole is close to the thermal expansion coefficient of the compound semiconductor layer, it is possible to suppress warping and cracking of the metal substrate when the compound semiconductor layer and the metal substrate are joined, and the light emitting diode This is because the production yield can be improved. Similarly, when a material having a larger thermal expansion coefficient than that of the compound semiconductor layer 2 is used as the second metal layer, the first metal layer may be made of a material having a smaller thermal expansion coefficient than that of the compound semiconductor layer 2. preferable. Since the thermal expansion coefficient of the metal substrate as a whole is close to the thermal expansion coefficient of the compound semiconductor layer, it is possible to suppress warping and cracking of the metal substrate when joining the compound semiconductor layer and the metal substrate, and the production yield of light emitting diodes It is because it can improve.
From the above viewpoint, any of the two types of metal layers may be the first metal layer or the second metal layer.
Examples of the two metal layers include silver (thermal expansion coefficient = 18.9 ppm / K), copper (thermal expansion coefficient = 16.5 ppm / K), gold (thermal expansion coefficient = 14.2 ppm / K), and aluminum. (Thermal expansion coefficient = 23.1 ppm / K), nickel (thermal expansion coefficient = 13.4 ppm / K) and a metal layer made of any of these alloys, molybdenum (thermal expansion coefficient = 5.1 ppm / K), Combinations of tungsten (thermal expansion coefficient = 4.3 ppm / K), chromium (thermal expansion coefficient = 4.9 ppm / K), and a metal layer made of any of these alloys can be used.
A preferred example is a metal substrate composed of three layers of Cu / Mo / Cu. From the above viewpoint, the same effect can be obtained with a metal substrate composed of three layers of Mo / Cu / Mo, but the metal substrate composed of three layers of Cu / Mo / Cu is a Cu layer that has high mechanical strength and is easy to process Mo. Therefore, there is an advantage that processing such as cutting is easier than a metal substrate composed of three layers of Mo / Cu / Mo.
　金属基板全体としての熱膨張係数は例えば、Ｃｕ（３０μｍ）／Ｍｏ（２５μｍ）／Ｃｕ（３０μｍ）の３層からなる金属基板では６．１ｐｐｍ／Ｋであり、Ｍｏ（２５μｍ）／Ｃｕ（７０μｍ）／Ｍｏ（２５μｍ）の３層からなる金属基板では５．７ｐｐｍ／Ｋとなる。 The thermal expansion coefficient of the entire metal substrate is, for example, 6.1 ppm / K for a three-layer metal substrate of Cu (30 μm) / Mo (25 μm) / Cu (30 μm), and Mo (25 μm) / Cu (70 μm). In the case of a metal substrate composed of three layers of / Mo (25 μm), it is 5.7 ppm / K.
　また、放熱の観点からは、金属基板を構成する金属層は熱伝導率が高い材料からなるのが好ましい。これにより、金属基板の放熱性を高くして、発光ダイオードを高輝度で発光させることができるとともに、発光ダイオードの寿命を長寿命とすることができるからである。
　例えば、銀（熱伝導率＝４２０Ｗ／ｍ・Ｋ）、銅（熱伝導率＝３９８Ｗ／ｍ・Ｋ）、金（熱伝導率＝３２０Ｗ／ｍ・Ｋ）、アルミニウム（熱伝導率＝２３６Ｗ／ｍ・Ｋ）、モリブデン（熱伝導率＝１３８Ｗ／ｍ・Ｋ）、タングステン（熱伝導率＝１７４Ｗ／ｍ・Ｋ）およびこれらの合金などを用いることが好ましい。
　それらの金属層の熱膨張係数が化合物半導体層の熱膨張係数と略等しい材料からなるのがさらに好ましい。特に、金属層の材料が、化合物半導体層の熱膨張係数の±１．５ｐｐｍ／Ｋ以内である熱膨張係数を有する材料であるのが好ましい。これにより、金属基板と化合物半導体層との接合時の発光部への熱によるストレスを小さくすることができ、金属基板を化合物半導体層と接続させたときの熱による金属基板の割れを抑制することができ、発光ダイオードの製造歩留まりを向上させることができる。
　金属基板全体としての熱伝導率は例えば、Ｃｕ（３０μｍ）／Ｍｏ（２５μｍ）／Ｃｕ（３０μｍ）の３層からなる金属基板では２５０Ｗ／ｍ・Ｋとなり、Ｍｏ（２５μｍ）／Ｃｕ（７０μｍ）／Ｍｏ（２５μｍ）の３層からなる金属基板では２２０Ｗ／ｍ・Ｋとなる。 From the viewpoint of heat dissipation, the metal layer constituting the metal substrate is preferably made of a material having high thermal conductivity. This is because the heat dissipation of the metal substrate can be increased, the light emitting diode can emit light with high brightness, and the life of the light emitting diode can be extended.
For example, silver (thermal conductivity = 420 W / m · K), copper (thermal conductivity = 398 W / m · K), gold (thermal conductivity = 320 W / m · K), aluminum (thermal conductivity = 236 W / m) · K), molybdenum (thermal conductivity = 138 W / m · K), tungsten (thermal conductivity = 174 W / m · K), and alloys thereof are preferably used.
More preferably, the metal layers are made of a material having a thermal expansion coefficient substantially equal to that of the compound semiconductor layer. In particular, the material of the metal layer is preferably a material having a thermal expansion coefficient that is within ± 1.5 ppm / K of the thermal expansion coefficient of the compound semiconductor layer. As a result, it is possible to reduce stress due to heat applied to the light emitting portion when the metal substrate and the compound semiconductor layer are joined, and to suppress cracking of the metal substrate due to heat when the metal substrate is connected to the compound semiconductor layer. The manufacturing yield of the light emitting diode can be improved.
The thermal conductivity of the entire metal substrate is, for example, 250 W / m · K for a three-layer metal substrate of Cu (30 μm) / Mo (25 μm) / Cu (30 μm), and Mo (25 μm) / Cu (70 μm) / In the case of a metal substrate composed of three layers of Mo (25 μm), it is 220 W / m · K.
　また、金属基板の上面及び下面を金属保護膜で覆うことが好ましい。さらにその側面も金属保護膜で覆うことが好ましい。
　金属保護膜の材料としては、密着性に優れるクロム、ニッケル、化学的に安定な白金、又は金の少なくともいずれか一つを含む金属からなるものであることが好ましい。
　金属保護膜は密着性がよいニッケルと耐薬品に優れる金を組み合わせた層からなるのが最適である。
　金属保護膜の厚さは特に制限はないが、エッチング液に対する耐性とコストのバランスから、０．２～５μｍ、好ましくは、０．５～３μｍが適正な範囲である。高価な金の場合は、厚さは２μｍ以下が望ましい。 Moreover, it is preferable to cover the upper surface and the lower surface of the metal substrate with a metal protective film. Further, it is preferable to cover the side surface with a metal protective film.
The material for the metal protective film is preferably made of a metal containing at least one of chromium, nickel, chemically stable platinum, and gold having excellent adhesion.
The metal protective film is optimally composed of a layer combining nickel having good adhesion and gold having excellent chemical resistance.
The thickness of the metal protective film is not particularly limited, but in the range of 0.2 to 5 μm, preferably 0.5 to 3 μm, from the balance between resistance to the etching solution and cost. In the case of expensive gold, the thickness is desirably 2 μm or less.
〔発光ダイオード（第1の実施形態）の製造方法〕
　次に、本発明の発光ダイオードの製造方法の一実施形態として、第1の実施形態の発光ダイオード（共振器型発光ダイオード）の製造方法を説明する。
　図８は、発光ダイオードの製造方法の一工程を示す断面摸式図である。また、図９は、図８の後の一工程を示す断面摸式図である。 [Method for Manufacturing Light-Emitting Diode (First Embodiment)]
Next, as an embodiment of the light emitting diode manufacturing method of the present invention, a method for manufacturing the light emitting diode (resonator light emitting diode) of the first embodiment will be described.
FIG. 8 is a schematic cross-sectional view showing one step of a method for manufacturing a light emitting diode. FIG. 9 is a schematic sectional view showing one process after FIG.
（化合物半導体層の形成工程）
　まず、図８に示す化合物半導体層２０を作製する。
　化合物半導体層２０は、基板１上に、下部ＤＢＲ層２と、活性層３と、上部ＤＢＲ層４と、コンタクト層５とを順次積層して作製する。 (Formation process of compound semiconductor layer)
First, the compound semiconductor layer 20 shown in FIG. 8 is produced.
The compound semiconductor layer 20 is produced by sequentially laminating the lower DBR layer 2, the active layer 3, the upper DBR layer 4, and the contact layer 5 on the substrate 1.
　基板１と下部ＤＢＲ層２との間に、緩衝層（バッファ）を設けてもよい。緩衝層は、基板１と活性層３の構成層との欠陥の伝搬を低減するために設けられている。このため、基板の品質やエピタキシャル成長条件を選択すれば、緩衝層は、必ずしも必要ではない。また、緩衝層の材質は、エピタキシャル成長させる基板と同じ材質とすることが好ましい。
緩衝層には、欠陥の伝搬を低減するために基板と異なる材質からなる多層膜を用いることもできる。緩衝層の厚さは、０．１μｍ以上とすることが好ましく、０．２μｍ以上とすることがより好ましい。 A buffer layer (buffer) may be provided between the substrate 1 and the lower DBR layer 2. The buffer layer is provided in order to reduce the propagation of defects between the substrate 1 and the constituent layers of the active layer 3. For this reason, the buffer layer is not necessarily required if the quality of the substrate and the epitaxial growth conditions are selected. The material of the buffer layer is preferably the same as that of the substrate to be epitaxially grown.
As the buffer layer, a multilayer film made of a material different from that of the substrate can be used in order to reduce the propagation of defects. The thickness of the buffer layer is preferably 0.1 μm or more, and more preferably 0.2 μm or more.
　本実施形態では、分子線エピタキシャル法（ＭＢＥ）や減圧有機金属化学気相堆積法（ＭＯＣＶＤ法）等の公知の成長方法を適用することができる。なかでも、量産性に優れるＭＯＣＶＤ法を適用することが、最も望ましい。具体的には、化合物半導体層のエピタキシャル成長に使用する基板１は、成長前に洗浄工程や熱処理等の前処理を実施して、表面の汚染や自然酸化膜を除去することが望ましい。上記化合物半導体層を構成する各層は、直径５０～１５０ｍｍの基板１をＭＯＣＶＤ装置内にセットし、同時にエピタキシャル成長させて積層することができる。また、ＭＯＣＶＤ装置としては、自公転型、高速回転型等の市販の大型装置を適用することができる。 In this embodiment, a known growth method such as a molecular beam epitaxial method (MBE) or a low pressure metal organic chemical vapor deposition method (MOCVD method) can be applied. Among these, it is most desirable to apply the MOCVD method which is excellent in mass productivity. Specifically, it is desirable that the substrate 1 used for the epitaxial growth of the compound semiconductor layer is subjected to a pretreatment such as a cleaning process or a heat treatment before the growth to remove surface contamination or a natural oxide film. Each layer constituting the compound semiconductor layer can be laminated by setting a substrate 1 having a diameter of 50 to 150 mm in an MOCVD apparatus and simultaneously epitaxially growing the substrate 1. As the MOCVD apparatus, a commercially available large-sized apparatus such as a self-revolving type or a high-speed rotating type can be applied.
　上記化合物半導体層２０の各層をエピタキシャル成長する際、ＩＩＩ族構成元素の原料としては、例えば、トリメチルアルミニウム（（ＣＨ３）３Ａｌ）、トリメチルガリウム（（ＣＨ３）３Ｇａ）及びトリメチルインジウム（（ＣＨ３）３Ｉｎ）を用いることができる。また、Ｍｇのドーピング原料としては、例えば、ビスシクロペンタジエニルマグネシウム（ｂｉｓ－（Ｃ５Ｈ５）２Ｍｇ）等を用いることができる。また、Ｓｉのドーピング原料としては、例えば、ジシラン（Ｓｉ２Ｈ６）等を用いることができる。また、Ｖ族構成元素の原料としては、ホスフィン（ＰＨ３）、アルシン（ＡｓＨ３）等を用いることができる。
　さらに、各層のキャリア濃度及び層厚、温度条件は、適宜選択することができる。 When the layers of the compound semiconductor layer 20 are epitaxially grown, examples of the group III constituent element include trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga), and trimethylindium ((CH 3 ) 3 In) can be used. As a Mg doping material, for example, biscyclopentadienyl magnesium (bis- (C 5 H 5 ) 2 Mg) or the like can be used. Further, as a Si doping material, for example, disilane (Si 2 H 6 ) or the like can be used. In addition, phosphine (PH 3 ), arsine (AsH 3 ), or the like can be used as a raw material for the group V constituent element.
Furthermore, the carrier concentration, layer thickness, and temperature conditions of each layer can be selected as appropriate.
　このようにして作製した化合物半導体層は、活性層３を有するにもかかわらず結晶欠陥が少ない良好な表面状態が得られる。また、化合物半導体層２０は、素子構造に対応して研磨などの表面加工を施しても良い。 The compound semiconductor layer produced in this way has a good surface state with few crystal defects despite having the active layer 3. The compound semiconductor layer 20 may be subjected to surface processing such as polishing corresponding to the element structure.
（裏面電極の形成工程）
　次に、図８に示すように、基板１の裏面に、裏面電極１０を形成する。
　具体的には、例えば、基板がｎ型基板である場合には、蒸着法により、例えば、Ａｕ、ＡｕＧｅを順に積層してｎ型オーミック電極の裏面電極１０を形成する。 (Back electrode formation process)
Next, as shown in FIG. 8, the back electrode 10 is formed on the back surface of the substrate 1.
Specifically, for example, when the substrate is an n-type substrate, the back electrode 10 of the n-type ohmic electrode is formed by sequentially stacking, for example, Au and AuGe by vapor deposition.
（メサ型構造部の形成工程）
　次に、メサ型構造部（保護膜及び電極膜を除く）を形成するために、メサ型構造部以外の部分の化合物半導体層すなわち、コンタクト層と上部ＤＢＲ層と活性層の少なくとも一部と、又は、コンタクト層と上部ＤＢＲ層と活性層と下部ＤＢＲ層の少なくとも一部とをウェットエッチングする。
　具体的には、まず、図９に示すように、化合物半導体層の最上層であるコンタクト層上にフォトレジストを堆積し、フォトリソグラフィによりメサ型構造部以外に開口２３ａを有するレジストパターン２３を形成する。
　レジストパターンにおいてメサ型構造部形成予定箇所の大きさを、「メサ型構造部」の頂面より各辺上下左右１０μｍ程度大きめに形成するのが好ましい。 (Mesa structure forming process)
Next, in order to form a mesa structure part (excluding a protective film and an electrode film), a compound semiconductor layer other than the mesa structure part, that is, a contact layer, an upper DBR layer, and at least a part of the active layer, Alternatively, the contact layer, the upper DBR layer, the active layer, and at least part of the lower DBR layer are wet-etched.
Specifically, first, as shown in FIG. 9, a photoresist is deposited on the contact layer which is the uppermost layer of the compound semiconductor layer, and a resist pattern 23 having an opening 23a other than the mesa structure is formed by photolithography. To do.
In the resist pattern, it is preferable that the size of the mesa-type structure portion scheduled to be formed is larger than the top surface of the “mesa-type structure portion” by about 10 μm above, below, left and right of each side.
　次いで、例えば、リン酸／過酸化水素水混合液を用いて、メサ型構造部以外の部分のコンタクト層と上部ＤＢＲ層と活性層の少なくとも一部、又は、コンタクト層と上部ＤＢＲ層と活性層と下部ＤＢＲ層の少なくとも一部をエッチングして除去する。
　リン酸／過酸化水素水混合液としては例えば、Ｈ２ＰＯ４：Ｈ２Ｏ２：Ｈ２Ｏ＝１～３：４～６：８～１０のリン酸／過酸化水素水混合液を用いて、ウェットエッチング時間を３０～１２０秒間として、上記エッチング除去を行うことができる。
　その後、レジストを除去する。 Next, for example, using a phosphoric acid / hydrogen peroxide mixture, at least a part of the contact layer, the upper DBR layer, and the active layer other than the mesa structure portion, or the contact layer, the upper DBR layer, and the active layer And at least part of the lower DBR layer is removed by etching.
As the phosphoric acid / hydrogen peroxide solution mixture, for example, a phosphoric acid / hydrogen peroxide solution mixture of H 2 PO 4 : H 2 O 2 : H 2 O = 1 to 3: 4 to 6: 8 to 10 is used. Thus, the etching removal can be performed with a wet etching time of 30 to 120 seconds.
Thereafter, the resist is removed.
　メサ型構造部の平面視形状はレジストパターン２３の開口２３ａの形状によって決まる。レジストパターン２３に所望の平面視形状に対応する形状の開口２３ａを形成する。
　また、エッチングの深さすなわち、化合物半導体層のうち、どの層までエッチング除去するかは、エッチャントの種類及びエッチング時間によって決まる。 The plan view shape of the mesa structure portion is determined by the shape of the opening 23 a of the resist pattern 23. An opening 23 a having a shape corresponding to a desired shape in plan view is formed in the resist pattern 23.
In addition, the depth of etching, that is, to which layer of the compound semiconductor layer is removed by etching depends on the type of etchant and the etching time.
　図１０に、Ｈ２ＰＯ４：Ｈ２Ｏ２：Ｈ２Ｏ＝２：５：９（１００：２５０：４５０）、５６％（Ｈ２Ｏ）、液温３０℃～３４℃のエッチャントを用いて、後述する実施例１で示した化合物半導体層についてウェットエッチングを行った場合のエッチング時間に対する深さ及び幅の関係を示す。表１にその条件及び結果を数値で示す。 In FIG. 10, an etchant having H 2 PO 4 : H 2 O 2 : H 2 O = 2: 5: 9 (100: 250: 450), 56% (H 2 O) and a liquid temperature of 30 ° C. to 34 ° C. is used. The relationship between the depth and the width with respect to the etching time when wet etching is performed on the compound semiconductor layer shown in Example 1 described later is shown. Table 1 shows the conditions and results in numerical values.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　図１０及び表１から、エッチング深さ（図１の「ｈ」に相当）はエッチング時間（sec）にほぼ比例するが、エッチング幅はエッチング時間が長くなるほど増大率が大きくなることがわかる。すなわち、図３に示すように、深くなるほど（図で下方に行くほど）、メサ型構造部の水平断面積（又は、幅もしくは径）の増大率が大きくなるように形成される。このエッチング形状はドライエッチングによるエッチング形状とは異なる。従って、メサ型構造部の傾斜斜面の形状から、メサ型構造部がドライエッチングで形成されたのか、又は、ウェットエッチングで形成されたのかを判別することができる。 10 and Table 1, it can be seen that the etching depth (corresponding to “h” in FIG. 1) is substantially proportional to the etching time (sec), but the increasing rate of the etching width increases as the etching time increases. That is, as shown in FIG. 3, it is formed so that the increasing rate of the horizontal sectional area (or width or diameter) of the mesa structure portion increases as the depth increases (as it goes downward in the drawing). This etching shape is different from the etching shape by dry etching. Therefore, it can be determined from the shape of the inclined slope of the mesa structure portion whether the mesa structure portion is formed by dry etching or wet etching.
（保護膜の形成工程）
　次に、全面に保護膜８の材料を成膜する。具体的には、例えば、ＳｉＯ２を全面にスパッタリング法により成膜する。 (Protective film formation process)
Next, a material for the protective film 8 is formed on the entire surface. Specifically, for example, SiO 2 is formed on the entire surface by sputtering.
（ストリートおよびコンタクト層の部分の保護膜の除去工程）
次に、全面にフォトレジストを堆積し、フォトリソグラフィによりコンタクト層上の通電窓８ｂに対応する部分とストリートに対応する部分と、を開口とするレジストパターンを形成する。
　次いで、例えば、バッファードフッ酸を用いてウェットエッチングにより、メサ型構造部の頂面の通電窓８ｂに対応する部分とストリートに対応する部分の保護膜８の材料を除去して保護膜８を形成する。
　図１１に、保護膜８の通電窓８ｂ近傍の平面図を示す。
　その後、レジストを除去する。 (Removal process of protective film on street and contact layer)
Next, a photoresist is deposited on the entire surface, and a resist pattern having openings corresponding to the energization windows 8b on the contact layer and portions corresponding to the streets is formed by photolithography.
Next, the protective film 8 is removed by removing the material of the protective film 8 at the portion corresponding to the current-carrying window 8b on the top surface of the mesa structure and the portion corresponding to the street by wet etching using buffered hydrofluoric acid, for example. Form.
FIG. 11 shows a plan view of the vicinity of the energization window 8 b of the protective film 8.
Thereafter, the resist is removed.
（おもて面電極層の形成工程）
　次に、おもて面電極層９を形成する。すなわち、保護膜８上、及び、保護膜８の通電窓８ｂから露出しているコンタクト層５上に、光射出孔９ｂを有するおもて面電極層９を形成する。
具体的には、全面にフォトレジストを堆積し、フォトリソグラフィにより光射出孔９ｂに対応する部分と、ウェハ基板上の多数の発光ダイオード間の切断部分（ストリート）とを含む、電極膜が不要な部分以外を開口とするレジストパターンを形成する。次いで、電極層材料を蒸着する。この蒸着だけではメサ型構造部の傾斜側面には電極層材料が十分には蒸着されない場合は、さらに、メサ型構造部の傾斜側面に電極層材料を蒸着するために蒸着金属が回りこみやすいプラネタリタイプの蒸着装置を用いて蒸着を行う。
　その後、レジストを除去する。 (Front surface electrode layer formation process)
Next, the front electrode layer 9 is formed. That is, the front electrode layer 9 having the light emission holes 9 b is formed on the protective film 8 and on the contact layer 5 exposed from the energization window 8 b of the protective film 8.
Specifically, a photoresist is deposited on the entire surface, and an electrode film including a portion corresponding to the light emission hole 9b by photolithography and a cut portion (street) between a plurality of light emitting diodes on the wafer substrate is unnecessary. A resist pattern having openings other than the portions is formed. Next, an electrode layer material is deposited. If the electrode layer material is not sufficiently deposited on the inclined side surface of the mesa structure by this deposition alone, the deposited metal tends to wrap around in order to deposit the electrode layer material on the inclined side surface of the mesa structure. Vapor deposition is performed using a type of vapor deposition apparatus.
Thereafter, the resist is removed.
　光射出孔９ｂの形状はレジストパターン（図示せず）の開口の形状によって決まる。この開口形状を所望の光射出孔９ｂの形状に対応するものとしたレジストパターンを形成する。 The shape of the light emission hole 9b is determined by the shape of the opening of the resist pattern (not shown). A resist pattern having the opening shape corresponding to the shape of the desired light emission hole 9b is formed.
（個片化工程）
　次に、ウェハ基板上の発光ダイオードを個片化する。
　具体的には、例えば、ダイシングソーもしくはレーザーにより、ストリート部分を切断してウェハ基板上の発光ダイオード毎に切断して個片化する。 (Individualization process)
Next, the light emitting diodes on the wafer substrate are separated into individual pieces.
Specifically, for example, the street portion is cut by a dicing saw or a laser and cut into individual light emitting diodes on the wafer substrate.
〔発光ダイオード（第２の実施形態）の製造方法〕
　本発明の発光ダイオード（第２の実施形態）は、発光ダイオード（第１の実施形態）と保護膜及び電極の配置構成が異なるだけであり、その製造方法は発光ダイオード（第１の実施形態）の製造方法と同様に行うことができる。 [Method for Manufacturing Light-Emitting Diode (Second Embodiment)]
The light emitting diode (second embodiment) of the present invention is different from the light emitting diode (first embodiment) only in the arrangement of the protective film and the electrode, and the manufacturing method thereof is the light emitting diode (first embodiment). It can carry out similarly to the manufacturing method of.
〔発光ダイオード（第３の実施形態）の製造方法〕
　本発明の発光ダイオード（第３の実施形態）の製造方法において、発光ダイオード（第１の実施形態）の製造方法と異なる点は、化合物半導体層の形成工程で、基板１上に、下部ＤＢＲ層２と、活性層３とを積層した後、活性層３上に電流拡散層４０を積層する点であり、その他は発光ダイオード（第１の実施形態）の製造方法と同様に行うことができる。 [Method for Manufacturing Light Emitting Diode (Third Embodiment)]
The manufacturing method of the light emitting diode (third embodiment) of the present invention is different from the manufacturing method of the light emitting diode (first embodiment) in the formation process of the compound semiconductor layer on the substrate 1 and the lower DBR layer. 2 and the active layer 3 are stacked, and then the current diffusion layer 40 is stacked on the active layer 3. The rest can be performed in the same manner as in the method of manufacturing the light emitting diode (first embodiment).
〔発光ダイオード（第４の実施形態）の製造方法〕
　次に、本発明の発光ダイオード（第４の実施形態）の製造方法を説明する。
　基板５１として金属基板を用いた場合について説明する。 [Method for Manufacturing Light-Emitting Diode (Fourth Embodiment)]
Next, the manufacturing method of the light emitting diode (4th Embodiment) of this invention is demonstrated.
A case where a metal substrate is used as the substrate 51 will be described.
　＜金属基板の製造工程＞
　図１２（ａ）～図１２（ｃ）は、金属基板の製造工程を説明するための金属基板の一部の断面模式図である。
　金属基板５１として、熱膨張係数が活性層の材料より大きい第１の金属層（第１の金属板）５１ｂと、熱膨張係数が活性層の材料より小さい第２の金属層（第２の金属板）５１ａとを採用して、ホットプレスして形成する。 <Manufacturing process of metal substrate>
FIG. 12A to FIG. 12C are schematic cross-sectional views of a part of the metal substrate for explaining the manufacturing process of the metal substrate.
As the metal substrate 51, a first metal layer (first metal plate) 51b having a thermal expansion coefficient larger than the material of the active layer, and a second metal layer (second metal) having a thermal expansion coefficient smaller than the material of the active layer. Plate) 51a, and hot-pressed to form.
　具体的にはまず、２枚の略平板状の第１の金属層５１ｂと、１枚の略平板状の第２の金属層５１ａを用意する。例えば、第１の金属層５１ｂとしては厚さ１０μｍのＣｕ、第２の金属層５１ａとしては厚さ７５μｍのＭｏを用いる。
　次に、図１２（ａ）に示すように、２枚の第１の金属層５１ｂの間に第２の金属層５１ａを挿入してこれらを重ねて配置する。 Specifically, first, two substantially flat plate-like first metal layers 51b and one substantially flat plate-like second metal layer 51a are prepared. For example, Cu having a thickness of 10 μm is used as the first metal layer 51b, and Mo having a thickness of 75 μm is used as the second metal layer 51a.
Next, as shown in FIG. 12A, the second metal layer 51a is inserted between the two first metal layers 51b, and these layers are stacked.
　次に、重ね合わせたそれらの金属層を所定の加圧装置に配置して、高温下で第１の金属層５１ｂと第２の金属層５１ａに矢印の方向に荷重をかける。これにより、図１２（ｂ）に示すように、第１の金属層５１ｂがＣｕであり、第２の金属層５１ａがＭｏであり、Ｃｕ（１０μｍ）／Ｍｏ（７５μｍ）／Ｃｕ（１０μｍ）の３層からなる金属基板１を形成する。
　金属基板５１は、例えば、熱膨張係数が５．７ｐｐｍ／Ｋとなり、熱伝導率は２２０Ｗ／ｍ・Ｋとなる。 Next, these superimposed metal layers are placed in a predetermined pressure device, and a load is applied to the first metal layer 51b and the second metal layer 51a in the direction of the arrow at a high temperature. Thus, as shown in FIG. 12B, the first metal layer 51b is Cu, the second metal layer 51a is Mo, and Cu (10 μm) / Mo (75 μm) / Cu (10 μm). A metal substrate 1 having three layers is formed.
For example, the metal substrate 51 has a thermal expansion coefficient of 5.7 ppm / K and a thermal conductivity of 220 W / m · K.
　次に、図１２（ｃ）に示すように、金属基板１の全面すなわち、上面、下面及び側面を覆う金属保護膜５１ｃを形成する。このとき、金属基板は各発光ダイオードに個片化のために切断される前なので、金属保護膜が覆う側面とは金属基板（プレート）の外周側面である。従って、個片化後の各発光ダイオードの金属基板５１の側面を金属保護膜５１ｃで覆う場合には別途、金属保護膜で側面を覆う工程を実施する。
　図１２（ｃ）は、金属基板（プレート）の外周端側でない箇所の一部を示しているものであり、外周側面の金属保護膜は図に表れていない。 Next, as shown in FIG. 12C, a metal protective film 51c that covers the entire surface of the metal substrate 1, that is, the upper surface, the lower surface, and the side surfaces is formed. At this time, since the metal substrate is before being cut into individual light emitting diodes, the side surface covered by the metal protective film is the outer peripheral side surface of the metal substrate (plate). Therefore, when the side surface of the metal substrate 51 of each light-emitting diode after separation is covered with the metal protective film 51c, a step of covering the side surface with the metal protective film is performed separately.
FIG. 12C shows a part of the metal substrate (plate) that is not on the outer peripheral end side, and the metal protective film on the outer peripheral side surface does not appear in the figure.
　金属保護膜は公知の膜形成方法を用いることができるが、側面を含めた全面に膜形成ができるめっき法が最も好ましい。
例えば、無電解めっき法では、ニッケルその後、金をめっきし、金属基板の上面、側面、下面をニッケル膜及び金膜（金属保護膜）で覆われた金属基板５１を作製できる。
　めっき材質は、特に制限はなく、銅、銀、ニッケル、クロム、白金、金など公知の材質が適用できるが、密着性がよいニッケルと耐薬品に優れる金を組み合わせた層が最適である。
　めっき法は、公知の技術、薬品が使用できる。電極が不要な無電解めっき法が、簡便で望ましい。　 A known film forming method can be used for the metal protective film, but a plating method capable of forming a film on the entire surface including the side surface is most preferable.
For example, in the electroless plating method, nickel is then plated with gold, and the metal substrate 51 in which the upper surface, side surfaces, and lower surface of the metal substrate are covered with the nickel film and the gold film (metal protective film) can be produced.
The plating material is not particularly limited, and known materials such as copper, silver, nickel, chromium, platinum, and gold can be applied. However, a layer that combines nickel having good adhesion and gold having excellent chemical resistance is optimal.
As the plating method, known techniques and chemicals can be used. An electroless plating method that does not require an electrode is simple and desirable.
＜化合物半導体層の形成工程＞
　まず、図１３に示すように、半導体基板（成長用基板）６１の一面６１ａ上に、複数のエピタキシャル層を成長させて活性層５４を含むエピタキシャル積層体８０を形成する。
　半導体基板６１は、エピタキシャル積層体８０形成用基板であり、例えば、一面６１ａが（１００）面から１５°傾けた面とされた、Ｓｉドープしたｎ型のＧａＡｓ単結晶基板である。エピタキシャル積層体８０としてＡｌＧａＩｎＰ層またはＡｌＧａＡｓ層を用いる場合、エピタキシャル積層体８０を形成する基板として砒化ガリウム（ＧａＡｓ）単結晶基板を用いることができる。 <Step of forming compound semiconductor layer>
First, as shown in FIG. 13, a plurality of epitaxial layers are grown on one surface 61 a of a semiconductor substrate (growth substrate) 61 to form an epitaxial stacked body 80 including an active layer 54.
The semiconductor substrate 61 is a substrate for forming the epitaxial stacked body 80, and is, for example, a Si-doped n-type GaAs single crystal substrate in which one surface 61a is inclined by 15 ° from the (100) plane. When an AlGaInP layer or an AlGaAs layer is used as the epitaxial laminated body 80, a gallium arsenide (GaAs) single crystal substrate can be used as a substrate on which the epitaxial laminated body 80 is formed.
　活性層５４の形成方法としては、有機金属化学気相成長（Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ：ＭＯＣＶＤ）法、分子線エピタキシャル（Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｉｃｙ：ＭＢＥ）法や液相エピタキシャル（Ｌｉｑｕｉｄ　Ｐｈａｓｅ　Ｅｐｉｔａｘｉｃｙ：ＬＰＥ）法などを用いることができる。 As a method for forming the active layer 54, a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, a liquid phase epitaxial (Liquid Phase EpiLex) method, or the like. Can be used.
　本実施形態では、トリメチルアルミニウム（（ＣＨ３）３Ａｌ）、トリメチルガリウム（（ＣＨ３）３Ｇａ）及びトリメチルインジウム（（ＣＨ３）３Ｉｎ）をＩＩＩ族構成元素の原料に用いた減圧ＭＯＣＶＤ法を用いて、各層をエピタキシャル成長させる。
　なお、Ｍｇのドーピング原料にはビスシクロペンタジエニルマグネシウム（（Ｃ５Ｈ５）２Ｍｇ）を用いる。また、Ｓｉのドーピング原料にはジシラン（Ｓｉ２Ｈ６）を用いる。また、Ｖ族構成元素の原料としては、ホスフィン（ＰＨ３）又はアルシン（ＡｓＨ３）を用いる。
　なお、ｐ型のＧａＰ層５３は、例えば、７５０°Ｃで成長させ、その他のエピタキシャル成長層は、例えば、７３０°Ｃで成長させる。 In the present embodiment, the low pressure MOCVD method using trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga), and trimethylindium ((CH 3 ) 3 In) as group III constituent elements. Each layer is epitaxially grown using
Note that biscyclopentadienyl magnesium ((C 5 H 5 ) 2 Mg) is used as a Mg doping material. Further, disilane (Si 2 H 6 ) is used as a Si doping raw material. Further, phosphine (PH 3 ) or arsine (AsH 3 ) is used as a raw material for the group V constituent element.
The p-type GaP layer 53 is grown at 750 ° C., for example, and the other epitaxial growth layers are grown at 730 ° C., for example.
　具体的には、まず、成長用基板６１の一面６１ａ上に、Ｓｉをドープしたｎ型のＧａＡｓからなる緩衝層６２ａを成膜する。緩衝層６２ａとしては、例えば、Ｓｉをドープしたｎ型のＧａＡｓを用い、キャリア濃度を２×１０１８ｃｍ－３とし、層厚を０．２μｍとする。 Specifically, first, a buffer layer 62 a made of n-type GaAs doped with Si is formed on one surface 61 a of the growth substrate 61. As the buffer layer 62a, for example, n-type GaAs doped with Si is used, the carrier concentration is 2 × 10 18 cm −3 , and the layer thickness is 0.2 μm.
　次に、本実施形態では、緩衝層６２ａ上にエッチングストップ層６２ｂを成膜する。
　エッチングストップ層６２ｂは、半導体基板をエッチング除去する際、クラッド層および発光層までがエッチングされてしまうことを防ぐための層であり、例えば、Ｓｉドープの（Ａｌ０．５Ｇａ０．５）０．５Ｉｎ０．５Ｐからなり、層厚を０．５μｍとする。 Next, in this embodiment, the etching stop layer 62b is formed on the buffer layer 62a.
The etching stop layer 62b is a layer for preventing the cladding layer and the light emitting layer from being etched when the semiconductor substrate is etched away. For example, Si-doped (Al 0.5 Ga 0.5 ) 0 It consists .5 In 0.5 P, the thickness and 0.5 [mu] m.
　次に、エッチングストップ層６２ｂ上に例えば、Ｓｉドープしたｎ型のＡｌｘＧａ１－ｘＡｓ（０．１≦Ｘ≦０．３）からなるコンタクト層５を成膜する。 Next, the contact layer 5 made of, for example, Si-doped n-type Al x Ga 1-x As (0.1 ≦ X ≦ 0.3) is formed on the etching stop layer 62b.
　次に、コンタクト層５上に例えば、Ｓｉをドープしたｎ型の（Ａｌ０．７Ｇａ０．３）０．５Ｉｎ０．５Ｐからなるクラッド層６３ａを成膜する。　 Next, for example, a clad layer 63 a made of n-type (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P doped with Si is formed on the contact layer 5.
　次に、クラッド層６３ａ上に例えば、Ａｌ０．１７Ｇａ０．８３Ａｓ／Ａｌ０．３Ｇａ０．７Ａｓの対からなる井戸層／バリア層の３対の積層構造からなる発光層６４を成膜する。 Next, for example, a light emitting layer 64 having a laminated structure of three pairs of a well layer / barrier layer made of Al 0.17 Ga 0.83 As / Al 0.3 Ga 0.7 As is formed on the cladding layer 63a. Form a film.
　次に、発光層６４上に例えば、Ｍｇをドープしたｐ型のＡｌ０．７Ｇａ０．３）０．５Ｉｎ０．５Ｐからなるクラッド層６３ｂを成膜する。 Then, for example, on the light-emitting layer 64, Al 0.7 Ga 0.3 of p-type doped with Mg) forming a clad layer 63b made of 0.5 In 0.5 P.
　次に、クラッド層６３ｂ上に例えば、Ｍｇドープしたｐ型のＧａＰ層５３を成膜する。
　後述する金属基板等の基板に貼り付けする前に、貼り付け面を整える（すなわち、鏡面加工する。例えば、表面粗さを０．２ｎｍ以下とする）ため、例えば、１μｍ程度研磨することが好ましい。 Next, for example, a p-type GaP layer 53 doped with Mg is formed on the cladding layer 63b.
Before affixing to a substrate such as a metal substrate, which will be described later, the affixing surface is adjusted (that is, mirror-finished. For example, the surface roughness is 0.2 nm or less). .
　なお、クラッド層と発光層との間にガイド層を設けてもよい。 A guide layer may be provided between the clad layer and the light emitting layer.
＜反射層の形成工程＞
　次に、図１３に示すように、ｐ型のＧａＰ層５３上に例えば、Ａｕからなる反射層５２を形成する。 <Reflective layer formation process>
Next, as shown in FIG. 13, a reflective layer 52 made of, for example, Au is formed on the p-type GaP layer 53.
＜金属基板の接合工程＞
　金属基板５１を、反射層５２に接合する前に、反射層５２上に、バリア層（図示せず）及び／又は接合層（図示せず）を形成してもよい。 <Metal substrate bonding process>
Before the metal substrate 51 is bonded to the reflective layer 52, a barrier layer (not shown) and / or a bonding layer (not shown) may be formed on the reflective layer 52.
　バリア層は、金属基板に含まれる金属が拡散して反射層５２と反応するのを抑制することができる。
　バリア層の材料としては、ニッケル、チタン、白金、クロム、タンタル、タングステン、モリブデン等を用いることができる。バリア層は、２種類以上の金属の組み合わせ、たとえば白金とチタンの組み合わせなどにより、バリアの性能を向上させることができる。
　なお、バリア層を設けなくても、接合層にそれらの材料を添加することにより接合層にバリア層と同様な機能を持たせることもできる。
　接合層は、活性層５４を含む化合物半導体層１０等を密着性よく金属基板１に接合するための層である。
　接合層の材料としては、化学的に安定で、融点の低いＡｕ系の共晶金属などを用いられる。Ａｕ系の共晶金属としては、例えば、ＡｕＧｅ、ＡｕＳｎ、ＡｕＳｉ、ＡｕＩｎなどの合金の共晶組成を挙げることができる。 The barrier layer can suppress the metal contained in the metal substrate from diffusing and reacting with the reflective layer 52.
As a material for the barrier layer, nickel, titanium, platinum, chromium, tantalum, tungsten, molybdenum, or the like can be used. The barrier layer can improve the performance of the barrier by a combination of two or more kinds of metals, for example, a combination of platinum and titanium.
Even if a barrier layer is not provided, the bonding layer can have the same function as the barrier layer by adding these materials to the bonding layer.
The bonding layer is a layer for bonding the compound semiconductor layer 10 including the active layer 54 to the metal substrate 1 with good adhesion.
As a material for the bonding layer, an Au-based eutectic metal that is chemically stable and has a low melting point is used. Examples of the Au-based eutectic metal include eutectic compositions of alloys such as AuGe, AuSn, AuSi, and AuIn.
　次に、図１４に示すように、エピタキシャル積層体８０や反射層６等を形成した半導体基板６１と、金属基板の製造工程で形成した金属基板５１とを減圧装置内に搬入して、その接合層の接合面と金属基板５１の接合面５１Ａとが対向して重ね合わされるように配置する。
　次に、減圧装置内を３×１０－５Ｐａまで排気した後、重ね合わせた半導体基板６１と金属基板５１とを４００℃に加熱した状態で、５００ｋｇの荷重を印加して接合層の接合面と金属基板５１の接合面５１Ａとを接合して、接合構造体９０を形成する。 Next, as shown in FIG. 14, the semiconductor substrate 61 on which the epitaxial laminated body 80, the reflective layer 6 and the like are formed, and the metal substrate 51 formed in the metal substrate manufacturing process are carried into a decompression device, and the bonding is performed. It arrange | positions so that the joint surface of a layer and the joint surface 51A of the metal substrate 51 may overlap and oppose.
Next, after evacuating the inside of the decompression device to 3 × 10 −5 Pa, in the state where the stacked semiconductor substrate 61 and the metal substrate 51 are heated to 400 ° C., a load of 500 kg is applied to bond the bonding surfaces of the bonding layers. And the bonding surface 51A of the metal substrate 51 are bonded to form a bonded structure 90.
＜半導体基板および緩衝層除去工程＞
　次に、図１５に示すように、接合構造体９０から、半導体基板６１及び緩衝層６２ａをアンモニア系エッチャントにより選択的に除去する。
　このとき、本発明の金属基板は金属保護膜に覆われており、エッチャントに対する耐性が高いため、金属基板が品質劣化することが防止される。 <Semiconductor substrate and buffer layer removal step>
Next, as shown in FIG. 15, the semiconductor substrate 61 and the buffer layer 62a are selectively removed from the bonded structure 90 with an ammonia-based etchant.
At this time, since the metal substrate of the present invention is covered with the metal protective film and has high resistance to the etchant, the quality of the metal substrate is prevented from being deteriorated.
＜エッチングストップ層除去工程＞
　さらに、図１５に示すように、エッチングストップ層６２ｂを塩酸系エッチャントにより選択的に除去する。
　本発明の金属基板は金属保護膜に覆われており、エッチャントに対する耐性が高いため、金属基板が品質劣化することが防止される。 <Etching stop layer removal process>
Further, as shown in FIG. 15, the etching stop layer 62b is selectively removed with a hydrochloric acid-based etchant.
Since the metal substrate of the present invention is covered with a metal protective film and has high resistance to an etchant, the metal substrate is prevented from being deteriorated in quality.
（裏面電極の形成工程）
　次に、図１５に示すように、金属基板５１の裏面に、裏面電極５６を形成する。 (Back electrode formation process)
Next, as shown in FIG. 15, a back electrode 56 is formed on the back surface of the metal substrate 51.
（メサ型構造部の形成工程）
　次に、発光ダイオード（第１の実施形態）の製造方法と同様に、メサ型構造部（保護膜及び電極膜を除く）を形成するために、メサ型構造部以外の部分の化合物半導体層すなわち、電流拡散層と活性層の少なくとも一部と、又は、電流拡散層と活性層の全部とをウェットエッチングする。
　具体的には、まず、発光ダイオード（第１の実施形態）の製造方法と同様に、レジストパターンを形成する。 (Mesa structure forming process)
Next, in the same manner as the manufacturing method of the light emitting diode (first embodiment), in order to form the mesa structure portion (excluding the protective film and the electrode film), the compound semiconductor layer of the portion other than the mesa structure portion, The current diffusion layer and at least a part of the active layer, or the current diffusion layer and the entire active layer are wet-etched.
Specifically, first, a resist pattern is formed in the same manner as in the method of manufacturing a light emitting diode (first embodiment).
　次に、メサ型構造部以外の部分の化合物半導体層についてウェットエッチングを行う。
　ウェットエッチングに用いるエッチャントとしては限定的ではないが、ＡｌＧａＡｓ等のＡｓ系の化合物半導体材料に対してはアンモニア系エッチャント（例えば、アンモニア／過酸化水素水混合液）が適しており、ＡｌＧａＩｎＰ等のＰ系の化合物半導体材料に対してはヨウ素系エッチャント（例えば、ヨウ化カリウム／アンモニア）が適しており、リン酸／過酸化水素水混合液はＡｌＧａＡｓ系に、ブロムメタノール混合液はＰ系に適している。
　また、Ａｓ系のみで形成されている構造では燐酸混合液、Ａｓ／P系が混在している構造ではＡｓ系構造部にアンモニア混合液、P系構造部にヨウ素混合液を使用してもよい。 Next, wet etching is performed on the compound semiconductor layer other than the mesa structure.
An etchant used for wet etching is not limited, but an ammonia-based etchant (for example, a mixed solution of ammonia / hydrogen peroxide solution) is suitable for an As-based compound semiconductor material such as AlGaAs, and P such as AlGaInP. An iodine-based etchant (for example, potassium iodide / ammonia) is suitable for a compound semiconductor material, a phosphoric acid / hydrogen peroxide mixture is suitable for an AlGaAs system, and a bromomethanol mixture is suitable for a P-system. Yes.
In addition, a phosphoric acid mixed solution may be used in a structure formed only of an As system, an ammonia mixed solution may be used in an As system structure portion, and an iodine mixed solution may be used in a P system structure portion in a structure in which an As / P system is mixed. .
　上記に示したような化合物半導体層の場合すなわち、最上層のＡｌＧａＡｓからなるコンタクト層５、ＡｌＧａＩｎＰからなるクラッド層６３ａ、ＡｌＧａＡｓからなる発光層６４、ＡｌＧａＩｎＰからなるクラッド層６３ｂ、ＧａＰ層５３の場合、Ａｓ系のコンタクト層５及び発光層６４と、他のＰ系の層とでそれぞれにエッチング速度が高い、異なるエッチャントを用いることが好ましい。
　例えば、Ｐ系の層のエッチングにはヨウ素系エッチャントを用い、Ａｓ系のコンタクト層５及び発光層６４のエッチングにはアンモニア系エッチャントを用いることが好ましい。
　ヨウ素系エッチャントとしては例えば、ヨウ素（Ｉ）、ヨウ化カリウム（ＫＩ）、純水（Ｈ２Ｏ）、アンモニア水（ＮＨ４ＯＨ）を混合したエッチャントを用いることができる。
　また、アンモニア系エッチャントとしては例えば、アンモニア／過酸化水素水混合液（ＮＨ４ＯＨ：Ｈ２Ｏ２：Ｈ２Ｏ）を用いることができる。 In the case of the compound semiconductor layer as described above, that is, in the case of the uppermost AlGaAs contact layer 5, the AlGaInP clad layer 63a, the AlGaAs light emitting layer 64, the AlGaInP clad layer 63b, and the GaP layer 53, It is preferable to use different etchants having high etching rates for the As-based contact layer 5 and the light-emitting layer 64 and the other P-based layers.
For example, it is preferable to use an iodine-based etchant for etching the P-based layer and an ammonia-based etchant for etching the As-based contact layer 5 and the light emitting layer 64.
As the iodine-based etchant, for example, an etchant in which iodine (I), potassium iodide (KI), pure water (H 2 O), and ammonia water (NH 4 OH) are mixed can be used.
Further, as the ammonia-based etchant, for example, an ammonia / hydrogen peroxide mixed solution (NH 4 OH: H 2 O 2 : H 2 O) can be used.
　この好ましいエッチャントを用いてメサ型構造部以外の部分を除去する場合を説明すると、まず、メサ型構造部以外の部分のＡｌＧａＡｓからなるコンタクト層５をアンモニア系エッチャントを用いてエッチング除去する。
　このエッチングの際、次の層であるＡｌＧａＩｎＰからなるクラッド層５５がエッチングストップ層として機能するので、エッチング時間を厳密に管理することは要しないが、例えば、コンタクト層５の厚さを０．０５μｍ程度とすると、１０秒程度エッチングを行えばよい。 The case where a portion other than the mesa structure portion is removed using this preferred etchant will be described. First, the contact layer 5 made of AlGaAs in the portion other than the mesa structure portion is removed by etching using an ammonia-based etchant.
At the time of this etching, the cladding layer 55 made of AlGaInP, which is the next layer, functions as an etching stop layer, so that it is not necessary to strictly control the etching time, but for example, the thickness of the contact layer 5 is 0.05 μm. If so, etching may be performed for about 10 seconds.
　次に、メサ型構造部以外の部分のＡｌＧａＩｎＰからなるクラッド層５５をヨウ素系エッチャントを用いてエッチング除去する。
　エッチング速度は、ヨウ素（Ｉ）５００ｃｃ、ヨウ化カリウム（ＫＩ）１００ｇ、純水（Ｈ２Ｏ）２０００ｃｃ、水酸化アンモニア水（ＮＨ４ＯＨ）９０ｃｃの比率で混合されたエッチャントを用いた場合、０．７２μｍ／ｍｉｎだった。
　このエッチングの際も、次の層であるＡｌＧａＡｓからなる発光層６４がエッチングストップ層として機能するので、エッチング時間を厳密に管理することは要しないが、このエッチャントの場合、クラッド層５５の厚さが４μｍ程度とすると、６分間程度エッチングを行えばよい。 Next, the cladding layer 55 made of AlGaInP other than the mesa structure is removed by etching using an iodine-based etchant.
The etching rate is 0 when an etchant mixed at a ratio of 500 cc of iodine (I), 100 g of potassium iodide (KI), 2000 cc of pure water (H 2 O) and 90 cc of aqueous ammonia hydroxide (NH 4 OH) is used. It was 72 μm / min.
Also in this etching, since the light emitting layer 64 made of AlGaAs as the next layer functions as an etching stop layer, it is not necessary to strictly control the etching time, but in the case of this etchant, the thickness of the cladding layer 55 If the thickness is about 4 μm, etching may be performed for about 6 minutes.
　次に、メサ型構造部以外の分のＡｌＧａＡｓからなる発光層６４をアンモニア系エッチャントを用いてエッチング除去する。
　このエッチングの際も、次の層であるＡｌＧａＩｎＰからなるクラッド層６３ｂがエッチングストップ層として機能するので、エッチング時間を厳密に管理することは要しないが、発光層６４の厚さを０．２５μｍ程度とすると、４０秒程度エッチングを行えばよい。 Next, the light emitting layer 64 made of AlGaAs other than the mesa structure is removed by etching using an ammonia-based etchant.
Also in this etching, the cladding layer 63b made of AlGaInP, which is the next layer, functions as an etching stop layer, so that it is not necessary to strictly control the etching time, but the thickness of the light emitting layer 64 is about 0.25 μm. Then, the etching may be performed for about 40 seconds.
　次に、メサ型構造部以外の部分のＡｌＧａＩｎＰからなるクラッド層６３ｂをヨウ素系エッチャントを用いてエッチング除去する。
　このクラッド層６３ｂの下にはＧａＰ層５３があるが、ＧａＰ層５３の下の金属からなる反射層５２が露出すると電気特性上好ましくないので、ＧａＰ層５３まででエッチングを止める必要がある。
　例えば、ＧａＰ層を３．５μｍ形成し、その後１μｍ研磨したとするとＧａＰ層の厚さは２．５μｍとなり、クラッド層６３ｂの厚さを０．５μｍとすると、上記のヨウ素系エッチャントを用いた場合には、エッチング時間は４分間以下にする必要がある。 Next, the cladding layer 63b made of AlGaInP other than the mesa structure portion is etched away using an iodine-based etchant.
Although there is a GaP layer 53 under the clad layer 63b, it is not preferable in terms of electrical characteristics if the reflective layer 52 made of metal under the GaP layer 53 is exposed. Therefore, it is necessary to stop the etching up to the GaP layer 53.
For example, when the GaP layer is formed to 3.5 μm and then polished by 1 μm, the thickness of the GaP layer is 2.5 μm, and the thickness of the cladding layer 63b is 0.5 μm, and the above iodine-based etchant is used. In this case, the etching time needs to be 4 minutes or less.
　この後の保護膜の形成工程、ストリートおよびコンタクト層の部分の保護膜の除去工程、おもて面電極層の形成工程については、発光ダイオード（第１の実施形態）の製造方法と同様に行うことができる。 The subsequent protective film forming process, the street and contact layer protective film removing process, and the front electrode layer forming process are performed in the same manner as in the method of manufacturing the light emitting diode (first embodiment). be able to.
（個片化工程）
　次に、ウェハ基板上の発光ダイオードを、エッチングとレーザー切断を順に行って個片化する。
　具体的には、ストリート部分に開口を有するレジストパターンを形成した後、ストリート上の化合物半導体層と反射層とをエッチング除去し、次いで、金属基板をレーザー切断して個片化を完了する。化合物半導体層だけエッチングしたり、化合物半導体層及び反射層の他に金属保護層もエッチングした後に、レーザー切断を行うなど、エッチングする層の選択は上記の場合に限らない。 (Individualization process)
Next, the light emitting diodes on the wafer substrate are singulated by performing etching and laser cutting in order.
Specifically, after forming a resist pattern having an opening in a street portion, the compound semiconductor layer and the reflective layer on the street are removed by etching, and then the metal substrate is laser-cut to complete singulation. Selection of the layer to be etched is not limited to the above case, such as etching only the compound semiconductor layer or laser cutting after etching the metal protective layer in addition to the compound semiconductor layer and the reflective layer.
（金属基板側面の金属保護膜形成工程）
　個片化された発光ダイオードの切断された金属基板の側面にについて、上面及び下面の金属保護膜の形成条件と同様な条件で金属保護膜を形成してもよい。 (Metal protective film forming process on the side of the metal substrate)
A metal protective film may be formed on the side surfaces of the cut metal substrate of the separated light emitting diodes under the same conditions as the conditions for forming the upper and lower metal protective films.
　以下に、本発明の発光ダイオード及びその製造方法を実施例によりさらに詳細に説明するが、本発明はこの実施例にのみ限定されるものではない。本実施例では、特性評価のために発光ダイオードチップを基板上に実装した発光ダイオードランプを作製した。 Hereinafter, the light-emitting diode of the present invention and the manufacturing method thereof will be described in more detail with reference to examples, but the present invention is not limited to these examples. In this example, a light-emitting diode lamp in which a light-emitting diode chip was mounted on a substrate was prepared for characteristic evaluation.
（実施例１）
　実施例１の発光ダイオードは、第1の実施形態の発光ダイオードの実施例である。
　実施例１の発光ダイオードは、まず、Ｓｉをドープしたｎ型のＧａＡｓ単結晶からなるＧａＡｓ基板上に、化合物半導体層を順次積層してエピタキシャルウェハを作製した。ＧａＡｓ基板は、（１００）面を成長面とし、キャリア濃度を２×１０１８ｃｍ－３とした。また、ＧａＡｓ基板の層厚は、約２５０μｍとした。化合物半導体層とは、ＳｉをドープしたＧａＡｓからなるｎ型の緩衝層、ＳｉをドープしたＡｌ０．９Ｇａ０．１ＡｓとＡｌ０．１Ｇａ０．９Ａｓの４０対の繰り返し構造であるｎ型の下部ＤＢＲ反射層、ＳｉをドープしたＡｌ０．４Ｇａ０．６Ａｓからなるｎ型の下部クラッド層、Ａｌ０．２５Ｇａ０．７５Ａｓからなる下部ガイド層、ＧａＡｓ/Ａｌ０．１５Ｇａ０．８５Ａｓの３対からなる井戸層／バリア層、Ａｌ０．２５Ｇａ０．７５Ａｓからなる上部ガイド層、ＣをドープしたＡｌ０．４Ｇａ０．６Ａｓからなるｐ型の上部クラッド層、ＣをドープしたＡｌ０．９Ｇａ０．１ＡｓとＡｌ０．１Ｇａ０．９Ａｓの５対の繰り返し構造であるｐ型の上部ＤＢＲ反射層、Ｃドープしたｐ型Ａｌ０．１Ｇａ０．９Ａｓからなるコンタクト層である。 Example 1
The light-emitting diode of Example 1 is an example of the light-emitting diode of the first embodiment.
In the light emitting diode of Example 1, first, an epitaxial wafer was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of n-type GaAs single crystal doped with Si. The GaAs substrate had a (100) plane as a growth plane and a carrier concentration of 2 × 10 18 cm −3 . The layer thickness of the GaAs substrate was about 250 μm. The compound semiconductor layer is an n-type buffer layer made of GaAs doped with Si, and 40 pairs of repeating structures of Al 0.9 Ga 0.1 As and Al 0.1 Ga 0.9 As doped with Si. n-type lower DBR reflective layer, n-type lower clad layer made of Si-doped Al 0.4 Ga 0.6 As, lower guide layer made of Al 0.25 Ga 0.75 As, GaAs / Al 0. Well layer / barrier layer composed of three pairs of 15 Ga 0.85 As, upper guide layer composed of Al 0.25 Ga 0.75 As, p-type composed of C 0.4 doped Al 0.4 Ga 0.6 As Upper clad layer, p-type upper DBR reflective layer having 5 pairs of repetitive structures of C-doped Al 0.9 Ga 0.1 As and Al 0.1 Ga 0.9 As, C-doped p-type Al 0 .1 Ga 0.9 It is a contact layer made of As.
　本実施例では、減圧有機金属化学気相堆積装置法（ＭＯＣＶＤ装置）を用い、直径５０ｍｍ、厚さ２５０μｍのＧａＡｓ基板に化合物半導体層をエピタキシャル成長させて、エピタキシャルウェハを形成した。エピタキシャル成長層を成長させる際、ＩＩＩ族構成元素の原料としては、トリメチルアルミニウム（（ＣＨ３）３Ａｌ）、トリメチルガリウム（（ＣＨ３）３Ｇａ）及びトリメチルインジウム（（ＣＨ３）３Ｉｎ）を使用した。また、Ｃのドーピング原料としては、テトラブロモメタン(ＣＢｒ４)を使用した。また、Ｓｉのドーピング原料としては、ジシラン（Ｓｉ２Ｈ６）を使用した。また、Ｖ族構成元素の原料としては、ホスフィン（ＰＨ３）、アルシン（ＡｓＨ３）を使用した。
　また、各層の成長温度としては、７００℃で成長させた。 In this example, a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 50 mm and a thickness of 250 μm by using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer. When growing an epitaxial growth layer, trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga) and trimethylindium ((CH 3 ) 3 In) are used as the raw materials for the group III constituent elements did. Further, tetrabromomethane (CBr 4 ) was used as a doping material for C. Further, disilane (Si 2 H 6 ) was used as a Si doping material. Further, phosphine (PH 3 ) and arsine (AsH 3 ) were used as raw materials for the group V constituent elements.
The growth temperature of each layer was 700 ° C.
　ＧａＡｓからなる緩衝層は、キャリア濃度を約２×１０１８ｃｍ－３、層厚を約０．５μｍとした。下部ＤＢＲ反射層はキャリア濃度を約１×１０１８ｃｍ－３、層厚を約５４ｎｍとしたＡｌ０．９Ｇａ０．１Ａｓと、キャリア濃度を約１×１０１８ｃｍ－３、層厚を約５１ｎｍとしたＡｌ０．１Ｇａ０．９Ａｓを交互に４０対積層した。下部クラッド層は、キャリア濃度を約１×１０１８ｃｍ－３、層厚を約５４ｎｍとした。下部ガイド層は、アンドープで層厚を約５０nｍとした。井戸層は、アンドープで層厚が約７ｎｍのＧａＡｓとし、バリア層はアンドープで層厚が約７ｎｍのＡｌ０．１５Ｇａ０．８５Ａｓとした。また、井戸層とバリア層とを交互に３対積層した。上部ガイド層は、アンドープで層厚を約５０nｍとした。上部クラッド層は、キャリア濃度を約１×１０１８ｃｍ－３、層厚を５４ｎｍとした。また、上部ＤＢＲ反射層はキャリア濃度を約１×１０１８ｃｍ－３、層厚を約５４ｎｍとしたＡｌ０．９Ｇａ０．１Ａｓと、キャリア濃度を約１×１０１８ｃｍ－３、層厚を約５１ｎｍとしたＡｌ０．１Ｇａ０．９Ａｓを交互に５対積層した。
Ａｌ０．１Ｇａ０．９Ａｓからなるコンタクト層は、キャリア濃度を約３×１０１８ｃｍ－３、層厚を約２５０ｎｍとした。 The buffer layer made of GaAs has a carrier concentration of about 2 × 10 18 cm −3 and a layer thickness of about 0.5 μm. Lower DBR reflection layer and the carrier concentration of about 1 × 10 18 cm -3, and Al 0.9 Ga 0.1 As that were about 54nm thickness, a carrier concentration of about 1 × 10 18 cm -3, layer thickness 40 pairs of Al 0.1 Ga 0.9 As having a thickness of about 51 nm were alternately laminated. The lower cladding layer had a carrier concentration of about 1 × 10 18 cm −3 and a layer thickness of about 54 nm. The lower guide layer was undoped and had a thickness of about 50 nm. The well layer was undoped GaAs having a thickness of about 7 nm, and the barrier layer was undoped Al 7 .5 Ga 0.85 As having a thickness of about 7 nm. Three pairs of well layers and barrier layers were alternately laminated. The upper guide layer was undoped and had a thickness of about 50 nm. The upper cladding layer had a carrier concentration of about 1 × 10 18 cm −3 and a layer thickness of 54 nm. The upper DBR reflection layer and the carrier concentration of about 1 × 10 18 cm -3, and Al 0.9 Ga 0.1 As that were about 54nm thickness, a carrier concentration of about 1 × 10 18 cm -3, layer Five pairs of Al 0.1 Ga 0.9 As having a thickness of about 51 nm were alternately stacked.
The contact layer made of Al 0.1 Ga 0.9 As had a carrier concentration of about 3 × 10 18 cm −3 and a layer thickness of about 250 nm.
　次に、裏面電極として基板裏面に、ＡｕＧｅ、Ｎｉ合金を厚さが０．５μｍ、Ｐｔを０．２μｍ、Ａｕを１μｍとなるように真空蒸着法によって成膜し、ｎ型オーミック電極を形成した。 Next, as a back electrode, an n-type ohmic electrode was formed on the back surface of the substrate by vacuum deposition so that the thickness of AuGe and Ni alloy was 0.5 μm, Pt was 0.2 μm, and Au was 1 μm. .
　次に、メサ型構造部を形成するため、パターニングしたレジスト（ＡＺ５２００ＮＪ（クラリアント社製））を用いて、Ｈ２ＰＯ４：Ｈ２Ｏ２：Ｈ２Ｏ＝２：５：９のリン酸／過酸化水素水混合液を用いて、６０秒間、ウェットエッチングを行って、メサ型構造部及び平坦部を形成した。このウェットエッチングによって、コンタクト層、上部ＤＢＲ反射層及び活性層の全層を除去して、頂面の大きさが１９０μｍ×１９０μｍ、高さｈが７μｍ、幅ｗが５μｍの平面視矩形のメサ型構造部（保護膜及び電極膜を除く）を形成した。 Next, in order to form a mesa structure portion, a patterned resist (AZ5200NJ (manufactured by Clariant)) was used, and phosphoric acid / H 2 PO 4 : H 2 O 2 : H 2 O = 2: 5: 9 Using a hydrogen peroxide solution mixture, wet etching was performed for 60 seconds to form a mesa structure portion and a flat portion. By this wet etching, the contact layer, the upper DBR reflection layer, and the active layer are all removed, and a mesa shape having a rectangular shape in plan view with a top surface size of 190 μm × 190 μm, a height h of 7 μm, and a width w of 5 μm. A structure part (excluding a protective film and an electrode film) was formed.
　次に、保護膜を形成するため、ＳｉＯ２からなる保護膜を０．５μｍ程度形成した。
　その後、レジスト（ＡＺ５２００ＮＪ（クラリアント社製））によるパターニング後、バッファードフッ酸を用いて、平面視同心円形（外径ｄout：１６６μｍ、内径ｄin：１５４μｍ）の開口（図１１参照）、および、ストリート部の開口を形成した。 Next, in order to form a protective film, a protective film made of SiO 2 was formed to a thickness of about 0.5 μm.
Then, after patterning with a resist (AZ5200NJ (manufactured by Clariant)), using a buffered hydrofluoric acid, a concentric circular opening (outer diameter dout: 166 μm, inner diameter din: 154 μm) (see FIG. 11) and street Part openings were formed.
　次に、おもて面電極（膜）を形成するため、レジスト（ＡＺ５２００ＮＪ（クラリアント社製））によるパターニング後、Ａｕを１．２μｍ、ＡｕＢｅを０．１５μｍを順に蒸着し、リフトオフにより平面視円形（径：１５０μｍ）の光射出孔９ｂを有する、長辺３５０μｍ、短辺２５０μｍに形成してなるおもて面電極（ｐ型オーミック電極）を形成した。
　その後、４５０℃で１０分間熱処理を行って合金化し、低抵抗のｐ型およびｎ型オーミック電極を形成した。 Next, in order to form a front surface electrode (film), after patterning with a resist (AZ5200NJ (manufactured by Clariant)), 1.2 μm of Au and 0.15 μm of AuBe are sequentially deposited and circularly viewed in plan view by lift-off. A front surface electrode (p-type ohmic electrode) having a light emission hole 9b (diameter: 150 μm) and having a long side of 350 μm and a short side of 250 μm was formed.
Thereafter, heat treatment was performed at 450 ° C. for 10 minutes to form an alloy, and low resistance p-type and n-type ohmic electrodes were formed.
　次に、メサ型構造部の側面に光漏れ防止膜１６を形成するため、レジスト（ＡＺ５２００ＮＪ（クラリアント社製））によるパターニング後、Ｔｉを０．５μｍ、Ａｕを０．１７μｍを順に蒸着し、リフトオフにより光漏れ防止膜１６を形成した。 Next, in order to form the light leakage prevention film 16 on the side surface of the mesa structure, after patterning with a resist (AZ5200NJ (manufactured by Clariant)), Ti 0.5 μm and Au 0.17 μm are sequentially deposited, and lift-off is performed. Thus, the light leakage prevention film 16 was formed.
　次に、化合物半導体層側からダイシングソーを用いストリート部で切断し、チップ化した。ダイシングによる破砕層および汚れを硫酸・過酸化水素混合液でエッチング除去して、実施例の発光ダイオードを作製した。 Next, the compound semiconductor layer side was cut at a street portion using a dicing saw to form a chip. The crushing layer and dirt by dicing were removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to produce the light emitting diode of the example.
　上記のようにして作製した実施例の発光ダイオードチップを、マウント基板上に実装した発光ダイオードランプを１００個組み立てた。この発光ダイオードランプは、マウントは、ダイボンダーで支持（マウント）し、ｐ型オーミック電極とｐ電極端子とを金線でワイヤボンディングした後、一般的なエポキシ樹脂で封止して作製した。 100 light-emitting diode lamps each having the light-emitting diode chip of the example manufactured as described above mounted on a mounting substrate were assembled. This light-emitting diode lamp was manufactured by supporting (mounting) a mount with a die bonder, wire-bonding a p-type ohmic electrode and a p-electrode terminal with a gold wire, and sealing with a general epoxy resin.
　この発光ダイオード（発光ダイオードランプ）について、ｎ型及びｐ型オーミック電極間に電流を流したところ、ピーク波長８５０ｎｍとする赤外光が出射された。順方向に２０ミリアンペア（ｍＡ）の電流を通流した際の順方向電圧（ＶＦ）は１．６Ｖであった。
順方向電流を２０ｍＡとした際の発光出力は１．５ｍＷであった。また、応答速度（立ち上がり時間：Ｔｒ）は１２．１ｎｓｅｃだった。 With respect to this light emitting diode (light emitting diode lamp), when a current was passed between the n-type and p-type ohmic electrodes, infrared light having a peak wavelength of 850 nm was emitted. The forward voltage (V F ) when a current of 20 mA (mA) was passed in the forward direction was 1.6V.
When the forward current was 20 mA, the light emission output was 1.5 mW. The response speed (rise time: Tr) was 12.1 nsec.
　作製した１００個の発光ダイオードランプのいずれについても、同程度の特性が得られ、保護膜が不連続な膜になった場合のリーク（短絡）や電極用金属膜が不連続な膜になった場合の通電不良が原因と思われる不良はなかった。 All of the 100 light-emitting diode lamps produced have the same characteristics, leak (short circuit) when the protective film becomes discontinuous, and the electrode metal film becomes discontinuous. There was no defect that was thought to be due to poor energization.
　図１６は、発光ダイオードの直上における光スペクトル（グラフ右の摸式図参照）の測定結果を示すグラフである。縦軸は光の強度、横軸は波長を示す。
　図１６に示すように、実施例の発光ダイオードでは、発光スペクトルの線幅が狭く（単色性が高く）、半値幅（HWHM）は６．３ｎｍであった。 FIG. 16 is a graph showing the measurement result of the light spectrum (see the schematic diagram on the right side of the graph) immediately above the light emitting diode. The vertical axis represents light intensity, and the horizontal axis represents wavelength.
As shown in FIG. 16, in the light emitting diode of the example, the line width of the emission spectrum was narrow (high monochromaticity), and the half width (HWHM) was 6.3 nm.
　図１７は、発光した光の指向性（グラフ右の摸式図参照）の測定結果を示すグラフである。グラフ中の横軸の「－１」から「１」につながる円周は光の強度（Ｉｎｔ．）として１３０００を示すものである。従って、例えば、ある方向で光の強度が６５００の場合には、その方向では横軸の「－０．５」から「０．５」につながる円周上にグラフがくることになる。また、例えば、実施例の発光ダイオードでは、真上（９０°）から±１０°の方向では約「－０．９」から「０．９」につながる円周（図示なし）上にグラフがあるので、その範囲では光の強度は１３０００の９０％程度であることがわかる。
図１７に示すように、実施例の発光ダイオードでは、光射出孔の直上から±１５°程度の範囲に高い強度（１３０００の７０％程度以上）を有しており、高い指向性を示した。 FIG. 17 is a graph showing the measurement results of the directivity of the emitted light (see the schematic diagram on the right side of the graph). The circumference from “−1” to “1” on the horizontal axis in the graph represents 13000 as the light intensity (Int.). Therefore, for example, when the intensity of light is 6500 in a certain direction, a graph is drawn on the circumference leading from “−0.5” to “0.5” on the horizontal axis in that direction. Further, for example, in the light emitting diode of the example, there is a graph on a circumference (not shown) leading from about “−0.9” to “0.9” in the direction of ± 10 ° from directly above (90 °). Thus, it can be seen that the light intensity is about 90% of 13000 in that range.
As shown in FIG. 17, the light emitting diode of the example had high intensity (about 70% or more of 13000) in a range of about ± 15 ° from directly above the light emitting hole, and showed high directivity.
（実施例２）
　実施例２の発光ダイオードは、第４の実施形態の発光ダイオード（金属基板を用いた場合）の実施例である。 (Example 2)
The light emitting diode of Example 2 is an example of the light emitting diode of the fourth embodiment (when a metal substrate is used).
　まず、厚さ７５μｍのＭｏ層（箔、板）、２枚の厚さ１０μｍのＣｕ層（箔、板）で挟み、加熱圧着して厚さ９５μｍの金属板プレート（個片化の切断前）を形成した。この金属板プレートの上面と下面を研磨し、上面を光沢面とした後に、有機溶剤で洗浄し、汚れを除去した。次に、この金属板プレートの全面に、無電解めっき法により金属保護膜として２μｍのＮｉ層、１μｍのＡｕ層を順に形成して金属基板（個片化の切断前の金属基板）５１を作製した。 First, a 75 μm thick Mo layer (foil, plate) is sandwiched between two 10 μm thick Cu layers (foil, plate) and thermocompression bonded to a 95 μm thick metal plate plate (before cutting into individual pieces). Formed. The upper and lower surfaces of the metal plate plate were polished to make the upper surface a glossy surface, and then washed with an organic solvent to remove dirt. Next, a 2 μm Ni layer and a 1 μm Au layer are sequentially formed on the entire surface of the metal plate plate as a metal protective film by electroless plating to produce a metal substrate (metal substrate before cutting into individual pieces) 51. did.
　次に、Ｓｉをドープしたｎ型のＧａＡｓ単結晶からなるＧａＡｓ基板上に、化合物半導体層を順次積層して発光波長７３０ｎｍのエピタキシャルウェハを作製した。
　ＧａＡｓ基板は、（１００）面から（０－１－１）方向に１５°傾けた面を成長面とし、キャリア濃度を２×１０１８ｃｍ－３とした。また、ＧａＡｓ基板の層厚は、約０．５μｍとした。化合物半導体層としては、ＳｉをドープしたＧａＡｓからなるｎ型の緩衝層６２ａ、Ｓｉドープの（Ａｌ０．５Ｇａ０．５）０．５Ｉｎ０．５Ｐからなるエッチングストップ層６２ｂ、Ｓｉドープしたｎ型のＡｌ０．３ＧａＡｓからなるコンタクト層５、Ｓｉをドープした（Ａｌ０．７Ｇａ０．３）０．５Ｉｎ０．５Ｐからなるｎ型の上部クラッド層６３ａ、Ａｌ０．４Ｇａ０．６Ａｓからなる上部ガイド層、Ａｌ０．１７Ｇａ０．８３Ａｓ／Ａｌ０．３Ｇａ０．７Ａｓの対からなる井戸層／バリア層６４、Ａｌ０．４Ｇａ０．６Ａｓからなる下部ガイド層、Ｍｇをドープした（Ａｌ０．７Ｇａ０．３）０．５Ｉｎ０．５Ｐからなるｐ型の下部クラッド層６３ｂ、（Ａｌ０．５Ｇａ０．５）０．５Ｉｎ０．５Ｐからなる薄膜の中間層、Ｍｇドープしたｐ型ＧａＰ層５３である。 Next, an epitaxial wafer having an emission wavelength of 730 nm was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of n-type GaAs single crystal doped with Si.
In the GaAs substrate, the plane inclined by 15 ° from the (100) plane in the (0-1-1) direction was used as the growth plane, and the carrier concentration was set to 2 × 10 18 cm −3 . The layer thickness of the GaAs substrate was about 0.5 μm. As the compound semiconductor layer, an n-type buffer layer 62a made of GaAs doped with Si, an etching stop layer 62b made of Si-doped (Al 0.5 Ga 0.5 ) 0.5 In 0.5 P, Si-doped the n-type contact layer 5 made of Al0.3GaAs of doped Si (Al 0.7 Ga 0.3) 0.5 in consisting 0.5 P n-type upper cladding layer 63a, Al 0.4 Ga An upper guide layer made of 0.6 As, a well layer / barrier layer 64 made of a pair of Al 0.17 Ga 0.83 As / Al 0.3 Ga 0.7 As, and Al 0.4 Ga 0.6 As A lower guide layer, Mg-doped (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P p-type lower cladding layer 63b, (Al 0.5 Ga 0.5 ) 0.5 In 0. An intermediate layer of a thin film made of P, a p-type GaP layer 53 and Mg-doped.
　本実施例では、減圧有機金属化学気相堆積装置法（ＭＯＣＶＤ装置）を用い、直径５０ｍｍ、厚さ２５０μｍのＧａＡｓ基板に化合物半導体層をエピタキシャル成長させて、エピタキシャルウェハを形成した。エピタキシャル成長層を成長させる際、ＩＩＩ族構成元素の原料としては、トリメチルアルミニウム（（ＣＨ３）３Ａｌ）、トリメチルガリウム（（ＣＨ３）３Ｇａ）及びトリメチルインジウム（（ＣＨ３）３Ｉｎ）を使用した。また、Ｍｇのドーピング原料としては、ビスシクロペンタジエニルマグネシウム（ｂｉｓ－（Ｃ５Ｈ５）２Ｍｇ）を使用した。また、Ｓｉのドーピング原料としては、ジシラン（Ｓｉ２Ｈ６）を使用した。また、Ｖ族構成元素の原料としては、ホスフィン（ＰＨ３）、アルシン（ＡｓＨ３）を使用した。
　また、各層の成長温度としては、ｐ型ＧａＰ層は７５０℃で成長させた。その他の各層では７００℃で成長させた。 In this example, a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 50 mm and a thickness of 250 μm by using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer. When growing an epitaxial growth layer, trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga) and trimethylindium ((CH 3 ) 3 In) are used as the raw materials for the group III constituent elements did. Further, biscyclopentadienyl magnesium (bis- (C 5 H 5 ) 2 Mg) was used as a Mg doping material. Further, disilane (Si 2 H 6 ) was used as a Si doping material. Further, phosphine (PH 3 ) and arsine (AsH 3 ) were used as raw materials for the group V constituent elements.
As the growth temperature of each layer, the p-type GaP layer was grown at 750 ° C. The other layers were grown at 700 ° C.
　ＧａＡｓからなる緩衝層は、キャリア濃度を約２×１０１８ｃｍ－３、層厚を約０．５μｍとした。エッチングストップ層は、キャリア濃度を２×１０１８ｃｍ－３、層厚を約０．５μｍとした。コンタクト層は、キャリア濃度を約２×１０１８ｃｍ－３、層厚を約０．０５μｍとした。上部クラッド層は、キャリア濃度を約１×１０１８ｃｍ－３、層厚を約３．０μｍとした。井戸層は、アンドープで層厚が約７ｎｍのＡｌ０．１７Ｇａ０．８３Ａｓとし、バリア層はアンドープで層厚が約１９ｎｍのＡｌ０．３Ｇａ０．７Ａｓとした。また、井戸層とバリア層とを交互に３対積層した。下部ガイド層は、アンドープで層厚を約５０nｍとした。下部クラッド層は、キャリア濃度を約８×１０１７ｃｍ－３、層厚を約０．５μｍとした。中間層は、キャリア濃度を約８×１０１７ｃｍ－３、層厚を約０．０５μｍとした。ＧａＰ層は、キャリア濃度を約３×１０１８ｃｍ－３、層厚を約３．５μｍとした。 The buffer layer made of GaAs has a carrier concentration of about 2 × 10 18 cm −3 and a layer thickness of about 0.5 μm. The etching stop layer had a carrier concentration of 2 × 10 18 cm −3 and a layer thickness of about 0.5 μm. The contact layer had a carrier concentration of about 2 × 10 18 cm −3 and a layer thickness of about 0.05 μm. The upper cladding layer had a carrier concentration of about 1 × 10 18 cm −3 and a layer thickness of about 3.0 μm. The well layer was undoped Al 0.17 Ga 0.83 As with a thickness of about 7 nm, and the barrier layer was undoped Al 0.3 Ga 0.7 As with a thickness of about 19 nm. Three pairs of well layers and barrier layers were alternately laminated. The lower guide layer was undoped and had a thickness of about 50 nm. The lower cladding layer had a carrier concentration of about 8 × 10 17 cm −3 and a layer thickness of about 0.5 μm. The intermediate layer had a carrier concentration of about 8 × 10 17 cm −3 and a layer thickness of about 0.05 μm. The GaP layer had a carrier concentration of about 3 × 10 18 cm −3 and a layer thickness of about 3.5 μm.
　次に、ＧａＰ層を表面から約１μｍの深さに至る領域まで研磨して、鏡面加工した。この鏡面加工によって、電流拡散層の表面の粗さを０．１８ｎｍとした。 Next, the GaP layer was polished up to a depth of about 1 μm from the surface and mirror-finished. By this mirror finishing, the roughness of the surface of the current diffusion layer was set to 0.18 nm.
　次に、ＧａＰ層上に、Ａｕからなる反射層を厚さ０．７μｍ形成した。さらに、反射層上にバリア層としてＴｉ層を厚さ０．５μｍ形成し、バリア層上に接合層としてＡｕＧｅ層を厚さ１．０μｍ形成した。 Next, a reflective layer made of Au was formed to a thickness of 0.7 μm on the GaP layer. Further, a Ti layer having a thickness of 0.5 μm was formed as a barrier layer on the reflective layer, and an AuGe layer having a thickness of 1.0 μm was formed as a bonding layer on the barrier layer.
　次に、ＧａＡｓ基板上に化合物半導体層及び反射層等を形成した構造体と、金属基板とを対向して重ね合わせるように配置して減圧装置内に搬入し、４００℃で加熱した状態で、５００ｋｇ重の荷重でそれらを接合して接合構造体を形成した。 Next, a structure in which a compound semiconductor layer, a reflective layer, and the like are formed on a GaAs substrate and a metal substrate are arranged so as to face each other and carried into a decompression device, and heated at 400 ° C., They were joined with a load of 500 kg to form a joined structure.
　次に、接合構造体から、化合物半導体層の成長基板であるＧａＡｓ基板と緩衝層とをアンモニア系エッチャントにより選択的に除去し、さらに、エッチングストップ層を塩酸系エッチャントにより選択的に除去した。 Next, the GaAs substrate, which is a growth substrate for the compound semiconductor layer, and the buffer layer were selectively removed from the bonded structure with an ammonia-based etchant, and the etching stop layer was selectively removed with a hydrochloric acid-based etchant.
（裏面電極の形成工程）
　次に、金属基板５１の裏面に、Ａｕを１．２μｍ、ＡｕＢｅを０．１５μｍを順に真空蒸着法によって成膜し、裏面電極５６を形成した。 (Back electrode formation process)
Next, on the back surface of the metal substrate 51, 1.2 μm of Au and 0.15 μm of AuBe were sequentially formed by a vacuum deposition method, and the back electrode 56 was formed.
　次に、メサ型構造部を形成するため、レジストパターンを形成後、アンモニア／過酸化水素水混合液（ＮＨ４ＯＨ：Ｈ２Ｏ２：Ｈ２Ｏ）を用いて、１０秒間ウェットエッチングを行って、メサ型構造部以外の部分の電流拡散層５５を除去した。
　次に、ヨウ素（Ｉ）５００ｃｃ、ヨウ化カリウム（ＫＩ）１００ｇ、純水（Ｈ２Ｏ）２０００ｃｃ、水酸化アンモニア水（ＮＨ４ＯＨ）９０ｃｃの比率で混合されたヨウ素系エッチャントを用いて、４５秒間ウェットエッチングを行って、メサ型構造部以外の部分の上部クラッド層５５を除去した。
　次に、上記アンモニア／過酸化水素水混合液（ＮＨ４ＯＨ：Ｈ２Ｏ２：Ｈ２Ｏ）を用いて、４０秒間ウェットエッチングを行って、メサ型構造部以外の部分の上部ガイド層、発光層６４及び下部ガイド層を除去した。
　次に、上記ヨウ素系エッチャントを用いて、５０秒間ウェットエッチングを行って、メサ型構造部以外の部分の下部クラッド層６３ｂを除去した。こうしてメサ型構造部を形成した。 Next, in order to form a mesa structure portion, after forming a resist pattern, wet etching is performed for 10 seconds using an ammonia / hydrogen peroxide mixed solution (NH 4 OH: H 2 O 2 : H 2 O). Thus, the current diffusion layer 55 other than the mesa structure portion was removed.
Next, using an iodine-based etchant mixed at a ratio of 500 cc of iodine (I), 100 g of potassium iodide (KI), 2000 cc of pure water (H 2 O), and 90 cc of aqueous ammonia hydroxide (NH 4 OH), 45 Wet etching was performed for 2 seconds to remove the upper clad layer 55 at portions other than the mesa structure portion.
Next, using the ammonia / hydrogen peroxide solution mixture (NH 4 OH: H 2 O 2 : H 2 O), wet etching is performed for 40 seconds, and the upper guide layer in a portion other than the mesa structure portion, The light emitting layer 64 and the lower guide layer were removed.
Next, wet etching was performed for 50 seconds using the iodine-based etchant to remove the lower clad layer 63b other than the mesa structure. A mesa structure was thus formed.
　次に、保護膜を形成するため、ＳｉＯ２からなる保護膜を０．５μｍ程度形成した。
　その後、レジストパターンを形成後、バッファードフッ酸を用いて、平面視同心円形（外径ｄout：１６６μｍ、内径ｄin：１５４μｍ）の開口（図１１参照）、および、ストリート部の開口を形成した。 Next, in order to form a protective film, a protective film made of SiO 2 was formed to a thickness of about 0.5 μm.
Thereafter, after forming a resist pattern, an opening (see FIG. 11) having a concentric circular shape (outer diameter dout: 166 μm, inner diameter din: 154 μm) and a street portion opening were formed using buffered hydrofluoric acid.
　次に、おもて面電極（膜）を形成するため、レジストパターンを形成後、ＡｕＧｅ、Ｎｉ合金を厚さが０．５μｍ、Ｐｔを０．２μｍ、Ａｕを１μｍとなるように真空蒸着法によって成膜し、リフトオフにより平面視円形（径：１５０μｍ）の光射出孔９ｂを有する、長辺３５０μｍ、短辺２５０μｍに形成してなるおもて面電極（ｎ型オーミック電極）を形成した。
　その後、４５０℃で１０分間熱処理を行って合金化し、低抵抗のｎ型オーミック電極を形成した。 Next, in order to form a front surface electrode (film), after forming a resist pattern, vacuum deposition is performed so that the thickness of AuGe and Ni alloy is 0.5 μm, Pt is 0.2 μm, and Au is 1 μm. A front surface electrode (n-type ohmic electrode) having a long side of 350 μm and a short side of 250 μm having a light emission hole 9b having a circular shape (diameter: 150 μm) in plan view was formed by lift-off.
Thereafter, heat treatment was performed at 450 ° C. for 10 minutes to form an alloy, and a low-resistance n-type ohmic electrode was formed.
　次に、メサ型構造部の側面に光漏れ防止膜１６を形成するため、レジストパターンを形成後、Ｔｉを０．５μｍ、Ａｕを０．１７μｍを順に蒸着し、リフトオフにより光漏れ防止膜１６を形成した。 Next, in order to form the light leakage prevention film 16 on the side surface of the mesa structure, after forming a resist pattern, Ti 0.5 μm and Au 0.17 μm are sequentially deposited, and the light leakage prevention film 16 is formed by lift-off. Formed.
　次に、ウェットエッチングとレーザー切断を順に行って個片化して、実施例の発光ダイオードを作製した。 Next, wet etching and laser cutting were performed in order to produce individual pieces, thereby producing the light emitting diodes of the examples.
　上記のようにして作製した実施例の発光ダイオードチップを、マウント基板上に実装した発光ダイオードランプを１００個組み立てた。この発光ダイオードランプは、マウントは、ダイボンダーで支持（マウント）し、ｐ型オーミック電極とｐ電極端子とを金線でワイヤボンディングした後、一般的なエポキシ樹脂で封止して作製した。 100 light-emitting diode lamps each having the light-emitting diode chip of the example manufactured as described above mounted on a mounting substrate were assembled. This light-emitting diode lamp was manufactured by supporting (mounting) a mount with a die bonder, wire-bonding a p-type ohmic electrode and a p-electrode terminal with a gold wire, and sealing with a general epoxy resin.
　この発光ダイオード（発光ダイオードランプ）について、ｎ型及びｐ型電極間に電流を流したところ、ピーク波長７３０ｎｍとする赤外光が出射された。順方向に２０ミリアンペア（ｍＡ）の電流を通流した際の順方向電圧（ＶＦ）は１．６Ｖであった。順方向電流を２０ｍＡとした際の発光出力は３．２ｍＷであった。また、応答速度（立ち上がり時間：Ｔｒ）は１２．６ｎｓｅｃだった。 In this light emitting diode (light emitting diode lamp), when an electric current was passed between the n-type and p-type electrodes, infrared light having a peak wavelength of 730 nm was emitted. The forward voltage (V F ) when a current of 20 mA (mA) was passed in the forward direction was 1.6V. The emission output when the forward current was 20 mA was 3.2 mW. The response speed (rise time: Tr) was 12.6 nsec.
　作製した１００個の発光ダイオードランプのいずれについても、同程度の特性が得られ、保護膜が不連続な膜になった場合のリーク（短絡）や電極用金属膜が不連続な膜になった場合の通電不良が原因と思われる不良はなかった。 All of the 100 light-emitting diode lamps produced have the same characteristics, leak (short circuit) when the protective film becomes discontinuous, and the electrode metal film becomes discontinuous. There was no defect that was thought to be due to poor energization.
（比較例）
　液相エピタキシャル法で、厚膜成長し、基板除去した構造の波長８５０ｎｍの発光ダイオードの例を示す。
　ＧａＡｓ基板に、スライドボート型成長装置を用いてＡｌＧａＡｓ層を成長した。
　スライドボート型成長装置の基板収納溝にｐ型ＧａＡｓ基板をセットし、各層の成長用に用意したルツボにＧａメタル、ＧａＡｓ多結晶、金属Ａｌ、及びドーパントを入れた。
成長する層は、透明厚膜層（第１のｐ型層）、下部クラッド層（ｐ型クラッド層）、活性層、上部クラッド層（ｎ型クラッド層）の4層構造とし、この順序で積層した。
　これらの原料をセットしたスライドボート型成長装置を、石英反応管内にセットし、水素気流中で９５０℃まで加温し、原料を溶解した後、雰囲気温度を９１０℃まで降温し、スライダーを右側に押して原料溶液（メルト）に接触させたあと０．５℃／分の速度で降温し、所定温度に達した後、またスライダーを押して順次各原料溶液に接触させたあと高温させる動作を繰り返し、最終的にはメルトと接触させた後、雰囲気温度を７０３℃まで降温してｎクラッド層を成長させた後、スライダーを押して原料溶液とウェハを切り離してエピタキシャル成長を終了させた。 (Comparative example)
An example of a light-emitting diode having a wavelength of 850 nm having a structure in which a thick film is grown and a substrate is removed by a liquid phase epitaxial method is shown.
An AlGaAs layer was grown on a GaAs substrate using a slide boat type growth apparatus.
A p-type GaAs substrate was set in a substrate storage groove of a slide boat type growth apparatus, and Ga metal, GaAs polycrystal, metal Al, and a dopant were put in a crucible prepared for growth of each layer.
The growing layer has a four-layer structure of a transparent thick film layer (first p-type layer), a lower clad layer (p-type clad layer), an active layer, and an upper clad layer (n-type clad layer). did.
A slide boat type growth apparatus in which these raw materials are set is set in a quartz reaction tube, heated to 950 ° C. in a hydrogen stream, dissolved, and then the ambient temperature is lowered to 910 ° C. After pressing and bringing into contact with the raw material solution (melt), the temperature is lowered at a rate of 0.5 ° C./min. After reaching the predetermined temperature, the operation of repeatedly touching each raw material solution after pressing the slider is repeated repeatedly. Specifically, after contact with the melt, the ambient temperature was lowered to 703 ° C. to grow the n-clad layer, and then the slider was pushed to separate the raw material solution from the wafer to complete the epitaxial growth.
　得られたエピタキシャル層の構造は、第１のｐ型層は、Ａｌ組成Ｘ１＝０．３～０．４、層厚６４μｍ、キャリア濃度３×１０１７ｃｍ－３、ｐ型クラッド層は、Ａｌ組成Ｘ２＝０．４～０．５、層厚７９μｍ、キャリア濃度５×１０１７ｃｍ－３、p型活性層は、発光波長が８５０ｎｍの組成で、層厚１μｍ、キャリア濃度１×１０１８ｃｍ－３、ｎ型クラッド層は、Ａｌ組成Ｘ４＝０．４～０．５、層厚２５μｍ、キャリア濃度５×１０１７ｃｍ－３、であった。 The structure of the obtained epitaxial layer is as follows: the first p-type layer has an Al composition X1 = 0.3 to 0.4, the layer thickness is 64 μm, the carrier concentration is 3 × 10 17 cm −3 , and the p-type cladding layer is Al Composition X2 = 0.4 to 0.5, layer thickness 79 μm, carrier concentration 5 × 10 17 cm −3 , p-type active layer has a composition with an emission wavelength of 850 nm, layer thickness 1 μm, carrier concentration 1 × 10 18 cm −3 , the n-type cladding layer had an Al composition X4 = 0.4 to 0.5, a layer thickness of 25 μm, and a carrier concentration of 5 × 10 17 cm −3 .
　エピタキシャル成長終了後、エピタキシャル基板を取り出し、ｎ型ＧａＡｌＡｓクラッド層表面を保護して、アンモニア－過酸化水素系エッチャントでｐ型ＧａＡｓ基板を選択的に除去した。その後、エピタキシャルウェハ両面に金電極を形成し、長辺が３５０μｍの電極マスクを用いて、直径１００μｍのワイヤボンディング用パッドを中央に配置された表面電極を形成した。裏面電極には、直径２０μｍのオーミック電極を８０μｍ間隔に形成した。その後、ダイシングで分離、エッチングすることにより、ｎ型ＡｌＧａＡｓ層が表面側となるようにした３５０μｍ角の発光ダイオードを作製した。 After the epitaxial growth was completed, the epitaxial substrate was taken out, the surface of the n-type GaAlAs cladding layer was protected, and the p-type GaAs substrate was selectively removed with an ammonia-hydrogen peroxide etchant. Thereafter, gold electrodes were formed on both sides of the epitaxial wafer, and a surface electrode in which a wire bonding pad having a diameter of 100 μm was arranged at the center was formed using an electrode mask having a long side of 350 μm. On the back electrode, ohmic electrodes having a diameter of 20 μm were formed at intervals of 80 μm. Thereafter, separation and etching were performed by dicing, so that a 350 μm square light-emitting diode in which the n-type AlGaAs layer was on the surface side was produced.
　比較例の発光ダイオードのｎ型及びｐ型オーミック電極間に電流を流したところ、ピーク波長を８５０ｎｍとする赤外光が出射された。順方向に２０ミリアンペア（ｍＡ）の電流を通流した際の順方向電圧（ＶＦ）は１．９Ｖであった。順方向電流を２０ｍＡとした際の発光出力は５．０ｍＷであった。また、応答速度（Ｔｒ）は１５．６ｎｓｅｃであり、本発明の実施例に比べて遅かった。 When a current was passed between the n-type and p-type ohmic electrodes of the light emitting diode of the comparative example, infrared light having a peak wavelength of 850 nm was emitted. The forward voltage (V F ) when a current of 20 mA (mA) was passed in the forward direction was 1.9V. The light emission output when the forward current was 20 mA was 5.0 mW. Further, the response speed (Tr) was 15.6 nsec, which was slower than the example of the present invention.
　図１６に示すように、比較例の発光ダイオードでは、発光スペクトルの線幅が広く、半値幅（HWHM）は４２ｎｍであった。 As shown in FIG. 16, in the light emitting diode of the comparative example, the line width of the emission spectrum was wide, and the half width (HWHM) was 42 nm.
図１７に示すように、比較例の発光ダイオードでは、発光ダイオードを中心として半球状に光を１３０００の２０％程度以下の強度の光を発光しており、指向性は実施例に比較してかなり低かった。 As shown in FIG. 17, in the light-emitting diode of the comparative example, light having a intensity of about 20% or less of 13000 is emitted hemispherically around the light-emitting diode, and the directivity is considerably higher than that of the example. It was low.
　本発明は、発光ダイオード及びその製造方法に適用できる。 The present invention can be applied to a light emitting diode and a manufacturing method thereof.
　１　基板
　２　下部ＤＢＲ層
　３　活性層
　４　上部ＤＢＲ層
　５　コンタクト層
　６　平坦部
　７　メサ型構造部
　７ａ　傾斜側面
　７ｂ　頂面
　７ｂａ　周縁領域
　８　保護膜
　８ｂ　通電窓
　９　電極膜
　９ｂ　光射出孔
　１１　下部クラッド層
　１２　下部ガイド層
　１３　発光層
　１４　上部ガイド層
　１５　上部クラッド層
　１６　光漏れ防止膜
　２０　化合物半導体層
　２３　レジストパターン
　４０　電流拡散層
　５１　金属基板（導電性基板）
　５１ｃ　金属保護膜
　５２　反射層
　５３　ＧａＰ層
　５４　活性層
　５６　裏面電極
　６１　半導体基板（成長用基板）
　６３ａ　上部クラッド層
　６３ｂ　下部クラッド層
　６４　発光層
　１００、２００、３００、４００　発光ダイオード DESCRIPTION OF SYMBOLS 1 Substrate 2 Lower DBR layer 3 Active layer 4 Upper DBR layer 5 Contact layer 6 Flat portion 7 Mesa structure portion 7a Inclined side surface 7b Top surface 7ba Peripheral region 8 Protective film 8b Current window 9 Electrode film 9b Light exit hole 11 Lower cladding layer 12 Lower Guide Layer 13 Light-Emitting Layer 14 Upper Guide Layer 15 Upper Clad Layer 16 Light Leakage Prevention Film 20 Compound Semiconductor Layer 23 Resist Pattern 40 Current Diffusion Layer 51 Metal Substrate (Conductive Substrate)
51c Metal protective film 52 Reflective layer 53 GaP layer 54 Active layer 56 Back electrode 61 Semiconductor substrate (growth substrate)
63a Upper clad layer 63b Lower clad layer 64 Light emitting layer 100, 200, 300, 400 Light emitting diode

Claims (16)

  1. 　基板上に反射層と活性層を含む化合物半導体層とを備えた発光ダイオードであって、
    　その上部に平坦部と、傾斜側面及び頂面を有するメサ型構造部とを有し、
    　前記平坦部及び前記メサ型構造部はそれぞれ、少なくとも一部は保護膜、電極膜によって順に覆われてなり、
    前記メサ型構造部は少なくとも前記活性層の一部を含むものであって、前記傾斜側面はウェットエッチングによって形成されてなると共に前記頂面に向かって水平方向の断面積が連続的に小さく形成されてなり、
    　前記保護膜は、前記平坦部の少なくとも一部と、前記メサ型構造部の前記傾斜側面と、前記メサ型構造部の前記頂面の周縁領域とを少なくとも覆うとともに、平面視して前記周縁領域の内側に前記化合物半導体層の表面の一部を露出する通電窓を有し、
    　前記電極層は、前記通電窓から露出された化合物半導体層の表面に直接接触すると共に、前記平坦部上に形成された保護膜の一部を少なくとも覆い、前記メサ型構造部の頂面上に光射出孔を有するように形成された連続膜である、ことを特徴とする発光ダイオード。     A light emitting diode comprising a compound semiconductor layer including a reflective layer and an active layer on a substrate,
    It has a flat part on its upper part, and a mesa structure part having an inclined side surface and a top surface,
    Each of the flat part and the mesa structure part is covered with a protective film and an electrode film in order,
    The mesa structure portion includes at least a part of the active layer, and the inclined side surface is formed by wet etching, and a horizontal sectional area is continuously reduced toward the top surface. And
    The protective film covers at least a part of the flat portion, the inclined side surface of the mesa structure portion, and the peripheral region of the top surface of the mesa structure portion, and the peripheral region in plan view. A current-carrying window that exposes a part of the surface of the compound semiconductor layer inside,
    The electrode layer is in direct contact with the surface of the compound semiconductor layer exposed from the energization window, covers at least a part of the protective film formed on the flat portion, and is on the top surface of the mesa structure portion. A light-emitting diode, which is a continuous film formed to have a light emission hole.
  2. 　前記反射層がＤＢＲ反射層であることを特徴とする請求項１に記載の発光ダイオード。 The light emitting diode according to claim 1, wherein the reflective layer is a DBR reflective layer.
  3. 前記活性層の基板とは反対側に上部ＤＢＲ反射層を備えることを特徴とする請求項２に記載の発光ダイオード。 The light emitting diode according to claim 2, further comprising an upper DBR reflective layer on a side opposite to the substrate of the active layer.
  4. 　前記反射層が金属からなることを特徴とする請求項１に記載の発光ダイオード。 The light emitting diode according to claim 1, wherein the reflective layer is made of metal.
  5. 　前記化合物半導体層が、前記電極層に接触するコンタクト層を有することを特徴とする請求項１～４のいずれか一項に記載の発光ダイオード。 The light emitting diode according to any one of claims 1 to 4, wherein the compound semiconductor layer has a contact layer in contact with the electrode layer.
  6. 　前記メサ型構造部が前記活性層のすべてと、前記反射層の一部または全部を含むことを特徴とする請求項１～４のいずれか一項に記載の発光ダイオード。 The light emitting diode according to any one of claims 1 to 4, wherein the mesa structure portion includes all of the active layer and part or all of the reflective layer.
  7. 　前記メサ型構造部は平面視して矩形であることを特徴とする請求項１～４のいずれか一項に記載の発光ダイオード。 The light emitting diode according to any one of claims 1 to 4, wherein the mesa structure portion is rectangular in plan view.
  8. 　前記メサ型構造部の各傾斜側面は前記基板のオリエンテーションフラットに対してオフセットして形成されていることを特徴とする請求項７に記載の発光ダイオード。 The light-emitting diode according to claim 7, wherein each inclined side surface of the mesa structure portion is formed offset with respect to an orientation flat of the substrate.
  9. 　前記メサ型構造部の高さが３～１０μｍであって、平面視した前記傾斜側面の幅が０．５～７μｍであることを特徴とする請求項１～４のいずれか一項に記載の発光ダイオード。 5. The height of the mesa structure portion is 3 to 10 μm, and the width of the inclined side surface in plan view is 0.5 to 7 μm. Light emitting diode.
  10. 　前記光射出孔は平面視して円形又は楕円であることを特徴とする請求項１～４のいずれか一項に記載の発光ダイオード。 The light emitting diode according to any one of claims 1 to 4, wherein the light emitting hole is circular or elliptical in plan view.
  11. 　前記光射出孔の径が５０～１５０μｍであることを特徴とする請求項１０に記載の発光ダイオード。 11. The light emitting diode according to claim 10, wherein the diameter of the light emitting hole is 50 to 150 μm.
  12. 　前記電極層の前記平坦部上の部分にボンディングワイヤを有することを特徴とする請求項１～４のいずれか一項に記載の発光ダイオード。 The light emitting diode according to any one of claims 1 to 4, further comprising a bonding wire in a portion on the flat portion of the electrode layer.
  13. 　前記活性層に含まれる発光層が多重量子井戸からなることを特徴とする請求項１～４のいずれか一項に記載の発光ダイオード。 The light emitting diode according to any one of claims 1 to 4, wherein the light emitting layer included in the active layer is formed of a multiple quantum well.
  14. 　前記活性層に含まれる発光層が（（ＡｌＸ１Ｇａ１－Ｘ１）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ１≦１，０＜Ｙ１≦１）、（ＡｌＸ２Ｇａ１－Ｘ２）Ａｓ（０≦Ｘ２≦１）、（ＩｎＸ３Ｇａ１－Ｘ３）Ａｓ（０≦Ｘ３≦１））のいずれかからなることを特徴とする請求項１～４のいずれか一項に記載の発光ダイオード。 The light emitting layer included in the active layer includes ((Al X1 Ga 1-X1 ) Y1 In 1-Y1 P (0 ≦ X1 ≦ 1, 0 <Y1 ≦ 1), (Al X2 Ga 1-X2 ) As (0 ≦ The light emitting diode according to any one of claims 1 to 4, wherein the light emitting diode is any one of ( X2≤1 ) and ( InX3Ga1 -X3 ) As (0≤X3≤1)).
  15. 　基板上に、反射層と活性層を含む化合物半導体層とを形成する工程と、
    　前記化合物半導体層をウェットエッチングして、頂面に向かって水平方向の断面積が連続的に小さく形成されてなるメサ型構造部と該メサ型構造部の周囲に配置する平坦部とを形成する工程と、
    　前記メサ型構造部の頂面に、前記化合物半導体層の表面の一部を露出する通電窓を有するように、前記メサ型構造部及び平坦部上に保護膜を形成する工程と、
    　前記通電窓から露出された化合物半導体層の表面に直接接触すると共に、前記平坦部上に形成された保護膜の一部を少なくとも覆い、前記メサ型構造部の頂面上に光射出孔を有するように、連続膜である電極層を形成する工程と、を有することを特徴とする発光ダイオードの製造方法。　     Forming a compound semiconductor layer including a reflective layer and an active layer on a substrate;
    The compound semiconductor layer is wet-etched to form a mesa structure portion having a horizontal cross-sectional area continuously reduced toward the top surface and a flat portion disposed around the mesa structure portion. Process,
    Forming a protective film on the mesa structure portion and the flat portion so as to have an energization window exposing a part of the surface of the compound semiconductor layer on the top surface of the mesa structure portion;
    It directly contacts the surface of the compound semiconductor layer exposed from the energization window, covers at least a part of the protective film formed on the flat portion, and has a light emission hole on the top surface of the mesa structure portion. And a step of forming an electrode layer which is a continuous film.
  16. 　前記ウェットエッチングを、リン酸／過酸化水素水混合液、アンモニア／過酸化水素水混合液、ブロムメタノール混合液、ヨウ化カリウム／アンモニアの群から選択される少なくとも1種以上を用いて行うことを特徴とする請求項１５に記載の発光ダイオードの製造方法。 The wet etching is performed using at least one selected from the group consisting of a phosphoric acid / hydrogen peroxide mixture, an ammonia / hydrogen peroxide mixture, a bromomethanol mixture, and potassium iodide / ammonia. The method of manufacturing a light emitting diode according to claim 15, wherein
PCT/JP2012/053348 2011-03-14 2012-02-14 Light-emitting diode and method for manufacturing same WO2012124420A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201280013022.0A CN103430332B (en) 2011-03-14 2012-02-14 Light emitting diode and its manufacture method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2011-055833 2011-03-14
JP2011055833 2011-03-14
JP2011-203449 2011-09-16
JP2011203449A JP5961358B2 (en) 2011-03-14 2011-09-16 Light emitting diode and manufacturing method thereof

Publications (1)

Publication Number Publication Date
WO2012124420A1 true WO2012124420A1 (en) 2012-09-20

Family

ID=46830497

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/053348 WO2012124420A1 (en) 2011-03-14 2012-02-14 Light-emitting diode and method for manufacturing same

Country Status (4)

Country Link
JP (1) JP5961358B2 (en)
CN (1) CN103430332B (en)
TW (1) TWI478389B (en)
WO (1) WO2012124420A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013084867A1 (en) * 2011-12-05 2013-06-13 昭和電工株式会社 Light-emitting diode and method for manufacturing same
WO2014065259A1 (en) * 2012-10-23 2014-05-01 昭和電工株式会社 Light-emitting diode and production method therefor
CN105304786A (en) * 2015-11-13 2016-02-03 杭州士兰明芯科技有限公司 Light emitting diode (LED) chip and fabrication method thereof

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9356212B2 (en) 2012-12-21 2016-05-31 Seoul Viosys Co., Ltd. Light emitting diode and method of fabricating the same
WO2014098510A1 (en) 2012-12-21 2014-06-26 Seoul Viosys Co., Ltd. Light emitting diode and method of fabricating the same
JP2014236038A (en) * 2013-05-31 2014-12-15 信越半導体株式会社 Light-emitting device
DE102014011893B4 (en) * 2013-08-16 2020-10-01 Seoul Viosys Co., Ltd. light emitting diode
CN105633224A (en) * 2016-01-04 2016-06-01 厦门市三安光电科技有限公司 LED chip electrode, LED chip structure and fabrication methods of LED chip electrode and LED chip structure
CN109994582B (en) * 2018-01-02 2020-08-25 山东华光光电子股份有限公司 DBR structure for reducing warping degree of GaAs-based epitaxial wafer
US10483430B1 (en) * 2018-05-01 2019-11-19 Facebook Technologies, Llc Micron-sized light emitting diode designs
KR102300384B1 (en) * 2019-10-17 2021-09-09 주식회사 피앤엘세미 Light emitting diode and manufacturing method therof
JP2022149786A (en) * 2021-03-25 2022-10-07 聯嘉光電股▲ふん▼有限公司 Vertical light emitting diode structure with testable and sidewall protective metal layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280602A (en) * 2001-03-21 2002-09-27 Toshiba Corp Vertically resonating light emitting diode and optical transmission module using the same
JP2005079595A (en) * 2003-08-28 2005-03-24 Lumileds Lighting Us Llc Resonant cavity light emitting device
JP2008053476A (en) * 2006-08-25 2008-03-06 Sanyo Electric Co Ltd Semiconductor chip and manufacturing method thereof
JP2008070865A (en) * 2006-08-16 2008-03-27 Oki Data Corp Optical scanner type projector apparatus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294475B1 (en) * 1998-06-23 2001-09-25 Trustees Of Boston University Crystallographic wet chemical etching of III-nitride material
JP3724620B2 (en) * 1998-09-29 2005-12-07 シャープ株式会社 Manufacturing method of light emitting diode
DE19911717A1 (en) * 1999-03-16 2000-09-28 Osram Opto Semiconductors Gmbh Monolithic electroluminescent device, especially an LED chip, has a row of emission zones individually associated with decoupling elements for decoupling radiation from the device
US6697413B2 (en) * 2001-10-31 2004-02-24 Applied Optoelectronics, Inc. Tunable vertical-cavity surface-emitting laser with tuning junction
WO2004013916A1 (en) * 2002-08-01 2004-02-12 Nichia Corporation Semiconductor light-emitting device, method for manufacturing same and light-emitting apparatus using same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280602A (en) * 2001-03-21 2002-09-27 Toshiba Corp Vertically resonating light emitting diode and optical transmission module using the same
JP2005079595A (en) * 2003-08-28 2005-03-24 Lumileds Lighting Us Llc Resonant cavity light emitting device
JP2008070865A (en) * 2006-08-16 2008-03-27 Oki Data Corp Optical scanner type projector apparatus
JP2008053476A (en) * 2006-08-25 2008-03-06 Sanyo Electric Co Ltd Semiconductor chip and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013084867A1 (en) * 2011-12-05 2013-06-13 昭和電工株式会社 Light-emitting diode and method for manufacturing same
WO2014065259A1 (en) * 2012-10-23 2014-05-01 昭和電工株式会社 Light-emitting diode and production method therefor
JP2014086533A (en) * 2012-10-23 2014-05-12 Showa Denko Kk Light-emitting diode and process of manufacturing the same
CN105304786A (en) * 2015-11-13 2016-02-03 杭州士兰明芯科技有限公司 Light emitting diode (LED) chip and fabrication method thereof

Also Published As

Publication number Publication date
JP5961358B2 (en) 2016-08-02
TW201244171A (en) 2012-11-01
CN103430332A (en) 2013-12-04
JP2012209529A (en) 2012-10-25
CN103430332B (en) 2017-07-07
TWI478389B (en) 2015-03-21

Similar Documents

Publication Publication Date Title
JP5961358B2 (en) Light emitting diode and manufacturing method thereof
JP5865695B2 (en) Light emitting diode and manufacturing method thereof
JP5913955B2 (en) Light emitting diode and manufacturing method thereof
WO2012073993A1 (en) Light-emitting diode, light-emitting diode lamp, and illumination device
JP5961359B2 (en) Light emitting diode and manufacturing method thereof
WO2011034080A1 (en) Light emitting diode, light emitting diode lamp and lighting device
JP5557649B2 (en) Light emitting diode, light emitting diode lamp, and lighting device
JP5608589B2 (en) Semiconductor light emitting device and method for manufacturing semiconductor light emitting device
JP6088132B2 (en) Light emitting diode and manufacturing method thereof
JP5586371B2 (en) Light emitting diode, light emitting diode lamp, and lighting device
WO2012020789A1 (en) Light-emitting diode, light-emitting diode lamp, and illumination device
JP6101303B2 (en) Light emitting diode, light emitting diode lamp, and lighting device
JP5557648B2 (en) Light emitting diode, light emitting diode lamp, and lighting device
WO2010092741A1 (en) Light-emitting diode, and light-emitting diode lamp
JP2014168101A (en) Light emitting diode, light emitting diode lamp, and lighting device
JP2014158057A (en) Light-emitting diode, light-emitting diode lamp, and illuminating device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12757186

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12757186

Country of ref document: EP

Kind code of ref document: A1