WO2012120951A1 - Production method for semiconductor device and semiconductor device - Google Patents
Production method for semiconductor device and semiconductor device Download PDFInfo
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- WO2012120951A1 WO2012120951A1 PCT/JP2012/052777 JP2012052777W WO2012120951A1 WO 2012120951 A1 WO2012120951 A1 WO 2012120951A1 JP 2012052777 W JP2012052777 W JP 2012052777W WO 2012120951 A1 WO2012120951 A1 WO 2012120951A1
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
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- H—ELECTRICITY
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Definitions
- the present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a transistor in which a channel region is formed in a semiconductor having a columnar structure, and the semiconductor device.
- Solid-state imaging devices such as CCD and CMOS type are widely used for video cameras, stale cameras and the like. Further, there is a demand for improved performance such as higher resolution, higher speed operation, and higher sensitivity of the solid-state imaging device.
- a solid-state imaging device in which one pixel is configured in one columnar semiconductor 110 is known (see, for example, Patent Document 1).
- an N + type silicon layer 51 that functions as a signal line of a solid-state imaging device is formed on a semiconductor substrate.
- the columnar semiconductor 110 is connected to the N + type silicon layer 51.
- the columnar semiconductor 110 is formed with a MOS transistor for removing accumulated charges, which includes a P-type silicon layer 52, insulating films 53a and 53b, and gate conductor layers 54a and 54b.
- the columnar semiconductor 110 is formed with a photodiode that is connected to the MOS transistor and accumulates charges generated by irradiation with light (electromagnetic energy wave).
- This photodiode is composed of a P-type silicon layer 52 and N-type silicon layers 58a and 58b.
- a P + type silicon layer 56 and an N + type silicon layer formed on the P type semiconductor 52 surrounded by the photodiode as a channel, the photodiode as a gate, and the photodiode are connected to the pixel selection lines 57a and 57b.
- a junction field effect transistor (junction transistor) is formed using the P-type silicon layer 52 in the vicinity of 51 as a source and a drain, respectively.
- the basic operation of this solid-state imaging device includes a signal charge accumulation operation in which signal charges (electrons in this case) generated by light irradiation are accumulated in a photodiode, and a P-type silicon layer 52 and P + in the vicinity of the N + -type silicon layer 51.
- a signal read operation for modulating the source / drain current flowing between the silicon layer 56 and the gate voltage by the photodiode voltage corresponding to the above-mentioned accumulated signal charge and reading this as a signal current, and completion of this signal read operation Thereafter, the signal charge accumulated in the photodiode is reset to remove the N + -type silicon layer 51 by applying an ON voltage to the gate conductor layers 54a and 54b of the MOS transistor.
- the pixels shown in FIG. 17 are two-dimensionally arranged in the photosensitive region.
- the signal reading operation is performed by transmitting a pixel signal (signal current) to an output circuit provided around the photosensitive region via the N + type silicon layer 51.
- the reset operation is also performed through electrical transmission between the pixel and the peripheral circuit of the photosensitive region.
- the bonding metal layer 59 formed on the silicon substrate 60 Possible structures are possible. As a result, the electric resistance of the signal line is almost determined by the metal layer 59, so that the high-speed operation of the signal reading operation described above is realized. However, it is difficult to form the metal layer 59 bonded to the N + type silicon layer 51 from the viewpoint of the affinity of bonding between the metal material and the silicon material.
- the following method can be considered to form the metal layer 59 on the silicon substrate 60. That is, as shown in FIG. 18B, a silicon oxide layer 62 is formed on the semiconductor substrate 61, and a metal layer 59 is formed on the silicon oxide layer 62. Then, the semiconductor substrate 61 on which the metal layer 59 is formed and the semiconductor substrate 64 are bonded. Thereafter, pixels are formed in the portion of the semiconductor substrate 64 indicated by the broken line in FIG. 18B.
- An alternate long and short dash line D-D ′ shown in FIG. 18B shows a state in which the semiconductor substrate 64 is formed to a predetermined height by polishing, etching, or other separation methods of the semiconductor substrate 64.
- the side surface of a columnar semiconductor having a columnar structure is used as a channel region, and a vertical MOS transistor having a structure in which a gate electrode surrounds the channel region is an SGT (Surrounding Gate Transistor).
- SGT Square Gate Transistor
- a planar silicon film 67 is formed on a buried oxide film substrate 66, and a planar structure is formed by the planar silicon film 67 and the columnar silicon layer 68.
- a P + -type silicon diffusion layer 69 that functions as a drain is formed in the planar silicon film 67.
- a P + -type silicon diffusion layer 70 functioning as a source is formed on the columnar silicon layer 68, and a gate insulating layer 71 is formed on the outer periphery of the columnar silicon layer 68.
- a gate electrode 72 is formed on the outer periphery of the gate insulating layer 71.
- a silicon nitride (SiN) film 73 and a silicon oxide (SiO 2 ) film 74 are formed so as to surround the gate electrode 72, the P + -type silicon diffusion layer 70, and the P + -type silicon diffusion layer 69.
- a contact hole 75 is formed in the silicon oxide layer 74, and the P + -type silicon diffusion layer 70 is connected to the source metal wiring 76 through the contact hole 75. Thereby, one P-type channel SGT is formed.
- the P + -type silicon diffusion layer 69 shown in FIG. 19 is connected to a metal wiring (not shown) at a predetermined portion where the planar silicon film 67 extends on the same plane.
- the connection between the P + -type silicon diffusion layer 69 and the metal wiring is as in the P + -type silicon diffusion layer 70. It is required to be performed at a short distance.
- a pixel signal (signal current) is provided around the photosensitive region and transmitted to an external circuit via the N + type silicon layer 51 functioning as a signal line. Is done.
- the reset operation is also performed through electrical transmission between the pixel and an external circuit in the photosensitive area. The responsiveness of this electrical transmission is greatly influenced by the electrical resistance and parasitic capacitance of the wiring connecting the pixel and the peripheral circuit. In order to increase the number of pixels of the solid-state imaging device or the number of readout screens per unit time, it is necessary to reduce the electrical resistance of such wiring.
- such an electrical resistance is substantially determined by the electrical resistance of the N + type silicon layer 51.
- N + -type silicon layer 51 is formed a donor impurity in silicon (Si) semiconductor, such as phosphorus (P), arsenic (As) by ion doping (ion implantation), electrical of the N + -type silicon layer 51
- Si silicon
- P phosphorus
- As arsenic
- ion doping ion implantation
- the resistance value cannot be made smaller than the electrical resistance value of a metal used in a normal semiconductor device such as aluminum (Al), copper (Cu), tungsten (W), nickel (Ni).
- the solid-state imaging device shown in FIG. 17 has a problem inferior in high-speed operation characteristics as compared with a solid-state imaging device that performs electrical connection between a pixel and a peripheral circuit by metal wiring.
- the P + -type silicon diffusion layer 69 is connected to the metal wiring at the portion where the planar silicon film 67 is extended.
- Such means by connecting the P + -type silicon diffusion layer 69 and the metal wiring cannot be connected to the metal wiring at a short distance as in the P + -type silicon diffusion layer 70, so that the metal wiring and the SGT channel are not connected.
- a considerable electrical resistance is present up to the end of the closest P + -type silicon diffusion layer 69. For this reason, in the semiconductor device having SGT, it is necessary to reduce the electrical resistance in order to realize further high-speed operation.
- the present invention has been made in view of the above-described circumstances, and an object thereof is to provide a semiconductor device capable of realizing high integration and high speed operation.
- a method of manufacturing a semiconductor device includes: Forming a first insulating layer in a predetermined region on the semiconductor substrate, and removing the first insulating layer on the predetermined region to form an insulating layer removal region; or A second insulating layer forming / removing step of partially removing the semiconductor substrate in a thickness direction around the predetermined region and forming a first insulating layer in the semiconductor substrate removing region from which the semiconductor substrate has been removed; A first semiconductor layer forming step of forming a first semiconductor layer containing a donor impurity or an acceptor impurity on the semiconductor substrate so as to cover at least the predetermined region; A conductor layer forming step of forming a conductor layer on the first semiconductor layer; A molding step of molding the conductor layer and the first semiconductor layer into a predetermined shape; A first insulating layer forming step of forming a second insulating layer so as to cover the conductor layer and the first semiconductor layer formed in the predetermined shape;
- the circuit element forming step includes Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer; Forming a fourth semiconductor region having the same conductivity type as the first semiconductor region in a portion above the gate conductor layer and in a surface layer portion of the columnar semiconductor;
- the columnar semiconductor includes a step of forming a third semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the third insulating layer.
- the circuit element forming step includes Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer; And forming a fifth semiconductor region having the same conductivity type as that of the first semiconductor region at a position above the third insulating layer in the columnar semiconductor.
- the circuit element forming step includes Preferably, the method includes a step of forming a sixth semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the columnar semiconductor.
- the first semiconductor layer forming step includes a step of forming a second semiconductor layer functioning as an electric resistance in the same layer as the first semiconductor layer.
- the first semiconductor layer forming step includes a step of forming an insulating film functioning as a capacitor insulating film in a predetermined region on the first semiconductor layer functioning as a capacitor electrode;
- the conductor layer forming step preferably includes a step of forming a conductor layer that functions as a capacitor electrode together with the first semiconductor layer on the insulating film.
- a fourth insulating layer is formed together with the first insulating layer on the semiconductor substrate, and the capacitor formation region set in advance is thicker than the fourth insulating layer.
- Forming a fifth insulating layer that is thin and functions as a capacitive insulating film includes a step of forming a conductor layer functioning as a capacitive electrode on the fifth insulating layer,
- the first and second insulating layer forming / removing steps preferably include a capacitor forming step of forming an impurity layer having donor impurities or acceptor impurities in the capacitor forming region and functioning as a capacitor electrode.
- a mask alignment mark formation region setting step for setting a mask alignment mark formation region on the semiconductor substrate; Forming a mask alignment hole in the mask alignment mark formation region, exposing at least one of the insulating layer removal region, the first insulating layer, and the conductor layer; A mask alignment mark forming step for forming a mask alignment mark made of at least one of the insulating layer removal region, the first insulating layer, and the conductor layer through the mask alignment hole; It is preferable that the method further includes a mask alignment step of performing mask alignment of the photomask with the mask alignment mark as a reference.
- a step of embedding a transparent insulator in the mask alignment hole In the mask alignment mark forming step, a mask alignment mark comprising at least one of the insulating layer removal region, the first insulating layer and the conductor layer is formed through the transparent insulator, In the mask alignment step, it is preferable that mask alignment of a photomask is performed using the mask alignment mark as a reference.
- a second semiconductor in which donor impurities and acceptor impurities are not doped so as to cover the insulating layer removal region between the first or second insulating layer forming / removing step and the first semiconductor layer forming step. It is preferable to further comprise a step of forming a layer.
- the second insulating layer forming / removing step includes a semiconductor substrate etching step of etching the semiconductor substrate around a region where the columnar semiconductor is formed, Forming the first insulating layer on the semiconductor substrate in the etched region; Forming the first semiconductor layer on the semiconductor substrate exposed by the etching and on the first insulating layer located around the exposed semiconductor substrate; It is preferable.
- the second insulating layer forming / removing step includes a step of selectively oxidizing a peripheral region of the semiconductor substrate in a region where the columnar semiconductor is formed to form a selective oxide layer as the first insulating layer. , It is preferable.
- a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
- the columnar semiconductor is A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor;
- a diode that accumulates signal charges generated by irradiation of electromagnetic energy waves from the second semiconductor region and the fourth semiconductor region is formed, The diode functions as a gate, one of the first semiconductor region and the third semiconductor region functions as a source, the other functions as a drain, and a channel formed in the second semiconductor region.
- a junction field effect transistor is formed which is capable of taking out a current that flows and changes according to the amount of signal charge accumulated in the diode by a signal taking-out means,
- the gate conductor layer functions as a gate, and a voltage is applied to the gate conductor layer by a MOS transistor in which one of the first semiconductor region and the fourth semiconductor region functions as a source and the other functions as a drain.
- signal charge removing means for removing the signal charge accumulated in the diode in the first semiconductor region is formed.
- a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
- the columnar semiconductor is A second semiconductor region formed on the first semiconductor region, the second semiconductor region comprising an opposite conductivity type or intrinsic semiconductor to the first semiconductor region;
- the gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain. To do.
- a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
- the columnar semiconductor is Between the first semiconductor region and the sixth semiconductor region, a second semiconductor region made of an opposite conductivity type or intrinsic semiconductor to the first semiconductor region is provided, A diode is formed from the second semiconductor region and the sixth semiconductor region.
- a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer;
- the plurality of columnar semiconductors include a plurality of first columnar semiconductors in which the first semiconductor region is doped with an acceptor impurity, and a plurality of second columnar semiconductors in which the first semiconductor region is doped with a donor impurity. It consists of a semiconductor.
- a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer; In the plurality of columnar semiconductors, both or one of the plurality of first semiconductor regions and the plurality of conductor layers are connected to each other.
- a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer; Each of the columnar semiconductors is A second semiconductor region made of a semiconductor or an intrinsic semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region; A fifth semiconductor region formed on the second semiconductor region; A third insulating layer formed on the outer periphery of the second semiconductor region; A gate conductor layer formed on the outer periphery of the third insulating layer, The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
- the first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer formed so as to be connected is a contact formed on an insulating layer. It is connected to a wiring layer for connecting to an external circuit through a hole.
- a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer; Each of the columnar semiconductors is A second semiconductor region made of a semiconductor or an intrinsic semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region; A fifth semiconductor region formed on the second semiconductor region; A third insulating layer formed on the outer periphery of the second semiconductor region; A gate conductor layer formed on the outer periphery of the third insulating layer, The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
- the first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer is connected to a predetermined hole via a contact hole formed in the insulating layer. It is connected to a wiring layer for connecting to the gate of the transistor.
- FIG. 20 is a circuit plan view for explaining a two-stage CMOS inverter circuit according to a tenth embodiment.
- FIGS. 1A to 16C a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1A to 16C.
- (First embodiment) 1A to 1L show a method for manufacturing a solid-state imaging device according to the first embodiment of the present invention.
- high-concentration hydrogen ions H +
- a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed (see Non-Patent Document 2).
- a first silicon oxide layer 3 that is an insulating film is formed on the first semiconductor substrate 1 by thermal oxidation or CVD (Chemical Vapor Deposition).
- the first semiconductor substrate 1 may be an intrinsic semiconductor (i-type silicon) that does not substantially contain impurities, instead of P-type silicon.
- the silicon oxide removal region is removed by removing silicon oxide (SiO 2 ) corresponding to the portion where the signal line drain of the solid-state imaging device is formed in the first silicon oxide layer 3.
- the hole 4 which is 48 (refer FIG. 11A and FIG. 13A) is formed.
- a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3 and the first semiconductor substrate 1 by the CVD method so as to cover the hole 4.
- the polycrystalline silicon layer 5 is ion-doped with a donor impurity such as phosphorus (P) or arsenic (As), thereby the first semiconductor substrate 1 and the first silicon oxide.
- a donor impurity such as phosphorus (P) or arsenic (As)
- P phosphorus
- As arsenic
- tungsten (W), tungsten silicide (WSi), nickel (Ni), nickel silicide (NiSi) is deposited on the N + polycrystalline silicon layer 5a by vapor deposition or CVD. Or a metal layer 7 formed by laminating a plurality of these layers.
- N + polysilicon layer 5a and the metal layer 7 are part that embeds the hole 4 remaining, N + polycrystalline silicon layer
- the 5a and the metal layer 7 are formed into a predetermined shape.
- the source or drain of the junction field effect transistor in the pixel of the solid-state imaging device is formed.
- a second silicon oxide layer 8 that is an insulating film is formed by a CVD method so as to cover the N + polycrystalline silicon layer 5a, the metal layer 7, and the first silicon oxide layer 3. . Then, the surface of the second silicon oxide layer 8 is planarized by CMP (Chemical Mechanical Polishing).
- a second semiconductor substrate 9 made of silicon (Si) and having a planarized surface is prepared, and the planarized surface of the second semiconductor substrate 9 and the second silicon oxide are prepared.
- the planarized surfaces of the layer 8 are bonded together by pressure bonding. In this bonding process, the difference in thermal expansion coefficient between the silicon layer in the second semiconductor substrate 9 and the silicon layer in the second silicon oxide layer 8 are bonded to each other. Due to the difference, it is possible to obtain a laminated structure in which warpage, cracking and peeling are unlikely to occur.
- the N + polycrystalline silicon layer 5a corresponds to the N + type silicon layer 51 shown in FIG. 14, and in this embodiment, the N + polycrystalline silicon layer 5a includes all of its formation regions.
- the metal layer 7 is joined over the entire area.
- the silicon layer in the region other than the silicon layer in the region directly above so that the silicon layer in the region immediately above the N + polycrystalline silicon layer 5 a remains. Are removed by etching. Thereby, a silicon (Si) pillar 1a having a pillar structure is formed.
- the silicon pillar 1a becomes a P-type silicon layer 30 shown in FIGS. 1K, 1L and the like.
- heat treatment is performed to thermally diffuse the donor impurity from the N + polycrystalline silicon layer 5a to the silicon pillar 1a, thereby forming the N + diffusion layer 6a in the lower part of the silicon pillar 1a.
- thermal oxidation is performed to form third silicon oxide layers 10a and 10b that are insulators on the outer periphery of the silicon pillar 1a.
- gate conductor layers 11a and 11b are formed on the outer peripheral portions of the third silicon oxide layers 10a and 10b by vapor deposition or CVD.
- an N-type is formed by ion-doping a donor impurity such as phosphorus (P) or arsenic (As) in the upper portion of the gate conductor layers 11a and 11b and the surface layer portion of the silicon pillar 1a.
- Silicon layers 12a and 12b are formed.
- the N-type silicon layers 12a and 12b and the P-type silicon layer 30 of the silicon pillar 1a form a photodiode as signal charge storage means for storing signal charges (electrons in this case) corresponding to incident light.
- the signal charge is accumulated in the silicon pillar 1a (P-type silicon layer 30) between the N + diffusion layer 6a and the P + -type silicon layer 13a.
- an upper portion of the third silicon oxide layers 10a and 10b is ion-doped with an acceptor impurity such as boron (B) to thereby form a P + -type silicon layer 13a.
- an acceptor impurity such as boron (B)
- a third oxide which is an insulator is formed by thermal oxidation on the outer periphery of the silicon pillar 1b constituting another pixel and adjacent to the silicon pillar 1a constituting the pixel of the solid-state imaging device. Silicon layers 10c and 10d are formed.
- the silicon pillar 1b is formed by the steps shown in FIGS. 1A to 1K, similarly to the silicon pillar 1a.
- gate conductor layers 11c and 11d are formed on the outer periphery of the third silicon oxide layers 10c and 10d by vapor deposition or CVD.
- the upper portion of the gate conductor layers 11c and 11d and the surface layer portion of the silicon pillar 1a are ion-doped with a donor impurity such as phosphorus (P) or arsenic (As).
- Silicon layers 12c and 12d are formed.
- the N-type silicon layers 12c and 12d and the silicon pillar 1b form a photodiode as signal charge storage means for storing signal charges (electrons in this case) corresponding to incident light.
- the signal charge is accumulated in the silicon pillar 1b (P-type silicon layer 30) between the N + diffusion layer 6ab and the P + -type silicon layer 13b.
- the N + diffusion layer 6a in the silicon pillar 1a is thermally diffused from the N + polycrystalline silicon layer 5a to the silicon pillar 1a by heat treatment. Formed.
- the N + diffusion layer 6a is not limited to this, and the N + diffusion layer 6a is formed from the N + polycrystalline silicon layer 5a to the first semiconductor substrate by heat treatment at an arbitrary stage after the N + polycrystalline silicon layer 5a shown in FIG. 1C is formed. It can also be formed by diffusing donor impurities in 1. That is, after the step of forming the N + polycrystalline silicon layer 5a shown in FIG.
- the impurities are diffused from the N + polycrystalline silicon layer 5a including the donor impurity, thereby the N + diffusion layer 6a is formed in the silicon pillar 1a.
- the N + diffusion layer 6a may be formed after forming the silicon pillar 1a (P-type silicon layer 30) in the stage shown in FIG. 1K. Further, the heat treatment for forming such an N + diffusion layer 6a may be performed only once or may be performed in a plurality of times.
- the solid-state imaging device is formed by the processes shown in FIGS. 1A to 1L. In addition, pixels of the solid-state imaging device are formed on each of the silicon pillars 1a and 1b.
- N + polycrystalline silicon layer 5a and metal layer 7 formed below silicon pillars 1a and 1b and joined to each other constitute a signal line of the solid-state imaging device.
- the N + diffusion layers 6a and 6ab in the two silicon pillars 1a and 1b are electrically connected to each other.
- junction field effect transistors are formed in the silicon pillars 1a and 1b.
- the photodiode constituted by the N-type silicon layers 12a and 12b (12c and 12d) and the P-type silicon layer 30 is the gate
- the P + type silicon layers 13a and 13b are the drain
- the N + diffusion layer 6a. , 6ab each function as a source.
- the junction field effect transistor channel is formed in the silicon pillars 1a and 1b.
- the junction field-effect transistor flows through the channels in the silicon pillars 1a and 1b, and serves as a signal extraction unit that extracts, as an electric signal, a current that changes according to the amount of signal charge accumulated in the photodiode.
- An external circuit (not shown) is provided.
- MOS transistors are formed as signal charge removing means for removing the signal charges accumulated in the photodiode to the N + diffusion layers 6a and 6ab.
- the gate conductor layers 11a, 11b, 11c, and 11d formed on the outer peripheral surfaces of the third silicon oxide layers 10a, 10b, 10c, and 10d so as to surround the silicon pillars 1a and 1b are the gate, N + diffusion
- the layers 6a and 6ab function as drains
- the N-type silicon layers 12a, 12b, 12c and 12d function as sources.
- a channel of this MOS transistor is formed in the P-type silicon layer 30, a channel of this MOS transistor is formed.
- the silicon layer of the second semiconductor substrate 9 and the second silicon oxide layer 8 on the first semiconductor substrate 1 are bonded to each other on the planarized surfaces. Is done.
- the first semiconductor substrate 1 (second silicon oxide layer 8) and the second semiconductor substrate 9 are bonded to each other over the entire surfaces of the first semiconductor substrate 1 and the second semiconductor substrate 9. Since this is performed between the Si (silicon) surface and the SiO 2 (silicon oxide) surface having a high affinity, it is possible to obtain a laminated structure in which warpage, cracking, and peeling are unlikely to occur.
- the metal layer 7 is bonded to the N + polycrystalline silicon layer 5a constituting the signal line in the pixel of the solid-state imaging device.
- the N + polycrystalline silicon layer 5a and the metal layer 7 may be converted into a silicide layer by the reaction between the N + polycrystalline silicon layer 5a and the metal layer 7 by heat treatment in the process leading to FIG. 1K or additional heat treatment. Good.
- the resistance of the N + polycrystalline silicon layer 5a and the metal layer 7 or the silicide layer thereof is reduced, the electrical resistance between the pixel and the peripheral circuit of the pixel can be lowered. .
- the solid-state imaging device can be operated at a higher speed even when the number of pixels is increased or the number of readout screens per unit time is increased as compared with the conventional solid-state imaging device.
- a PN junction (photodiode) composed of a P-type silicon layer 30 and N-type silicon layers 12a and 12b, and a P-type silicon layer 30 and N + diffusion are used.
- the PN junction composed of the layer 6a is formed in the silicon pillar 1a made of single crystal silicon. Since the PN junction is thus formed in single crystal silicon, a pixel of a solid-state imaging device with low leakage current is configured.
- the silicon pillar 1a which is a photoelectric conversion region and is reflected by the metal layer 7.
- the optical path length in the silicon pillar 1a increases, and the sensitivity of the solid-state imaging device is improved.
- the solid-state imaging device can be easily manufactured while obtaining the same sensitivity as that of the conventional example. An effect is also obtained.
- N + polycrystal is formed by CVD so as to fill (cover) the hole 4 on the first silicon oxide layer 3 and the first semiconductor substrate 1.
- a polycrystalline silicon layer 5 to be a silicon layer 5a was formed.
- a single crystalline silicon layer may be formed by epitaxial growth.
- a single crystal silicon layer can be formed also on the first silicon oxide layer 3, and thereafter, a solid-state imaging device is formed in the same manner as the steps shown in FIGS. 1C to 1K. Can do.
- the first semiconductor substrate 1 is thinned to a predetermined thickness by removing the lower part of the first semiconductor substrate 1 by using a heat treatment at 400 to 600 ° C. with the separation layer 2 as a boundary. did.
- the first semiconductor substrate 1 is not limited to this, but the first semiconductor substrate 1 is formed of a P + -type substrate and a P-type silicon layer formed by epitaxial growth on the P + -type substrate. Can also be performed by etching and CMP.
- the gate insulating layers 15a and 15b are formed on the outer periphery of the silicon pillar 1a by the oxidation method or the CVD method, and the gate insulating layers 15a and 15b are formed.
- Gate conductor layers 16a and 16b functioning as SGT gates are formed on the outer periphery of the gate electrode.
- an N + type silicon layer functioning as a source of SGT by ion doping a donor impurity such as phosphorus (P) or arsenic (As) in the upper part of the gate conductor layers 16a and 16b. 17a is formed.
- a metal wiring layer 18a is formed on the N + type silicon layer 17a by vapor deposition and pattern etching.
- an N-channel SGT is formed on the second semiconductor substrate 9.
- the N + diffusion layer 6a and the N + polycrystalline silicon layer 55a function as a source or a drain in the N channel type SGT.
- the metal layer 7 is bonded to the entire back surface of the N + polycrystalline silicon layer 55a that functions as a drain. With this configuration, the electrical resistance from the metal layer 7 to the N + diffusion layer 6a is reduced, so that an SGT with high speed operation is obtained.
- the manufacturing method of the semiconductor device which has SGT based on 3rd Embodiment of this invention is demonstrated.
- the N channel type SGT and the P channel type SGT are formed on the same semiconductor substrate.
- the manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
- an N channel type SGT formation region 1n is an N channel type SGT
- a P channel type SGT formation region 1p is a P channel type.
- Each SGT is formed.
- the N-channel SGT in the N-channel SGT formation region 1n is formed in the same manner as the steps shown in FIGS. 1A to 1J of the first embodiment and FIG. 2 of the second embodiment.
- the P-channel SGT in the P-channel SGT formation region 1p is formed in substantially the same manner as the steps shown in FIGS. 1A to 1J of the first embodiment and FIG. 2 of the second embodiment.
- the step corresponding to FIG. 1C instead of forming the N + polycrystalline silicon layer 55a that functions as the drain of the N channel type SGT, boron (B ) Or the like is ion-doped to form a P + diffusion layer 6a and a P + polycrystalline silicon layer 55b that function as a source of the P channel type SGT.
- an N channel type SGT constituted by the silicon pillar 1a and a silicon pillar 1b are formed.
- a P channel type SGT is formed.
- the N-type silicon layer 30a is formed by ion doping a P-channel SGT silicon pillar 1b (P-type silicon) with a donor impurity such as phosphorus (P) or arsenic (As).
- the gate insulating layers 15a, 15b, 15c, and 15d are formed on the outer peripheral portions of the silicon pillars 1a and 1b by thermal oxidation or CVD, and the gate insulating layers 15a, 15b, and 15c are formed. , 15d, gate conductor layers 16a, 16b, 16c, 16d are formed by CVD (see FIG. 3B).
- donor impurities and acceptor impurities are ion-doped in the upper portions of the gate conductor layers 16a, 16b, 16c, and 16d, respectively.
- An N + type silicon layer 17a functioning as a source or drain and a P + type silicon layer 17b functioning as a source or drain of the P channel type SGT are formed.
- the N channel type SGT and the P channel type SGT are formed on the second semiconductor substrate 9.
- any one of the N + polycrystalline silicon layer 55a and the N + diffusion layer 6a in the silicon pillar 1a in the N channel type SGT and the N + type silicon layer 17a is a drain, and the other is Act as a source.
- any one of the P + polycrystalline silicon layer 55b and the P + diffusion layer 6b and the P + type silicon layer 17b in the silicon pillar 1b in the P channel type SGT is a drain, the other functions as a source.
- the N-channel SGT and the P-channel SGT can be easily formed on the second semiconductor substrate 9.
- the P-channel SGT silicon pillar 1b (P-type silicon) is formed with phosphorus (P), arsenic (As), or the like.
- the N-type silicon layer 30a was formed by ion doping of the donor impurities.
- the first semiconductor substrate 1 in FIG. 1A is replaced with p-type silicon, i-type silicon, which is an intrinsic semiconductor not doped with impurities, and corresponds to FIG. 1I.
- the silicon pillar 1a in the N-channel SGT is ion-doped with an acceptor impurity such as boron (B) to form the P-type silicon layer 30, and the silicon pillar 1a in the P-channel SGT has phosphorus It is also possible to form the N-type silicon layer 30a by ion doping with a donor impurity such as (P) or arsenic (As).
- a donor impurity such as (P) or arsenic (As).
- an intrinsic semiconductor may be used for both of the silicon pillars 1a and 1b, and the intrinsic semiconductor inside the silicon pillars 1a and 1b may be used as N-channel and P-channel SGT channels.
- an N channel type SGT and a P channel type SGT are formed on the second semiconductor substrate 9, which is the same semiconductor substrate, in substantially the same manner as in the first and third embodiments (FIGS. 1A to 1D). 1J, see FIGS. 3A and 3B).
- N + polycrystalline silicon layers 55a functioning as sources and P + many functioning as drains.
- the crystalline silicon layers 55b are electrically connected to each other by extending the metal layers 7aa and 7bb.
- the metal layer 7 is formed by vapor deposition and etching so as to cover the silicon layers to be the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b. . Then, the metal layer 7, the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b are formed into a predetermined shape by etching. As a result, as shown in FIG. 4, an N + polycrystalline silicon layer 55a, a P + polycrystalline silicon layer 55b, and first connection metal layers 7a and 7b are formed.
- a silicon oxide layer 20 is formed on the first connection metal layer 7a, and a contact hole 21c is formed in the silicon oxide layer 20.
- a contact hole 21c is formed in the silicon oxide layer 20.
- the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b and the external metal wiring layer 22c formed on the silicon oxide layer 20 through the contact hole 21c and the first connection metal layer 7a. And connect.
- metal layers 7aa and 7bb are bonded to the entire back surfaces of the N + polycrystalline silicon layer 55a of the N channel type SGT and the P + polycrystalline silicon layer 55b of the P channel type SGT, respectively. Yes.
- the N + diffusion layers 6a and 6b and the plurality of metal layers 7aa and 7bb are connected to each other.
- the N + diffusion layer 6a and the N + polycrystalline silicon layer 55a are the source or drain of the N channel type SGT, and the P + polycrystalline silicon layer 55b is the source or drain of the P channel type SGT. Function as each.
- the source and drain constituted by the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b are arranged on the upper surface of the silicon oxide layer 20. Electrically connected to each other by extending the first connecting metal layer 7a without being connected to each other after being drawn out through a contact hole or the like to the region where the metal wiring layers 22a, 22b, and 22c are formed. Is done. Thereby, the integration degree of the circuit element which has SGT can be raised.
- the semiconductor device manufacturing method according to the present embodiment can be applied to a solid-state imaging device manufacturing method.
- the drains of the pixels are connected to each other by the first connection metal layer 7a. Connect with.
- the drain and source of each pixel need not be connected to each other after being connected to another metal wiring in the upper layer portion via a contact hole or the like. For this reason, further high integration of the pixels of the solid-state imaging device is realized.
- FIGS. 5A to 5C a method for forming an electrical resistance in a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 5A to 5C.
- the manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
- an electrical resistance which is a circuit element of the semiconductor device is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
- a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
- a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
- a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3, and in the process shown in FIG. 1C, phosphorus (P) or The N + polycrystalline silicon layer 5a is formed by ion doping with a donor impurity such as arsenic (As).
- a donor impurity such as arsenic (As).
- N + polycrystalline silicon layers 23a and 23b are formed by ion doping with a donor impurity such as) at a predetermined concentration.
- the N + polycrystalline silicon layers 23a and 23b, the polycrystalline silicon layer 23 in which donor impurities are not ion-doped, or the polycrystalline silicon layer 23 doped with predetermined impurities are used to form a predetermined region ( The electrical resistance value in the polycrystalline silicon layer 23) decreases and an electrical resistance is formed.
- the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23 are formed from the polycrystalline silicon layer 5 (see FIG. 1B) in the same manner as the N + polycrystalline silicon layer 5a (see FIG. 1C). Therefore, it is located in the same layer as the N + polycrystalline silicon layer 5a.
- metal wiring layers 24a and 24b located in the same layer as the metal layer 7 are formed in the same manner as the metal layer 7 on the N + polycrystalline silicon layers 23a and 23b.
- a predetermined region of the polycrystalline silicon layer 5 is ion-doped with a donor impurity having a predetermined concentration, so that N + polycrystalline silicon layers 23a and 23b having a predetermined electric resistance value, polycrystalline silicon Layer 23 is formed.
- the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23 are formed in the same layer as the N + polycrystalline silicon layer 5a.
- the polycrystalline silicon layer 25 is formed in the step shown in FIG. 1B and formed into a predetermined shape by etching
- the polycrystalline silicon layer is formed by vapor deposition or CVD.
- Metal wiring layers 26 a and 26 b connected to the layer 25 are formed. In this way, electrical resistance in the semiconductor device is also formed by the polycrystalline silicon layer 25.
- the second silicon oxide layer 8 is formed on the second semiconductor substrate 9, and the N + is formed on the second silicon oxide layer 8 by the method described above.
- Polycrystalline silicon layers 23a and 23b and a polycrystalline silicon layer 23 are formed.
- the first silicon oxide layer 3 is formed on the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23, and the silicon oxide layer 20 (see FIG. 4) is formed on the first silicon oxide layer 3. It is also possible to do.
- the electrical resistance shown in FIG. 5A is formed from the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23.
- a circuit element or metal wiring having SGT is formed on the first silicon oxide layer 3. Further, in the modification shown in FIG. 5C, the polycrystalline silicon layer 23 constituting the electric resistance is formed below the first silicon oxide layer 3 which is an insulator.
- the upper and lower sides of the SiO 2 layer (first silicon oxide layer 3) are shown in FIG. 4 so as to overlap with the polycrystalline silicon layer 23 constituting the electric resistance.
- the metal wiring layers 22a, 22b and 22c of the circuit element can be formed. Thereby, further high integration of the semiconductor device (circuit element) having electric resistance is realized.
- FIGS. 6A to 6C a method of forming a capacitor in a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 6A to 6C.
- the manufacturing process of the semiconductor device according to the present embodiment is the same as that of the first embodiment, except as described below.
- a capacitor which is a circuit element of a semiconductor device, is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
- a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
- a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
- a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3, and in the process shown in FIG. 1C, phosphorus (P) or The N + polycrystalline silicon layer 5a is formed by ion doping with a donor impurity such as arsenic (As).
- a donor impurity such as arsenic (As).
- capacitive silicon oxide layer 27 is formed on the surface layer portion of N + polycrystalline silicon layer 5a by thermal oxidation or CVD.
- the capacitor silicon oxide layer 27 functioning as a capacitor insulating film is formed into a predetermined shape in the capacitor region where the capacitor is formed by etching using a mask.
- a metal layer 28 that functions as a capacitor electrode is formed on the capacitor silicon oxide layer 27 formed in a predetermined shape by vapor deposition or CVD.
- the metal layer 28 is formed in the same layer as the metal layer 7 of the first embodiment.
- a laminated structure as shown in FIG. 6C is formed. That is, a second silicon oxide layer 8 is formed on the second semiconductor substrate 9, and inside the second silicon oxide layer 8, a metal layer 28 functioning as a capacitor electrode is formed in a capacitor region where a capacitor is formed, and A capacitive silicon oxide layer 27 that is stacked on the metal layer 28 and functions as a capacitive insulating film is disposed. Then, the N + polycrystalline silicon layer 5a, the first silicon oxide layer 3 and the silicon oxide layer 29 (silicon oxide layer 20) are stacked in this order on the capacitive silicon oxide layer 27 and the second silicon oxide layer 8. Is obtained. In this structure, the metal layer 28 and the N + polycrystalline silicon layer 5a function as a capacitor electrode, and a capacitor in which the capacitor silicon oxide layer 27 functions as a capacitor insulating film is formed.
- the process of forming the insulating layer 27 on the surface layer of the N + polycrystalline silicon layer 5a (see FIG. 6A).
- a step of forming the capacitive silicon oxide layer 27 and the metal layer 28 see FIG. 6B.
- a method of forming a capacitor in a semiconductor device according to a seventh embodiment of the present invention will be described.
- the manufacturing process of the semiconductor device according to the present embodiment is the same as that of the first embodiment, except as described below.
- a capacitor which is a circuit element of a semiconductor device, is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
- a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
- a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
- the capacitance forming region 100 shown in FIG. 7A is set on the first silicon oxide layer 3, and the capacitance forming region 100 in this capacitance forming region 100 is set.
- a concave silicon oxide layer removal region is formed. That is, in the step shown in FIG. 1B, as shown in FIG. 7A, the silicon oxide layers 101a and 101b are left around the silicon oxide layer removal region, and the silicon oxide layer removal region has a silicon oxide layer.
- a silicon oxide layer 103 having a thickness smaller than those of 101a and 101b is left.
- acceptor impurities such as boron (B) are ion-doped or thermally diffused, whereby the surface layer of the first semiconductor substrate 1 in the capacitor formation region 100 through the silicon oxide layer 103.
- the P + diffusion layer 102 is formed.
- a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3 so as to embed a silicon oxide layer removal region.
- the polysilicon layer 5 is ion-doped with a donor impurity such as phosphorus (P) or arsenic (As) to form an N + polycrystalline silicon layer 104 (see FIG. 1C). (See FIG. 7A).
- a donor impurity such as phosphorus (P) or arsenic (As)
- a metal layer 105 is formed on the N + polycrystalline silicon layer 104 by vapor deposition or CVD (see FIG. 7A).
- the metal layer 105 is formed in the same layer as the metal layer 7 in the first embodiment.
- the N + polycrystalline silicon layer 104 and the N + polycrystalline silicon layer 104 are formed and function as a capacitor electrode.
- the metal layer 105 to be formed is formed into a predetermined shape.
- the P + diffusion layer 102 is left in the silicon pillar 1a, and the P + diffusion layer 102 and the oxidation layer are oxidized.
- a silicon oxide layer 107 is formed so as to cover the silicon layers 101a and 101b.
- a contact hole 108 is formed in the silicon oxide layer 107, and the metal wiring layer 109 and the P + diffusion layer 102 on the silicon oxide layer 107 are electrically connected via the contact hole 108. Connect to.
- the N + polycrystalline silicon layer 104, the metal layer 105, and the P + diffusion layer 102 function as a capacitor electrode in the capacitor formation region 100 (see FIG. 7A).
- a capacitor is formed in which the silicon oxide layer 103 between 101a and 101b functions as a capacitor insulating film.
- the P + diffusion layer 102 is formed by ion doping or thermal diffusion of acceptor impurities such as boron (B) into the first semiconductor substrate 1 using the silicon oxide layers 101a and 101b as a mask.
- acceptor impurities such as boron (B)
- the P + diffusion layer 102 performs ion doping with a high acceleration voltage on the first silicon oxide layer 3 (see FIG. 1A) having a uniform thickness before the silicon oxide layers 101a and 101b are formed. Thus, it can be formed in a predetermined region other than the capacitance forming region 100.
- the contact hole 108 enables connection between capacitors and extraction of an electric signal to an external circuit from an arbitrary location of the semiconductor device. As a result, further integration of circuit elements can be realized.
- FIGS. 8A to 8C a method for forming a diode in a semiconductor device according to an eighth embodiment of the present invention will be described with reference to FIGS. 8A to 8C.
- the manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
- a diode which is a circuit element of a semiconductor device is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
- the second silicon oxide layer 8 is formed on the second semiconductor substrate 9 as shown in FIG. 8A through the steps shown in FIGS. 1A to 1I of the first embodiment.
- the metal layer 7, the N + polycrystalline silicon layer 5a, and the silicon pillar 1a are formed in this order from below.
- a first silicon oxide layer 3 is formed around the N + polycrystalline silicon layer 5a.
- an ion impurity is doped with an acceptor impurity such as boron (B) to thereby form a P-type silicon layer shown in FIG. 8B. 30 is formed.
- acceptor impurity such as boron (B)
- N + diffusion layer 6a is formed.
- ion implantation of acceptor impurities such as boron (B) is formed on the upper portion of the P-type silicon layer 30 (silicon pillar 1 a), thereby forming a P + -type silicon layer 31.
- the metal layer 32 is formed on the P + type silicon layer 31 by vapor deposition and etching.
- a silicon oxide layer 33 is formed so as to cover the P-type silicon layer 30 and the metal layer 32.
- contact holes 34, The metal wiring layer 35 is formed in this order. Thereby, the metal wiring layer 35 and the metal layer 32 are electrically connected via the contact hole 34.
- a pn junction diode is formed by the P + type silicon layer 31 and the P type silicon layer 30.
- a diode circuit element
- a semiconductor device such as SGT
- FIG. 8C shows a modification of this embodiment in which a PIN photodiode is formed on the silicon pillar 1a.
- an i-type silicon layer 30b which is an intrinsic semiconductor is formed on the silicon pillar 1a shown in the eighth embodiment instead of the P-type silicon layer 30.
- a P + type silicon layer 31 is formed on the i type silicon layer 30b.
- a PIN photodiode is formed by the i-type silicon layer 30 b and the P + -type silicon layer 31.
- the depletion layer is formed in the entire i-type silicon layer 30b or in a wide area, so that a wide photoelectric conversion area can be secured and the thickness of the capacitance formation area can be increased. Since the thickness of the corresponding depletion layer is increased, the capacity can be reduced.
- the PIN photodiode is formed as an optical connection light receiving element on the same semiconductor substrate as the circuit element of the semiconductor device.
- the PIN photodiode of this modification functions as an optical switch, there is no RC delay due to the resistance / capacitance of the input circuit wiring, and the speed of the circuit input section and the speed of the entire circuit can be increased.
- a PIN photodiode (circuit element) can be formed on the same semiconductor substrate together with a pixel of a solid-state imaging device, a semiconductor device such as SGT, and the manufacturing process can be simplified. become.
- FIG. 9A shows a CMOS inverter circuit using the SGT according to the present embodiment.
- a P-channel MOS transistor 37a and an N-channel MOS transistor 37b are connected in series.
- the gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b are connected through a gate connection wiring 38, and the gate connection wiring 38 is connected to the input terminal wiring Vi.
- the source of the P-channel MOS transistor 37a is connected to the power supply terminal wiring Vdd.
- the drain of the P-channel MOS transistor 37a and the drain of the N-channel transistor 37b are connected to the output terminal wiring Vo via the drain connection wiring 39, and the source of the N-channel MOS transistor 37b is at the ground potential. It is connected to the ground terminal wiring Vss.
- FIG. 9B shows a plan layout of a CMOS inverter circuit using this SGT. As shown in FIG. 9B, the contact hole 41c, the silicon pillar 40a, the contact hole 41a, the contact hole 41b, and the contact hole 41d are arranged in a straight line.
- the input terminal wiring Vi is for inputting an electric signal (gate voltage) from the contact hole 41c.
- the power supply terminal wiring Vdd is for supplying a power supply voltage from the contact hole 41a.
- the ground terminal wiring Vss is for connecting to the ground via the contact hole 41b.
- the output terminal wiring Vo is for outputting an electrical signal from the contact hole 41d.
- the contact hole 41c is formed on the gate connection wiring 38 that connects the gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b.
- the silicon pillar 40a constitutes a P channel type MOS transistor 37a.
- the contact hole 41a is formed on the silicon pillar 40a.
- the silicon pillar 40b constitutes an N channel type MOS transistor 37b.
- the contact hole 41b is formed on the silicon pillar 40b.
- the contact hole 41d is formed on a drain connection wiring 39 that connects the drain of the P-channel MOS transistor 37a and the drain of the N-channel MOS transistor 37b to each other.
- the input terminal wiring Vi, the power supply terminal wiring Vdd, the ground terminal wiring Vss, and the output terminal wiring Vo are arranged so as to extend in the row direction orthogonal to the column direction of the contact holes 41b and 41d, respectively. (See FIG. 9A).
- FIG. 9C is a sectional structural view taken along line B-B ′ of FIG. 9B.
- a method of forming the above-described CMOS inverter circuit will be described with reference to FIG. 9C.
- the process of forming the CMOS inverter circuit is the same as that of the first embodiment, except as specifically described below.
- the CMOS inverter circuit having the P-channel MOS transistor 37a and the N-channel MOS transistor 37b shown in FIG. 9C is the same as the N-channel MOS transistor and the P-channel MOS transistor in the circuit shown in FIG. 3B. Are formed in the same manner as the third embodiment shown in FIGS. 3A and 3B.
- the description of the parts indicated by the same or corresponding symbols as those of the above embodiment will be omitted.
- the drain connection wiring 39 is formed below the N + polycrystalline silicon layer 55a.
- a drain connection wiring 39 is bonded to the lower surfaces of the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b.
- the N + polycrystalline silicon layer 55 a and the P + polycrystalline silicon layer 55 b are connected via the drain connection wiring 39.
- the drain connection wiring 39 is formed on the insulating layer 43 b and is connected to the output terminal wiring layer Vo through a contact hole 41 d penetrating the silicon oxide layer 45.
- the gate conductor layers 16ba and 16bb of the P-channel MOS transistor 37a and the gate conductor layers 16aa and 16ab of the N-channel MOS transistor 37b are connected through a gate connection wiring 38 formed on the insulating layer 43a. ing.
- the N + diffusion layer 6a, the metal wiring layer 18a formed on the N + type silicon layer 17a, and the drain connection wiring 39 are respectively connected via contact holes 41c, 41a, 41b, and 41d penetrating the silicon oxide layer 45.
- the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vo formed on the silicon oxide layer 45 are connected.
- the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vo are wired in parallel to each other (see FIG. 9C).
- the N + polycrystalline silicon layer 55a is connected in a state of being close to each other and electrically connected by a drain connection wiring 39 having a low electric resistance.
- FIG. 10A shows a CMOS inverter circuit having a two-stage structure used in this embodiment.
- P-channel MOS transistors 37a and 37c and N-channel MOS transistors 37b and 37d are connected in series at the first and second stages, respectively.
- the gates of the first-stage P-channel MOS transistor 37a and N-channel MOS transistor 37b are connected to the input terminal wiring Vi through the gate connection wiring 38a.
- the gates of the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37d are connected to the first-stage output terminal wiring Vo through the gate connection wiring 38b.
- the drains of the first-stage and second-stage P-channel MOS transistors 37a and 37c are connected to the power supply terminal wiring Vdd.
- the sources of the first-stage and second-stage P-channel MOS transistors 37b and 37d are connected to the ground terminal wiring Vss.
- the drain of the P-channel MOS transistor 37a and the drain of the N-channel transistor 37b are connected to the first-stage output terminal wiring Vo via the drain connection wiring 39a.
- the drain of the P-channel transistor 37c and the drain of the N-channel transistor 37d are connected to the output terminal wiring Vout via the drain connection wiring 39b.
- FIG. 10B shows a plan layout of this CMOS inverter circuit.
- a contact hole 41c is formed on the gate connection wiring 38a formed on the silicon pillar 40a constituting the first-stage P-channel MOS transistor 37a and the silicon pillar 40b constituting the N-channel MOS transistor 37b.
- the contact hole 41c is connected to the input terminal wiring Vi.
- the gate connection wiring 38a connects the gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b.
- the drain of the P-channel MOS transistor 37a and the drain of the N-channel MOS transistor 37b are connected via the first-stage drain connection wiring 39a.
- a contact hole 41e is formed on the gate connection wiring 38b formed in the silicon pillar 40c constituting the second-stage P-channel MOS transistor 37c and the silicon pillar 40d constituting the N-channel MOS transistor 37d. It is connected to the first-stage output terminal wiring Vo (see FIG. 10A).
- the first-stage drain connection wiring 39a is connected to the gate connection wiring 38b through the contact hole 41e (see FIG. 10C).
- the gate connection wiring 38b connects the gates of the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37d.
- Contact holes 41a and 41c are formed on the silicon pillars 40a and 40c of the first-stage and second-stage P-channel MOS transistors 37a and 37c, respectively.
- the contact holes 41a and 41c are both connected to the power supply terminal wiring layer Vdd.
- Contact holes 41b and 41d are formed on the silicon pillars 40b and 40d of the first-stage and second-stage P-channel MOS transistors 37b and 37d, respectively, and both of the contact holes 41b and 41d are connected to the ground terminal wiring layer Vss. Has been.
- a contact hole 41f is formed on the second-stage drain connection wiring 39b, and the contact hole 41f is connected to the output terminal wiring layer Vout.
- the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout are wired in parallel to each other.
- FIG. 10C is a cross-sectional structural view taken along the line C-C ′ of FIG. 10B.
- the above-described two-stage CMOS inverter circuit will be described with reference to FIG. 10C.
- the two-stage CMOS inverter circuit is formed in the same manner as in the first embodiment.
- CMOS inverter circuit having the P-channel MOS transistor 37a and the N-channel MOS transistor 37b shown in FIG. 10C is the same as the CMOS inverter circuit shown in FIG. 3B in terms of the left and right sides of the N-channel MOS transistor and the P-channel MOS transistor. However, they are formed in the same manner as the third embodiment shown in FIGS. 3A and 3B.
- the conductor layers 16aa and 16ab are connected via the gate connection wiring 38a.
- a contact hole 41b connected to the metal wiring layer 18a on the N-channel MOS transistor 37b is formed in the silicon oxide layer 45 formed on the gate connection wiring 38a.
- the contact hole 41b is connected to the ground terminal wiring Vss of the N channel type MOS transistor 37b.
- a silicon oxide layer 43 is formed between the first silicon oxide layer 3 and the gate connection wiring 38a.
- the N + polycrystalline silicon layer 55a functioning as the drain is electrically connected to each other through the metal wiring layer 42 which is the first-stage drain connection wiring 39a.
- the metal wiring layer 42 is connected via a gate connection wiring 38b that connects the gates of the second-stage P-channel MOS transistor 37c and the N-channel MOS transistor 37d, and a contact hole 41e formed in the silicon oxide layer 45. Are connected (see FIGS. 10A and 10B).
- a contact hole 41a is formed on the silicon pillar 40a of the first-stage P-channel MOS transistor 37a, and the contact hole 41a is connected to the power supply terminal wiring layer Vdd.
- a contact hole 41b is formed on the silicon pillar 40b of the first-stage N-channel MOS transistor 37b, and the contact hole 41b is connected to the ground terminal wiring layer Vss.
- a contact hole 41f is formed on the second-stage drain connection wiring 39b, and the output terminal wiring layer Vout is connected to the contact hole 41f on the silicon oxide layer 45 (see FIGS. 10A and 10B). Further, the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout are wired in parallel to each other (see FIG. 10B).
- the metal wiring layer 42 functioning as the drain connection wiring 39a of the first-stage P-channel MOS transistor 37a and N-channel MOS transistor 37b is replaced with the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37c.
- the channel type MOS transistor 37d is directly connected to the gate connection wiring 38b via the contact hole 41e.
- the metal wiring layer 42 (39a) is connected to the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout through the contact holes formed in the silicon oxide layer 45 (FIG. 10B), it is not necessary to pull up to the same layer as that, so that high integration of circuit elements is realized.
- FIGS. 11A and 11B a method for forming a mask alignment mark on a semiconductor substrate according to an eleventh embodiment of the present invention will be described with reference to FIGS. 11A and 11B.
- the process shown in FIG. 11A corresponds to the process shown in FIG. 1H in the first embodiment.
- the other steps are the same as those in the first embodiment except for the case specifically described below.
- a second silicon oxide layer 8 is formed on the second semiconductor substrate 9.
- the first silicon oxide layer 3 and the first semiconductor substrate 1 are formed in this order.
- a mask alignment mark formation region 47a for mask alignment and a circuit formation region 47b for forming a circuit are set at predetermined positions on the first semiconductor substrate 1.
- a silicon oxide layer removal region 48 is formed in the first silicon oxide layer 3 (see FIG. 1B). At the center of the silicon oxide layer removal region 48, a mark metal layer 49a and a mark polycrystalline silicon layer 49b are formed in a laminated state.
- the silicon oxide layer removal region 48 is formed simultaneously with the hole 4 in which the source or drain of the junction field effect transistor in the pixel of the solid-state imaging device is formed.
- a metal layer 7 and an N + polycrystalline silicon layer 5a are formed in a laminated state in the center of the circuit formation region 47b (see FIG. 1H).
- a mask alignment hole 50 is formed at a predetermined position as shown in FIG. 11B.
- the mark metal layer 49 a, the mark polycrystalline silicon layer 49 b, and the silicon oxide layer removal region 48 are exposed through the mask alignment hole 50.
- the mask alignment of the photomask is performed using any one of the mark metal layer 49a, the mark polycrystalline silicon layer 49b, and the silicon oxide layer removal region 48 in the mask alignment hole 50 as a reference mask alignment mark. Do.
- a photomask is overlaid on the region where the photoresist is formed, and light is irradiated to transfer the circuit.
- the first semiconductor substrate 1 is covered with a photoresist, and the mark metal layer 49a and the mark polycrystalline silicon layer located below the first semiconductor substrate 1 are covered.
- Mask alignment is performed using either of 49b and the silicon oxide layer removal region 48 as a mark.
- the first semiconductor substrate 1 is made of silicon and absorbs blue light and ultraviolet light. Therefore, red wavelength light or infrared light having high transmittance is used for mask alignment. For this reason, the resolution of the mark image is lowered and the mask alignment accuracy is lowered.
- the mask alignment mark formation region 47a does not include a silicon layer that absorbs a large amount of blue light and ultraviolet light, so the mark metal layer 49a, the mark polycrystalline silicon layer 49b, the oxidation layer A photoresist can be formed directly on the silicon layer removal region 48. For this reason, a high-resolution mark image is obtained, and the mask alignment accuracy is improved.
- the photoresist is directly formed on the silicon oxide layer removal region 48, the alignment accuracy between the N + polycrystalline silicon layer 5a and the silicon pillar 1a shown in FIG. .
- a transparent insulating layer 50a that transmits blue light or ultraviolet light is embedded in the mask alignment hole 50 shown in FIG. 11B.
- An SiO 2 film is used for the transparent insulating layer 50a. Thereafter, the SiO 2 film and the surface of the first semiconductor substrate 1 are planarized by CMP. The step of filling the mask alignment hole 50 with the SiO 2 film is performed before the silicon pillar 1a on which the junction field effect transistor is formed is formed with reference to FIG. 1I.
- the transparent insulating layer 50a in the mask alignment hole 50 can make the photoresist covering the mask alignment mark formation region 47a and the circuit formation region 47b thin and uniform. Compared with the embodiment, the mask alignment accuracy is further improved.
- FIG. 13A corresponds to the step shown in FIG. 1B in the first embodiment.
- the other steps are the same as those in the first embodiment except for the case specifically described below.
- the separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
- a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
- holes 4 are formed in the first silicon oxide layer 3 by removing silicon oxide (SiO 2 ) in a predetermined region.
- polycrystalline silicon is formed on the first silicon oxide layer 3 and the first semiconductor substrate 1 by the CVD method so as to fill the hole 4 (silicon oxide layer removal region 48).
- Layer 111 is formed. This polycrystalline silicon layer 111 is not doped with donor impurities or acceptor impurities.
- an N + polycrystalline silicon layer 106 doped with donor impurities is formed on the polycrystalline silicon layer 111 by CVD and ion doping of donor impurities.
- a metal layer 7 is formed on the N + polycrystalline silicon layer 106 in the same manner as the step shown in FIG. 1D. Further, a semiconductor device is formed in the same manner as the steps shown in FIGS. 1E to 1L.
- the polycrystalline silicon layer 111 which is not doped with impurities is formed between the first semiconductor substrate 1 and the N + polycrystalline silicon layer 106. Due to the presence of the polycrystalline silicon layer 111, the diffusion depth of the donor impurity to the silicon pillar 1a when the N + polycrystalline silicon layer 106 is used as a diffusion source by the heat treatment in the step shown in FIG. 1J can be adjusted. it can.
- N + is changed depending on the conditions (temperature, time) of heat treatment after bonding the second semiconductor substrate 9 and the second silicon oxide layer 8 on the first semiconductor substrate 1.
- the diffusion layer 6a diffuses beyond a desired depth, this is effective for suppressing the diffusion depth.
- a P + polycrystalline silicon layer can be used in place of the N + polycrystalline silicon layer 106. Even if the polycrystalline silicon layer 111 that is not doped with donor impurities or acceptor impurities contains a small amount of impurities even if they are not actively doped, the effect of this embodiment is not affected.
- FIG. 14A corresponds to the process shown in FIG. 1C in the first embodiment
- FIG. 14B corresponds to the process shown in FIG. 1K.
- the other steps are the same as those in the first embodiment except for the case specifically described below.
- the silicon oxide layer 3a is formed on the surface of the first semiconductor substrate 1 around the region 4a corresponding to the hole 4 in FIG. 1B by the STI (Shallow Trench Isolation) method. .
- the silicon semiconductor substrate 1 around the region 4a is etched.
- a silicon oxide layer is deposited by a CVD (Chemical Vapor Deposition) method, and the first silicon oxide layer 3a is formed by smoothing the surface by CMP (Chemical V Mechanical Polishing).
- the etching of the silicon semiconductor substrate 1 is preferably performed so as to form a taper rather than in the vertical direction using the silicon nitride layer as a mask.
- the bottom of the first silicon oxide layer 3a can be positioned more inside the silicon semiconductor substrate 1 than the surface of the silicon semiconductor substrate 1 in the region 4a. Thereafter, a polycrystalline silicon layer 5aa containing donor impurities (corresponding to the polycrystalline silicon layer 5a in FIG. 1C) is formed.
- FIG. 14B differs from FIG. 1K in the following three points.
- the N + diffusion layer 6aa is formed by thermal diffusion from the N + polycrystalline silicon layer 5aa, and is a layer in which donor impurities are not present before the thermal diffusion heat treatment, and in FIG. 13B of the twelfth embodiment A function similar to that of the polycrystalline silicon layer 111 can be provided. For this reason, even if the polycrystalline silicon layer 111 is not used, the N + diffusion layer 6aa in which the end of the diffusion layer is located below the gate conductor layers 11aa and 11bb can be formed.
- the silicon pillar 1a is formed by etching in alignment with the N + diffusion layer 6aa, even if the side surface of the silicon pillar 1a is displaced to the inside of the N + diffusion layer 6aa, the first silicon oxide layer 3a , Because it is a thick N + diffusion layer or is formed to be deflated inward, it is difficult for silicon etching to reach the metal layer 7aa (in FIG. 1K, the silicon pillar 1a is the N + polycrystalline silicon layer 5a Since the N + polycrystalline silicon layer 5a is directly exposed when the position is shifted from, the N + polycrystalline silicon layer 5a and the metal layer 7 existing therebelow are easily etched).
- FIGS. 15A and 15B another method for manufacturing the semiconductor device according to the thirteenth embodiment will be described.
- FIG. 15A corresponds to the step shown in FIG. 1C in the first embodiment
- FIG. 15B corresponds to the step shown in FIG. 1K.
- the other steps are the same as those in the first embodiment except for the case specifically described below.
- the first silicon oxide layer 3b is formed in the peripheral region of the region 4a by the LOCOS (Local Oxidation of Silicon) method.
- LOCOS Local Oxidation of Silicon
- a silicon oxide layer 3b is formed by forming a thin silicon oxide layer and a silicon nitride layer on the region 4a and then performing an oxidation treatment. Thereafter, an N + polycrystalline silicon layer 5bb is formed through the same process as in FIG. 1C.
- FIG. 15B differs from FIG. 1K in the following two points.
- the N + diffusion layer 6aa surrounded by the first silicon oxide layer 3a is formed in an inverted trapezoidal shape as in FIG. 14B, whereas in FIG. 1K, the N + diffusion layer 5a is It is formed in a trapezoidal shape along the side surface of the monoacid silicon layer 3.
- the gate conductor layers 11aa and 11bb are in contact with the first silicon oxide layer 3b, whereas in FIG. 1K, the gate conductor layers 11a and 11b are separated from the first silicon oxide layer 3. thing.
- the present embodiment has the following advantages. That is, (1) Similar to FIG. 14B, the N + diffusion layer 6bb is formed by thermal diffusion from the N + polycrystalline silicon layer 5bb, and is a layer without donor impurities before heat treatment by thermal diffusion. It can be made to have the same function as the polycrystalline silicon layer 111 in FIG. Therefore, even if the polycrystalline silicon layer 111 is not used, it is possible to form the N + diffusion layer 6bb in which the end portion of the diffusion layer is located below the gate conductor layers 11aa and 11bb. (2) Similarly to FIG.
- FIGS. 16A to 16C A method for manufacturing a semiconductor device according to a fourteenth embodiment of the present invention will be described below with reference to FIGS. 16A to 16C.
- the present embodiment is characterized in that two or more impurity regions are formed at the bottom of the silicon pillar 1a.
- FIG. 16A shows a sectional structural view corresponding to FIG. 1C.
- a first hole 4b1 and a second hole 4b2 are formed in a region corresponding to the hole 4 in FIG. 1B of the first silicon oxide layer 3b, and the surface of the P-type silicon semiconductor substrate 1 is exposed.
- the first region B1 including the first hole 4b1 is doped with acceptor ions (in this case, boron B ions) to form the P + polycrystalline silicon layer 5b1, and the second region including the second hole is formed.
- acceptor ions in this case, boron B ions
- N + polycrystalline silicon layer 5b doped with donor ions in this case, arsenic (As) ions
- the doping of the acceptor ion and the donor ion is performed after the ion doping of one is completed.
- the P + polycrystalline silicon layer 5b1 and the N + polycrystalline silicon layer 5b2 are covered with a metal layer, and P + surrounding the first silicon oxide layer 3b around the holes 4b1 and 4b2.
- a polycrystalline silicon layer 5bb1, a metal layer 7b1, an N + polycrystalline silicon layer 5bb2, and a metal layer 7b2 are formed.
- the P + diffusion layer 6b1 and the P + polycrystalline silicon layer 5bb1 function as the drain of the junction field effect transistor for signal readout
- the N + diffusion layer 6b2 and the N + polycrystalline silicon layer Reference numeral 5bb2 functions as a drain for removing signal charges accumulated in the photodiode including the N-type silicon layers 12a and 12b and the P-type silicon layer 30.
- the P + polycrystalline silicon layer 5bb1 and the N + polycrystalline silicon layer 5bb2 are connected to the metal layers 7b1 and 7b2 and wired to an external circuit. Thereby, the resistance of the signal readout line and the signal charge removal line from the pixel formed on the silicon pillar 1a to the external circuit is reduced, and high-speed driving of the solid-state imaging device is realized.
- two or more impurity regions can be formed at the bottom of the silicon pillar 1a in the same manner as the above steps.
- this embodiment can be applied to embodiments other than the present embodiment, for example, a method for manufacturing a semiconductor device in which circuit elements other than the solid-state imaging device are formed on the silicon pillar 1a.
- the first silicon oxide layer 3 is formed by thermal oxidation, anodization, CVD (Chemical Vapor Deposition), or the like. Formed.
- CVD Chemical Vapor Deposition
- the present invention is not limited to this, and a multilayer structure with another insulating film such as a silicon nitride (SiN) film may be used.
- the present invention is not limited to the embodiments described in the first to fourteenth embodiments, and various modifications can be made.
- the first semiconductor substrate 1 is P-type conductivity.
- the first semiconductor substrate 1 is not limited to this, and may be i-type (intrinsic type) which is an intrinsic semiconductor. Further, depending on the circuit element formed on the first semiconductor substrate 1, an N-type conductivity type may be used.
- the channel of the P-channel MOS transistor is formed in the N-type silicon layer 30a, and the channel of the N-channel MOS transistor is the P-type silicon layer.
- the channel of the N-channel MOS transistor is the P-type silicon layer.
- any of them may be formed on i-type silicon which is an intrinsic semiconductor.
- the N + polycrystalline silicon layer 5a, the metal layer 7, and the N + diffusion layer 6a are used as individual material layers.
- the metal layer 7 is reacted with the metal material (Ni, W, etc.) of the metal layer 7 and a part of the N + polycrystalline silicon layer 5a or the N + diffusion layer 6a. 7.
- All or part of the N + polycrystalline silicon layer 5a or the N + diffusion layer 6a may be changed to a silicide layer (NiSi, WSi, etc.).
- the temperature is 400 to 600 ° C.
- the first semiconductor substrate 1 was separated into a top and bottom by heat treatment, and the first semiconductor substrate 1 was thinned to a predetermined thickness.
- a method of forming a porous layer in the separation layer 2 shown in Non-Patent Document 3 may be employed to reduce the thickness of the first semiconductor substrate 1 to a predetermined thickness.
- a method of separating the first semiconductor substrate 1 vertically can be employed.
- the second semiconductor substrate 9 may be a semiconductor different from silicon, for example, a compound semiconductor such as silicon carbide (SiC), an insulator, or an organic resin body. Also with this configuration, the circuit elements formed on the first semiconductor substrate 1 can be held.
- the second silicon oxide layer 8 and the silicon oxide layers 20, 29, 45 may have a multilayer structure with other insulating films such as a silicon nitride (SiN) film.
- SiN silicon nitride
- the N + polycrystalline silicon layers 5a and 55a and the P + polycrystalline silicon layer 55b were formed by ion doping.
- the present invention is not limited to this, and it may be formed by thermal diffusion of impurities or a doped polycrystalline silicon layer mixed with impurities. Such a doped polycrystalline silicon layer can be similarly applied to other embodiments in this specification.
- the polycrystalline silicon layer 5 was formed by a CVD method.
- the present invention is not limited to this, and the polycrystalline silicon layer 5 may be formed by epitaxial growth.
- a single crystal silicon layer is grown on the first semiconductor substrate 1, and a polycrystalline silicon layer is formed on the first silicon oxide layer 3 depending on the growth conditions.
- the single crystal silicon layer becomes a diffusion source to the silicon pillar 1a of the donor or acceptor.
- the silicon layer can be prevented from being formed on the first silicon oxide layer 3 depending on the growth conditions (temperature, etc.) of the single crystal silicon layer.
- the silicon layer is not formed on the first silicon oxide layer 3.
- the second semiconductor substrate 9 made of silicon and the second silicon oxide layer 8 flattened by CMP are bonded together, and an oxide layer is formed on the surface of the second semiconductor substrate 9 by oxidation or CVD.
- the second semiconductor substrate 9 and the second silicon oxide layer 8 can be bonded after the insulating layer is formed.
- the drain connection wiring 39 and the output terminal wiring Vo are connected via the contact hole 41d.
- the drain connection wiring 39 and the output terminal wiring Vo can be connected so that the bottom of the contact hole 41 d is in contact with the N + polycrystalline silicon layer 55 a on the drain connection wiring 39. Also with this configuration, the electrical resistance of the N + polycrystalline silicon layer 55a is sufficiently small, so that high-speed operation of the circuit element is realized.
- the metal wiring layer 42 (39a) functioning as the drain connection wiring and the second-stage gate connection wiring 38b are connected via the contact hole 41e.
- the connection is not limited to this, and the contact hole 41 e can be connected so that the bottom thereof is in contact with the N + polycrystalline silicon layer 55 a on the metal wiring layer 42. Also with this configuration, the electrical resistance of the N + polycrystalline silicon layer 55a is sufficiently small, so that high-speed operation of the circuit element is realized.
- gate conductor layers 11a, 11b, 11c, 11d, 16a, 16b, 16c, 16d, and gate connection wirings 38, 38a, as shown in FIG. 10C, as shown in FIG. 1L, FIG. 2, and FIG. 38b was formed by a vapor deposition method or a CVD method.
- the present invention is not limited to this, and a single layer or a plurality of different types of metal layers, a polycrystalline silicon layer doped with impurities, or a multilayer configuration of the polycrystalline silicon layer and the metal layer may be used.
- the gate connection wirings 38, 38a, and 38b may use different materials for the N channel type and the P channel type. The use of different materials for the N-channel type and the P-channel type for the gate connection wirings 38, 38a, and 38b can be similarly applied to the other embodiments in this specification.
- the two-stage CMOS inverter circuit shown in FIGS. 10B and 10C can be configured as follows. That is, the P + -type silicon layer 17b and the N + -type silicon layer 17a in the upper part of the silicon pillar 40a of the P-channel MOS transistor 37a and the silicon pillar 40b of the N-channel MOS transistor 37b are formed in the silicon oxide layer 45. It is connected to the first-stage output terminal wiring layer Vout through the formed contact holes 41a and 41b.
- the metal layer 46b connected to the P + polycrystalline silicon layer 55b and the P + diffusion layer 6b below the silicon pillar 40a of the P channel MOS transistor 37a is used as a power supply terminal wiring layer Vdd, and N channel
- the metal layer 46a connected to the N + polycrystalline silicon layer 55a and the N + diffusion layer 6a below the silicon pillar 40b of the type MOS transistor 37b is defined as a ground terminal wiring layer Vss. Also in this structure, the same effect as the structure shown in FIG. 10C can be obtained.
- arsenic is formed after the gate conductor layers 11a and 11b are formed in order to perform self-alignment between the gate conductor layers 11a and 11b and the N + diffusion layer 6a serving as a signal line.
- the N + -type silicon layer may be formed in the silicon pillar 1a between the gate conductor layers 11a and 11b and the N + diffusion layer 6a by using the ion doping or the deposited As-doped silicon oxide layer as a diffusion source.
- the first semiconductor substrate 1 is etched to the surface of the first silicon oxide layer 3 to form the silicon pillar 1a. It may be stopped before reaching the surface of the layer 3.
- an N + type silicon layer may be formed by doping a remaining silicon layer without being etched with a donor impurity.
- arsenic (As) ion doping or deposition As doping is performed in order to perform self-alignment between the gate conductor layers 16a and 16b and the N + diffusion layer 6a serving as the source or drain.
- An N + type silicon layer may be formed in the silicon pillar 1a between the gate conductor layers 16a and 16b and the N + diffusion layer 6a using the silicon oxide layer as a diffusion source.
- the third silicon oxide layer 10a on the outer peripheral portion of the N-type silicon layers 12a and 12b constituting the photodiode, A conductor layer that reflects light through 10b may be formed. This prevents color mixing. Further, by forming a P + -type silicon layer connected to the P + -type silicon layer 13 a in the silicon pillar 1 a on the outer periphery of the N-type silicon layers 12 a and 12 b, it is possible to realize a low afterimage and low noise. Good. As described above, a structure in which the function of the solid-state imaging device is further enhanced can be appropriately formed in the silicon pillar 1a.
- the present invention can be applied to a semiconductor device including a transistor in which a channel region is formed in a semiconductor having a columnar structure.
Abstract
Description
この画素構造においては、半導体基板上に固体撮像装置の信号線として機能するN+型シリコン層51が形成されている。また、N+型シリコン層51に柱状半導体110が接続されている。その柱状半導体110には、P型シリコン層52、絶縁膜53a、53b、ゲート導体層54a、54bからなる、蓄積電荷を除去するためのMOSトランジスタが形成されている。さらに、柱状半導体110には、このMOSトランジスタに接続され、光(電磁エネルギー波)の照射によって発生する電荷を蓄積するフォトダイオードが形成されている。このフォトダイオードは、P型シリコン層52とN型シリコン層58a、58bとから構成される。また、このフォトダイオードで囲まれたP型半導体52をチャネル、フォトダイオードをゲート、フォトダイオード上に形成され、画素選択線57a、57bに接続されたP+型シリコン層56、N+型シリコン層51近傍のP型シリコン層52を、それぞれ、ソース、ドレインとした接合電界効果トランジスタ(接合トランジスタ)が形成されている。 As shown in FIG. 17, a solid-state imaging device in which one pixel is configured in one
In this pixel structure, an N +
半導体基板上の所定領域に第1の絶縁層を形成し、前記所定領域上の第1の絶縁層を除去することで、絶縁層除去領域を形成する第1絶縁層形成・除去工程、または、前記所定領域の周辺において、前記半導体基板を厚さ方向に一部除去し、当該半導体基板を除去した半導体基板除去領域に第1の絶縁層を形成する第2絶縁層形成・除去工程と、
少なくとも前記所定の領域を覆うように、前記半導体基板上にドナー不純物又はアクセプタ不純物を含む第1の半導体層を形成する第1半導体層形成工程と、
前記第1の半導体層上に導体層を形成する導体層形成工程と、
前記導体層及び前記第1の半導体層を所定の形状に成形する成形工程と、
前記所定の形状に成形した導体層及び第1の半導体層を覆うように、第2の絶縁層を形成する第1絶縁層形成工程と、
前記第2の絶縁層の表面を平坦化する平坦化工程と、
前記平坦化された前記第2の絶縁層の表面に、基板を接着する接着工程と、
前記半導体基板を所定の厚さまで薄くする薄膜化工程と、
前記第1の半導体層上に、前記半導体基板から柱状構造を有する柱状半導体を形成する柱状半導体形成工程と、
前記柱状半導体に回路素子を形成する回路素子形成工程と、を備え、
少なくとも前記第1半導体層形成工程以後に、前記ドナー不純物又はアクセプタ不純物を含む前記第1の半導体層から当該不純物を拡散させることで前記柱状半導体に第1の半導体領域を形成する第1半導体領域形成工程をさらに備える、
ことを特徴とする。 In order to achieve the above object, a method of manufacturing a semiconductor device according to the first aspect of the present invention includes:
Forming a first insulating layer in a predetermined region on the semiconductor substrate, and removing the first insulating layer on the predetermined region to form an insulating layer removal region; or A second insulating layer forming / removing step of partially removing the semiconductor substrate in a thickness direction around the predetermined region and forming a first insulating layer in the semiconductor substrate removing region from which the semiconductor substrate has been removed;
A first semiconductor layer forming step of forming a first semiconductor layer containing a donor impurity or an acceptor impurity on the semiconductor substrate so as to cover at least the predetermined region;
A conductor layer forming step of forming a conductor layer on the first semiconductor layer;
A molding step of molding the conductor layer and the first semiconductor layer into a predetermined shape;
A first insulating layer forming step of forming a second insulating layer so as to cover the conductor layer and the first semiconductor layer formed in the predetermined shape;
A planarization step of planarizing the surface of the second insulating layer;
An adhesion step of adhering a substrate to the flattened surface of the second insulating layer;
A thinning process for thinning the semiconductor substrate to a predetermined thickness;
Forming a columnar semiconductor having a columnar structure from the semiconductor substrate on the first semiconductor layer; and
A circuit element forming step of forming a circuit element on the columnar semiconductor,
Forming a first semiconductor region in the columnar semiconductor by diffusing the impurity from the first semiconductor layer containing the donor impurity or acceptor impurity at least after the first semiconductor layer forming step The process further includes
It is characterized by that.
前記柱状半導体の外周部に第3の絶縁層を形成するとともに、前記第3の絶縁層の外周部にゲート導体層を形成する工程と、
前記ゲート導体層の上方部位かつ前記柱状半導体の表層部に、前記第1の半導体領域と同一導電型である第4の半導体領域を形成する工程と、
前記柱状半導体において、前記第3の絶縁層の上方部位に、前記第1の半導体領域と反対導電型の第3の半導体領域を形成する工程と、を含む、ことが好ましい。 The circuit element forming step includes
Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer;
Forming a fourth semiconductor region having the same conductivity type as the first semiconductor region in a portion above the gate conductor layer and in a surface layer portion of the columnar semiconductor;
Preferably, the columnar semiconductor includes a step of forming a third semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the third insulating layer.
前記柱状半導体の外周部に第3の絶縁層を形成するとともに、前記第3の絶縁層の外周部にゲート導体層を形成する工程と、
前記柱状半導体における前記第3の絶縁層の上方部位に、前記第1の半導体領域と同一導電型の第5の半導体領域を形成する工程と、を含む、ことが好ましい。 The circuit element forming step includes
Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer;
And forming a fifth semiconductor region having the same conductivity type as that of the first semiconductor region at a position above the third insulating layer in the columnar semiconductor.
前記柱状半導体の上方部位に、前記第1の半導体領域と反対導電型の第6の半導体領域を形成する工程を含む、ことが好ましい。 The circuit element forming step includes
Preferably, the method includes a step of forming a sixth semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the columnar semiconductor.
前記導体層形成工程は、前記絶縁膜上に、前記第1の半導体層と共に容量電極として機能する導体層を形成する工程を含む、ことが好ましい。 The first semiconductor layer forming step includes a step of forming an insulating film functioning as a capacitor insulating film in a predetermined region on the first semiconductor layer functioning as a capacitor electrode;
The conductor layer forming step preferably includes a step of forming a conductor layer that functions as a capacitor electrode together with the first semiconductor layer on the insulating film.
前記導体層形成工程は、前記第5の絶縁層上に、容量電極として機能する導体層を形成する工程を含み、
前記第1及び第2絶縁層形成・除去工程は、前記容量形成領域に、ドナー不純物又はアクセプタ不純物を有し、容量電極として機能する不純物層を形成する容量形成工程を含む、ことが好ましい。 In the first insulating layer forming / removing step, a fourth insulating layer is formed together with the first insulating layer on the semiconductor substrate, and the capacitor formation region set in advance is thicker than the fourth insulating layer. Forming a fifth insulating layer that is thin and functions as a capacitive insulating film,
The conductor layer forming step includes a step of forming a conductor layer functioning as a capacitive electrode on the fifth insulating layer,
The first and second insulating layer forming / removing steps preferably include a capacitor forming step of forming an impurity layer having donor impurities or acceptor impurities in the capacitor forming region and functioning as a capacitor electrode.
前記マスク合わせマーク形成領域に、マスク合わせ孔を形成し、前記絶縁層除去領域、前記第1の絶縁層及び前記導体層の少なくとも一つを露出させる工程と、
前記マスク合わせ孔を通して、前記絶縁層除去領域、前記第1の絶縁層及び前記導体層の内の少なくとも一つからなるマスク合わせマークを形成するマスク合わせマーク形成工程と、
前記マスク合わせマークを基準として、フォトマスクのマスク合わせを行うマスク合わせ工程と、をさらに備える、ことが好ましい。 A mask alignment mark formation region setting step for setting a mask alignment mark formation region on the semiconductor substrate;
Forming a mask alignment hole in the mask alignment mark formation region, exposing at least one of the insulating layer removal region, the first insulating layer, and the conductor layer;
A mask alignment mark forming step for forming a mask alignment mark made of at least one of the insulating layer removal region, the first insulating layer, and the conductor layer through the mask alignment hole;
It is preferable that the method further includes a mask alignment step of performing mask alignment of the photomask with the mask alignment mark as a reference.
前記マスク合わせマーク形成工程では、前記透明絶縁体を通して、前記絶縁層除去領域、前記第1の絶縁層及び前記導体層の内の少なくとも一つからなるマスク合わせマークを形成し、
前記マスク合わせ工程では、前記マスク合わせマークを基準として、フォトマスクのマスク合わせを行う、ことが好ましい。 A step of embedding a transparent insulator in the mask alignment hole;
In the mask alignment mark forming step, a mask alignment mark comprising at least one of the insulating layer removal region, the first insulating layer and the conductor layer is formed through the transparent insulator,
In the mask alignment step, it is preferable that mask alignment of a photomask is performed using the mask alignment mark as a reference.
前記エッチングされた領域の前記半導体基板上に、前記第1の絶縁層を形成する工程と、
前記エッチングにより露出した前記半導体基板と、当該露出した半導体基板の周辺に位置する前記第1の絶縁層上に、前記第1の半導体層を形成する工程と、を含む、
ことが好ましい。 The second insulating layer forming / removing step includes a semiconductor substrate etching step of etching the semiconductor substrate around a region where the columnar semiconductor is formed,
Forming the first insulating layer on the semiconductor substrate in the etched region;
Forming the first semiconductor layer on the semiconductor substrate exposed by the etching and on the first insulating layer located around the exposed semiconductor substrate;
It is preferable.
ことが好ましい。 The second insulating layer forming / removing step includes a step of selectively oxidizing a peripheral region of the semiconductor substrate in a region where the columnar semiconductor is formed to form a selective oxide layer as the first insulating layer. ,
It is preferable.
前記互いに分離された領域における前記第1の絶縁層で囲まれ、かつ、露出した前記半導体基板の表面上に、互いに分離され、ドナーまたはアクセプタがドープされた複数の前記第1の半導体層と、前記第1の半導体層に接続された前記導体層と、を形成する工程を含む、
ことが好ましい。 Forming at least two or more regions for forming the first insulating layers separated from each other on the semiconductor substrate in the region for forming the columnar semiconductor;
A plurality of first semiconductor layers that are surrounded by the first insulating layer in the regions isolated from each other and that are separated from each other and doped with donors or acceptors on the exposed surface of the semiconductor substrate; Forming the conductor layer connected to the first semiconductor layer,
It is preferable.
前記柱状半導体は、
前記第1の半導体領域上に形成された当該第1の半導体領域と反対導電型の半導体又は真性半導体からなる第2の半導体領域を備え、
前記第2の半導体領域と前記第4の半導体領域とから電磁エネルギー波の照射により発生する信号電荷を蓄積するダイオードが形成され、
前記ダイオードがゲートとして機能し、前記第1の半導体領域と前記第3の半導体領域のいずれか一方がソース、他方がドレインとしてそれぞれ機能し、かつ、前記第2の半導体領域に形成されたチャネルを流れるとともに前記ダイオードに蓄積された信号電荷量に応じて変化する電流を信号取り出し手段によって取り出し可能とされた接合電界効果トランジスタが形成され、
前記ゲート導体層がゲートとして機能するとともに、前記第1の半導体領域及び前記第4の半導体領域の一方がソースとして機能し、他方がドレインとして機能するMOSトランジスタによって、前記ゲート導体層に電圧が印加されることで、前記ダイオードに蓄積された信号電荷を前記第1の半導体領域に除去する信号電荷除去手段が形成されている、ことを特徴とする。 A semiconductor device according to a second aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
The columnar semiconductor is
A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor;
A diode that accumulates signal charges generated by irradiation of electromagnetic energy waves from the second semiconductor region and the fourth semiconductor region is formed,
The diode functions as a gate, one of the first semiconductor region and the third semiconductor region functions as a source, the other functions as a drain, and a channel formed in the second semiconductor region. A junction field effect transistor is formed which is capable of taking out a current that flows and changes according to the amount of signal charge accumulated in the diode by a signal taking-out means,
The gate conductor layer functions as a gate, and a voltage is applied to the gate conductor layer by a MOS transistor in which one of the first semiconductor region and the fourth semiconductor region functions as a source and the other functions as a drain. Thus, signal charge removing means for removing the signal charge accumulated in the diode in the first semiconductor region is formed.
前記柱状半導体は、
前記第1の半導体領域上に形成された当該第1の半導体領域と反対導電型又は真性半導体からなる第2の半導体領域を備え、
前記ゲート導体層がゲートとして機能するとともに、前記第1の半導体領域及び前記第5の半導体領域の一方がソースとして機能し、他方がドレインとして機能するMOSトランジスタが形成されている、ことを特徴とする。 A semiconductor device according to a third aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
The columnar semiconductor is
A second semiconductor region formed on the first semiconductor region, the second semiconductor region comprising an opposite conductivity type or intrinsic semiconductor to the first semiconductor region;
The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain. To do.
前記柱状半導体は、
前記第1の半導体領域と第6の半導体領域との間に、前記第1の半導体領域と反対導電型又は真性半導体からなる第2の半導体領域を備え、
前記第2の半導体領域と、前記第6の半導体領域と、からダイオードが形成されている、ことを特徴とする。 A semiconductor device according to a fourth aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
The columnar semiconductor is
Between the first semiconductor region and the sixth semiconductor region, a second semiconductor region made of an opposite conductivity type or intrinsic semiconductor to the first semiconductor region is provided,
A diode is formed from the second semiconductor region and the sixth semiconductor region.
前記第1の半導体層上に複数の前記柱状半導体が形成されており、
前記複数の柱状半導体は、前記第1の半導体領域にアクセプタ不純物がドープされている複数の第1の柱状半導体と、前記第1の半導体領域にドナー不純物がドープされている複数の第2の柱状半導体とからなる、ことを特徴とする。 A semiconductor device according to a fifth aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
The plurality of columnar semiconductors include a plurality of first columnar semiconductors in which the first semiconductor region is doped with an acceptor impurity, and a plurality of second columnar semiconductors in which the first semiconductor region is doped with a donor impurity. It consists of a semiconductor.
前記第1の半導体層上に複数の前記柱状半導体が形成されており、
前記複数の柱状半導体における、複数の前記第1の半導体領域、及び、複数の前記導体層の内の両方、又は、一方が互いに接続されている、ことを特徴とする。 A semiconductor device according to a sixth aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
In the plurality of columnar semiconductors, both or one of the plurality of first semiconductor regions and the plurality of conductor layers are connected to each other.
前記第1の半導体層上に複数の前記柱状半導体が形成されており、
前記各柱状半導体は、
前記第1の半導体領域上に形成された当該第1の半導体領域と反対導電型の半導体又は真性半導体からなる第2の半導体領域と、
前記第2の半導体領域上に形成された第5の半導体領域と、
前記第2の半導体領域の外周部に形成された第3の絶縁層と、
前記第3の絶縁層の外周部に形成されたゲート導体層と、を備え、
前記ゲート導体層がゲートとして機能するとともに、前記第1の半導体領域及び前記第5の半導体領域の一方がソースとして機能し、他方がドレインとして機能するMOSトランジスタが形成され、
前記第1の半導体層は、前記複数の柱状半導体に亘って連続して繋がるように形成されているとともに、前記繋がるように形成された前記第1の半導体層は、絶縁層に形成されたコンタクトホールを介して、外部回路に接続するための配線層に接続されている、ことを特徴とする。 A semiconductor device according to a seventh aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
Each of the columnar semiconductors is
A second semiconductor region made of a semiconductor or an intrinsic semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region;
A fifth semiconductor region formed on the second semiconductor region;
A third insulating layer formed on the outer periphery of the second semiconductor region;
A gate conductor layer formed on the outer periphery of the third insulating layer,
The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
The first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer formed so as to be connected is a contact formed on an insulating layer. It is connected to a wiring layer for connecting to an external circuit through a hole.
前記第1の半導体層上に複数の前記柱状半導体が形成されており、
前記各柱状半導体は、
前記第1の半導体領域上に形成された当該第1の半導体領域と反対導電型の半導体又は真性半導体からなる第2の半導体領域と、
前記第2の半導体領域上に形成された第5の半導体領域と、
前記第2の半導体領域の外周部に形成された第3の絶縁層と、
前記第3の絶縁層の外周部に形成されたゲート導体層と、を備え、
前記ゲート導体層がゲートとして機能するとともに、前記第1の半導体領域及び前記第5の半導体領域の一方がソースとして機能し、他方がドレインとして機能するMOSトランジスタが形成され、
前記第1の半導体層は、前記複数の柱状半導体に亘って連続して繋がるように形成されているとともに、前記第1の半導体層は、絶縁層に形成されたコンタクトホールを介して、所定のトランジスタのゲートに接続するための配線層に接続されていることを特徴とする。 A semiconductor device according to an eighth aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
Each of the columnar semiconductors is
A second semiconductor region made of a semiconductor or an intrinsic semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region;
A fifth semiconductor region formed on the second semiconductor region;
A third insulating layer formed on the outer periphery of the second semiconductor region;
A gate conductor layer formed on the outer periphery of the third insulating layer,
The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
The first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer is connected to a predetermined hole via a contact hole formed in the insulating layer. It is connected to a wiring layer for connecting to the gate of the transistor.
図1A~図1Lに、本発明の第1実施形態に係る、固体撮像装置の製造方法を示す。
本実施形態に係る固体撮像装置の製造方法においては、図1Aに示されるように、P型シリコンからなる第1の半導体基板1の所定の深さに、高濃度水素イオン(H+)をイオンドープすることによって、第1の半導体基板1を上下の2つの部分に分離するための分離層2を形成する(非特許文献2参照)。また、第1の半導体基板1上に、熱酸化又はCVD(Chemical Vapor Deposition)法によって、絶縁膜である第1酸化シリコン層3を形成する。なお、第1の半導体基板1は、P型シリコンの代わりに、実質的に不純物を含まない真性半導体(i型シリコン)であってもよい。 (First embodiment)
1A to 1L show a method for manufacturing a solid-state imaging device according to the first embodiment of the present invention.
In the method for manufacturing a solid-state imaging device according to the present embodiment, as shown in FIG. 1A, high-concentration hydrogen ions (H + ) are ionized at a predetermined depth of the
そして、このP+型シリコン層13a、13bを画素選択金属配線14c、14dに電気的に接続する。以上の工程により、固体撮像装置における複数の画素が形成される。 Subsequently, as shown in FIG. 1L, the
Then, the P + type silicon layers 13a and 13b are electrically connected to the pixel
以下、図2を参照して、本発明の第2実施形態に係る、SGT(Surrounding Gate Transistor)を有する半導体装置の製造方法を説明する。
本実施形態では、第1実施形態の図1A~図1Lで示される工程において、図1A~図1Jで示される工程までは、図1Jにおいて信号線を構成するN+多結晶シリコン層5aを、SGTにおいてドレインとして機能するN+多結晶シリコン層55aに置き換えるものとする。第1実施形態(図1J参照)と同様に、N+多結晶シリコン層55aには金属層7が接合されており、N+多結晶シリコン層55aからのドナー不純物の熱拡散によってシリコン柱1a内にN+拡散層6aが形成されている。 (Second Embodiment)
Hereinafter, with reference to FIG. 2, the manufacturing method of the semiconductor device which has SGT (Surrounding Gate Transistor) based on 2nd Embodiment of this invention is demonstrated.
In the present embodiment, in the steps shown in FIGS. 1A to 1L of the first embodiment, until the steps shown in FIGS. 1A to 1J, the N +
以上により、第2半導体基板9上にNチャネル型SGTが形成される。ここで、N+拡散層6a、N+多結晶シリコン層55aは、Nチャネル型SGTにおいてソースまたはドレインとして機能する。 Subsequently, a
As a result, an N-channel SGT is formed on the
以下、図3A、図3Bを参照して、本発明の第3実施形態に係る、SGTを有する半導体装置の製造方法を説明する。本実施形態では、Nチャネル型SGTとPチャネル型SGTとを同一の半導体基板上に形成する。本実施形態及びその変形例における半導体装置の製造工程は、以下に特に説明する場合を除いて、第1実施形態と同様である。 (Third embodiment)
Hereinafter, with reference to FIG. 3A and FIG. 3B, the manufacturing method of the semiconductor device which has SGT based on 3rd Embodiment of this invention is demonstrated. In this embodiment, the N channel type SGT and the P channel type SGT are formed on the same semiconductor substrate. The manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
Nチャネル型SGT形成領域1nにおけるNチャネル型SGTは、第1実施形態の図1A~図1J、第2実施形態の図2に示される工程と同様にして形成する。 In the present embodiment, referring to FIGS. 3A and 3B, on the
The N-channel SGT in the N-channel
以上により、第2半導体基板9上にNチャネル型SGT及びPチャネル型SGTが形成される。 Subsequently, in the step shown in FIG. 3B, for example, by vapor deposition and etching so as to be electrically connected to the N +
Thus, the N channel type SGT and the P channel type SGT are formed on the
本実施形態によれば、第2半導体基板9上に、Nチャネル型SGTとPチャネル型SGTとを容易に形成することができる。 In the present embodiment, any one of the N +
According to this embodiment, the N-channel SGT and the P-channel SGT can be easily formed on the
以下、図4を参照して、本発明の第4実施形態に係る、複数のSGTを有する半導体装置の製造方法を説明する。
本実施形態では、第3実施形態と同様にして、Nチャネル型SGT形成領域1nにはNチャネル型SGT、Pチャネル型SGT形成領域1pにはPチャネル型SGTをそれぞれ形成する(図3A、図3B参照)。 (Fourth embodiment)
Hereinafter, with reference to FIG. 4, the manufacturing method of the semiconductor device which has several SGT based on 4th Embodiment of this invention is demonstrated.
In this embodiment, as in the third embodiment, an N-channel SGT is formed in the N-channel
以下、図5A~図5Cを参照して、本発明の第5実施形態に係る、半導体装置に電気抵抗を形成する方法を説明する。本実施形態及びその変形例における半導体装置の製造工程は、以下に特に説明する場合を除いて、第1実施形態と同様である。
本実施形態では、図1Bに示される、第1の半導体基板1上に形成された多結晶シリコン層5を用いることで、半導体装置の回路素子である電気抵抗を形成する。 (Fifth embodiment)
Hereinafter, a method for forming an electrical resistance in a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 5A to 5C. The manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
In this embodiment, an electrical resistance which is a circuit element of the semiconductor device is formed by using the
さらに、図5Cに示される変形例では、電気抵抗を構成する多結晶シリコン層23は、絶縁体である第1酸化シリコン層3の下方に形成されている。 In the present embodiment and the modification shown in FIG. 5C, referring to FIG. 4, a circuit element or metal wiring having SGT is formed on the first
Further, in the modification shown in FIG. 5C, the
以下、図6A~図6Cを参照して、本発明の第6実施形態に係る、半導体装置に容量を形成する方法を説明する。本実施形態における半導体装置の製造工程は、以下に特に説明する場合を除いて、第1実施形態と同様である。
本実施形態では、図1Bに示される、第1の半導体基板1上に形成された多結晶シリコン層5を用いることで、半導体装置の回路素子である容量を形成する。 (Sixth embodiment)
Hereinafter, a method of forming a capacitor in a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 6A to 6C. The manufacturing process of the semiconductor device according to the present embodiment is the same as that of the first embodiment, except as described below.
In this embodiment, a capacitor, which is a circuit element of a semiconductor device, is formed by using the
そして、図1Dに示される工程では、所定形状に成形された容量酸化シリコン層27上に、蒸着法又はCVD法によって、容量電極として機能する金属層28を形成する。この金属層28は、第1実施形態の金属層7と同層に形成する。 Subsequently, referring to FIG. 6B, the capacitor
In the step shown in FIG. 1D, a
以下、図7A、図7Bを参照して、本発明の第7実施形態に係る、半導体装置に容量を形成する方法を説明する。本実施形態における半導体装置の製造工程は、以下に特に説明する場合を除いて、第1実施形態と同様である。
本実施形態では、図1Bに示される、第1の半導体基板1上に形成された多結晶シリコン層5を用いることで、半導体装置の回路素子である容量を形成する。 (Seventh embodiment)
Hereinafter, with reference to FIGS. 7A and 7B, a method of forming a capacitor in a semiconductor device according to a seventh embodiment of the present invention will be described. The manufacturing process of the semiconductor device according to the present embodiment is the same as that of the first embodiment, except as described below.
In this embodiment, a capacitor, which is a circuit element of a semiconductor device, is formed by using the
以下、図8A~図8Cを参照して、本発明の第8実施形態に係る、半導体装置にダイオードを形成する方法を説明する。本実施形態及びその変形例における半導体装置の製造工程は、以下に特に説明する場合を除いて、第1実施形態と同様である。
本実施形態では、図1Bに示される、第1の半導体基板1上に形成された多結晶シリコン層5を用いることで、半導体装置の回路素子であるダイオードを形成する。 (Eighth embodiment)
Hereinafter, a method for forming a diode in a semiconductor device according to an eighth embodiment of the present invention will be described with reference to FIGS. 8A to 8C. The manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
In this embodiment, a diode which is a circuit element of a semiconductor device is formed by using the
以下、図9A~図9Cを参照して、本発明の第9実施形態に係る、SGTを用いたCMOSインバータ回路について説明する。
図9Aに、本実施形態によるSGTを用いたCMOSインバータ回路を示す。図9Aに示されるように、Pチャネル型MOSトランジスタ37aとNチャネル型MOSトランジスタ37bとが直列に接続されている。Pチャネル型MOSトランジスタ37aとNチャネル型MOSトランジスタ37bのゲート同士がゲート接続配線38を介して接続され、ゲート接続配線38は入力端子配線Viに接続されている。Pチャネル型MOSトランジスタ37aのソースは、電源端子配線Vddに接続されている。Pチャネル型MOSトランジスタ37aのドレインとNチャネル型トランジスタ37bのドレインとはドレイン接続配線39を介して出力端子配線Voに接続されるとともに、Nチャネル型MOSトランジスタ37bのソースはグランド電位となっているグランド端子配線Vssに接続されている。 (Ninth embodiment)
A CMOS inverter circuit using an SGT according to the ninth embodiment of the present invention will be described below with reference to FIGS. 9A to 9C.
FIG. 9A shows a CMOS inverter circuit using the SGT according to the present embodiment. As shown in FIG. 9A, a P-
図9Bに示されるように、コンタクトホール41c、シリコン柱40a、コンタクトホール41a、コンタクトホール41b、及びコンタクトホール41d、が直線状に並んで配置されている。 FIG. 9B shows a plan layout of a CMOS inverter circuit using this SGT.
As shown in FIG. 9B, the
以下、図10A~図10Cを参照して、本発明の第10実施形態に係る2段構造のCMOSインバータ回路について説明する。以下、上記第9実施形態と共通又は対応する符号で示される部分及び構造の説明は省略する。
図10Aに、本実施形態で用いる2段構造のCMOSインバータ回路を示す。
図10Aに示されるように、Pチャネル型MOSトランジスタ37a、37cと、Nチャネル型MOSトランジスタ37b、37dとが、それぞれ、1段目、2段目において直列に接続されている。1段目のPチャネル型MOSトランジスタ37aとNチャネル型MOSトランジスタ37bの各ゲートは、ゲート接続配線38aを介して入力端子配線Viに接続されている。2段目のPチャネル型MOSトランジスタ37cとNチャネル型MOSトランジスタ37dの各ゲートは、ゲート接続配線38bを介して1段目の出力端子配線Voに接続されている。1段目及び2段目のPチャネル型MOSトランジスタ37a、37cの各ドレインは、電源端子配線Vddに接続されている。1段目及び2段目のPチャネル型MOSトランジスタ37b、37dの各ソースは、グランド端子配線Vssに接続されている。 (10th Embodiment)
A two-stage CMOS inverter circuit according to a tenth embodiment of the present invention will be described below with reference to FIGS. 10A to 10C. Hereinafter, description of portions and structures indicated by reference numerals common or corresponding to those of the ninth embodiment will be omitted.
FIG. 10A shows a CMOS inverter circuit having a two-stage structure used in this embodiment.
As shown in FIG. 10A, P-
2段目において、Pチャネル型トランジスタ37cのドレインとNチャネル型トランジスタ37dのドレインとは、ドレイン接続配線39bを介して出力端子配線Voutに接続されている。 In the first stage, the drain of the P-
In the second stage, the drain of the P-
図10Bに示されるように、1段目のPチャネル型MOSトランジスタ37aを構成するシリコン柱40a及びNチャネル型MOSトランジスタ37bを構成するシリコン柱40bに形成されたゲート接続配線38a上にコンタクトホール41cが形成され、コンタクトホール41cは、入力端子配線Viと接続されている。ゲート接続配線38aは、Pチャネル型MOSトランジスタ37a及びNチャネル型MOSトランジスタ37bのゲート同士を接続する。 FIG. 10B shows a plan layout of this CMOS inverter circuit.
As shown in FIG. 10B, a
また、入力端子配線層Vi、電源端子配線層Vdd、グランド端子配線層Vss、出力端子配線層Voutは、互いに平行に配線されている。 A
The input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout are wired in parallel to each other.
また、入力端子配線層Vi、電源端子配線層Vdd、グランド端子配線層Vss、出力端子配線層Voutは互いに平行に配線されている(図10B参照)。 A
Further, the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout are wired in parallel to each other (see FIG. 10B).
以下、図11A、図11Bを参照して、本発明の第11実施形態に係る、半導体基板にマスク合わせマークを形成する方法を説明する。
図11Aで示される工程は、第1実施形態における図1Hで示される工程に対応するものである。その他の工程は、以下に特に説明する場合を除いて、第1実施形態と同様である。 (Eleventh embodiment)
Hereinafter, a method for forming a mask alignment mark on a semiconductor substrate according to an eleventh embodiment of the present invention will be described with reference to FIGS. 11A and 11B.
The process shown in FIG. 11A corresponds to the process shown in FIG. 1H in the first embodiment. The other steps are the same as those in the first embodiment except for the case specifically described below.
続いて、マスク合わせ孔50内における、マーク金属層49a、マーク多結晶シリコン層49b及び酸化シリコン層除去領域48の内のいずれか1つを基準となるマスク合わせマークとして、フォトマスクのマスク合わせを行う。
続いて、フォトレジストが形成された領域にフォトマスクを重ねて光を照射し、回路を転写する。 By etching the
Subsequently, the mask alignment of the photomask is performed using any one of the
Subsequently, a photomask is overlaid on the region where the photoresist is formed, and light is irradiated to transfer the circuit.
その後、CMPによって、そのSiO2膜及び第1の半導体基板1の表面を平坦化する。このマスク合わせ孔50のSiO2膜による埋め込み工程は、図1Iを参照して、接合電界効果トランジスタが形成されるシリコン柱1aが形成される前に行われる。 As shown in FIG. 12, a transparent insulating
Thereafter, the SiO 2 film and the surface of the
以下、図13A、図13Bを参照して、本発明の第12実施形態に係る半導体装置の製造方法を説明する。
図13Aは、第1実施形態における図1Bに示される工程に対応するものである。その他の工程は、以下に特に説明する場合を除いて、第1実施形態と同様である。 (Twelfth embodiment)
A method for manufacturing a semiconductor device according to the twelfth embodiment of the present invention will be described below with reference to FIGS. 13A and 13B.
FIG. 13A corresponds to the step shown in FIG. 1B in the first embodiment. The other steps are the same as those in the first embodiment except for the case specifically described below.
以下、図14A、図14B、図15A、図15Bを参照して、本発明の第13実施形態に係る半導体装置の製造方法を説明する。 (13th Embodiment)
Hereinafter, a method for fabricating a semiconductor device according to a thirteenth embodiment of the present invention will be described with reference to FIGS. 14A, 14B, 15A, and 15B.
(1)図14Bでは、N+多結晶シリコン層5aa、金属層7aaが平坦に形成されているのに対し、図1Kでは、N+多結晶シリコン層5a、金属層7が上に凸状に形成されていること。
(2)図14Bでは、第1酸化シリコン層3aが囲むN+拡散層6aaが逆台形状に形成されているのに対し、図1Kでは、N+拡散層5aは第1酸シリコン層3の側面に沿って台形状に形成されていること。
(3)図14Bでは、ゲート導体層11aa、11bbが第1酸化シリコン層3aに接しているのに対し、図1Kでは、ゲート導体層11a、11bは第1酸化シリコン層3と離間していること。 Thereafter, the pixel structure shown in FIG. 14B is obtained through steps similar to those shown in FIGS. 1D to 1K. Comparing FIG. 1K and FIG. 14B, FIG. 14B differs from FIG. 1K in the following three points.
(1) In FIG. 14B, the N + polycrystalline silicon layer 5aa and the metal layer 7aa are formed flat, whereas in FIG. 1K, the N +
(2) In FIG. 14B, the N + diffusion layer 6aa surrounded by the first
(3) In FIG. 14B, the gate conductor layers 11aa and 11bb are in contact with the first
(1)N+拡散層6aaは、N+多結晶シリコン層5aaからの熱拡散により形成され、熱拡散の熱処理の前は、ドナー不純物が存在しない層であり、第12実施形態の図13Bにおける多結晶シリコン層111と同様な機能を有するようにできる。このため、多結晶シリコン層111を用いないでも、ゲート導体層11aa、11bbの下部位置に拡散層端が位置するN+拡散層6aaを形成することができる。
(2)N+拡散層6aaに位置合わせしてシリコン柱1aをエッチングで形成する場合、シリコン柱1aの側面がN+拡散層6aaの内側に位置ずれしても、第1酸化シリコン層3aは、厚みのあるN+拡散層であるか、または内側に萎んで形成されているため、シリコンエッチングが金属層7aaまで到達し難くなる(図1Kでは、シリコン柱1aがN+多結晶シリコン層5aから位置ずれすると、N+多結晶シリコン層5aが直接に露出するため、N+多結晶シリコン層5aと、その下方に存在する金属層7まで容易にエッチングされる)。
(3)ゲート導体層11aa、11bbと第1酸化シリコン層3aとの間に隙間を形成する必要がないため、ゲート導体層11aa、11bbと、第1酸化シリコン3a上でのゲート導体層配線の形成が容易となる。即ち、図1Kでは、リーク電流低減のため、N+拡散層6aとP層シリコン層30とのPN接合の界面の位置を、シリコン柱1aの内部に形成する必要があるので、第1酸化シリコン層3とゲート導体層11a,11bとは離間させねばならない。 Due to the differences (1) to (3), according to the present embodiment, the following advantages can be obtained. That is,
(1) The N + diffusion layer 6aa is formed by thermal diffusion from the N + polycrystalline silicon layer 5aa, and is a layer in which donor impurities are not present before the thermal diffusion heat treatment, and in FIG. 13B of the twelfth embodiment A function similar to that of the
(2) When the
(3) Since it is not necessary to form a gap between the gate conductor layers 11aa and 11bb and the first
(1)図15Bでは、第1酸化シリコン層3aが囲むN+拡散層6aaが、図14Bと同様に逆台形状に形成されているのに対し、図1Kでは、N+拡散層5aは第1酸シリコン層3の側面に沿って台形状に形成されていること。
(2)図15Bでは、ゲート導体層11aa,11bbが第1酸化シリコン層3bに接しているのに対し、図1Kでは、ゲート導体層11a,11bは第1酸化シリコン層3と離間していること。 Thereafter, the pixel structure shown in FIG. 15B is obtained through the steps shown in FIGS. 1D to 1K. Comparing FIG. 1K and FIG. 15B, FIG. 15B differs from FIG. 1K in the following two points.
(1) In FIG. 15B, the N + diffusion layer 6aa surrounded by the first
(2) In FIG. 15B, the gate conductor layers 11aa and 11bb are in contact with the first
(1)図14Bと同様に、N+拡散層6bbはN+多結晶シリコン層5bbからの熱拡散により形成され、熱拡散で熱処理する以前は、ドナー不純物がない層であり、第12実施形態を説明する図13Bにおける多結晶シリコン層111と同様な機能を有するようにできる。このため、多結晶シリコン層111を用いないでも、ゲート導体層11aa,11bbの下方に拡散層の端部が位置するN+拡散層6bbを形成することができる。
(2)図14Bと同様に、N+拡散層6bbに位置合わせしてシリコン柱1aをエッチング形成する場合、シリコン柱1aの側面がN+拡散層6bbの内側に位置ずれしても、第1酸化シリコン層3bは、厚みのあるN+拡散層6bbであるか、または内側に萎んで形成されているため、シリコンエッチングが金属層7aaまで到達し難くなっている。
(3)図14Bと同様に、ゲート導体層11aa,11bbと第1酸化シリコン層3bとの間に隙間を形成する必要がないため、ゲート導体層11aa,11bbと、第1酸化シリコン3bの上方でのゲート導体層配線の形成が容易化される。 Due to the difference between (1) and (2), the present embodiment has the following advantages. That is,
(1) Similar to FIG. 14B, the N + diffusion layer 6bb is formed by thermal diffusion from the N + polycrystalline silicon layer 5bb, and is a layer without donor impurities before heat treatment by thermal diffusion. It can be made to have the same function as the
(2) Similarly to FIG. 14B, when the
(3) Similar to FIG. 14B, it is not necessary to form a gap between the gate conductor layers 11aa and 11bb and the first
以下、図16A~図16Cを参照して、本発明の第14実施形態に係る半導体装置の製造方法を説明する。本実施形態では、シリコン柱1aの底部に2箇所以上の不純物領域を形成する点に特徴がある。 (14th Embodiment)
A method for manufacturing a semiconductor device according to a fourteenth embodiment of the present invention will be described below with reference to FIGS. 16A to 16C. The present embodiment is characterized in that two or more impurity regions are formed at the bottom of the
上記実施形態では、第1の半導体基板1はP型の導電型とした。これに限られず、第1の半導体基板1は、真性半導体であるi型(イントリンシック型)でもよい。また、第1の半導体基板1に形成する回路素子に応じて、N型の導電型とすることもできる。 The present invention is not limited to the embodiments described in the first to fourteenth embodiments, and various modifications can be made.
In the above embodiment, the
1a、1b、40a、40b、40c、40d シリコン柱
1n Nチャネル型SGT形成領域
1p Pチャネル型SGT形成領域
2 分離層
3、3a、3b、29、101a、101b 第1酸化シリコン層
4 孔
5、23 多結晶シリコン層
5a、5b、5aa、5b2、5bb2、23a、23b、51、55a、104 N+多結晶シリコン層
5b1、5bb1、55b P+多結晶シリコン層
6a、6aa、6ab、6b2 N+拡散層
6b、102、6b1 P+拡散層
7、7a、7b、7b1,7b2、7aa、7bb、26a、26b、28、32、59、105 金属層
7a、7b、7aa、7bb 第1接続用金属層
8 第2酸化シリコン層
9 第2半導体基板
10a、10b 第3酸化シリコン層
11a、11b、11c、11d、16a、16b、16c、16d、16aa、16ab、16ba、16bb、54a、54b ゲート導体層
12a、12b、12c、12d N型シリコン層
13a、13b、17b、31、56 P+型シリコン層
14a、14b、14c、14d 画素選択金属配線層
15a、15b、15c、15d、71 ゲート絶縁層
17a、51 N+型シリコン層
18a、18b、22a、22b、22c、24a、24b、26a、26b、35、42、109 金属配線層
20、29、33、43、45、62、101a、101b、103、107 酸化シリコン層
21c、34、41a、41b、41c、41d、41e、41f、75、108 コンタクトホール
27 容量酸化シリコン層
30、52 P型シリコン層
30a、58a、58b N型シリコン層
30b i型シリコン層
37a、37c Pチャネル型MOSトランジスタ
37b、37d Nチャネル型MOSトランジスタ
38、38a、38b ゲート接続配線
39、39a、39b ドレイン接続配線
47a マスク合わせマーク形成領域
47b 回路形成領域
48 酸化シリコン層除去領域
49a マーク金属層
49b マーク多結晶シリコン層
50 マスク合わせ孔
50a 透明絶縁層
53a、53b 絶縁膜
57a、57b 画素選択線
60 シリコン基板
61、64 半導体基板
66 埋め込み酸化膜基板
67 平面状シリコン膜
68 PMOS柱状シリコン層
69、70 P+型シリコン拡散層
71 ゲート絶縁層
72 ゲート電極
73 窒化シリコン(SiN)膜
74 酸化シリコン(SiO2)膜
76 ソース金属配線
100 容量形成領域
106 (ドナー不純物がドープされた)N+多結晶シリコン層
110 柱状半導体
111 (ドナー不純物又はアクセプタ不純物がドープされていない)多結晶シリコン層
Vi 入力端子配線(層)
Vdd 電源端子配線(層)
Vss グランド端子配線(層)
Vo、Vout 出力端子配線(層) DESCRIPTION OF SYMBOLS 1 1st semiconductor substrate 1a, 1b, 40a, 40b, 40c, 40d Silicon pillar 1n N channel type SGT formation region 1p P channel type SGT formation region 2 Separation layer 3, 3a, 3b, 29, 101a, 101b 1st oxidation Silicon layer 4 Hole 5, 23 Polycrystalline silicon layer 5a, 5b, 5aa, 5b2, 5bb2, 23a, 23b, 51, 55a, 104 N + Polycrystalline silicon layer 5b1, 5bb1, 55b P + Polycrystalline silicon layer 6a, 6aa 6ab, 6b2 N + diffusion layer 6b, 102, 6b1 P + diffusion layer 7, 7a, 7b, 7b1, 7b2, 7aa, 7bb, 26a, 26b, 28, 32, 59, 105 Metal layers 7a, 7b, 7aa, 7bb Metal layer for first connection 8 Second silicon oxide layer 9 Second semiconductor substrate 10a, 10b Third silicon oxide layer 11a 11b, 11c, 11d, 16a, 16b, 16c, 16d, 16aa, 16ab, 16ba, 16bb, 54a, 54b the gate conductor layer 12a, 12b, 12c, 12d N-type silicon layer 13a, 13b, 17b, 31,56 P + Type silicon layer 14a, 14b, 14c, 14d Pixel selection metal wiring layer 15a, 15b, 15c, 15d, 71 Gate insulating layer 17a, 51 N + type silicon layer 18a, 18b, 22a, 22b, 22c, 24a, 24b, 26a , 26b, 35, 42, 109 Metal wiring layer 20, 29, 33, 43, 45, 62, 101a, 101b, 103, 107 Silicon oxide layer 21c, 34, 41a, 41b, 41c, 41d, 41e, 41f, 75 108 Contact hole 27 Capacitance silicon oxide layer 30, 52 P type Recon layer 30a, 58a, 58b N-type silicon layer 30b i-type silicon layer 37a, 37c P-channel MOS transistor 37b, 37d N-channel MOS transistor 38, 38a, 38b Gate connection wiring 39, 39a, 39b Drain connection wiring 47a Mask Alignment mark formation region 47b Circuit formation region 48 Silicon oxide layer removal region 49a Mark metal layer 49b Mark polycrystalline silicon layer 50 Mask alignment hole 50a Transparent insulating layer 53a, 53b Insulating film 57a, 57b Pixel selection line 60 Silicon substrate 61, 64 Semiconductor substrate 66 buried oxide layer substrate 67 planar silicon film 68 PMOS pillar-shaped silicon layer 69, 70 P + -type silicon diffusion layer 71 gate insulating layer 72 a gate electrode 73, a silicon nitride (SiN) film 74 of silicon oxide SiO 2) film 76 source metal wiring 100 capacitor forming region 106 (donor impurities are doped) N + polycrystalline silicon layer 110 columnar semiconductor 111 (donor impurities or acceptor impurities are not doped) polycrystalline silicon layer Vi input terminal Wiring (layer)
Vdd Power supply terminal wiring (layer)
Vss ground terminal wiring (layer)
Vo, Vout Output terminal wiring (layer)
Claims (20)
- 半導体基板上の所定領域に第1の絶縁層を形成し、前記所定領域上の第1の絶縁層を除去することで、絶縁層除去領域を形成する第1絶縁層形成・除去工程、または、前記所定領域の周辺において、前記半導体基板を厚さ方向に一部除去し、当該半導体基板を除去した半導体基板除去領域に第1の絶縁層を形成する第2絶縁層形成・除去工程と、
少なくとも前記所定の領域を覆うように、前記半導体基板上にドナー不純物又はアクセプタ不純物を含む第1の半導体層を形成する第1半導体層形成工程と、
前記第1の半導体層上に導体層を形成する導体層形成工程と、
前記導体層及び前記第1の半導体層を所定の形状に成形する成形工程と、
前記所定の形状に成形した導体層及び第1の半導体層を覆うように、第2の絶縁層を形成する第1絶縁層形成工程と、
前記第2の絶縁層の表面を平坦化する平坦化工程と、
前記平坦化された前記第2の絶縁層の表面に、基板を接着する接着工程と、
前記半導体基板を所定の厚さまで薄くする薄膜化工程と、
前記第1の半導体層上に、前記半導体基板から柱状構造を有する柱状半導体を形成する柱状半導体形成工程と、
前記柱状半導体に回路素子を形成する回路素子形成工程と、を備え、
少なくとも前記第1半導体層形成工程以後に、前記ドナー不純物又はアクセプタ不純物を含む前記第1の半導体層から当該不純物を拡散させることで前記柱状半導体に第1の半導体領域を形成する第1半導体領域形成工程をさらに備える、
ことを特徴とする半導体装置の製造方法。 Forming a first insulating layer in a predetermined region on the semiconductor substrate, and removing the first insulating layer on the predetermined region to form an insulating layer removal region; or A second insulating layer forming / removing step of partially removing the semiconductor substrate in a thickness direction around the predetermined region and forming a first insulating layer in the semiconductor substrate removing region from which the semiconductor substrate has been removed;
A first semiconductor layer forming step of forming a first semiconductor layer containing a donor impurity or an acceptor impurity on the semiconductor substrate so as to cover at least the predetermined region;
A conductor layer forming step of forming a conductor layer on the first semiconductor layer;
A molding step of molding the conductor layer and the first semiconductor layer into a predetermined shape;
A first insulating layer forming step of forming a second insulating layer so as to cover the conductor layer and the first semiconductor layer formed in the predetermined shape;
A planarization step of planarizing the surface of the second insulating layer;
An adhesion step of adhering a substrate to the flattened surface of the second insulating layer;
A thinning process for thinning the semiconductor substrate to a predetermined thickness;
Forming a columnar semiconductor having a columnar structure from the semiconductor substrate on the first semiconductor layer; and
A circuit element forming step of forming a circuit element on the columnar semiconductor,
Forming a first semiconductor region in the columnar semiconductor by diffusing the impurity from the first semiconductor layer containing the donor impurity or acceptor impurity at least after the first semiconductor layer forming step The process further includes
A method for manufacturing a semiconductor device. - 前記回路素子形成工程は、
前記柱状半導体の外周部に第3の絶縁層を形成するとともに、前記第3の絶縁層の外周部にゲート導体層を形成する工程と、
前記ゲート導体層の上方部位かつ前記柱状半導体の表層部に、前記第1の半導体領域と同一導電型である第4の半導体領域を形成する工程と、
前記柱状半導体において、前記第3の絶縁層の上方部位に、前記第1の半導体領域と反対導電型の第3の半導体領域を形成する工程と、を含む、ことを特徴とする請求項1に記載の半導体装置の製造方法。 The circuit element forming step includes
Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer;
Forming a fourth semiconductor region having the same conductivity type as the first semiconductor region in a portion above the gate conductor layer and in a surface layer portion of the columnar semiconductor;
Forming a third semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the third insulating layer in the columnar semiconductor. The manufacturing method of the semiconductor device of description. - 前記回路素子形成工程は、
前記柱状半導体の外周部に第3の絶縁層を形成するとともに、前記第3の絶縁層の外周部にゲート導体層を形成する工程と、
前記柱状半導体における前記第3の絶縁層の上方部位に、前記第1の半導体領域と同一導電型の第5の半導体領域を形成する工程と、を含む、ことを特徴とする請求項1に記載の半導体装置の製造方法。 The circuit element forming step includes
Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer;
Forming a fifth semiconductor region having the same conductivity type as that of the first semiconductor region at a position above the third insulating layer in the columnar semiconductor. Semiconductor device manufacturing method. - 前記回路素子形成工程は、
前記柱状半導体の上方部位に、前記第1の半導体領域と反対導電型の第6の半導体領域を形成する工程を含む、ことを特徴とする請求項1に記載の半導体装置の製造方法。 The circuit element forming step includes
2. The method of manufacturing a semiconductor device according to claim 1, comprising a step of forming a sixth semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the columnar semiconductor. - 前記第1半導体層形成工程は、前記第1の半導体層と同層に、電気抵抗として機能する第2の半導体層を形成する工程を含む、ことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。 5. The method according to claim 1, wherein the first semiconductor layer forming step includes a step of forming a second semiconductor layer functioning as an electric resistance in the same layer as the first semiconductor layer. 2. A method for manufacturing a semiconductor device according to item 1.
- 前記第1半導体層形成工程は、容量電極として機能する前記第1の半導体層上の所定の領域に容量絶縁膜として機能する絶縁膜を形成する工程を含み、
前記導体層形成工程は、前記絶縁膜上に、前記第1の半導体層と共に容量電極として機能する導体層を形成する工程を含む、ことを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置の製造方法。 The first semiconductor layer forming step includes a step of forming an insulating film functioning as a capacitor insulating film in a predetermined region on the first semiconductor layer functioning as a capacitor electrode;
The said conductor layer formation process includes the process of forming the conductor layer which functions as a capacity | capacitance electrode with the said 1st semiconductor layer on the said insulating film, The any one of Claim 1 thru | or 5 characterized by the above-mentioned. The manufacturing method of the semiconductor device of description. - 前記第1絶縁層形成・除去工程は、前記半導体基板上に、第1の絶縁層と共に第4の絶縁層を形成するとともに、予め設定した容量形成領域に、前記第4の絶縁層よりも厚さが薄く、容量絶縁膜として機能する第5の絶縁層を形成する工程を含み、
前記導体層形成工程は、前記第5の絶縁層上に、容量電極として機能する導体層を形成する工程を含み、
前記第1及び第2絶縁層形成・除去工程は、前記容量形成領域に、ドナー不純物又はアクセプタ不純物を有し、容量電極として機能する不純物層を形成する容量形成工程を含む、ことを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置の製造方法。 In the first insulating layer forming / removing step, a fourth insulating layer is formed together with the first insulating layer on the semiconductor substrate, and the capacitor formation region set in advance is thicker than the fourth insulating layer. Forming a fifth insulating layer that is thin and functions as a capacitive insulating film,
The conductor layer forming step includes a step of forming a conductor layer functioning as a capacitive electrode on the fifth insulating layer,
The first and second insulating layer forming / removing steps include a capacitor forming step of forming an impurity layer having a donor impurity or an acceptor impurity and functioning as a capacitor electrode in the capacitor forming region. The method for manufacturing a semiconductor device according to claim 1. - 前記半導体基板上にマスク合わせマーク形成領域を設定するマスク合わせマーク形成領域設定工程と、
前記マスク合わせマーク形成領域に、マスク合わせ孔を形成し、前記絶縁層除去領域、前記第1の絶縁層及び前記導体層の少なくとも一つを露出させる工程と、
前記マスク合わせ孔を通して、前記絶縁層除去領域、前記第1の絶縁層及び前記導体層の内の少なくとも一つからなるマスク合わせマークを形成するマスク合わせマーク形成工程と、
前記マスク合わせマークを基準として、フォトマスクのマスク合わせを行うマスク合わせ工程と、をさらに備える、ことを特徴とする請求項1乃至7のいずれか1項に記載の半導体装置の製造方法。 A mask alignment mark formation region setting step for setting a mask alignment mark formation region on the semiconductor substrate;
Forming a mask alignment hole in the mask alignment mark formation region, exposing at least one of the insulating layer removal region, the first insulating layer, and the conductor layer;
A mask alignment mark forming step for forming a mask alignment mark made of at least one of the insulating layer removal region, the first insulating layer, and the conductor layer through the mask alignment hole;
The method of manufacturing a semiconductor device according to claim 1, further comprising: a mask alignment step of performing mask alignment of a photomask with the mask alignment mark as a reference. - 前記マスク合わせ孔に透明絶縁体を埋め込む工程をさらに備え、
前記マスク合わせマーク形成工程では、前記透明絶縁体を通して、前記絶縁層除去領域、前記第1の絶縁層及び前記導体層の内の少なくとも一つからなるマスク合わせマークを形成し、
前記マスク合わせ工程では、前記マスク合わせマークを基準として、フォトマスクのマスク合わせを行う、ことを特徴とする請求項8に記載の半導体装置の製造方法。 A step of embedding a transparent insulator in the mask alignment hole;
In the mask alignment mark forming step, a mask alignment mark comprising at least one of the insulating layer removal region, the first insulating layer and the conductor layer is formed through the transparent insulator,
9. The method of manufacturing a semiconductor device according to claim 8, wherein in the mask alignment step, mask alignment of a photomask is performed with reference to the mask alignment mark. - 前記第1または第2絶縁層形成・除去工程と、前記第1半導体層形成工程との間に、前記絶縁層除去領域を覆うように、ドナー不純物及びアクセプタ不純物がドープされていない第2の半導体層を形成する工程をさらに備える、ことを特徴とする請求項1乃至9のいずれか1項に記載の半導体装置の製造方法。 A second semiconductor in which donor impurities and acceptor impurities are not doped so as to cover the insulating layer removal region between the first or second insulating layer forming / removing step and the first semiconductor layer forming step. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a layer.
- 請求項2に記載の半導体装置の製造方法によって製造される半導体装置であって、
前記柱状半導体は、
前記第1の半導体領域上に形成された当該第1の半導体領域と反対導電型の半導体又は真性半導体からなる第2の半導体領域を備え、
前記第2の半導体領域と前記第4の半導体領域とから電磁エネルギー波の照射により発生する信号電荷を蓄積するダイオードが形成され、
前記ダイオードがゲートとして機能し、前記第1の半導体領域と前記第3の半導体領域のいずれか一方がソース、他方がドレインとしてそれぞれ機能し、かつ、前記第2の半導体領域に形成されたチャネルを流れるとともに前記ダイオードに蓄積された信号電荷量に応じて変化する電流を信号取り出し手段によって取り出し可能とされた接合電界効果トランジスタが形成され、
前記ゲート導体層がゲートとして機能するとともに、前記第1の半導体領域及び前記第4の半導体領域の一方がソースとして機能し、他方がドレインとして機能するMOSトランジスタによって、前記ゲート導体層に電圧が印加されることで、前記ダイオードに蓄積された信号電荷を前記第1の半導体領域に除去する信号電荷除去手段が形成されている、ことを特徴とする半導体装置。 A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 2,
The columnar semiconductor is
A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor;
A diode that accumulates signal charges generated by irradiation of electromagnetic energy waves from the second semiconductor region and the fourth semiconductor region is formed,
The diode functions as a gate, one of the first semiconductor region and the third semiconductor region functions as a source, the other functions as a drain, and a channel formed in the second semiconductor region. A junction field effect transistor is formed which is capable of taking out a current that flows and changes according to the amount of signal charge accumulated in the diode by a signal taking-out means,
The gate conductor layer functions as a gate, and a voltage is applied to the gate conductor layer by a MOS transistor in which one of the first semiconductor region and the fourth semiconductor region functions as a source and the other functions as a drain. Thus, a signal charge removing means for removing signal charges accumulated in the diode in the first semiconductor region is formed. - 請求項3に記載の半導体装置の製造方法によって製造される半導体装置であって、
前記柱状半導体は、
前記第1の半導体領域上に形成された当該第1の半導体領域と反対導電型又は真性半導体からなる第2の半導体領域を備え、
前記ゲート導体層がゲートとして機能するとともに、前記第1の半導体領域及び前記第5の半導体領域の一方がソースとして機能し、他方がドレインとして機能するMOSトランジスタが形成されている、ことを特徴とする半導体装置。 A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 3,
The columnar semiconductor is
A second semiconductor region formed on the first semiconductor region, the second semiconductor region comprising an opposite conductivity type or intrinsic semiconductor to the first semiconductor region;
The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain. Semiconductor device. - 請求項4に記載の半導体装置の製造方法によって製造される半導体装置であって、
前記柱状半導体は、
前記第1の半導体領域と第6の半導体領域との間に、前記第1の半導体領域と反対導電型又は真性半導体からなる第2の半導体領域を備え、
前記第2の半導体領域と、前記第6の半導体領域と、からダイオードが形成されている、ことを特徴とする半導体装置。 A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 4,
The columnar semiconductor is
Between the first semiconductor region and the sixth semiconductor region, a second semiconductor region made of an opposite conductivity type or intrinsic semiconductor to the first semiconductor region is provided,
2. A semiconductor device, wherein a diode is formed from the second semiconductor region and the sixth semiconductor region. - 請求項1又は3に記載の半導体装置の製造方法によって製造される半導体装置であって、
前記第1の半導体層上に複数の前記柱状半導体が形成されており、
前記複数の柱状半導体は、前記第1の半導体領域にアクセプタ不純物がドープされている複数の第1の柱状半導体と、前記第1の半導体領域にドナー不純物がドープされている複数の第2の柱状半導体とからなる、ことを特徴とする半導体装置。 A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1 or 3,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
The plurality of columnar semiconductors include a plurality of first columnar semiconductors in which the first semiconductor region is doped with an acceptor impurity, and a plurality of second columnar semiconductors in which the first semiconductor region is doped with a donor impurity. A semiconductor device comprising a semiconductor. - 請求項1乃至3のいずれか1項に記載の半導体装置の製造方法によって製造される半導体装置であって、
前記第1の半導体層上に複数の前記柱状半導体が形成されており、
前記複数の柱状半導体における、複数の前記第1の半導体領域、及び、複数の前記導体層の内の両方、又は、一方が互いに接続されている、ことを特徴とする半導体装置。 A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
In the plurality of columnar semiconductors, both or one of the plurality of first semiconductor regions and the plurality of conductor layers are connected to each other. - 請求項3に記載の半導体装置の製造方法によって製造される半導体装置であって、
前記第1の半導体層上に複数の前記柱状半導体が形成されており、
前記各柱状半導体は、
前記第1の半導体領域上に形成された当該第1の半導体領域と反対導電型の半導体又は真性半導体からなる第2の半導体領域と、
前記第2の半導体領域上に形成された第5の半導体領域と、
前記第2の半導体領域の外周部に形成された第3の絶縁層と、
前記第3の絶縁層の外周部に形成されたゲート導体層と、を備え、
前記ゲート導体層がゲートとして機能するとともに、前記第1の半導体領域及び前記第5の半導体領域の一方がソースとして機能し、他方がドレインとして機能するMOSトランジスタが形成され、
前記第1の半導体層は、前記複数の柱状半導体に亘って連続して繋がるように形成されているとともに、前記繋がるように形成された前記第1の半導体層は、絶縁層に形成されたコンタクトホールを介して、外部回路に接続するための配線層に接続されている、ことを特徴とする半導体装置。 A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 3,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
Each of the columnar semiconductors is
A second semiconductor region made of a semiconductor or an intrinsic semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region;
A fifth semiconductor region formed on the second semiconductor region;
A third insulating layer formed on the outer periphery of the second semiconductor region;
A gate conductor layer formed on the outer periphery of the third insulating layer,
The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
The first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer formed so as to be connected is a contact formed on an insulating layer. A semiconductor device which is connected to a wiring layer for connecting to an external circuit through a hole. - 請求項3に記載の半導体装置の製造方法によって製造される半導体装置であって、
前記第1の半導体層上に複数の前記柱状半導体が形成されており、
前記各柱状半導体は、
前記第1の半導体領域上に形成された当該第1の半導体領域と反対導電型の半導体又は真性半導体からなる第2の半導体領域と、
前記第2の半導体領域上に形成された第5の半導体領域と、
前記第2の半導体領域の外周部に形成された第3の絶縁層と、
前記第3の絶縁層の外周部に形成されたゲート導体層と、を備え、
前記ゲート導体層がゲートとして機能するとともに、前記第1の半導体領域及び前記第5の半導体領域の一方がソースとして機能し、他方がドレインとして機能するMOSトランジスタが形成され、
前記第1の半導体層は、前記複数の柱状半導体に亘って連続して繋がるように形成されているとともに、前記第1の半導体層は、絶縁層に形成されたコンタクトホールを介して、所定のトランジスタのゲートに接続するための配線層に接続されている、ことを特徴とする半導体装置。 A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 3,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
Each of the columnar semiconductors is
A second semiconductor region made of a semiconductor or an intrinsic semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region;
A fifth semiconductor region formed on the second semiconductor region;
A third insulating layer formed on the outer periphery of the second semiconductor region;
A gate conductor layer formed on the outer periphery of the third insulating layer,
The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
The first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer is connected to a predetermined hole via a contact hole formed in the insulating layer. A semiconductor device, wherein the semiconductor device is connected to a wiring layer for connecting to a gate of a transistor. - 前記第2絶縁層形成・除去工程は、前記柱状半導体を形成する領域の周辺の前記半導体基板をエッチングする半導体基板エッチング工程と、
前記エッチングされた領域の前記半導体基板上に、前記第1の絶縁層を形成する工程と、
前記エッチングにより露出した前記半導体基板と、当該露出した半導体基板の周辺に位置する前記第1の絶縁層上に、前記第1の半導体層を形成する工程と、を含む、
ことを特徴とする請求項1に記載の半導体装置の製造方法。 The second insulating layer forming / removing step includes a semiconductor substrate etching step of etching the semiconductor substrate around a region where the columnar semiconductor is formed,
Forming the first insulating layer on the semiconductor substrate in the etched region;
Forming the first semiconductor layer on the semiconductor substrate exposed by the etching and on the first insulating layer located around the exposed semiconductor substrate;
The method of manufacturing a semiconductor device according to claim 1. - 前記第2絶縁層形成・除去工程は、前記柱状半導体を形成する領域の前記半導体基板の周辺の領域を選択的に酸化して前記第1の絶縁層としての選択酸化層を形成する工程を含む、
ことを特徴とする請求項1に記載の半導体装置の製造方法。 The second insulating layer forming / removing step includes a step of selectively oxidizing a peripheral region of the semiconductor substrate in a region where the columnar semiconductor is formed to form a selective oxide layer as the first insulating layer. ,
The method of manufacturing a semiconductor device according to claim 1. - 前記柱状半導体を形成する領域における前記半導体基板上に、少なくとも2つ以上の、互いに分離された前記第1の絶縁層を形成する領域を形成する工程と、
前記互いに分離された領域における前記第1の絶縁層で囲まれ、かつ、露出した前記半導体基板の表面上に、互いに分離され、ドナーまたはアクセプタがドープされた複数の前記第1の半導体層と、前記第1の半導体層に接続された前記導体層と、を形成する工程を含む、
ことを特徴とする請求項1に記載の半導体装置の製造方法。 Forming at least two or more regions for forming the first insulating layers separated from each other on the semiconductor substrate in the region for forming the columnar semiconductor;
A plurality of first semiconductor layers that are surrounded by the first insulating layer in the regions isolated from each other and that are separated from each other and doped with donors or acceptors on the exposed surface of the semiconductor substrate; Forming the conductor layer connected to the first semiconductor layer,
The method of manufacturing a semiconductor device according to claim 1.
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