WO2012120653A1 - Production method for semiconductor device and semiconductor device - Google Patents

Production method for semiconductor device and semiconductor device Download PDF

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Publication number
WO2012120653A1
WO2012120653A1 PCT/JP2011/055408 JP2011055408W WO2012120653A1 WO 2012120653 A1 WO2012120653 A1 WO 2012120653A1 JP 2011055408 W JP2011055408 W JP 2011055408W WO 2012120653 A1 WO2012120653 A1 WO 2012120653A1
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Prior art keywords
semiconductor
layer
region
insulating layer
forming
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PCT/JP2011/055408
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French (fr)
Japanese (ja)
Inventor
舛岡　富士雄
原田　望
Original Assignee
ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
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Application filed by ユニサンティス エレクトロニクス シンガポール プライベート リミテッド filed Critical ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
Priority to PCT/JP2011/055408 priority Critical patent/WO2012120653A1/en
Priority to PCT/JP2012/052777 priority patent/WO2012120951A1/en
Priority to JP2012521405A priority patent/JP5114608B2/en
Priority to CN2012800004124A priority patent/CN102792452A/en
Priority to KR1020127015784A priority patent/KR101350577B1/en
Priority to TW101107287A priority patent/TW201242003A/en
Publication of WO2012120653A1 publication Critical patent/WO2012120653A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a transistor in which a channel region is formed in a semiconductor having a columnar structure, and the semiconductor device.
  • Solid-state imaging devices such as CCD and CMOS type are widely used for video cameras, stale cameras and the like. Further, there is a demand for improved performance such as higher resolution, higher speed operation, and higher sensitivity of the solid-state imaging device.
  • a solid-state imaging device in which one pixel is configured in one columnar semiconductor 110 is known (see, for example, Patent Document 1).
  • an N + type silicon layer 51 that functions as a signal line of a solid-state imaging device is formed on a semiconductor substrate.
  • the columnar semiconductor 110 is connected to the N + type silicon layer 51.
  • the columnar semiconductor 110 is formed with a MOS transistor for removing accumulated charges, which includes a P-type silicon layer 52, insulating films 53a and 53b, and gate conductor layers 54a and 54b.
  • the columnar semiconductor 110 is formed with a photodiode that is connected to the MOS transistor and accumulates charges generated by irradiation with light (electromagnetic energy wave).
  • This photodiode is composed of a P-type silicon layer 52 and N-type silicon layers 58a and 58b.
  • a P + type silicon layer 56 and an N + type silicon layer formed on the P type semiconductor 52 surrounded by the photodiode as a channel, the photodiode as a gate, and the photodiode are connected to the pixel selection lines 57a and 57b.
  • Junction transistors are formed using the P-type silicon layer 52 in the vicinity of 51 as a source and a drain, respectively.
  • the basic operation of this solid-state imaging device includes a signal charge accumulation operation in which signal charges (electrons in this case) generated by light irradiation are accumulated in a photodiode, and a P-type silicon layer 52 and P + in the vicinity of the N + -type silicon layer 51.
  • a signal read operation for modulating the source / drain current flowing between the silicon layer 56 and the gate voltage by the photodiode voltage corresponding to the above-mentioned accumulated signal charge and reading this as a signal current, and completion of this signal read operation Thereafter, the signal charge accumulated in the photodiode is reset to remove the N + -type silicon layer 51 by applying an ON voltage to the gate conductor layers 54a and 54b of the MOS transistor.
  • the pixels shown in FIG. 14 are two-dimensionally arranged in the photosensitive area.
  • the signal reading operation is performed by transmitting a pixel signal (signal current) to an output circuit provided around the photosensitive region via the N + type silicon layer 51.
  • the reset operation is also performed through electrical transmission between the pixel and the peripheral circuit of the photosensitive region.
  • the bonding metal layer 59 formed on the silicon substrate 60 Possible structures are possible. As a result, the electric resistance of the signal line is almost determined by the metal layer 59, so that the high-speed operation of the signal reading operation described above is realized. However, it is difficult to form the metal layer 59 bonded to the N + type silicon layer 51 from the viewpoint of the affinity of bonding between the metal material and the silicon material.
  • the following method can be considered to form the metal layer 59 on the silicon substrate 60. That is, as shown in FIG. 15B, a silicon oxide layer 62 is formed on the semiconductor substrate 61, and a metal layer 59 is formed on the silicon oxide layer 62. Then, the semiconductor substrate 61 on which the metal layer 59 is formed and the semiconductor substrate 64 are bonded. Thereafter, pixels are formed in the portion of the semiconductor substrate 64 indicated by the broken line in FIG. 15B.
  • a dot-dash line D-D ′ shown in FIG. 15B shows a state in which the semiconductor substrate 64 is formed to a predetermined height by polishing, etching, or other separation methods of the semiconductor substrate 64.
  • the side surface of a columnar semiconductor having a columnar structure is used as a channel region, and a vertical MOS transistor having a structure in which a gate electrode surrounds the channel region is an SGT (Surrounding Gate Transistor).
  • SGT Square Gate Transistor
  • a planar silicon film 67 is formed on the buried oxide film substrate 66, and a columnar structure is formed by the planar silicon film 67 and the PMOS columnar silicon layer 68. .
  • a P + -type silicon diffusion layer 69 that functions as a drain is formed in the planar silicon film 67.
  • a P + -type silicon diffusion layer 70 functioning as a source is formed on the PMOS columnar silicon layer 68, and a gate insulating layer 71 is formed on the outer periphery of the PMOS columnar silicon layer 68.
  • a gate electrode 72 is formed on the outer periphery of the gate insulating layer 71.
  • a silicon nitride (SiN) film 73 and a silicon oxide (SiO 2 ) film 74 are formed so as to surround the gate electrode 72, the P + -type silicon diffusion layer 70, and the P + -type silicon diffusion layer 69.
  • a contact hole 75 is formed in the silicon oxide layer 74, and the P + -type silicon diffusion layer 70 is connected to the source metal wiring 76 through the contact hole 75.
  • one MOS transistor is formed in a columnar structure.
  • the P + -type silicon diffusion layer 69 shown in FIG. 16 is connected to a metal wiring (not shown) at a predetermined portion where the planar silicon film 67 extends on the same plane.
  • the connection between the P + -type silicon diffusion layer 69 and the metal wiring is as in the P + -type silicon diffusion layer 70. It is required to be performed at a short distance.
  • a pixel signal (signal current) is provided around the photosensitive region and transmitted to an external circuit via the N + type silicon layer 51 functioning as a signal line. Is done.
  • the reset operation is also performed through electrical transmission between the pixel and an external circuit in the photosensitive area. The responsiveness of this electrical transmission is greatly influenced by the electrical resistance and parasitic capacitance of the wiring connecting the pixel and the peripheral circuit. In order to increase the number of pixels of the solid-state imaging device or the number of readout screens per unit time, it is necessary to reduce the electrical resistance of such wiring.
  • such an electric resistance is substantially determined by the electric resistance of the N + type silicon layer 51.
  • N + -type silicon layer 51 is formed a donor impurity in silicon (Si) semiconductor, such as phosphorus (P), arsenic (As) by ion doping (ion implantation), electrical of the N + -type silicon layer 51
  • Si silicon
  • P phosphorus
  • As arsenic
  • ion doping ion implantation
  • the resistance value cannot be made smaller than the electrical resistance value of a metal used in a normal semiconductor device such as aluminum (Al), copper (Cu), tungsten (W), nickel (Ni).
  • the solid-state imaging device shown in FIG. 14 has a problem inferior in high-speed operation characteristics as compared with a solid-state imaging device that performs electrical connection between a pixel and a peripheral circuit by a metal wiring.
  • the P + -type silicon diffusion layer 69 is connected to the metal wiring at the portion where the planar silicon film 67 is extended.
  • Such means by connecting the P + -type silicon diffusion layer 69 and the metal wiring cannot be connected to the metal wiring at a short distance as in the P + -type silicon diffusion layer 70, so that the metal wiring and the SGT channel are not connected.
  • a considerable electrical resistance is present up to the end of the closest P + -type silicon diffusion layer 69. For this reason, in the semiconductor device having SGT, it is necessary to reduce this electric resistance in order to realize further high-speed signal reading operation.
  • the present invention has been made in view of the above-described circumstances, and an object thereof is to provide a semiconductor device capable of realizing high integration and high speed operation.
  • a method of manufacturing a semiconductor device includes: A first insulating layer forming step of forming a first insulating layer on the semiconductor substrate; An insulating layer removing step of removing a predetermined portion of the first insulating layer to form an insulating layer removal region; A first semiconductor layer forming step of forming a first semiconductor layer containing a donor impurity or an acceptor impurity on the semiconductor substrate so as to cover at least the insulating layer removal region; A conductive layer forming step of forming a conductive layer on the first semiconductor layer; A molding step of molding the conductive layer and the first semiconductor layer into a predetermined shape; A second insulating layer forming step of forming a second insulating layer so as to cover the conductive layer and the first semiconductor layer formed in the predetermined shape; A planarization step of planarizing the surface of the second insulating layer; An adhesion step of adhering a substrate to the flattened surface of the second insulating layer;
  • the circuit element forming step includes Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer; Forming a fourth semiconductor region having the same conductivity type as the first semiconductor region in a portion above the gate conductor layer and in a surface layer portion of the columnar semiconductor;
  • the columnar semiconductor includes a step of forming a third semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the third insulating layer.
  • the circuit element forming step includes Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer; And forming a fifth semiconductor region having the same conductivity type as that of the first semiconductor region at a position above the third insulating layer in the columnar semiconductor.
  • the circuit element forming step includes Preferably, the method includes a step of forming a sixth semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the columnar semiconductor.
  • the first semiconductor layer forming step includes a step of forming a second semiconductor layer functioning as an electric resistance in the same layer as the first semiconductor layer.
  • the first semiconductor layer forming step includes a step of forming an insulating film functioning as a capacitor insulating film in a predetermined region on the first semiconductor layer functioning as a capacitor electrode;
  • the conductive layer forming step preferably includes a step of forming a conductive layer functioning as a capacitor electrode together with the first semiconductor layer on the insulating film.
  • the first insulating layer forming step forms a fourth insulating layer together with the first insulating layer on the semiconductor substrate, and has a thickness larger than that of the fourth insulating layer in a preset capacitance forming region.
  • Forming a thin fifth insulating layer functioning as a capacitive insulating film includes a step of forming a conductive layer functioning as a capacitor electrode on the fifth insulating layer,
  • the insulating layer removing step preferably includes a capacitor forming step of forming an impurity layer having a donor impurity or an acceptor impurity in the capacitor forming region and functioning as a capacitor electrode.
  • a mask alignment mark formation region setting step for setting a mask alignment mark formation region on the semiconductor substrate; Forming a mask alignment hole in the mask alignment mark formation region to expose at least one of the insulating layer removal region, the first insulating layer, and the conductive layer; A mask alignment mark forming step of forming a mask alignment mark comprising at least one of the insulating layer removal region, the first insulating layer, and the conductive layer through the mask alignment hole; It is preferable that the method further includes a mask alignment step of performing mask alignment of the photomask with the mask alignment mark as a reference.
  • a mask alignment mark comprising at least one of the insulating layer removal region, the first insulating layer, and the conductive layer is formed through the transparent insulator,
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
  • the columnar semiconductor is A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor;
  • a diode that accumulates signal charges generated by irradiation of electromagnetic energy waves from the second semiconductor region and the fourth semiconductor region is formed, The diode functions as a gate, one of the first semiconductor region and the third semiconductor region functions as a source, the other functions as a drain, and a channel formed in the second semiconductor region.
  • a junction transistor is formed that is capable of taking out a current that flows and changes in accordance with the amount of signal charge accumulated in the diode by a signal taking-out means,
  • the gate conductor layer functions as a gate, and a voltage is applied to the gate conductor layer by a MOS transistor in which one of the first semiconductor region and the fourth semiconductor region functions as a source and the other functions as a drain.
  • signal charge removing means for removing the signal charge accumulated in the diode in the first semiconductor region is formed.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
  • the columnar semiconductor is A second semiconductor region formed on the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region or an intrinsic semiconductor;
  • the gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain. To do.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
  • the columnar semiconductor is Between the first semiconductor region and the sixth semiconductor region, a second semiconductor region made of a conductive type or a specific semiconductor opposite to the first semiconductor region is provided, A diode is formed from the second semiconductor region and the sixth semiconductor region.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer;
  • the plurality of columnar semiconductors include a plurality of first columnar semiconductors in which the first semiconductor region is doped with an acceptor impurity, and a plurality of second columnar semiconductors in which the first semiconductor region is doped with a donor impurity. It consists of a semiconductor.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer; In the plurality of columnar semiconductors, both or one of the plurality of first semiconductor regions and the plurality of conductive layers are connected to each other.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer; Each of the columnar semiconductors is A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor; A fifth semiconductor region formed on the second semiconductor region; A third insulating layer formed on the outer periphery of the second semiconductor region; A gate conductor layer formed on the outer periphery of the third insulating layer, The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
  • the first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer formed so as to be connected is a contact formed on an insulating layer. It is connected to a wiring layer for connecting to an external circuit through a hole.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer; Each of the columnar semiconductors is A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor; A fifth semiconductor region formed on the second semiconductor region; A third insulating layer formed on the outer periphery of the second semiconductor region; A gate conductor layer formed on the outer periphery of the third insulating layer, The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
  • the first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer is connected to a predetermined hole via a contact hole formed in the insulating layer. It is connected to a wiring layer for connecting to the gate of the transistor.
  • FIG. 20 is a circuit plan view for explaining a two-stage CMOS inverter circuit according to a tenth embodiment.
  • (First embodiment) 1A to 1L show a method for manufacturing a solid-state imaging device according to the first embodiment of the present invention.
  • high-concentration hydrogen ions H +
  • a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed (see Non-Patent Document 2).
  • a first silicon oxide layer 3 that is an insulating film is formed on the first semiconductor substrate 1 by thermal oxidation or CVD (Chemical Vapor Deposition).
  • the first semiconductor substrate 1 may be a unique semiconductor (i-type silicon) that does not substantially contain impurities, instead of P-type silicon.
  • the hole 4 is formed by removing silicon oxide (SiO 2 ) corresponding to the portion where the signal line drain of the solid-state imaging device is formed in the first silicon oxide layer 3. To do.
  • the region (hole 4) from which the silicon oxide has been removed becomes the silicon oxide layer removal region 48 (see FIGS. 11A and 13A).
  • a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3 and the first semiconductor substrate 1 by the CVD method so as to cover the hole 4.
  • the polycrystalline silicon layer 5 is ion-doped with a donor impurity such as phosphorus (P) or arsenic (As), thereby the first semiconductor substrate 1 and the first silicon oxide.
  • a donor impurity such as phosphorus (P) or arsenic (As)
  • P phosphorus
  • As arsenic
  • tungsten (W), tungsten silicide (WSi), nickel (Ni), nickel silicide (NiSi) is deposited on the N + polycrystalline silicon layer 5a by vapor deposition or CVD. Or a metal layer 7 formed by laminating a plurality of these layers.
  • N + polysilicon layer 5a and the metal layer 7 are part that embeds the hole 4 remaining, N + polycrystalline silicon layer
  • the 5a and the metal layer 7 are formed into a predetermined shape.
  • the source or drain of the junction transistor in the pixel of the solid-state imaging device is formed.
  • a second silicon oxide layer 8 that is an insulating film is formed by a CVD method so as to cover the N + polycrystalline silicon layer 5a, the metal layer 7, and the first silicon oxide layer 3. . Then, the surface of the second silicon oxide layer 8 is planarized by CMP (Chemical Mechanical Polishing).
  • a second semiconductor substrate 9 made of silicon (Si) and having a planarized surface is prepared, and the planarized surface of the second semiconductor substrate 9 and the second silicon oxide are prepared.
  • the planarized surfaces of the layer 8 are bonded together by pressure bonding. In this bonding process, the difference in thermal expansion coefficient between the silicon layer in the second semiconductor substrate 9 and the silicon layer in the second silicon oxide layer 8 are bonded to each other. Due to the difference, it is possible to obtain a laminated structure in which warpage, cracking and peeling are unlikely to occur.
  • the N + polycrystalline silicon layer 5a corresponds to the N + type silicon layer 51 shown in FIG. 14, and in this embodiment, the N + polycrystalline silicon layer 5a includes all of its formation regions.
  • the metal layer 7 is joined over the entire area.
  • the silicon layer in the region other than the silicon layer in the region directly above so that the silicon layer in the region immediately above the N + polycrystalline silicon layer 5 a remains. Are removed by etching. Thereby, a silicon (Si) pillar 1a having a pillar structure is formed.
  • the silicon pillar 1a becomes a P-type silicon layer 30 shown in FIGS. 1K, 1L and the like.
  • heat treatment is performed to thermally diffuse the donor impurity from the N + polycrystalline silicon layer 5a to the silicon pillar 1a, thereby forming the N + diffusion layer 6a in the lower part of the silicon pillar 1a.
  • thermal oxidation is performed to form third silicon oxide layers 10a and 10b that are insulators on the outer periphery of the silicon pillar 1a.
  • gate conductor layers 11a and 11b are formed on the outer peripheral portions of the third silicon oxide layers 10a and 10b by vapor deposition or CVD.
  • an N-type is formed by ion-doping a donor impurity such as phosphorus (P) or arsenic (As) in the upper portion of the gate conductor layers 11a and 11b and the surface layer portion of the silicon pillar 1a.
  • Silicon layers 12a and 12b are formed.
  • the N-type silicon layers 12a and 12b and the silicon pillar 1a (P-type silicon layer 30) form a photodiode as signal charge storage means for storing signal charges (electrons in this case) corresponding to incident light. Is done.
  • the signal charge is accumulated in the silicon pillar 1a (P-type silicon layer 30) between the N + diffusion layer 6a and the P + -type silicon layer 13a.
  • an upper portion of the third silicon oxide layers 10a and 10b is ion-doped with an acceptor impurity such as boron (B) to thereby form a P + -type silicon layer 13a.
  • an acceptor impurity such as boron (B)
  • a third oxide which is an insulator is formed by thermal oxidation on the outer periphery of the silicon pillar 1b constituting another pixel and adjacent to the silicon pillar 1a constituting the pixel of the solid-state imaging device. Silicon layers 10c and 10d are formed.
  • the silicon pillar 1b is formed by the steps shown in FIGS. 1A to 1K, similarly to the silicon pillar 1a.
  • gate conductor layers 11c and 11d are formed on the outer periphery of the third silicon oxide layers 10c and 10d by vapor deposition or CVD.
  • the upper portion of the gate conductor layers 11c and 11d and the surface layer portion of the silicon pillar 1a are ion-doped with a donor impurity such as phosphorus (P) or arsenic (As).
  • Silicon layers 12c and 12d are formed.
  • the N-type silicon layers 12c and 12d and the silicon pillar 1b form a photodiode as signal charge storage means for storing signal charges (electrons in this case) corresponding to incident light.
  • the signal charge is accumulated in the silicon pillar 1b (P-type silicon layer 30) between the N + diffusion layer 6ab and the P + -type silicon layer 13b.
  • the N + diffusion layer 6a in the silicon pillar 1a is thermally diffused from the N + polycrystalline silicon layer 5a to the silicon pillar 1a by heat treatment. Formed.
  • the N + diffusion layer 6a is not limited to this, and the N + diffusion layer 6a is formed from the N + polycrystalline silicon layer 5a to the first semiconductor substrate by heat treatment at an arbitrary stage after the N + polycrystalline silicon layer 5a shown in FIG. 1C is formed. It can also be formed by diffusing donor impurities in 1. That is, after the step of forming the N + polycrystalline silicon layer 5a shown in FIG.
  • the impurities are diffused from the N + polycrystalline silicon layer 5a including the donor impurity, thereby the N + diffusion layer 6a is formed in the silicon pillar 1a.
  • the N + diffusion layer 6a may be formed by performing heat treatment on the silicon pillar 1a (P-type silicon layer 30) in the stage shown in FIG. 1K. Further, the heat treatment for forming such an N + diffusion layer 6a may be performed only once or may be performed in a plurality of times.
  • the solid-state imaging device is formed by the processes shown in FIGS. 1A to 1L. In addition, pixels of the solid-state imaging device are formed on each of the silicon pillars 1a and 1b.
  • N + polycrystalline silicon layer 5a and metal layer 7 formed below silicon pillars 1a and 1b and joined to each other constitute a signal line of the solid-state imaging device.
  • the N + diffusion layers 6a and 6ab in the two silicon pillars 1a and 1b are electrically connected to each other.
  • junction transistors are formed in the silicon pillars 1a and 1b.
  • a photodiode constituted by N-type silicon layers 12a and 12b (12c and 12d) and a silicon pillar 1a (P-type silicon layer 30) is a gate
  • P + -type silicon layers 13a and 13b are drains
  • N + The diffusion layers 6a and 6ab function as sources.
  • the junction transistor channel is formed in the silicon pillars 1a and 1b.
  • an external circuit serving as a signal extraction unit that flows as channels through the channels in the silicon pillars 1a and 1b by the junction transistor and extracts a current that changes according to the amount of signal charge accumulated in the photodiode as an electric signal. (Not shown) is provided.
  • the silicon pillars 1a and 1b shown in FIG. 1L are formed on the silicon pillars 1a and 1b (P-type silicon layer 30) between the N + diffusion layers 6a and 6ab and the P + -type silicon layers 13a and 13b by the photodiode.
  • MOS transistors are formed as signal charge removing means for removing the signal charges accumulated in the N + diffusion layers 6a and 6ab.
  • gate conductor layers 11a, 11b, 11c formed on the outer peripheral surfaces of the third silicon oxide layers 10a, 10b, 10c, 10d so as to surround the silicon pillars 1a, 1b (P-type silicon layer 30).
  • 11d functions as a gate
  • N + diffusion layers 6a and 6ab function as a drain
  • N-type silicon layers 12a, 12b, 12c, and 12d function as a source, respectively.
  • the channel of this MOS transistor is formed in the silicon pillars 1a and 1b.
  • the silicon layer of the second semiconductor substrate 9 and the second silicon oxide layer 8 on the first semiconductor substrate 1 are bonded to each other on the planarized surfaces. Is done.
  • the first semiconductor substrate 1 (second silicon oxide layer 8) and the second semiconductor substrate 9 are bonded to each other over the entire surfaces of the first semiconductor substrate 1 and the second semiconductor substrate 9. Since this is performed between the Si (silicon) surface and the SiO 2 (silicon oxide) surface having a high affinity, it is possible to obtain a laminated structure in which warpage, cracking, and peeling are unlikely to occur.
  • the metal layer 7 is bonded to the N + polycrystalline silicon layer 5a constituting the signal line in the pixel of the solid-state imaging device, the electrical resistance between the pixel and the peripheral circuit of the pixel Can be lowered.
  • the solid-state imaging device can be operated at a higher speed even when the number of pixels is increased or the number of readout screens per unit time is increased as compared with the conventional solid-state imaging device.
  • a PN junction (photodiode) composed of a P-type silicon layer 30 and N-type silicon layers 12a and 12b, and a P-type silicon layer 30 and N + diffusion are used.
  • the PN junction composed of the layer 6a is formed in the silicon pillar 1a made of single crystal silicon. Since the PN junction is thus formed in single crystal silicon, a pixel of a solid-state imaging device with low leakage current is configured.
  • the silicon pillar 1a which is a photoelectric conversion region and is reflected by the metal layer 7.
  • the optical path length in the silicon pillar 1a increases, and the sensitivity of the solid-state imaging device is improved.
  • the solid-state imaging device can be easily manufactured while obtaining the same sensitivity as that of the conventional example. An effect is also obtained.
  • N + polycrystal is formed by CVD so as to fill (cover) the hole 4 on the first silicon oxide layer 3 and the first semiconductor substrate 1.
  • a polycrystalline silicon layer 5 to be a silicon layer 5a was formed.
  • a single crystalline silicon layer may be formed by epitaxial growth.
  • a single crystal silicon layer can be formed also on the first silicon oxide layer 3, and thereafter, a solid-state imaging device is formed in the same manner as the steps shown in FIGS. 1C to 1K. Can do.
  • the first semiconductor substrate 1 is thinned to a predetermined thickness by removing the lower part of the first semiconductor substrate 1 by using a heat treatment at 400 to 600 ° C. with the separation layer 2 as a boundary. did.
  • the first semiconductor substrate 1 is not limited to this, but the first semiconductor substrate 1 is formed of a P + -type substrate and a P-type silicon layer formed by epitaxial growth on the P + -type substrate. Can also be performed by etching and CMP.
  • the gate insulating layers 15a and 15b are formed on the outer periphery of the silicon pillar 1a by the oxidation method or the CVD method, and the gate insulating layers 15a and 15b are formed.
  • Gate conductor layers 16a and 16b functioning as gates of SGTs (MOS transistors) are formed on the outer periphery of the gate electrode.
  • an upper portion of the gate conductor layers 16a and 16b is ion-doped with a donor impurity such as phosphorus (P) or arsenic (As), thereby functioning as an NGT functioning as a source of SGT (MOS transistor).
  • a donor impurity such as phosphorus (P) or arsenic (As)
  • P phosphorus
  • As arsenic
  • a + type silicon layer 17a is formed.
  • a metal wiring layer 18a is formed on the N + type silicon layer 17a by vapor deposition and pattern etching.
  • an SGT specifically, an N-channel SGT is formed on the second semiconductor substrate 9.
  • the N + polycrystalline silicon layer 55a functioning as the drain of the N channel type SGT may function as a source in the N channel type SGT
  • the N + type silicon layer 17a functioning as the source may be the N channel type SGT. , It may function as a drain.
  • the metal layer 7 is bonded to the entire back surface of the N + polycrystalline silicon layer 55a that functions as a drain. With this configuration, the electrical resistance from the metal layer 7 to the N + diffusion layer 6a is reduced, so that an SGT with high speed operation is obtained.
  • an N channel type SGT formation region 1n is an N channel type SGT
  • a P channel type SGT formation region 1p is a P channel type.
  • Each SGT is formed.
  • the N-channel SGT in the N-channel SGT formation region 1n is formed in the same manner as the steps shown in FIGS. 1A to 1J of the first embodiment and FIG. 2 of the second embodiment.
  • the P-channel SGT in the P-channel SGT formation region 1p is formed in substantially the same manner as the steps shown in FIGS. 1A to 1J of the first embodiment and FIG. 2 of the second embodiment.
  • the step corresponding to FIG. 1C instead of forming the N + polycrystalline silicon layer 55a that functions as the drain of the N channel type SGT, boron (B ) Or the like is ion-doped to form a P + polycrystalline silicon layer 55b that functions as a source of the P-channel SGT.
  • an N channel type SGT constituted by the silicon pillar 1a and a silicon pillar 1b are formed.
  • a P channel type SGT is formed.
  • the N-type silicon layer 30a is formed by ion doping a P-channel SGT silicon pillar 1b (P-type silicon) with a donor impurity such as phosphorus (P) or arsenic (As).
  • the gate insulating layers 15a, 15b, 15c, and 15d are formed on the outer peripheral portions of the silicon pillars 1a and 1b by thermal oxidation or CVD, and the gate insulating layers 15a, 15b, and 15c are formed. , 15d, gate conductor layers 16a, 16b, 16c, 16d are formed by CVD (see FIG. 3B).
  • donor impurities and acceptor impurities are ion-doped in the upper portions of the gate conductor layers 16a, 16b, 16c, and 16d, respectively.
  • An N + type silicon layer 17a that functions as a source and a P + type silicon layer 17b that functions as a source of a P-channel type SGT are formed.
  • the N channel type SGT and the P channel type SGT are formed on the second semiconductor substrate 9.
  • any one of the N + polycrystalline silicon layer 55a and the N + diffusion layer 6a in the silicon pillar 1a in the N channel type SGT and the N + type silicon layer 17a is a drain, and the other is Act as a source.
  • any one of the P + polycrystalline silicon layer 55b and the P + diffusion layer 6b and the P + type silicon layer 17b in the silicon pillar 1b in the P channel type SGT is a drain, the other functions as a source.
  • the N-channel SGT and the P-channel SGT can be easily formed on the second semiconductor substrate 9.
  • the P-channel SGT silicon pillar 1b (P-type silicon) is formed with phosphorus (P), arsenic (As), or the like.
  • the N-type silicon layer 30a was formed by ion doping of the donor impurities.
  • the first semiconductor substrate 1 in FIG. 1A is replaced with i-type silicon, which is a unique semiconductor, instead of P-type silicon. In the process corresponding to FIG.
  • the silicon pillar 1a in the type SGT is ion-doped with an acceptor impurity such as boron (B) to form a P-type silicon layer 30, and the silicon pillar 1a in the P-channel type SGT has phosphorus (P) or arsenic (As). It is also possible to form the N-type silicon layer 30a by ion doping with a donor impurity such as
  • an N channel type SGT and a P channel type SGT are formed on the second semiconductor substrate 9, which is the same semiconductor substrate, in substantially the same manner as in the first and third embodiments (FIGS. 1A to 1D). 1J, see FIGS. 3A and 3B).
  • N + polycrystalline silicon layers 55a functioning as sources and P + many functioning as drains.
  • the crystalline silicon layers 55b are electrically connected to each other by the metal layers 7aa and 7bb, the first connection metal layer 7a, and the second connection metal layer 7b.
  • the metal layer 7 is formed by vapor deposition and etching so as to cover the silicon layers to be the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b. . Then, the metal layer 7, the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b are formed into a predetermined shape by etching. Thereby, as shown in FIG. 4, an N + polycrystalline silicon layer 55a, a P + polycrystalline silicon layer 55b, metal layers 7aa and 7bb, and a first connection metal layer 7a are formed.
  • a silicon oxide layer 20 is formed on the first connection metal layer 7a, and a contact hole 21c is formed in the silicon oxide layer 20.
  • the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b and the external metal wiring layer 22c formed on the silicon oxide layer 20 through the contact hole 21c and the first connection metal layer 7a.
  • a second connection metal layer 7b is formed in a portion extending from the first connection metal layer 7a, and the second connection metal layer 7b is used to electrically connect from a predetermined location through a contact hole (not shown). Take out the contact.
  • metal layers 7aa and 7bb are bonded to the entire back surfaces of N + polycrystalline silicon layers 55a and 55b that function as drains of the N-channel SGT, respectively.
  • the N + diffusion layers 6a and 6b and the plurality of metal layers 7aa and 7bb which are one of the plurality of metal layers 7aa and 7bb are connected to each other.
  • both of the N + diffusion layers 6a and 6b and the plurality of metal layers 7aa and 7bb may be connected to each other.
  • the N + polycrystalline silicon layer 55a functions as an N-channel SGT source
  • the P + polycrystalline silicon layer 55b functions as a P-channel SGT drain.
  • the present invention is not limited to this, and the N + polycrystalline silicon layer 55a can also function as an N-channel SGT drain and the P + polycrystalline silicon layer 55b can function as a P-channel SGT source. Further, both the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b may function as a source or a drain.
  • the source and drain constituted by the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b are arranged on the upper surface of the silicon oxide layer 20.
  • the metal wiring layers 22a, 22b, and 22c are electrically connected to each other by the first connection metal layer 7a without being connected after being drawn out through a contact hole or the like. Thereby, the integration degree of the circuit element which has SGT can be raised.
  • the semiconductor device manufacturing method according to the present embodiment can be applied to a solid-state imaging device manufacturing method.
  • the drains of the pixels are connected to each other by the first connection metal layer 7a. Connect with.
  • the drain and source of each pixel need not be connected to each other after being connected to another metal wiring in the upper layer portion via a contact hole or the like. For this reason, further high integration of the pixels of the solid-state imaging device is realized.
  • FIGS. 5A to 5C a method for forming an electrical resistance in a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 5A to 5C.
  • the manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
  • an electrical resistance which is a circuit element of the semiconductor device is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
  • a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
  • a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
  • a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3, and in the process shown in FIG. 1C, phosphorus (P) or The N + polycrystalline silicon layer 5a is formed by ion doping with a donor impurity such as arsenic (As).
  • a donor impurity such as arsenic (As).
  • N + polycrystalline silicon layers 23a and 23b are formed by ion doping with a donor impurity such as) at a predetermined concentration.
  • the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23 in which the donor impurity is not ion-doped reduce the electric resistance value in a predetermined region (polycrystalline silicon layer 23) of the polycrystalline silicon layer 5 and A resistance is formed.
  • the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23 are formed from the polycrystalline silicon layer 5 (see FIG. 1B) in the same manner as the N + polycrystalline silicon layer 5a (see FIG. 1C). Therefore, it is located in the same layer as the N + polycrystalline silicon layer 5a.
  • metal wiring layers 24a and 24b located in the same layer as the metal layer 7 are formed in the same manner as the metal layer 7 on the N + polycrystalline silicon layers 23a and 23b.
  • a predetermined region of the polycrystalline silicon layer 5 is ion-doped with a donor impurity having a predetermined concentration, so that N + polycrystalline silicon layers 23a and 23b having a predetermined electric resistance value, polycrystalline silicon Layer 23 is formed.
  • the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23 are formed in the same layer as the N + polycrystalline silicon layer 5a.
  • the polycrystalline silicon layer 25 is formed in the step shown in FIG. 1B and formed into a predetermined shape by etching
  • the polycrystalline silicon layer is formed by vapor deposition or CVD.
  • Metal wiring layers 26 a and 26 b connected to the layer 25 are formed. In this way, electrical resistance in the semiconductor device is also formed by the polycrystalline silicon layer 25.
  • the second silicon oxide layer 8 is formed on the second semiconductor substrate 9, and the N + is formed on the second silicon oxide layer 8 by the method described above.
  • Polycrystalline silicon layers 23a and 23b and a polycrystalline silicon layer 23 are formed.
  • the first silicon oxide layer 3 is formed on the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23, and the silicon oxide layer 20 (see FIG. 4) is formed on the first silicon oxide layer 3. It is also possible to do.
  • the electrical resistance shown in FIG. 5A is formed from the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23.
  • a circuit element or metal wiring having SGT is formed on the first silicon oxide layer 3. Further, in the modification shown in FIG. 5C, the polycrystalline silicon layer 23 constituting the electric resistance is formed below the first silicon oxide layer 3 which is an insulator.
  • the upper and lower sides of the SiO 2 layer (first silicon oxide layer 3) are shown in FIG. 4 so as to overlap with the polycrystalline silicon layer 23 constituting the electric resistance.
  • the metal wiring layers 22a, 22b and 22c of the circuit element can be formed. Thereby, further high integration of the semiconductor device (circuit element) having electric resistance is realized.
  • FIGS. 6A to 6C a method of forming a capacitor in a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 6A to 6C.
  • the manufacturing process of the semiconductor device according to the present embodiment is the same as that of the first embodiment, except as described below.
  • a capacitor which is a circuit element of a semiconductor device, is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
  • a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
  • a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
  • a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3, and in the process shown in FIG. 1C, phosphorus (P) or The N + polycrystalline silicon layer 5a is formed by ion doping with a donor impurity such as arsenic (As).
  • a donor impurity such as arsenic (As).
  • capacitive silicon oxide layer 27 is formed on the surface layer portion of N + polycrystalline silicon layer 5a by thermal oxidation or CVD.
  • the capacitor silicon oxide layer 27 functioning as a capacitor insulating film is formed into a predetermined shape in the capacitor region where the capacitor is formed by etching using a mask.
  • a metal layer 28 that functions as a capacitor electrode is formed on the capacitor silicon oxide layer 27 formed in a predetermined shape by vapor deposition or CVD.
  • the metal layer 28 is formed in the same layer as the metal layer 7 of the first embodiment.
  • a laminated structure as shown in FIG. 6C is formed. That is, a second silicon oxide layer 8 is formed on the second semiconductor substrate 9, and inside the second silicon oxide layer 8, a metal layer 28 functioning as a capacitor electrode is formed in a capacitor region where a capacitor is formed, and A capacitive silicon oxide layer 27 that is stacked on the metal layer 28 and functions as a capacitive insulating film is disposed. Then, the N + polycrystalline silicon layer 5a, the first silicon oxide layer 3 and the silicon oxide layer 29 (silicon oxide layer 20) are stacked in this order on the capacitive silicon oxide layer 27 and the second silicon oxide layer 8. Is obtained. In this structure, the metal layer 28 and the N + polycrystalline silicon layer 5a function as a capacitor electrode, and a capacitor in which the capacitor silicon oxide layer 27 functions as a capacitor insulating film is formed.
  • the process of forming the insulating layer 27 on the surface layer of the N + polycrystalline silicon layer 5a (see FIG. 6A).
  • a step of forming the capacitive silicon oxide layer 27 and the metal layer 28 see FIG. 6B.
  • a method of forming a capacitor in a semiconductor device according to a seventh embodiment of the present invention will be described.
  • the manufacturing process of the semiconductor device according to the present embodiment is the same as that of the first embodiment, except as described below.
  • a capacitor which is a circuit element of a semiconductor device, is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
  • a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
  • a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
  • the capacitance forming region 100 shown in FIG. 7A is set on the first silicon oxide layer 3, and the capacitance forming region 100 in this capacitance forming region 100 is set.
  • a concave silicon oxide layer removal region is formed. That is, in the step shown in FIG. 1B, as shown in FIG. 7A, the silicon oxide layers 101a and 101b are left around the silicon oxide layer removal region, and the silicon oxide layer removal region has a silicon oxide layer.
  • a silicon oxide layer 103 having a thickness smaller than those of 101a and 101b is left.
  • acceptor impurities such as boron (B) are ion-doped or thermally diffused, whereby the surface layer of the first semiconductor substrate 1 in the capacitor formation region 100 through the silicon oxide layer 103.
  • the P + diffusion layer 102 is formed.
  • a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3 so as to embed a silicon oxide layer removal region.
  • the polysilicon layer 5 is ion-doped with a donor impurity such as phosphorus (P) or arsenic (As) to form an N + polycrystalline silicon layer 104 (see FIG. 1C). (See FIG. 7A).
  • a donor impurity such as phosphorus (P) or arsenic (As)
  • a metal layer 105 is formed on the N + polycrystalline silicon layer 104 by vapor deposition or CVD (see FIG. 7A).
  • the metal layer 105 is formed in the same layer as the metal layer 7 in the first embodiment.
  • the N + polycrystalline silicon layer 104 and the N + polycrystalline silicon layer 104 are formed and function as a capacitor electrode.
  • the metal layer 105 to be formed is formed into a predetermined shape.
  • the P + diffusion layer 102 is left in the silicon pillar 1a, and the P + diffusion layer 102 and the oxidation layer are oxidized.
  • a silicon oxide layer 107 is formed so as to cover the silicon layers 101a and 101b.
  • a contact hole 108 is formed in the silicon oxide layer 107, and the metal wiring layer 109 and the P + diffusion layer 102 on the silicon oxide layer 107 are electrically connected via the contact hole 108. Connect to.
  • the N + polycrystalline silicon layer 104, the metal layer 105, and the P + diffusion layer 102 function as a capacitor electrode in the capacitor formation region 100 (see FIG. 7A).
  • a capacitor is formed in which the silicon oxide layer 103 between 101a and 101b functions as a capacitor insulating film.
  • the P + diffusion layer 102 is formed by ion doping or thermal diffusion of acceptor impurities such as boron (B) into the first semiconductor substrate 1 using the silicon oxide layers 101a and 101b as a mask.
  • acceptor impurities such as boron (B)
  • the P + diffusion layer 102 performs ion doping with a high acceleration voltage on the first silicon oxide layer 3 (see FIG. 1A) having a uniform thickness before the silicon oxide layers 101a and 101b are formed. Thus, it can be formed in a predetermined region other than the capacitance forming region 100.
  • the contact hole 108 enables connection between capacitors and extraction of an electric signal to an external circuit from an arbitrary location of the semiconductor device. As a result, further integration of circuit elements can be realized.
  • FIGS. 8A to 8C a method for forming a diode in a semiconductor device according to an eighth embodiment of the present invention will be described with reference to FIGS. 8A to 8C.
  • the manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
  • a diode which is a circuit element of a semiconductor device is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
  • the second silicon oxide layer 8 is formed on the second semiconductor substrate 9 as shown in FIG. 8A through the steps shown in FIGS. 1A to 1I of the first embodiment.
  • the metal layer 7, the N + polycrystalline silicon layer 5a, and the silicon pillar 1a are formed in this order from below.
  • a first silicon oxide layer 3 is formed around the N + polycrystalline silicon layer 5a.
  • an ion impurity is doped with an acceptor impurity such as boron (B) to thereby form a P-type silicon layer shown in FIG. 8B. 30 is formed.
  • acceptor impurity such as boron (B)
  • N + diffusion layer 6a is formed.
  • ion implantation of acceptor impurities such as boron (B) is formed on the upper portion of the P-type silicon layer 30 (silicon pillar 1 a), thereby forming a P + -type silicon layer 31.
  • the metal layer 32 is formed on the P + type silicon layer 31 by vapor deposition and etching.
  • a silicon oxide layer 33 is formed so as to cover the P-type silicon layer 30 and the metal layer 32.
  • contact holes 34, The metal wiring layer 35 is formed in this order. Thereby, the metal wiring layer 35 and the metal layer 32 are electrically connected via the contact hole 34.
  • a pn junction diode is formed by the P + type silicon layer 31 and the P type silicon layer 30.
  • a diode circuit element
  • a semiconductor device such as SGT
  • FIG. 8C shows a modification of this embodiment in which a PIN photodiode is formed on the silicon pillar 1a.
  • an i-type silicon layer 30b which is a unique semiconductor, is formed on the silicon pillar 1a shown in the eighth embodiment instead of the P-type silicon layer 30.
  • a P + type silicon layer 31 is formed on the i type silicon layer 30b.
  • a PIN photodiode is formed by the i-type silicon layer 30 b and the P + -type silicon layer 31.
  • the depletion layer is formed in the entire i-type silicon layer 30b or in a wide area, so that a wide photoelectric conversion area can be secured and the thickness of the capacitance formation area can be increased. Since the thickness of the corresponding depletion layer is increased, the capacity can be reduced.
  • the PIN photodiode is formed as an optical connection light receiving element on the same semiconductor substrate as the circuit element of the semiconductor device.
  • the PIN photodiode of this modification functions as an optical switch, there is no RC delay due to the resistance / capacitance of the input circuit wiring, and the speed of the circuit input section and the speed of the entire circuit can be increased.
  • a PIN photodiode (circuit element) can be formed on the same semiconductor substrate together with a pixel of a solid-state imaging device, a semiconductor device such as SGT, and the manufacturing process can be simplified. become.
  • FIG. 9A shows a CMOS inverter circuit used in this embodiment.
  • a P-channel MOS transistor 37a and an N-channel MOS transistor 37b are connected in series.
  • the gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b are connected through a gate connection wiring 38, and the gate connection wiring 38 is connected to the input terminal wiring Vi.
  • the source of the P-channel MOS transistor 37a is connected to the power supply terminal wiring Vdd.
  • the drain of the P-channel MOS transistor 37a and the drain of the N-channel transistor 37b are connected to the output terminal wiring Vo via the drain connection wiring 39, and the source of the N-channel MOS transistor 37b is at the ground potential. It is connected to the ground terminal wiring Vss.
  • FIG. 9B shows a plan layout of this CMOS inverter circuit. As shown in FIG. 9B, the contact hole 41c, the silicon pillar 40a, the contact hole 41a, the contact hole 41b, and the contact hole 41d are arranged in a straight line.
  • the input terminal wiring Vi is for inputting an electric signal (gate voltage) from the contact hole 41c.
  • the power supply terminal wiring Vdd is for supplying a power supply voltage from the contact hole 41a.
  • the ground terminal wiring Vss is for connecting to the ground via the contact hole 41b.
  • the output terminal wiring Vo is for outputting an electrical signal from the contact hole 41d.
  • the contact hole 41c is formed on the gate connection wiring 38 that connects the gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b.
  • the silicon pillar 40a constitutes a P channel type MOS transistor 37a.
  • the contact hole 41a is formed on the silicon pillar 40a.
  • the silicon pillar 40b constitutes an N channel type MOS transistor 37b.
  • the contact hole 41b is formed on the silicon pillar 40b.
  • the contact hole 41d is formed on a drain connection wiring 39 that connects the drain of the P-channel MOS transistor 37a and the drain of the N-channel MOS transistor 37b to each other.
  • the input terminal wiring Vi, the power supply terminal wiring Vdd, the ground terminal wiring Vss, and the output terminal wiring Vo are arranged so as to extend in the row direction orthogonal to the column direction of the contact holes 41b and 41d, respectively. (See FIG. 9A).
  • FIG. 9C is a sectional structural view taken along line B-B ′ of FIG. 9B.
  • a method of forming the above-described CMOS inverter circuit will be described with reference to FIG. 9C.
  • the process of forming the CMOS inverter circuit is the same as that of the first embodiment, except as specifically described below.
  • the CMOS inverter circuit having the P-channel MOS transistor 37a and the N-channel MOS transistor 37b shown in FIG. 9C is the same as the N-channel MOS transistor and the P-channel type in the CMOS inverter circuit shown in FIG. 3B.
  • the left and right positional relationship with the MOS transistor is switched, it is formed in the same manner as the third embodiment shown in FIGS. 3A and 3B.
  • the description of the parts indicated by the same or corresponding symbols as those of the above embodiment will be omitted.
  • a drain connection wiring 39 is formed below the P + polycrystalline silicon layer 55b functioning as the drain in the P-channel MOS transistor 37a and the N + polycrystalline silicon layer 55a functioning as the drain in the N-channel MOS transistor 37b.
  • a drain connection wiring 39 is formed.
  • a drain connection wiring 39 is bonded to the lower surfaces of the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b.
  • the N + polycrystalline silicon layer 55 a and the P + polycrystalline silicon layer 55 b are connected via the drain connection wiring 39.
  • the drain connection wiring 39 is formed on the insulating layer 43 b and is connected to the output terminal wiring layer Vo through a contact hole 41 d penetrating the silicon oxide layer 45.
  • the gate conductor layers 16ba and 16bb of the P-channel MOS transistor 37a and the gate conductor layers 16aa and 16ab of the N-channel MOS transistor 37b are connected through a gate connection wiring 38 formed on the insulating layer 43a. ing.
  • the metal wiring layer 18a and the drain connection wiring 39 formed above are input terminal wirings formed on the silicon oxide layer 45 through contact holes 41c, 41a, 41b and 41d penetrating the silicon oxide layer 45, respectively.
  • the layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vo are connected.
  • the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vo are wired in parallel to each other (see FIG. 9C).
  • the P + polycrystalline silicon layer 55b functioning as a drain in the P-channel MOS transistor 37a and the N + polycrystalline silicon layer 55a functioning as a drain in the N-channel MOS transistor 37b are close to each other.
  • the drain connection wiring 39 having a low electric resistance is electrically connected.
  • FIG. 10A shows a CMOS inverter circuit having a two-stage structure used in this embodiment.
  • P-channel MOS transistors 37a and 37c and N-channel MOS transistors 37b and 37d are connected in series at the first and second stages, respectively.
  • the gates of the first-stage P-channel MOS transistor 37a and N-channel MOS transistor 37b are connected to the input terminal wiring Vi through the gate connection wiring 38a.
  • the gates of the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37d are connected to the first-stage output terminal wiring Vo through the gate connection wiring 38b.
  • the drains of the first-stage and second-stage P-channel MOS transistors 37a and 37c are connected to the power supply terminal wiring Vdd.
  • the sources of the first-stage and second-stage P-channel MOS transistors 37b and 37d are connected to the ground terminal wiring Vss.
  • the drain of the P-channel MOS transistor 37a and the drain of the N-channel transistor 37b are connected to the first-stage output terminal wiring Vo via the drain connection wiring 39a.
  • the drain of the P-channel transistor 37c and the drain of the N-channel transistor 37d are connected to the output terminal wiring Vout via the drain connection wiring 39b.
  • FIG. 10B shows a plan layout of this CMOS inverter circuit.
  • a contact hole 41c is formed on the gate connection wiring 38a formed on the silicon pillar 40a constituting the first-stage P-channel MOS transistor 37a and the silicon pillar 40b constituting the N-channel MOS transistor 37b.
  • the contact hole 41c is connected to the input terminal wiring Vi.
  • the gate connection wiring 38a connects the gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b.
  • the drain of the P-channel MOS transistor 37a and the drain of the N-channel MOS transistor 37b are connected via the first-stage drain connection wiring 39a.
  • a contact hole 41e is formed on the gate connection wiring 38b formed in the silicon pillar 40c constituting the second-stage P-channel MOS transistor 37c and the silicon pillar 40d constituting the N-channel MOS transistor 37d. It is connected to the first-stage output terminal wiring Vo (see FIG. 10A).
  • the first-stage drain connection wiring 39a is connected to the gate connection wiring 38b through the contact hole 41e (see FIG. 10C).
  • the gate connection wiring 38b connects the gates of the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37d.
  • Contact holes 41a and 41c are formed on the silicon pillars 40a and 40c of the first-stage and second-stage P-channel MOS transistors 37a and 37c, respectively.
  • the contact holes 41a and 41c are both connected to the power supply terminal wiring layer Vdd.
  • Contact holes 41b and 41d are formed on the silicon pillars 40b and 40d of the first-stage and second-stage P-channel MOS transistors 37b and 37d, respectively, and both of the contact holes 41b and 41d are connected to the ground terminal wiring layer Vss. Has been.
  • a contact hole 41f is formed on the second-stage drain connection wiring 39b, and the contact hole 41f is connected to the output terminal wiring layer Vout.
  • the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout are wired in parallel to each other.
  • FIG. 10C is a cross-sectional structural view taken along the line C-C ′ of FIG. 10B.
  • the above-described two-stage CMOS inverter circuit will be described with reference to FIG. 10C.
  • the two-stage CMOS inverter circuit is formed in the same manner as in the first embodiment.
  • CMOS inverter circuit having the P-channel MOS transistor 37a and the N-channel MOS transistor 37b shown in FIG. 10C is the same as the CMOS inverter circuit shown in FIG. 3B in terms of the left and right sides of the N-channel MOS transistor and the P-channel MOS transistor. However, they are formed in the same manner as the third embodiment shown in FIGS. 3A and 3B.
  • the conductor layers 16aa and 16ab are connected via the gate connection wiring 38a.
  • a contact hole 41b connected to the metal wiring layer 18a on the N-channel MOS transistor 37b is formed in the silicon oxide layer 45 formed on the gate connection wiring 38a.
  • the contact hole 41b is connected to the ground terminal wiring Vss of the N channel type MOS transistor 37b.
  • a silicon oxide layer 43 is formed between the first silicon oxide layer 3 and the gate connection wiring 38a.
  • the N + polycrystalline silicon layer 55a functioning as the drain is electrically connected to each other through the metal wiring layer 42 which is the first-stage drain connection wiring 39a.
  • the metal wiring layer 42 is connected via a gate connection wiring 38b that connects the gates of the second-stage P-channel MOS transistor 37c and the N-channel MOS transistor 37d, and a contact hole 41e formed in the silicon oxide layer 45. Are connected (see FIGS. 10A and 10B).
  • a contact hole 41a is formed on the silicon pillar 40a of the first-stage P-channel MOS transistor 37a, and the contact hole 41a is connected to the power supply terminal wiring layer Vdd.
  • a contact hole 41b is formed on the silicon pillar 40b of the first-stage N-channel MOS transistor 37b, and the contact hole 41b is connected to the ground terminal wiring layer Vss.
  • a contact hole 41f is formed on the second-stage drain connection wiring 39b, and the output terminal wiring layer Vout is connected to the contact hole 41f on the silicon oxide layer 45 (see FIGS. 10A and 10B). Further, the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout are wired in parallel to each other (see FIG. 10B).
  • the metal wiring layer 42 functioning as the drain connection wiring 39a of the first-stage P-channel MOS transistor 37a and N-channel MOS transistor 37b is replaced with the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37c.
  • the channel type MOS transistor 37d is directly connected to the gate connection wiring 38b via the contact hole 41e.
  • the metal wiring layer 42 (39a) is connected to the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout through the contact holes formed in the silicon oxide layer 45 (FIG. 10B), it is not necessary to pull up to the same layer as that, so that high integration of circuit elements is realized.
  • FIGS. 11A and 11B a method for forming a mask alignment mark on a semiconductor substrate according to an eleventh embodiment of the present invention will be described with reference to FIGS. 11A and 11B.
  • the process shown in FIG. 11A corresponds to the process shown in FIG. 1H in the first embodiment.
  • the other steps are the same as those in the first embodiment except for the case specifically described below.
  • a second silicon oxide layer 8 is formed on the second semiconductor substrate 9.
  • the first silicon oxide layer 3 and the first semiconductor substrate 1 are formed in this order.
  • a mask alignment mark formation region 47a for mask alignment and a circuit formation region 47b for forming a circuit are set at predetermined positions on the first semiconductor substrate 1.
  • a silicon oxide layer removal region 48 is formed in the first silicon oxide layer 3 (see FIG. 1B). At the center of the silicon oxide layer removal region 48, a mark metal layer 49a and a mark polycrystalline silicon layer 49b are formed in a laminated state.
  • the silicon oxide layer removal region 48 is formed simultaneously with the hole 4 in which the source or drain of the junction transistor in the pixel of the solid-state imaging device is formed.
  • a metal layer 7 and an N + polycrystalline silicon layer 5a are formed in a laminated state in the center of the circuit formation region 47b (see FIG. 1H).
  • a mask alignment hole 50 is formed at a predetermined position as shown in FIG. 11B.
  • the mark metal layer 49 a, the mark polycrystalline silicon layer 49 b, and the silicon oxide layer removal region 48 are exposed through the mask alignment hole 50.
  • the mask alignment of the photomask is performed using any one of the mark metal layer 49a, the mark polycrystalline silicon layer 49b, and the silicon oxide layer removal region 48 in the mask alignment hole 50 as a reference mask alignment mark. Do.
  • a photomask is overlaid on the region where the photoresist is formed, and light is irradiated to transfer the circuit.
  • the first semiconductor substrate 1 is covered with a photoresist, and the mark metal layer 49a and the mark polycrystalline silicon layer located below the first semiconductor substrate 1 are covered.
  • Mask alignment is performed using either of 49b and the silicon oxide layer removal region 48 as a mark.
  • the first semiconductor substrate 1 is made of silicon and absorbs blue light and ultraviolet light. Therefore, red wavelength light or infrared light having high transmittance is used for mask alignment. For this reason, the resolution of the mark image is lowered and the mask alignment accuracy is lowered.
  • the mask alignment mark formation region 47a does not include a silicon layer that absorbs a large amount of blue light and ultraviolet light, so the mark metal layer 49a, the mark polycrystalline silicon layer 49b, the oxidation layer A photoresist can be formed directly on the silicon layer removal region 48. For this reason, a high-resolution mark image is obtained, and the mask alignment accuracy is improved.
  • the photoresist is directly formed on the silicon oxide layer removal region 48, the alignment accuracy between the N + polycrystalline silicon layer 5a and the silicon pillar 1a shown in FIG. .
  • a transparent insulating layer 50a that transmits blue light or ultraviolet light is embedded in the mask alignment hole 50 shown in FIG. 11B.
  • An SiO 2 film is used for the transparent insulating layer 50a. Thereafter, the SiO 2 film and the surface of the first semiconductor substrate 1 are planarized by CMP. The step of filling the mask alignment hole 50 with the SiO 2 film is performed before the silicon pillar 1a on which the junction transistor is formed is formed with reference to FIG. 1I.
  • the transparent insulating layer 50a in the mask alignment hole 50 can make the photoresist covering the mask alignment mark formation region 47a and the circuit formation region 47b thin and uniform. Compared with the embodiment, the mask alignment accuracy is further improved.
  • FIG. 13A corresponds to the step shown in FIG. 1B in the first embodiment.
  • the other steps are the same as those in the first embodiment except for the case specifically described below.
  • the separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
  • a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
  • holes 4 are formed in the first silicon oxide layer 3 by removing silicon oxide (SiO 2 ) in a predetermined region.
  • polycrystalline silicon is formed on the first silicon oxide layer 3 and the first semiconductor substrate 1 by the CVD method so as to fill the hole 4 (silicon oxide layer removal region 48).
  • Layer 111 is formed. This polycrystalline silicon layer 111 is not doped with donor impurities or acceptor impurities.
  • an N + polycrystalline silicon layer 106 doped with donor impurities is formed on the polycrystalline silicon layer 111 by CVD and ion doping of donor impurities.
  • a metal layer 7 is formed on the N + polycrystalline silicon layer 106 in the same manner as the step shown in FIG. 1D. Further, a semiconductor device is formed in the same manner as the steps shown in FIGS. 1E to 1L.
  • the polycrystalline silicon layer 111 which is not doped with impurities is formed between the first semiconductor substrate 1 and the N + polycrystalline silicon layer 106. Due to the presence of the polycrystalline silicon layer 111, the diffusion depth of the donor impurity to the silicon pillar 1a when the N + polycrystalline silicon layer 106 is used as a diffusion source by the heat treatment in the step shown in FIG. 1J can be adjusted. it can.
  • the donor impurity is diffused from the N + polycrystalline silicon layer 106 by heat treatment, so that the polycrystalline silicon layer 111 becomes an N + polycrystalline silicon layer. Then, by diffusing donor impurities by heat treatment of N + polysilicon layer 111 in the silicon pillar 1a to form the N + diffusion layer 6a.
  • the polycrystalline silicon layer 111 not doped with donor impurities by heat treatment into an N + polycrystalline silicon layer, the diffusion performance of donor impurities from the N + polycrystalline silicon layer 106 to the outside is reduced.
  • N 2 is changed depending on the heat treatment conditions (temperature, time) after bonding the second semiconductor substrate 9 and the second silicon oxide layer 8 on the first semiconductor substrate 1.
  • the + diffusion layer 6a is assumed to diffuse beyond a desired depth, this is effective for suppressing the diffusion depth.
  • a P + polycrystalline silicon layer can be used in place of the N + polycrystalline silicon layer 106. Even if the polycrystalline silicon layer 111 that is not doped with donor impurities or acceptor impurities contains a small amount of impurities even if they are not actively doped, the effect of this embodiment is not affected.
  • the first silicon oxide layer 3 is formed by thermal oxidation, anodization, CVD (Chemical Vapor Deposition), or the like. Formed.
  • CVD Chemical Vapor Deposition
  • the present invention is not limited to this, and a multilayer structure with another insulating film such as a silicon nitride (SiN) film may be used.
  • the present invention is not limited to the embodiments described in the first to twelfth embodiments described above, and various modifications can be made.
  • the first semiconductor substrate 1 is P-type conductivity.
  • the first semiconductor substrate 1 is not limited to this, and may be i-type (intrinsic type) which is a unique semiconductor. Further, depending on the circuit element formed on the first semiconductor substrate 1, an N-type conductivity type may be used.
  • the channel of the P-channel MOS transistor is formed in the N-type silicon layer 30a, and the channel of the N-channel MOS transistor is the P-type silicon layer.
  • the channel of the N-channel MOS transistor may be formed on i-type silicon which is a unique semiconductor.
  • the N + polycrystalline silicon layer 5a, the metal layer 7, and the N + diffusion layer 6a are used as individual material layers.
  • the metal layer 7 is reacted with the metal material (Ni, W, etc.) of the metal layer 7 and a part of the N + polycrystalline silicon layer 5a or the N + diffusion layer 6a. 7.
  • All or part of the N + polycrystalline silicon layer 5a or the N + diffusion layer 6a may be changed to a silicide layer (NiSi, WSi, etc.).
  • the temperature is 400 to 600 ° C.
  • the first semiconductor substrate 1 was separated into a top and bottom by heat treatment, and the first semiconductor substrate 1 was thinned to a predetermined thickness.
  • a method of forming a porous layer in the separation layer 2 shown in Non-Patent Document 3 may be employed to reduce the thickness of the first semiconductor substrate 1 to a predetermined thickness.
  • a method of separating the first semiconductor substrate 1 vertically can be employed.
  • the second semiconductor substrate 9 may be a semiconductor different from silicon, for example, a compound semiconductor such as silicon carbide (SiC), an insulator, or an organic resin body. Also with this configuration, the circuit elements formed on the first semiconductor substrate 1 can be held.
  • the second silicon oxide layer 8 and the silicon oxide layers 20, 29, 45 may have a multilayer structure with other insulating films such as a silicon nitride (SiN) film.
  • SiN silicon nitride
  • the N + polycrystalline silicon layers 5a and 55a and the P + polycrystalline silicon layer 55b were formed by ion doping.
  • the present invention is not limited to this, and it may be formed by thermal diffusion of impurities or a doped polycrystalline silicon layer mixed with impurities.
  • the polycrystalline silicon layer 5 was formed by a CVD method.
  • the present invention is not limited to this, and the polycrystalline silicon layer 5 may be formed by epitaxial growth.
  • a single crystal silicon layer is grown on the first semiconductor substrate 1, and a polycrystalline silicon layer is formed on the first silicon oxide layer 3 depending on the growth conditions.
  • the single crystal silicon layer becomes a diffusion source to the silicon pillar 1a of the donor or acceptor.
  • the silicon layer can be prevented from being formed on the first silicon oxide layer 3 depending on the growth conditions (temperature, etc.) of the single crystal silicon layer.
  • the second semiconductor substrate 9 made of silicon and the second silicon oxide layer 8 flattened by CMP are bonded together, and an oxide layer is formed on the surface of the second semiconductor substrate 9 by oxidation or CVD.
  • the second semiconductor substrate 9 and the second silicon oxide layer 8 can be bonded after the insulating layer is formed.
  • the drain connection wiring 39 and the output terminal wiring Vo are connected via the contact hole 41d.
  • the drain connection wiring 39 and the output terminal wiring Vo can be connected so that the bottom of the contact hole 41 d is in contact with the N + polycrystalline silicon layer 55 a on the drain connection wiring 39. Also with this configuration, the electrical resistance of the N + polycrystalline silicon layer 55a is sufficiently small, so that high-speed operation of the circuit element is realized.
  • the metal wiring layer 42 (39a) functioning as the drain connection wiring and the second-stage gate connection wiring 38b are connected via the contact hole 41e.
  • the connection is not limited to this, and the contact hole 41 e can be connected so that the bottom thereof is in contact with the N + polycrystalline silicon layer 55 a on the metal wiring layer 42. Also with this configuration, the electrical resistance of the N + polycrystalline silicon layer 55a is sufficiently small, so that high-speed operation of the circuit element is realized.
  • gate conductor layers 11a, 11b, 11c, 11d, 16a, 16b, 16c, 16d, and gate connection wirings 38, 38a, as shown in FIG. 10C, as shown in FIG. 1L, FIG. 2, and FIG. 38b was formed by a vapor deposition method or a CVD method.
  • the present invention is not limited to this, and a single layer or a plurality of different types of metal layers, a polycrystalline silicon layer doped with impurities, or a multilayer configuration of the polycrystalline silicon layer and the metal layer may be used.
  • the gate connection wirings 38, 38a, and 38b may use different materials for the N channel type and the P channel type.
  • the two-stage CMOS inverter circuit shown in FIGS. 10B and 10C can be configured as follows. That is, the P + -type silicon layer 17b and the N + -type silicon layer 17a in the upper part of the silicon pillar 40a of the P-channel MOS transistor 37a and the silicon pillar 40b of the N-channel MOS transistor 37b are formed in the silicon oxide layer 45. It is connected to the first-stage output terminal wiring layer Vout through the formed contact holes 41a and 41b.
  • the metal layer 46b connected to the P + polycrystalline silicon layer 55b and the P + diffusion layer 6b below the silicon pillar 40a of the P channel MOS transistor 37a is used as a power supply terminal wiring layer Vdd, and N channel
  • the metal layer 46a connected to the N + polycrystalline silicon layer 55a and the N + diffusion layer 6a below the silicon pillar 40b of the type MOS transistor 37b is defined as a ground terminal wiring layer Vss. Also in this structure, the same effect as the structure shown in FIG. 10C can be obtained.
  • arsenic is formed after the gate conductor layers 11a and 11b are formed in order to perform self-alignment between the gate conductor layers 11a and 11b and the N + diffusion layer 6a serving as a signal line.
  • the N + -type silicon layer may be formed in the silicon pillar 1a between the gate conductor layers 11a and 11b and the N + diffusion layer 6a by using the ion doping or the deposited As-doped silicon oxide layer as a diffusion source.
  • the first semiconductor substrate 1 is etched to the surface of the first silicon oxide layer 3 to form the silicon pillar 1a. It may be stopped before reaching the surface of the layer 3.
  • an N + type silicon layer may be formed by doping a remaining silicon layer without being etched with a donor impurity.
  • arsenic (As) ion doping or deposition As doping is performed in order to perform self-alignment between the gate conductor layers 16a and 16b and the N + diffusion layer 6a serving as the source or drain.
  • An N + type silicon layer may be formed in the silicon pillar 1a between the gate conductor layers 16a and 16b and the N + diffusion layer 6a using the silicon oxide layer as a diffusion source.
  • the third silicon oxide layer 10a on the outer peripheral portion of the N-type silicon layers 12a and 12b constituting the photodiode, A conductor layer that reflects light through 10b may be formed. This prevents color mixing. Further, by forming a P + -type silicon layer connected to the P + -type silicon layer 13 a in the silicon pillar 1 a on the outer periphery of the N-type silicon layers 12 a and 12 b, it is possible to realize a low afterimage and low noise. Good. As described above, a structure in which the function of the solid-state imaging device is further enhanced can be appropriately formed in the silicon pillar 1a.
  • the present invention can be applied to a semiconductor device including a transistor in which a channel region is formed in a semiconductor having a columnar structure.

Abstract

A production method for a semiconductor device having: a step in which a conductive layer (7) and a first semiconductor layer (5a) including donor impurities or acceptor impurities are formed upon a first semiconductor substrate; a step in which a second insulating layer (8) is formed so as to cover the first semiconductor layer (5a); a step in which the thickness of the first semiconductor substrate (9) is reduced to a prescribed thickness; a step in which a columnar semiconductor (1a) having a columnar structure is formed from the first semiconductor substrate upon the first semiconductor layer (5a); a step in which a first semiconductor area (6a) is formed on the columnar semiconductor (1a) by scattering impurities from the first semiconductor layer (5a); and a step in which pixels for a solid-state imaging device are formed using the columnar semiconductor (1a) after the impurities have been scattered.

Description

半導体装置の製造方法、及び、半導体装置Semiconductor device manufacturing method and semiconductor device
　本発明は、半導体装置の製造方法、及び、半導体装置に関し、特に、柱状構造を有する半導体内にチャネル領域が形成されているトランジスタを備える半導体装置の製造方法、及び、半導体装置に関する。 The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a transistor in which a channel region is formed in a semiconductor having a columnar structure, and the semiconductor device.
　ＣＣＤ及びＣＭＯＳ型などの固体撮像装置はビデオカメラ、ステールカメラなどに広く用いられている。そして、固体撮像装置の高解像度化、高速動作化、及び高感度化などの性能向上が求められている。 Solid-state imaging devices such as CCD and CMOS type are widely used for video cameras, stale cameras and the like. Further, there is a demand for improved performance such as higher resolution, higher speed operation, and higher sensitivity of the solid-state imaging device.
　図１４に示されるように、１つの画素が１つの柱状半導体１１０内に構成されている固体撮像装置が知られている（例えば、特許文献１を参照）。
　この画素構造においては、半導体基板上に固体撮像装置の信号線として機能するＮ＋型シリコン層５１が形成されている。また、Ｎ＋型シリコン層５１に柱状半導体１１０が接続されている。その柱状半導体１１０には、Ｐ型シリコン層５２、絶縁膜５３ａ、５３ｂ、ゲート導体層５４ａ、５４ｂからなる、蓄積電荷を除去するためのＭＯＳトランジスタが形成されている。さらに、柱状半導体１１０には、このＭＯＳトランジスタに接続され、光（電磁エネルギー波）の照射によって発生する電荷を蓄積するフォトダイオードが形成されている。このフォトダイオードは、Ｐ型シリコン層５２とＮ型シリコン層５８ａ、５８ｂとから構成される。また、このフォトダイオードで囲まれたＰ型半導体５２をチャネル、フォトダイオードをゲート、フォトダイオード上に形成され、画素選択線５７ａ、５７ｂに接続されたＰ＋型シリコン層５６、Ｎ＋型シリコン層５１近傍のＰ型シリコン層５２を、それぞれ、ソース、ドレインとした接合トランジスタが形成されている。 As shown in FIG. 14, a solid-state imaging device in which one pixel is configured in one columnar semiconductor 110 is known (see, for example, Patent Document 1).
In this pixel structure, an N + type silicon layer 51 that functions as a signal line of a solid-state imaging device is formed on a semiconductor substrate. Further, the columnar semiconductor 110 is connected to the N + type silicon layer 51. The columnar semiconductor 110 is formed with a MOS transistor for removing accumulated charges, which includes a P-type silicon layer 52, insulating films 53a and 53b, and gate conductor layers 54a and 54b. Further, the columnar semiconductor 110 is formed with a photodiode that is connected to the MOS transistor and accumulates charges generated by irradiation with light (electromagnetic energy wave). This photodiode is composed of a P-type silicon layer 52 and N- type silicon layers 58a and 58b. In addition, a P + type silicon layer 56 and an N + type silicon layer formed on the P type semiconductor 52 surrounded by the photodiode as a channel, the photodiode as a gate, and the photodiode are connected to the pixel selection lines 57a and 57b. Junction transistors are formed using the P-type silicon layer 52 in the vicinity of 51 as a source and a drain, respectively.
　この固体撮像装置の基本動作は、光照射により発生した信号電荷（この場合は電子）をフォトダイオードに蓄積する信号電荷蓄積動作と、Ｎ＋型シリコン層５１近傍のＰ型シリコン層５２とＰ＋型シリコン層５６との間に流れるソース・ドレイン電流を、前述の蓄積信号電荷に応じたフォトダイオード電圧によるゲート電圧により変調し、これを信号電流として読み出す信号読み出し動作と、この信号読み出し動作の完了後、フォトダイオードに蓄積されている信号電荷を、ＭＯＳトランジスタのゲート導体層５４ａ、５４ｂにオン電圧を印加してＮ＋型シリコン層５１に除去するリセット動作とからなる。 The basic operation of this solid-state imaging device includes a signal charge accumulation operation in which signal charges (electrons in this case) generated by light irradiation are accumulated in a photodiode, and a P-type silicon layer 52 and P + in the vicinity of the N + -type silicon layer 51. A signal read operation for modulating the source / drain current flowing between the silicon layer 56 and the gate voltage by the photodiode voltage corresponding to the above-mentioned accumulated signal charge and reading this as a signal current, and completion of this signal read operation Thereafter, the signal charge accumulated in the photodiode is reset to remove the N + -type silicon layer 51 by applying an ON voltage to the gate conductor layers 54a and 54b of the MOS transistor.
　２次元固体撮像装置においては、図１４に示される画素が感光領域に２次元状に配列されている。そして、信号読み出し動作は、Ｎ＋型シリコン層５１を介して、画素信号（信号電流）が感光領域の周辺に設けられた出力回路に伝達されることにより行われる。また、リセット動作も、画素と感光領域の周辺回路との電気的伝送を介して行われる。そして、固体撮像装置の画素数、又は単位時間当たりの読出し画面数を増加させるには、信号読み出し動作の高速動作化が必要となる。このため、信号線であるＮ＋型シリコン層５１の電気抵抗の低減が求められる。 In the two-dimensional solid-state imaging device, the pixels shown in FIG. 14 are two-dimensionally arranged in the photosensitive area. The signal reading operation is performed by transmitting a pixel signal (signal current) to an output circuit provided around the photosensitive region via the N + type silicon layer 51. The reset operation is also performed through electrical transmission between the pixel and the peripheral circuit of the photosensitive region. In order to increase the number of pixels of the solid-state imaging device or the number of readout screens per unit time, it is necessary to increase the speed of the signal readout operation. For this reason, a reduction in electrical resistance of the N + type silicon layer 51 which is a signal line is required.
　このようなＮ＋型シリコン層５１の低電気抵抗化を実現するために、図１５Ａに示されるように、Ｎ＋型シリコン層５１の裏面に、シリコン基板６０上に形成した金属層５９を接合させた構造が考えられる。これにより信号線の電気抵抗は、金属層５９によってほぼ決定されるので、前述した信号読出し動作の高速動作化が実現される。しかし、Ｎ＋型シリコン層５１に接合させた金属層５９を形成することは、金属材料とシリコン材料との接合の親和性の観点から困難である。 To achieve the low electrical resistance of such N + -type silicon layer 51, as shown in FIG. 15A, on the rear surface of the N + -type silicon layer 51, the bonding metal layer 59 formed on the silicon substrate 60 Possible structures are possible. As a result, the electric resistance of the signal line is almost determined by the metal layer 59, so that the high-speed operation of the signal reading operation described above is realized. However, it is difficult to form the metal layer 59 bonded to the N + type silicon layer 51 from the viewpoint of the affinity of bonding between the metal material and the silicon material.
　また、シリコン基板６０上に金属層５９を形成するには、以下の方法が考えられる。即ち、図１５Ｂに示されるように、半導体基板６１上に酸化シリコン層６２を形成し、その酸化シリコン層６２上に金属層５９を形成する。そして、金属層５９が形成された半導体基板６１と半導体基板６４とを接着する。その後、半導体基板６４において、図１５Ｂにおいて破線で示した部分に画素を形成する。図１５Ｂに示される一点鎖線Ｄ－Ｄ’は半導体基板６４の研磨、エッチング、又は他の分離方法により、半導体基板６４を所定の高さに成形した状態を示している。 Also, the following method can be considered to form the metal layer 59 on the silicon substrate 60. That is, as shown in FIG. 15B, a silicon oxide layer 62 is formed on the semiconductor substrate 61, and a metal layer 59 is formed on the silicon oxide layer 62. Then, the semiconductor substrate 61 on which the metal layer 59 is formed and the semiconductor substrate 64 are bonded. Thereafter, pixels are formed in the portion of the semiconductor substrate 64 indicated by the broken line in FIG. 15B. A dot-dash line D-D ′ shown in FIG. 15B shows a state in which the semiconductor substrate 64 is formed to a predetermined height by polishing, etching, or other separation methods of the semiconductor substrate 64.
　しかしながら、このような製造方法では、金属層５９と半導体基板６４とが直接接着されるので、金属層５９と半導体基板６４との熱膨張係数の異なりによって、半導体基板６１、６４にソリ、クラック、又はハガレが発生してしまう。図１５Ａに示されるように、信号読出し動作の高速動作化のため、Ｎ＋型シリコン層５１の裏面に、ソリ、クラック、又はハガレの発生なく金属層５９を直接貼り合わせる方法を開発することには大きな技術的意義がある。 However, in such a manufacturing method, since the metal layer 59 and the semiconductor substrate 64 are directly bonded, due to the difference in thermal expansion coefficient between the metal layer 59 and the semiconductor substrate 64, the semiconductor substrates 61 and 64 are warped, cracked, Or peeling occurs. As shown in FIG. 15A, a method for directly bonding the metal layer 59 to the back surface of the N + -type silicon layer 51 without causing warpage, cracks, or peeling to increase the speed of the signal reading operation will be developed. Has great technical significance.
　そして、このような課題を解決することで、固体撮像装置以外の半導体装置や、半導体装置に設けられる回路素子の高集積化、高性能化を実現することが強く求められている。 Further, by solving such a problem, there is a strong demand to realize high integration and high performance of semiconductor devices other than solid-state imaging devices and circuit elements provided in the semiconductor devices.
　また、信号読出し動作の高速動作化のため、柱状構造を有する柱状半導体の側面をチャネル領域とするとともに、ゲート電極が当該チャネル領域を取り囲む構造を有する縦型のＭＯＳトランジスタであるＳＧＴ（Surrounding Gate Transistor）（以下、単に「ＳＧＴ」と省略する。）がある（例えば、特許文献２を参照）。 In addition, in order to increase the speed of signal readout operation, the side surface of a columnar semiconductor having a columnar structure is used as a channel region, and a vertical MOS transistor having a structure in which a gate electrode surrounds the channel region is an SGT (Surrounding Gate Transistor). (Hereinafter simply referred to as “SGT”) (see, for example, Patent Document 2).
　このようなＳＧＴでは、図１６に示されるように、埋め込み酸化膜基板６６上に平面状シリコン膜６７が形成され、平面状シリコン膜６７とＰＭＯＳ柱状シリコン層６８とによって柱状構造が形成されている。平面状シリコン膜６７にはドレインとして機能するＰ＋型シリコン拡散層６９が形成されている。ＰＭＯＳ柱状シリコン層６８の上部にはソースとして機能するＰ＋型シリコン拡散層７０が形成され、ＰＭＯＳ柱状シリコン層６８の外周部にはゲート絶縁層７１が形成されている。このゲート絶縁層７１の外周部にはゲート電極７２が形成されている。これにより、Ｐ＋型シリコン拡散層６９とＰ＋型シリコン拡散層７０との間のＰＭＯＳ柱状シリコン層６８をチャネルとしたＰ型チャネルＳＧＴが形成されている。 In such an SGT, as shown in FIG. 16, a planar silicon film 67 is formed on the buried oxide film substrate 66, and a columnar structure is formed by the planar silicon film 67 and the PMOS columnar silicon layer 68. . In the planar silicon film 67, a P + -type silicon diffusion layer 69 that functions as a drain is formed. A P + -type silicon diffusion layer 70 functioning as a source is formed on the PMOS columnar silicon layer 68, and a gate insulating layer 71 is formed on the outer periphery of the PMOS columnar silicon layer 68. A gate electrode 72 is formed on the outer periphery of the gate insulating layer 71. As a result, a P-type channel SGT is formed using the PMOS columnar silicon layer 68 as a channel between the P + -type silicon diffusion layer 69 and the P + -type silicon diffusion layer 70.
　また、ゲート電極７２、Ｐ＋型シリコン拡散層７０、及びＰ＋型シリコン拡散層６９を囲むように、窒化シリコン（ＳｉＮ）膜７３と酸化シリコン（ＳｉＯ２）膜７４とが形成されている。酸化シリコン層７４内にコンタクトホール７５が形成され、このコンタクトホール７５を介して、Ｐ＋型シリコン拡散層７０がソース金属配線７６に接続されている。これにより、１個のＭＯＳトランジスタが柱状構造に形成されている。 Further, a silicon nitride (SiN) film 73 and a silicon oxide (SiO 2 ) film 74 are formed so as to surround the gate electrode 72, the P + -type silicon diffusion layer 70, and the P + -type silicon diffusion layer 69. A contact hole 75 is formed in the silicon oxide layer 74, and the P + -type silicon diffusion layer 70 is connected to the source metal wiring 76 through the contact hole 75. Thereby, one MOS transistor is formed in a columnar structure.
　図１６に示されるＰ＋型シリコン拡散層６９は、平面状シリコン膜６７が同一平面上で延長された所定の部位で図示しない金属配線と接続されている。ＳＧＴを有する半導体装置において、更なる信号読出し動作の高速動作化を実現するには、このＰ＋型シリコン拡散層６９と上記金属配線との接続が、Ｐ＋型シリコン拡散層７０のように、短い距離で行われることが要求される。 The P + -type silicon diffusion layer 69 shown in FIG. 16 is connected to a metal wiring (not shown) at a predetermined portion where the planar silicon film 67 extends on the same plane. In a semiconductor device having SGT, in order to realize further high-speed signal readout operation, the connection between the P + -type silicon diffusion layer 69 and the metal wiring is as in the P + -type silicon diffusion layer 70. It is required to be performed at a short distance.
　しかしながら、図１６に示されるＳＧＴでは、上記金属配線とＰ＋型シリコン拡散層６９との間、又は、Ｐ＋型シリコン拡散層６９においてＳＧＴのチャネルのドレイン端までの距離に相当する電気抵抗が存在するようになる。このため、ＳＧＴを有する半導体装置においても、固体撮像装置と同様に、信号読出し動作の高速動作化を実現するには、Ｐ＋型シリコン拡散層６９の裏面に直接的に金属層を接合して電気抵抗の低下を図ることが必要になる。 However, in the SGT shown in FIG. 16, there is an electric resistance corresponding to the distance between the metal wiring and the P + -type silicon diffusion layer 69 or the drain end of the SGT channel in the P + -type silicon diffusion layer 69. It comes to exist. For this reason, even in a semiconductor device having SGT, as in the solid-state imaging device, in order to realize a high-speed signal reading operation, a metal layer is directly bonded to the back surface of the P + -type silicon diffusion layer 69. It is necessary to reduce the electrical resistance.
国際公開第２００９／０３４６２３号International Publication No. 2009/034623
米国特許出願公開第２０１０／０２１３５３９（Ａ１）号明細書US Patent Application Publication No. 2010/0213539 (A1)
　２次元固体撮像装置においては、上述したとおり、信号読み出し動作は、信号線として機能するＮ＋型シリコン層５１を介して、画素信号（信号電流）が感光領域の周辺に設けられ外部回路に伝達されることにより行われる。また、リセット動作も、画素と感光領域の外部回路との電気的伝送を介して行われる。この電気的伝送の応答性は、画素と周辺回路間とを接続する配線の電気抵抗と寄生容量とに大きく影響される。固体撮像装置の画素数、又は単位時間当たりの読出し画面数を増加させるには、そのような配線の電気抵抗の低減が求められる。 In the two-dimensional solid-state imaging device, as described above, in the signal readout operation, a pixel signal (signal current) is provided around the photosensitive region and transmitted to an external circuit via the N + type silicon layer 51 functioning as a signal line. Is done. The reset operation is also performed through electrical transmission between the pixel and an external circuit in the photosensitive area. The responsiveness of this electrical transmission is greatly influenced by the electrical resistance and parasitic capacitance of the wiring connecting the pixel and the peripheral circuit. In order to increase the number of pixels of the solid-state imaging device or the number of readout screens per unit time, it is necessary to reduce the electrical resistance of such wiring.
　図１４に示される固体撮像装置においては、そのような電気抵抗は、Ｎ＋型シリコン層５１の電気抵抗によってほぼ決定される。Ｎ＋型シリコン層５１はシリコン（Ｓｉ）半導体にリン（Ｐ）やヒ素（Ａｓ）などのドナー不純物をイオンドーピング（イオン注入）することで形成されるため、このＮ＋型シリコン層５１の電気抵抗値は、アルミニウム（Ａｌ）、銅（Ｃｕ）、タングステン（Ｗ）、ニッケル（Ｎｉ）など通常の半導体装置に使用されている金属の電気抵抗値よりも小さくすることができない。このため、図１４に示される固体撮像装置では、金属配線によって画素と周辺回路との間の電気的接続を行う固体撮像装置と比較して、高速動作特性に劣る問題がある。 In the solid-state imaging device shown in FIG. 14, such an electric resistance is substantially determined by the electric resistance of the N + type silicon layer 51. Since N + -type silicon layer 51 is formed a donor impurity in silicon (Si) semiconductor, such as phosphorus (P), arsenic (As) by ion doping (ion implantation), electrical of the N + -type silicon layer 51 The resistance value cannot be made smaller than the electrical resistance value of a metal used in a normal semiconductor device such as aluminum (Al), copper (Cu), tungsten (W), nickel (Ni). For this reason, the solid-state imaging device shown in FIG. 14 has a problem inferior in high-speed operation characteristics as compared with a solid-state imaging device that performs electrical connection between a pixel and a peripheral circuit by a metal wiring.
　また、画素内でＮ＋多結晶シリコン層を横方向に拡張するとともに、この拡張領域に形成されたコンタクトホールを用いて構成した金属配線によって画素と周辺回路との電気的接続を行う画素構造では、画素の集積度が低下するようになる。 In addition, in the pixel structure in which the N + polycrystalline silicon layer is expanded in the horizontal direction in the pixel and the pixel and the peripheral circuit are electrically connected by the metal wiring formed using the contact hole formed in the extended region. As a result, the degree of integration of the pixels decreases.
　また、上述したように、図１６に示されるＳＧＴにおいても、Ｐ＋型シリコン拡散層６９は平面状シリコン膜６７が延長された部位で金属配線と接続される。このようなＰ＋型シリコン拡散層６９と金属配線との接続による手段では、Ｐ＋型シリコン拡散層７０のように金属配線と短い距離で接続することができないので、金属配線とＳＧＴのチャネルに最も近接したＰ＋型シリコン拡散層６９の端部までに相当の電気抵抗が存在するようになる。このため、ＳＧＴを有する半導体装置において、更なる信号読出し動作の高速動作化を実現するには、この電気抵抗を低減することが必要になる。 Further, as described above, also in the SGT shown in FIG. 16, the P + -type silicon diffusion layer 69 is connected to the metal wiring at the portion where the planar silicon film 67 is extended. Such means by connecting the P + -type silicon diffusion layer 69 and the metal wiring cannot be connected to the metal wiring at a short distance as in the P + -type silicon diffusion layer 70, so that the metal wiring and the SGT channel are not connected. A considerable electrical resistance is present up to the end of the closest P + -type silicon diffusion layer 69. For this reason, in the semiconductor device having SGT, it is necessary to reduce this electric resistance in order to realize further high-speed signal reading operation.
　本発明は、上述した事情に鑑みてなされたものであり、高集積、高速動作が実現される半導体装置を提供することを目的とする。 The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a semiconductor device capable of realizing high integration and high speed operation.
　上記目的を達成するため、本発明の第１の観点に係る半導体装置の製造方法は、
　半導体基板上に第１の絶縁層を形成する第１絶縁層形成工程と、
　前記第１の絶縁層の所定の部分を除去し、絶縁層除去領域を形成する絶縁層除去工程と、
　少なくとも前記絶縁層除去領域を覆うように、前記半導体基板上にドナー不純物又はアクセプタ不純物を含む第１の半導体層を形成する第１半導体層形成工程と、
　前記第１の半導体層上に導電層を形成する導電層形成工程と、
　前記導電層及び前記第１の半導体層を所定の形状に成形する成形工程と、
　前記所定の形状に形成した導電層及び第１の半導体層を覆うように、第２の絶縁層を形成する第２絶縁層形成工程と、
　前記第２の絶縁層の表面を平坦化する平坦化工程と、
　前記平坦化された前記第２の絶縁層の表面に、基板を接着する接着工程と、
　前記半導体基板を所定の厚さまで薄くする薄膜化工程と、
　前記第１の半導体層上に、前記半導体基板から柱状構造を有する柱状半導体を形成する柱状半導体形成工程と、
　前記柱状半導体に前記回路素子を形成する回路素子形成工程と、を備え、
　少なくとも前記第１半導体層形成工程以後に、前記ドナー不純物又はアクセプタ不純物を含む前記第１の半導体層から当該不純物を拡散させることで前記柱状半導体に第１の半導体領域を形成する第１半導体領域形成工程をさらに備える、
　ことを特徴とする半導体装置の製造方法。 In order to achieve the above object, a method of manufacturing a semiconductor device according to the first aspect of the present invention includes:
A first insulating layer forming step of forming a first insulating layer on the semiconductor substrate;
An insulating layer removing step of removing a predetermined portion of the first insulating layer to form an insulating layer removal region;
A first semiconductor layer forming step of forming a first semiconductor layer containing a donor impurity or an acceptor impurity on the semiconductor substrate so as to cover at least the insulating layer removal region;
A conductive layer forming step of forming a conductive layer on the first semiconductor layer;
A molding step of molding the conductive layer and the first semiconductor layer into a predetermined shape;
A second insulating layer forming step of forming a second insulating layer so as to cover the conductive layer and the first semiconductor layer formed in the predetermined shape;
A planarization step of planarizing the surface of the second insulating layer;
An adhesion step of adhering a substrate to the flattened surface of the second insulating layer;
A thinning process for thinning the semiconductor substrate to a predetermined thickness;
Forming a columnar semiconductor having a columnar structure from the semiconductor substrate on the first semiconductor layer; and
A circuit element forming step of forming the circuit element on the columnar semiconductor,
Forming a first semiconductor region in the columnar semiconductor by diffusing the impurity from the first semiconductor layer containing the donor impurity or acceptor impurity at least after the first semiconductor layer forming step The process further includes
A method for manufacturing a semiconductor device.
　前記回路素子形成工程は、
　前記柱状半導体の外周部に第３の絶縁層を形成するとともに、前記第３の絶縁層の外周部にゲート導体層を形成する工程と、
　前記ゲート導体層の上方部位かつ前記柱状半導体の表層部に、前記第１の半導体領域と同一導電型である第４の半導体領域を形成する工程と、
　前記柱状半導体において、前記第３の絶縁層の上方部位に、前記第１の半導体領域と反対導電型の第３の半導体領域を形成する工程と、を含む、ことが好ましい。 The circuit element forming step includes
Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer;
Forming a fourth semiconductor region having the same conductivity type as the first semiconductor region in a portion above the gate conductor layer and in a surface layer portion of the columnar semiconductor;
Preferably, the columnar semiconductor includes a step of forming a third semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the third insulating layer.
　前記回路素子形成工程は、
　前記柱状半導体の外周部に第３の絶縁層を形成するとともに、前記第３の絶縁層の外周部にゲート導体層を形成する工程と、
　前記柱状半導体における前記第３の絶縁層の上方部位に、前記第１の半導体領域と同一導電型の第５の半導体領域を形成する工程と、を含む、ことが好ましい。 The circuit element forming step includes
Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer;
And forming a fifth semiconductor region having the same conductivity type as that of the first semiconductor region at a position above the third insulating layer in the columnar semiconductor.
　前記回路素子形成工程は、
　前記柱状半導体の上方部位に、前記第１の半導体領域と反対導電型の第６の半導体領域を形成する工程を含む、ことが好ましい。 The circuit element forming step includes
Preferably, the method includes a step of forming a sixth semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the columnar semiconductor.
　前記第１半導体層形成工程は、前記第１の半導体層と同層に、電気抵抗として機能する第２の半導体層を形成する工程を含む、ことが好ましい。 Preferably, the first semiconductor layer forming step includes a step of forming a second semiconductor layer functioning as an electric resistance in the same layer as the first semiconductor layer.
　前記第１半導体層形成工程は、容量電極として機能する前記第１の半導体層上の所定の領域に容量絶縁膜として機能する絶縁膜を形成する工程を含み、
　前記導電層形成工程は、前記絶縁膜上に、前記第１の半導体層と共に容量電極として機能する導電層を形成する工程を含む、ことが好ましい。 The first semiconductor layer forming step includes a step of forming an insulating film functioning as a capacitor insulating film in a predetermined region on the first semiconductor layer functioning as a capacitor electrode;
The conductive layer forming step preferably includes a step of forming a conductive layer functioning as a capacitor electrode together with the first semiconductor layer on the insulating film.
　前記第１絶縁層形成工程は、前記半導体基板上に、第１の絶縁層と共に第４の絶縁層を形成するとともに、予め設定した容量形成領域に、前記第４の絶縁層よりも厚さが薄く、容量絶縁膜として機能する第５の絶縁層を形成する工程を含み、
　前記導電層形成工程は、前記第５の絶縁層上に、容量電極として機能する導電層を形成する工程を含み、
　前記絶縁層除去工程は、前記容量形成領域に、ドナー不純物又はアクセプタ不純物を有し、容量電極として機能する不純物層を形成する容量形成工程を含む、ことが好ましい。 The first insulating layer forming step forms a fourth insulating layer together with the first insulating layer on the semiconductor substrate, and has a thickness larger than that of the fourth insulating layer in a preset capacitance forming region. Forming a thin fifth insulating layer functioning as a capacitive insulating film,
The conductive layer forming step includes a step of forming a conductive layer functioning as a capacitor electrode on the fifth insulating layer,
The insulating layer removing step preferably includes a capacitor forming step of forming an impurity layer having a donor impurity or an acceptor impurity in the capacitor forming region and functioning as a capacitor electrode.
　前記半導体基板上にマスク合わせマーク形成領域を設定するマスク合わせマーク形成領域設定工程と、
　前記マスク合わせマーク形成領域に、マスク合わせ孔を形成し、前記絶縁層除去領域、前記第１の絶縁層及び前記導電層の少なくとも一つを露出させる工程と、
　前記マスク合わせ孔を通して、前記絶縁層除去領域、前記第１の絶縁層及び前記導電層の内の少なくとも一つからなるマスク合わせマークを形成するマスク合わせマーク形成工程と、
　前記マスク合わせマークを基準として、フォトマスクのマスク合わせを行うマスク合わせ工程と、をさらに備える、ことが好ましい。 A mask alignment mark formation region setting step for setting a mask alignment mark formation region on the semiconductor substrate;
Forming a mask alignment hole in the mask alignment mark formation region to expose at least one of the insulating layer removal region, the first insulating layer, and the conductive layer;
A mask alignment mark forming step of forming a mask alignment mark comprising at least one of the insulating layer removal region, the first insulating layer, and the conductive layer through the mask alignment hole;
It is preferable that the method further includes a mask alignment step of performing mask alignment of the photomask with the mask alignment mark as a reference.
　前記マスク合わせ孔に透明絶縁体を埋め込む工程をさらに備え、
　前記マスク合わせマーク形成工程では、前記透明絶縁体を通して、前記絶縁層除去領域、前記第１の絶縁層及び前記導電層の内の少なくとも一つからなるマスク合わせマークを形成し、
　前記マスク合わせ工程では、前記マスク合わせマークを基準として、フォトマスクのマスク合わせを行う、ことが好ましい。 A step of embedding a transparent insulator in the mask alignment hole;
In the mask alignment mark forming step, a mask alignment mark comprising at least one of the insulating layer removal region, the first insulating layer, and the conductive layer is formed through the transparent insulator,
In the mask alignment step, it is preferable that mask alignment of a photomask is performed using the mask alignment mark as a reference.
　前記絶縁層除去工程と、前記第１半導体層形成工程との間に、前記絶縁層除去領域を覆うように、ドナー不純物及びアクセプタ不純物がドープされていない第２の半導体層を形成する工程をさらに備える、ことが好ましい。 Forming a second semiconductor layer not doped with donor impurities and acceptor impurities so as to cover the insulating layer removal region between the insulating layer removing step and the first semiconductor layer forming step; It is preferable to provide.
　本発明の第２の観点に係る半導体装置は、本発明の第１の観点に係る半導体装置の製造方法によって製造される半導体装置であって、
　前記柱状半導体は、
　前記第１の半導体領域上に形成された当該第１の半導体領域と反対導電型の半導体又は固有半導体からなる第２の半導体領域を備え、
　前記第２の半導体領域と前記第４の半導体領域とから電磁エネルギー波の照射により発生する信号電荷を蓄積するダイオードが形成され、
　前記ダイオードがゲートとして機能し、前記第１の半導体領域と前記第３の半導体領域のいずれか一方がソース、他方がドレインとしてそれぞれ機能し、かつ、前記第２の半導体領域に形成されたチャネルを流れるとともに前記ダイオードに蓄積された信号電荷量に応じて変化する電流を信号取り出し手段によって取り出し可能とされた接合トランジスタが形成され、
　前記ゲート導体層がゲートとして機能するとともに、前記第１の半導体領域及び前記第４の半導体領域の一方がソースとして機能し、他方がドレインとして機能するＭＯＳトランジスタによって、前記ゲート導体層に電圧が印加されることで、前記ダイオードに蓄積された信号電荷を前記第１の半導体領域に除去する信号電荷除去手段が形成されている、ことを特徴とする。 A semiconductor device according to a second aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
The columnar semiconductor is
A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor;
A diode that accumulates signal charges generated by irradiation of electromagnetic energy waves from the second semiconductor region and the fourth semiconductor region is formed,
The diode functions as a gate, one of the first semiconductor region and the third semiconductor region functions as a source, the other functions as a drain, and a channel formed in the second semiconductor region. A junction transistor is formed that is capable of taking out a current that flows and changes in accordance with the amount of signal charge accumulated in the diode by a signal taking-out means,
The gate conductor layer functions as a gate, and a voltage is applied to the gate conductor layer by a MOS transistor in which one of the first semiconductor region and the fourth semiconductor region functions as a source and the other functions as a drain. Thus, signal charge removing means for removing the signal charge accumulated in the diode in the first semiconductor region is formed.
　本発明の第３の観点に係る半導体装置は、本発明の第１の観点に係る半導体装置の製造方法によって製造される半導体装置であって、
　前記柱状半導体は、
　前記第１の半導体領域上に形成された当該第１の半導体領域と反対導電型又は固有半導体からなる第２の半導体領域を備え、
　前記ゲート導体層がゲートとして機能するとともに、前記第１の半導体領域及び前記第５の半導体領域の一方がソースとして機能し、他方がドレインとして機能するＭＯＳトランジスタが形成されている、ことを特徴とする。 A semiconductor device according to a third aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
The columnar semiconductor is
A second semiconductor region formed on the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region or an intrinsic semiconductor;
The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain. To do.
　本発明の第４の観点に係る半導体装置は、本発明の第１の観点に係る半導体装置の製造方法によって製造される半導体装置であって、
　前記柱状半導体は、
　前記第１の半導体領域と第６の半導体領域との間に、前記第１の半導体領域と反対導電型又は固有半導体からなる第２の半導体領域を備え、
　前記第２の半導体領域と、前記第６の半導体領域と、からダイオードが形成されている、ことを特徴とする。 A semiconductor device according to a fourth aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
The columnar semiconductor is
Between the first semiconductor region and the sixth semiconductor region, a second semiconductor region made of a conductive type or a specific semiconductor opposite to the first semiconductor region is provided,
A diode is formed from the second semiconductor region and the sixth semiconductor region.
　本発明の第５の観点に係る半導体装置は、本発明の第１の観点に係る半導体装置の製造方法によって製造される半導体装置であって、
　前記第１の半導体層上に複数の前記柱状半導体が形成されており、
　前記複数の柱状半導体は、前記第１の半導体領域にアクセプタ不純物がドープされている複数の第１の柱状半導体と、前記第１の半導体領域にドナー不純物がドープされている複数の第２の柱状半導体とからなる、ことを特徴とする。 A semiconductor device according to a fifth aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
The plurality of columnar semiconductors include a plurality of first columnar semiconductors in which the first semiconductor region is doped with an acceptor impurity, and a plurality of second columnar semiconductors in which the first semiconductor region is doped with a donor impurity. It consists of a semiconductor.
　本発明の第６の観点に係る半導体装置は、本発明の第１の観点に係る半導体装置の製造方法によって製造される半導体装置であって、
　前記第１の半導体層上に複数の前記柱状半導体が形成されており、
　前記複数の柱状半導体における、複数の前記第１の半導体領域、及び、複数の前記導電層の内の両方、又は、一方が互いに接続されている、ことを特徴とする。 A semiconductor device according to a sixth aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
In the plurality of columnar semiconductors, both or one of the plurality of first semiconductor regions and the plurality of conductive layers are connected to each other.
　本発明の第７の観点に係る半導体装置は、本発明の第１の観点に係る半導体装置の製造方法によって製造される半導体装置であって、
　前記第１の半導体層上に複数の前記柱状半導体が形成されており、
　前記各柱状半導体は、
　前記第１の半導体領域上に形成された当該第１の半導体領域と反対導電型の半導体又は固有半導体からなる第２の半導体領域と、
　前記第２の半導体領域上に形成された第５の半導体領域と、
　前記第２の半導体領域の外周部に形成された第３の絶縁層と、
　前記第３の絶縁層の外周部に形成されたゲート導体層と、を備え、
　前記ゲート導体層がゲートとして機能するとともに、前記第１の半導体領域及び前記第５の半導体領域の一方がソースとして機能し、他方がドレインとして機能するＭＯＳトランジスタが形成され、
　前記第１の半導体層は、前記複数の柱状半導体に亘って連続して繋がるように形成されているとともに、前記繋がるように形成された前記第１の半導体層は、絶縁層に形成されたコンタクトホールを介して、外部回路に接続するための配線層に接続されている、ことを特徴とする。 A semiconductor device according to a seventh aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
Each of the columnar semiconductors is
A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor;
A fifth semiconductor region formed on the second semiconductor region;
A third insulating layer formed on the outer periphery of the second semiconductor region;
A gate conductor layer formed on the outer periphery of the third insulating layer,
The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
The first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer formed so as to be connected is a contact formed on an insulating layer. It is connected to a wiring layer for connecting to an external circuit through a hole.
　本発明の第８の観点に係る半導体装置は、本発明の第１の観点に係る半導体装置の製造方法によって製造される半導体装置であって、
　前記第１の半導体層上に複数の前記柱状半導体が形成されており、
　前記各柱状半導体は、
　前記第１の半導体領域上に形成された当該第１の半導体領域と反対導電型の半導体又は固有半導体からなる第２の半導体領域と、
　前記第２の半導体領域上に形成された第５の半導体領域と、
　前記第２の半導体領域の外周部に形成された第３の絶縁層と、
　前記第３の絶縁層の外周部に形成されたゲート導体層と、を備え、
　前記ゲート導体層がゲートとして機能するとともに、前記第１の半導体領域及び前記第５の半導体領域の一方がソースとして機能し、他方がドレインとして機能するＭＯＳトランジスタが形成され、
　前記第１の半導体層は、前記複数の柱状半導体に亘って連続して繋がるように形成されているとともに、前記第１の半導体層は、絶縁層に形成されたコンタクトホールを介して、所定のトランジスタのゲートに接続するための配線層に接続されていることを特徴とする。 A semiconductor device according to an eighth aspect of the present invention is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
A plurality of the columnar semiconductors are formed on the first semiconductor layer;
Each of the columnar semiconductors is
A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor;
A fifth semiconductor region formed on the second semiconductor region;
A third insulating layer formed on the outer periphery of the second semiconductor region;
A gate conductor layer formed on the outer periphery of the third insulating layer,
The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
The first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer is connected to a predetermined hole via a contact hole formed in the insulating layer. It is connected to a wiring layer for connecting to the gate of the transistor.
　本発明によれば、高集積化、高速動作化が実現される半導体装置を提供することができる。 According to the present invention, it is possible to provide a semiconductor device in which high integration and high speed operation are realized.
本発明の第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment of this invention. 第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１実施形態に係る固体撮像装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 本発明の第２実施形態に係るＮチャネル型ＳＧＴの構造を示す断面図である。It is sectional drawing which shows the structure of N channel type | mold SGT which concerns on 2nd Embodiment of this invention. 本発明の第３実施形態に係る、Ｎチャネル型ＳＧＴとＰチャネル型ＳＧＴとを同一基板上に形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form N channel type | mold SGT and P channel type | mold SGT on the same board | substrate based on 3rd Embodiment of this invention. 第３実施形態に係る、Ｎチャネル型ＳＧＴとＰチャネル型ＳＧＴとを同一基板上に形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form N channel type SGT and P channel type SGT on the same board | substrate based on 3rd Embodiment. 本発明の第４実施形態に係る、複数のＳＧＴが金属配線層で接続される構造を有する半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which has the structure where several SGT is connected by a metal wiring layer based on 4th Embodiment of this invention. 本発明の第５実施形態に係る、半導体装置に電気抵抗を形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form an electrical resistance in the semiconductor device based on 5th Embodiment of this invention. 第５実施形態に係る、半導体装置に電気抵抗を形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form an electrical resistance in the semiconductor device based on 5th Embodiment. 第５実施形態に係る、半導体装置に電気抵抗を形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form an electrical resistance in the semiconductor device based on 5th Embodiment. 本発明の第６実施形態に係る、半導体装置に容量を形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form a capacity | capacitance in the semiconductor device based on 6th Embodiment of this invention. 第６実施形態に係る、半導体装置に容量を形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form a capacity | capacitance in the semiconductor device based on 6th Embodiment. 第６実施形態に係る、半導体装置に容量を形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form a capacity | capacitance in the semiconductor device based on 6th Embodiment. 本発明の第７実施形態に係る、半導体装置に容量を形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form a capacity | capacitance in the semiconductor device based on 7th Embodiment of this invention. 第７実施形態に係る、半導体装置に容量を形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form a capacity | capacitance in the semiconductor device based on 7th Embodiment. 本発明の第８実施形態に係る、半導体装置にダイオードを形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form a diode in the semiconductor device based on 8th Embodiment of this invention. 第８実施形態に係る、半導体装置にダイオードを形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form a diode in the semiconductor device based on 8th Embodiment. 第８実施形態の変形例に係る、半導体装置にＰＩＮダイオードを形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form a PIN diode in the semiconductor device based on the modification of 8th Embodiment. 本発明の第９実施形態に係るＣＭＯＳインバータ回路を説明するための回路図である。It is a circuit diagram for demonstrating the CMOS inverter circuit which concerns on 9th Embodiment of this invention. 第９実施形態に係るＣＭＯＳインバータ回路を説明するための回路平面配置図である。It is a circuit plane layout for demonstrating the CMOS inverter circuit which concerns on 9th Embodiment. 第９実施形態に係る、半導体装置にＣＭＯＳインバータ回路を形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form a CMOS inverter circuit in the semiconductor device based on 9th Embodiment. 本発明の第１０実施形態に係る、２段構造のＣＭＯＳインバータ回路を説明するための回路図である。It is a circuit diagram for demonstrating the CMOS inverter circuit of the 2 step | paragraph structure based on 10th Embodiment of this invention. 第１０実施形態に係る、２段構造のＣＭＯＳインバータ回路を説明するための回路平面配置図である。FIG. 20 is a circuit plan view for explaining a two-stage CMOS inverter circuit according to a tenth embodiment. 第１０実施形態に係る、２段構造のＣＭＯＳインバータ回路を形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method of forming the CMOS inverter circuit of the 2 step | paragraph structure based on 10th Embodiment. 本発明の第１１実施形態に係る、シリコン柱の位置精度を高める方法を説明するための断面図である。It is sectional drawing for demonstrating the method to improve the positional accuracy of a silicon pillar based on 11th Embodiment of this invention. 第１１実施形態に係る、半導体基板にマスク合わせマークを形成する方法を説明するための断面図である。It is sectional drawing for demonstrating the method to form a mask alignment mark in the semiconductor substrate based on 11th Embodiment. 第１１実施形態の変形例に係る、シリコン柱の位置精度を高める製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method which raises the position accuracy of a silicon pillar based on the modification of 11th Embodiment. 本発明の第１２実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 12th Embodiment of this invention. 第１２実施形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 12th Embodiment. 従来例の固体撮像装置の画素の構造を示す断面図である。It is sectional drawing which shows the structure of the pixel of the solid-state imaging device of a prior art example. 従来例の固体撮像装置を高速動作させる画素の断面図である。It is sectional drawing of the pixel which operates the solid-state imaging device of a prior art example at high speed. 従来例の固体撮像装置を高速動作させる画素を得るための半導体基板の接着工程を説明するための図である。It is a figure for demonstrating the adhesion process of the semiconductor substrate for obtaining the pixel which operates the solid-state imaging device of a prior art example at high speed. 従来例のＳＧＴを有する画素の断面図である。It is sectional drawing of the pixel which has SGT of a prior art example.
　以下、本発明の実施形態に係る半導体装置の製造方法について、図１～図１３の図面を参照しながら説明する。 Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings of FIGS.
（第１実施形態）
　図１Ａ～図１Ｌに、本発明の第１実施形態に係る、固体撮像装置の製造方法を示す。
　本実施形態に係る固体撮像装置の製造方法においては、図１Ａに示されるように、Ｐ型シリコンからなる第１の半導体基板１の所定の深さに、高濃度水素イオン（Ｈ＋）をイオンドープすることによって、第１の半導体基板１を上下の２つの部分に分離するための分離層２を形成する（非特許文献２参照）。また、第１の半導体基板１上に、熱酸化又はＣＶＤ（Chemical Vapor Deposition)法によって、絶縁膜である第１酸化シリコン層３を形成する。なお、第１の半導体基板１は、Ｐ型シリコンの代わりに、実質的に不純物を含まない固有半導体（ｉ型シリコン）であってもよい。 (First embodiment)
1A to 1L show a method for manufacturing a solid-state imaging device according to the first embodiment of the present invention.
In the method for manufacturing a solid-state imaging device according to the present embodiment, as shown in FIG. 1A, high-concentration hydrogen ions (H + ) are ionized at a predetermined depth of the first semiconductor substrate 1 made of P-type silicon. By doping, a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed (see Non-Patent Document 2). A first silicon oxide layer 3 that is an insulating film is formed on the first semiconductor substrate 1 by thermal oxidation or CVD (Chemical Vapor Deposition). The first semiconductor substrate 1 may be a unique semiconductor (i-type silicon) that does not substantially contain impurities, instead of P-type silicon.
　続いて、図１Ｂに示されるように、第１酸化シリコン層３において、固体撮像装置の信号線用ドレインが形成される部分に相当する酸化シリコン（ＳｉＯ２）を除去することで孔４を形成する。この酸化シリコンが除去された領域（孔４）は、酸化シリコン層除去領域４８となる（図１１Ａ、図１３Ａ参照）。 Subsequently, as shown in FIG. 1B, the hole 4 is formed by removing silicon oxide (SiO 2 ) corresponding to the portion where the signal line drain of the solid-state imaging device is formed in the first silicon oxide layer 3. To do. The region (hole 4) from which the silicon oxide has been removed becomes the silicon oxide layer removal region 48 (see FIGS. 11A and 13A).
　続いて、図１Ｂに示されるように、この孔４を覆うように、第１酸化シリコン層３及び第１の半導体基板１の上に、ＣＶＤ法によって多結晶シリコン層５を形成する。 Subsequently, as shown in FIG. 1B, a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3 and the first semiconductor substrate 1 by the CVD method so as to cover the hole 4.
　続いて、図１Ｃに示されるように、この多結晶シリコン層５に、リン（Ｐ）又はヒ素（Ａｓ）などのドナー不純物をイオンドープすることで、第１の半導体基板１及び第１酸化シリコン層３上に、固体撮像装置の信号線となるＮ＋多結晶シリコン層５ａを形成する。 Subsequently, as shown in FIG. 1C, the polycrystalline silicon layer 5 is ion-doped with a donor impurity such as phosphorus (P) or arsenic (As), thereby the first semiconductor substrate 1 and the first silicon oxide. On the layer 3, an N + polycrystalline silicon layer 5 a serving as a signal line of the solid-state imaging device is formed.
　続いて、図１Ｄに示されるように、Ｎ＋多結晶シリコン層５ａ上に、蒸着法又はＣＶＤ法によって、タングステン（Ｗ）、タングステン・シリサイド（ＷＳｉ）、ニッケル（Ｎｉ）、ニッケルシリサイド（ＮｉＳｉ）などからなる単層、又は、これらの層が複数積層されてなる金属層７を形成する。 Subsequently, as shown in FIG. 1D, tungsten (W), tungsten silicide (WSi), nickel (Ni), nickel silicide (NiSi) is deposited on the N + polycrystalline silicon layer 5a by vapor deposition or CVD. Or a metal layer 7 formed by laminating a plurality of these layers.
　続いて、図１Ｅに示されるように、マスクを用いたエッチング処理によって、Ｎ＋多結晶シリコン層５ａ及び金属層７において孔４を埋め込んでいる部分が残存するように、Ｎ＋多結晶シリコン層５ａ及び金属層７を所定の形状に成形する。このＮ＋多結晶シリコン層５ａ上には、固体撮像装置の画素における接合トランジスタのソース又はドレインが形成される。 Subsequently, as shown in FIG. 1E, by an etching process using a mask, as in N + polysilicon layer 5a and the metal layer 7 is part that embeds the hole 4 remaining, N + polycrystalline silicon layer The 5a and the metal layer 7 are formed into a predetermined shape. On the N + polycrystalline silicon layer 5a, the source or drain of the junction transistor in the pixel of the solid-state imaging device is formed.
　続いて、図１Ｆに示されるように、Ｎ＋多結晶シリコン層５ａ、金属層７及び第１酸化シリコン層３を覆うように、ＣＶＤ法によって絶縁膜である第２酸化シリコン層８を形成する。そして、その第２酸化シリコン層８の表面をＣＭＰ（Chemical Mechanical Polishing；化学機械的研磨）によって平坦化する。 Subsequently, as shown in FIG. 1F, a second silicon oxide layer 8 that is an insulating film is formed by a CVD method so as to cover the N + polycrystalline silicon layer 5a, the metal layer 7, and the first silicon oxide layer 3. . Then, the surface of the second silicon oxide layer 8 is planarized by CMP (Chemical Mechanical Polishing).
　続いて、図１Ｇに示されるように、シリコン（Ｓｉ）からなり、表面が平坦化された第２半導体基板９を用意し、その第２半導体基板９の平坦化された表面と第２酸化シリコン層８の平坦化された表面同士を圧着によって接着する。この接着処理では、互いの熱膨張率の差異が小さい、第２半導体基板９におけるシリコン層と、第２酸化シリコン層８におけるシリコン層とが互いに接着されるので、両接着部材の熱膨張係数の異なりによる、ソリ、クラック、ハガレが発生しにくい積層構造が得られる。 Subsequently, as shown in FIG. 1G, a second semiconductor substrate 9 made of silicon (Si) and having a planarized surface is prepared, and the planarized surface of the second semiconductor substrate 9 and the second silicon oxide are prepared. The planarized surfaces of the layer 8 are bonded together by pressure bonding. In this bonding process, the difference in thermal expansion coefficient between the silicon layer in the second semiconductor substrate 9 and the silicon layer in the second silicon oxide layer 8 are bonded to each other. Due to the difference, it is possible to obtain a laminated structure in which warpage, cracking and peeling are unlikely to occur.
　続いて、図１Ｈに示されるように、４００～６００℃の熱処理によって、第１の半導体基板１において、分離層２を境界として下方の部分を除去して第１の半導体基板１を所定の厚さまで薄くする（図１Ｈでは、図１Ａ～図１Ｇと図面の上下関係を反転表示している。）。ここで、Ｎ＋多結晶シリコン層５ａは、図１４に示されるＮ＋型シリコン層５１に対応するものであり、本実施形態では、Ｎ＋多結晶シリコン層５ａには、その全ての形成領域に亘って金属層７が接合されている。 Subsequently, as shown in FIG. 1H, by heat treatment at 400 to 600 ° C., the lower portion of the first semiconductor substrate 1 with the separation layer 2 as a boundary is removed to remove the first semiconductor substrate 1 to a predetermined thickness. (In FIG. 1H, the vertical relationship between FIGS. 1A to 1G and the drawing is highlighted.) Here, the N + polycrystalline silicon layer 5a corresponds to the N + type silicon layer 51 shown in FIG. 14, and in this embodiment, the N + polycrystalline silicon layer 5a includes all of its formation regions. The metal layer 7 is joined over the entire area.
　続いて、図１Ｉに示されるように、第１の半導体基板１において、Ｎ＋多結晶シリコン層５ａの直上領域のシリコン層が残存するように、当該直上領域におけるシリコン層以外の領域のシリコン層をエッチングによって除去する。これにより、柱状構造を有するシリコン（Ｓｉ）柱１ａを形成する。このシリコン柱１ａは、図１Ｋ、図１Ｌなどに示されるＰ型シリコン層３０となる。 Subsequently, as shown in FIG. 1I, in the first semiconductor substrate 1, the silicon layer in the region other than the silicon layer in the region directly above so that the silicon layer in the region immediately above the N + polycrystalline silicon layer 5 a remains. Are removed by etching. Thereby, a silicon (Si) pillar 1a having a pillar structure is formed. The silicon pillar 1a becomes a P-type silicon layer 30 shown in FIGS. 1K, 1L and the like.
　続いて、図１Ｊに示されるように、熱処理を行い、Ｎ＋多結晶シリコン層５ａからシリコン柱１ａにドナー不純物を熱拡散させ、シリコン柱１ａの下方部分にＮ＋拡散層６ａを形成する。 Subsequently, as shown in FIG. 1J, heat treatment is performed to thermally diffuse the donor impurity from the N + polycrystalline silicon layer 5a to the silicon pillar 1a, thereby forming the N + diffusion layer 6a in the lower part of the silicon pillar 1a.
　続いて、図１Ｋに示されるように、熱酸化を行い、シリコン柱１ａの外周部に、絶縁体である第３酸化シリコン層１０ａ、１０ｂを形成する。さらに、蒸着法又はＣＶＤ法によって、第３酸化シリコン層１０ａ、１０ｂの外周部にゲート導体層１１ａ、１１ｂを形成する。 Subsequently, as shown in FIG. 1K, thermal oxidation is performed to form third silicon oxide layers 10a and 10b that are insulators on the outer periphery of the silicon pillar 1a. Further, gate conductor layers 11a and 11b are formed on the outer peripheral portions of the third silicon oxide layers 10a and 10b by vapor deposition or CVD.
　続いて、図１Ｋに示されるように、ゲート導体層１１ａ、１１ｂの上方部位かつシリコン柱１ａの表層部に、リン（Ｐ）やヒ素（Ａｓ）などのドナー不純物をイオンドーピングすることでＮ型シリコン層１２ａ、１２ｂを形成する。このＮ型シリコン層１２ａ、１２ｂと、シリコン柱１ａ（Ｐ型シリコン層３０）とから、入射した光に応じた信号電荷（この場合は電子）を蓄積する信号電荷蓄積手段としてのフォトダイオードが形成される。信号電荷は、Ｎ＋拡散層６ａとＰ＋型シリコン層１３ａとの間におけるシリコン柱１ａ（Ｐ型シリコン層３０）に蓄積される。 Subsequently, as shown in FIG. 1K, an N-type is formed by ion-doping a donor impurity such as phosphorus (P) or arsenic (As) in the upper portion of the gate conductor layers 11a and 11b and the surface layer portion of the silicon pillar 1a. Silicon layers 12a and 12b are formed. The N-type silicon layers 12a and 12b and the silicon pillar 1a (P-type silicon layer 30) form a photodiode as signal charge storage means for storing signal charges (electrons in this case) corresponding to incident light. Is done. The signal charge is accumulated in the silicon pillar 1a (P-type silicon layer 30) between the N + diffusion layer 6a and the P + -type silicon layer 13a.
　続いて、図１Ｋに示されるように、シリコン柱１ａにおいて、第３酸化シリコン層１０ａ、１０ｂの上方部位に、ボロン（Ｂ）などのアクセプタ不純物をイオンドーピングすることによって、Ｐ＋型シリコン層１３ａを形成する。そして、このＰ＋型シリコン層１３ａを画素選択金属配線１４ａ、１４ｂに電気的に接続する。 Subsequently, as shown in FIG. 1K, in the silicon pillar 1a, an upper portion of the third silicon oxide layers 10a and 10b is ion-doped with an acceptor impurity such as boron (B) to thereby form a P + -type silicon layer 13a. Form. The P + -type silicon layer 13a is electrically connected to the pixel selection metal wirings 14a and 14b.
　また、図１Ｌに示されるように、固体撮像装置の画素を構成するシリコン柱１ａに隣接し、別の画素を構成するシリコン柱１ｂの外周部に、熱酸化によって、絶縁体である第３酸化シリコン層１０ｃ、１０ｄを形成する。このシリコン柱１ｂは、シリコン柱１ａと同様に、図１Ａ～図１Ｋに示される工程で形成されたものである。 Further, as shown in FIG. 1L, a third oxide which is an insulator is formed by thermal oxidation on the outer periphery of the silicon pillar 1b constituting another pixel and adjacent to the silicon pillar 1a constituting the pixel of the solid-state imaging device. Silicon layers 10c and 10d are formed. The silicon pillar 1b is formed by the steps shown in FIGS. 1A to 1K, similarly to the silicon pillar 1a.
　続いて、図１Ｌに示されるように、第３酸化シリコン層１０ｃ、１０ｄの外周部に、蒸着法又はＣＶＤ法によって、ゲート導体層１１ｃ、１１ｄを形成する。 Subsequently, as shown in FIG. 1L, gate conductor layers 11c and 11d are formed on the outer periphery of the third silicon oxide layers 10c and 10d by vapor deposition or CVD.
　続いて、図１Ｌに示されるように、ゲート導体層１１ｃ、１１ｄの上方部位かつシリコン柱１ａの表層部に、リン（Ｐ）やヒ素（Ａｓ）などのドナー不純物をイオンドーピングすることでＮ型シリコン層１２ｃ、１２ｄを形成する。このＮ型シリコン層１２ｃ、１２ｄと、シリコン柱１ｂと、によって、入射した光に応じた信号電荷（この場合は電子）を蓄積する信号電荷蓄積手段としてのフォトダイオードが形成される。信号電荷は、Ｎ＋拡散層６ａｂとＰ＋型シリコン層１３ｂとの間におけるシリコン柱１ｂ（Ｐ型シリコン層３０）に蓄積される。 Subsequently, as shown in FIG. 1L, the upper portion of the gate conductor layers 11c and 11d and the surface layer portion of the silicon pillar 1a are ion-doped with a donor impurity such as phosphorus (P) or arsenic (As). Silicon layers 12c and 12d are formed. The N-type silicon layers 12c and 12d and the silicon pillar 1b form a photodiode as signal charge storage means for storing signal charges (electrons in this case) corresponding to incident light. The signal charge is accumulated in the silicon pillar 1b (P-type silicon layer 30) between the N + diffusion layer 6ab and the P + -type silicon layer 13b.
　続いて、図１Ｌに示されるように、シリコン柱１ａにおいて、第３酸化シリコン層１０ｃ、１０ｄの上方部位に、ボロン（Ｂ）などのアクセプタ不純物をシリコン柱１ｂにイオンドーピングすることによって、Ｐ＋型シリコン層１３ｂを形成する。
　そして、このＰ＋型シリコン層１３ａ、１３ｂを画素選択金属配線１４ｃ、１４ｄに電気的に接続する。以上の工程により、固体撮像装置における複数の画素が形成される。 Subsequently, as shown in FIG. 1L, the silicon pillar 1a, the third silicon oxide layer 10c, the upper part of the 10d, by ion doping in the silicon pillar 1b the acceptor impurities such as boron (B), P + A mold silicon layer 13b is formed.
Then, the P + type silicon layers 13a and 13b are electrically connected to the pixel selection metal wirings 14c and 14d. Through the above steps, a plurality of pixels in the solid-state imaging device are formed.
　なお、本実施形態では、図１Ｊに示される工程において、熱処理によって、シリコン柱１ａ内のＮ＋拡散層６ａは、Ｎ＋多結晶シリコン層５ａからシリコン柱１ａにドナー不純物を熱拡散させることで形成した。これに限られず、Ｎ＋拡散層６ａは、図１Ｃに示されるＮ＋多結晶シリコン層５ａが形成された後の任意の段階における熱処理によって、Ｎ＋多結晶シリコン層５ａから第１の半導体基板１内にドナー不純物を拡散させることで形成することもできる。即ち、図１Ｃに示される、Ｎ＋多結晶シリコン層５ａを形成した工程以後に、ドナー不純物を含むＮ＋多結晶シリコン層５ａから当該不純物を拡散させることでシリコン柱１ａにＮ＋拡散層６ａを形成することもできる。例えば、Ｎ＋拡散層６ａは、図１Ｋで示す段階において、シリコン柱１ａ（Ｐ型シリコン層３０）に熱処理を行って形成してもよい。さらに、このようなＮ＋拡散層６ａを形成するための熱処理は、１回のみでもよいし、複数回に分けて行うこともできる。 In this embodiment, in the step shown in FIG. 1J, the N + diffusion layer 6a in the silicon pillar 1a is thermally diffused from the N + polycrystalline silicon layer 5a to the silicon pillar 1a by heat treatment. Formed. The N + diffusion layer 6a is not limited to this, and the N + diffusion layer 6a is formed from the N + polycrystalline silicon layer 5a to the first semiconductor substrate by heat treatment at an arbitrary stage after the N + polycrystalline silicon layer 5a shown in FIG. 1C is formed. It can also be formed by diffusing donor impurities in 1. That is, after the step of forming the N + polycrystalline silicon layer 5a shown in FIG. 1C, the impurities are diffused from the N + polycrystalline silicon layer 5a including the donor impurity, thereby the N + diffusion layer 6a is formed in the silicon pillar 1a. Can also be formed. For example, the N + diffusion layer 6a may be formed by performing heat treatment on the silicon pillar 1a (P-type silicon layer 30) in the stage shown in FIG. 1K. Further, the heat treatment for forming such an N + diffusion layer 6a may be performed only once or may be performed in a plurality of times.
　以上の図１Ａ～図１Ｌに示される工程によって、本実施形態に係る固体撮像装置が形成される。また、各シリコン柱１ａ、１ｂには、固体撮像装置の画素が形成される。 The solid-state imaging device according to this embodiment is formed by the processes shown in FIGS. 1A to 1L. In addition, pixels of the solid-state imaging device are formed on each of the silicon pillars 1a and 1b.
　本実施形態では、図１Ｌを参照して、シリコン柱１ａ、１ｂの下方に形成され、互いに接合されているＮ＋多結晶シリコン層５ａ及び金属層７は、固体撮像装置の信号線を構成するとともに、２つのシリコン柱１ａ、１ｂにおけるＮ＋拡散層６ａ、６ａｂを互いに電気的に接続している。これにより、Ｎ＋多結晶シリコン層５ａ及び金属層７から構成される信号線が低電気抵抗化され、固体撮像装置の高速駆動化が実現される。 In this embodiment, referring to FIG. 1L, N + polycrystalline silicon layer 5a and metal layer 7 formed below silicon pillars 1a and 1b and joined to each other constitute a signal line of the solid-state imaging device. In addition, the N + diffusion layers 6a and 6ab in the two silicon pillars 1a and 1b are electrically connected to each other. Thereby, the signal line composed of the N + polycrystalline silicon layer 5a and the metal layer 7 is reduced in electrical resistance, and high-speed driving of the solid-state imaging device is realized.
　本実施形態では、シリコン柱１ａ、１ｂ内において、接合トランジスタが形成されている。この接合トランジスタでは、Ｎ型シリコン層１２ａ、１２ｂ（１２ｃ、１２ｄ）及びシリコン柱１ａ（Ｐ型シリコン層３０）によって構成されるフォトダイオードがゲート、Ｐ＋型シリコン層１３ａ、１３ｂがドレイン、Ｎ＋拡散層６ａ、６ａｂがソースとしてそれぞれ機能する。そして、シリコン柱１ａ、１ｂ内には、この接合トランジスタのチャネルが形成されている。 In the present embodiment, junction transistors are formed in the silicon pillars 1a and 1b. In this junction transistor, a photodiode constituted by N-type silicon layers 12a and 12b (12c and 12d) and a silicon pillar 1a (P-type silicon layer 30) is a gate, P + -type silicon layers 13a and 13b are drains, and N + The diffusion layers 6a and 6ab function as sources. The junction transistor channel is formed in the silicon pillars 1a and 1b.
　また、本実施形態では、接合トランジスタによってシリコン柱１ａ、１ｂ内のチャネルを流れるとともに、上記フォトダイオードに蓄積された信号電荷量に応じて変化する電流を電気信号として取り出す信号取り出し手段としての外部回路（図示せず）が設けられている。 In the present embodiment, an external circuit serving as a signal extraction unit that flows as channels through the channels in the silicon pillars 1a and 1b by the junction transistor and extracts a current that changes according to the amount of signal charge accumulated in the photodiode as an electric signal. (Not shown) is provided.
　さらに、図１Ｌに示すシリコン柱１ａ、１ｂには、上記フォトダイオードによってＮ＋拡散層６ａ、６ａｂとＰ＋型シリコン層１３ａ、１３ｂとの間におけるシリコン柱１ａ、１ｂ（Ｐ型シリコン層３０）に蓄積された信号電荷を、Ｎ＋拡散層６ａ、６ａｂに除去する信号電荷除去手段としてのＭＯＳトランジスタが形成されている。 Further, the silicon pillars 1a and 1b shown in FIG. 1L are formed on the silicon pillars 1a and 1b (P-type silicon layer 30) between the N + diffusion layers 6a and 6ab and the P + -type silicon layers 13a and 13b by the photodiode. MOS transistors are formed as signal charge removing means for removing the signal charges accumulated in the N + diffusion layers 6a and 6ab.
　このＭＯＳトランジスタでは、シリコン柱１ａ、１ｂ（Ｐ型シリコン層３０）を囲むように、第３酸化シリコン層１０ａ、１０ｂ、１０ｃ、１０ｄの外周面に形成されたゲート導体層１１ａ、１１ｂ、１１ｃ、１１ｄがゲート、Ｎ＋拡散層６ａ、６ａｂがドレイン、Ｎ型シリコン層１２ａ、１２ｂ、１２ｃ、１２ｄがソースとしてそれぞれ機能する。そして、シリコン柱１ａ、１ｂ内には、このＭＯＳトランジスタのチャネルが形成される。 In this MOS transistor, gate conductor layers 11a, 11b, 11c formed on the outer peripheral surfaces of the third silicon oxide layers 10a, 10b, 10c, 10d so as to surround the silicon pillars 1a, 1b (P-type silicon layer 30). 11d functions as a gate, N + diffusion layers 6a and 6ab function as a drain, and N- type silicon layers 12a, 12b, 12c, and 12d function as a source, respectively. The channel of this MOS transistor is formed in the silicon pillars 1a and 1b.
　本実施形態では、図１Ｇに示されるように、第２半導体基板９のシリコン層と、第１の半導体基板１上の第２酸化シリコン層８とが、平坦化された互いの表面同士で接着される。このように本実施形態では、第１の半導体基板１（第２酸化シリコン層８）と第２半導体基板９との接着が、第１の半導体基板１と第２半導体基板９の全面において、接着の親和性が高いＳｉ（シリコン）面とＳｉＯ２（酸化シリコン）面との間で行われるので、ソリ、クラック、ハガレが発生しにくい積層構造が得られる。 In this embodiment, as shown in FIG. 1G, the silicon layer of the second semiconductor substrate 9 and the second silicon oxide layer 8 on the first semiconductor substrate 1 are bonded to each other on the planarized surfaces. Is done. As described above, in this embodiment, the first semiconductor substrate 1 (second silicon oxide layer 8) and the second semiconductor substrate 9 are bonded to each other over the entire surfaces of the first semiconductor substrate 1 and the second semiconductor substrate 9. Since this is performed between the Si (silicon) surface and the SiO 2 (silicon oxide) surface having a high affinity, it is possible to obtain a laminated structure in which warpage, cracking, and peeling are unlikely to occur.
　また、本実施形態では、固体撮像装置の画素において信号線を構成するＮ＋多結晶シリコン層５ａには金属層７が接合されているので、画素と該画素の周辺回路との間の電気抵抗を下げることができる。これにより、従来例の固体撮像装置と比較して、画素数の増加、又は単位時間あたりの読出し画面数の増加に際しても、固体撮像装置の高速動作化が実現できる。 In the present embodiment, since the metal layer 7 is bonded to the N + polycrystalline silicon layer 5a constituting the signal line in the pixel of the solid-state imaging device, the electrical resistance between the pixel and the peripheral circuit of the pixel Can be lowered. As a result, the solid-state imaging device can be operated at a higher speed even when the number of pixels is increased or the number of readout screens per unit time is increased as compared with the conventional solid-state imaging device.
　また、本実施形態では、図１Ｋを参照して、Ｐ型シリコン層３０とＮ型シリコン層１２ａ、１２ｂとから構成されるＰＮ接合部（フォトダイオード）と、Ｐ型シリコン層３０とＮ＋拡散層６ａとから構成されるＰＮ接合部は、いずれも単結晶シリコンからなるシリコン柱１ａ内に形成される。このようにＰＮ接合部が単結晶シリコン内で形成されるため、リーク電流が低い固体撮像装置の画素が構成される。 In this embodiment, referring to FIG. 1K, a PN junction (photodiode) composed of a P-type silicon layer 30 and N-type silicon layers 12a and 12b, and a P-type silicon layer 30 and N + diffusion are used. The PN junction composed of the layer 6a is formed in the silicon pillar 1a made of single crystal silicon. Since the PN junction is thus formed in single crystal silicon, a pixel of a solid-state imaging device with low leakage current is configured.
　さらに、本実施形態では、画素を構成するシリコン柱１ａ、１ｂ（図１Ｌ参照）の上方部から入射した光は、光電変換領域であるシリコン柱１ａに到達し、金属層７で反射されるので、シリコン柱１ａ内での光路長が増加し、固体撮像装置の感度向上が実現される。また、本実施形態では、シリコン柱１ａ、１ｂの高さを低くしても、従来例と同じ感度を得ることができるので、従来例と同じ感度を得ながら固体撮像装置の製造が容易になる効果も得られる。 Furthermore, in this embodiment, light incident from the upper part of the silicon pillars 1a and 1b (see FIG. 1L) constituting the pixel reaches the silicon pillar 1a which is a photoelectric conversion region and is reflected by the metal layer 7. The optical path length in the silicon pillar 1a increases, and the sensitivity of the solid-state imaging device is improved. In the present embodiment, even if the height of the silicon pillars 1a and 1b is lowered, the same sensitivity as that of the conventional example can be obtained. Therefore, the solid-state imaging device can be easily manufactured while obtaining the same sensitivity as that of the conventional example. An effect is also obtained.
　なお、本実施形態においては、図１Ｂに示されるように、第１酸化シリコン層３及び第１の半導体基板１上に、孔４を埋め込む（覆う）ように、ＣＶＤ法によって、Ｎ＋多結晶シリコン層５ａとなる多結晶シリコン層５を形成した。このようにＣＶＤ法によって多結晶シリコン層５を形成する代わりに、エピタキシャル成長により単結晶シリコン層を形成してもよい。エピタキシャル成長を用いる場合には、第１酸化シリコン層３上にも単結晶シリコン層を形成することができるので、その後、図１Ｃ～図１Ｋに示される工程と同様にして固体撮像装置を形成することができる。 In the present embodiment, as shown in FIG. 1B, N + polycrystal is formed by CVD so as to fill (cover) the hole 4 on the first silicon oxide layer 3 and the first semiconductor substrate 1. A polycrystalline silicon layer 5 to be a silicon layer 5a was formed. Thus, instead of forming the polycrystalline silicon layer 5 by the CVD method, a single crystalline silicon layer may be formed by epitaxial growth. When epitaxial growth is used, a single crystal silicon layer can be formed also on the first silicon oxide layer 3, and thereafter, a solid-state imaging device is formed in the same manner as the steps shown in FIGS. 1C to 1K. Can do.
　また、図１Ｈにおいては、第１の半導体基板１において、分離層２を境界とし、４００～６００℃の熱処理によって下方の部分を除去することで、第１の半導体基板１を所定の厚さまで薄くした。これに限られず、第１の半導体基板１の薄膜化は、第１の半導体基板１として、Ｐ＋型基板と、このＰ＋型基板にエピタキシャル成長で形成したＰ型シリコン層とから構成される基板を用いて、エッチングとＣＭＰによって行うこともできる。 Further, in FIG. 1H, the first semiconductor substrate 1 is thinned to a predetermined thickness by removing the lower part of the first semiconductor substrate 1 by using a heat treatment at 400 to 600 ° C. with the separation layer 2 as a boundary. did. The first semiconductor substrate 1 is not limited to this, but the first semiconductor substrate 1 is formed of a P + -type substrate and a P-type silicon layer formed by epitaxial growth on the P + -type substrate. Can also be performed by etching and CMP.
（第２実施形態）
　以下、図２を参照して、本発明の第２実施形態に係る、ＳＧＴ（ＭＯＳトランジスタ）を有する半導体装置の製造方法を説明する。
　本実施形態では、第１実施形態の図１Ａ～図１Ｌで示される工程において、図１Ａ～図１Ｊで示される工程までは、図１Ｊにおいて信号線を構成するＮ＋多結晶シリコン層５ａを、ＳＧＴ（ＭＯＳトランジスタ）においてドレインとして機能するＮ＋多結晶シリコン層５５ａに置き換えるものとする。第１実施形態（図１Ｊ参照）と同様に、Ｎ＋多結晶シリコン層５５ａには金属層７が接合されており、Ｎ＋多結晶シリコン層５５ａからのドナー不純物の熱拡散によってシリコン柱１ａ内にＮ＋拡散層６ａが形成されている。 (Second Embodiment)
Hereinafter, with reference to FIG. 2, the manufacturing method of the semiconductor device which has SGT (MOS transistor) based on 2nd Embodiment of this invention is demonstrated.
In the present embodiment, in the steps shown in FIGS. 1A to 1L of the first embodiment, until the steps shown in FIGS. 1A to 1J, the N + polycrystalline silicon layer 5a constituting the signal line in FIG. It is assumed that it is replaced with an N + polycrystalline silicon layer 55a that functions as a drain in the SGT (MOS transistor). Similar to the first embodiment (see FIG. 1 J), N + numerous to crystalline silicon layer 55a and the metal layer 7 is bonded, the silicon pillar in 1a by thermal diffusion of donor impurities from the N + polysilicon layer 55a N + diffusion layer 6a is formed.
　本実施形態では、図１Ｊに続いて、図２に示される工程において、酸化法又はＣＶＤ法によって、シリコン柱１ａの外周部にゲート絶縁層１５ａ、１５ｂを形成するとともに、ゲート絶縁層１５ａ、１５ｂの外周部に、ＳＧＴ（ＭＯＳトランジスタ）のゲートとして機能するゲート導体層１６ａ、１６ｂを形成する。 In the present embodiment, subsequent to FIG. 1J, in the step shown in FIG. 2, the gate insulating layers 15a and 15b are formed on the outer periphery of the silicon pillar 1a by the oxidation method or the CVD method, and the gate insulating layers 15a and 15b are formed. Gate conductor layers 16a and 16b functioning as gates of SGTs (MOS transistors) are formed on the outer periphery of the gate electrode.
　続いて、シリコン柱１ａにおいて、ゲート導体層１６ａ、１６ｂの上方部位に、リン（Ｐ）やヒ素（Ａｓ)などのドナー不純物をイオンドーピングすることによって、ＳＧＴ（ＭＯＳトランジスタ）のソースとして機能するＮ＋型シリコン層１７ａを形成する。 Subsequently, in the silicon pillar 1a, an upper portion of the gate conductor layers 16a and 16b is ion-doped with a donor impurity such as phosphorus (P) or arsenic (As), thereby functioning as an NGT functioning as a source of SGT (MOS transistor). A + type silicon layer 17a is formed.
　続いて、そのＮ＋型シリコン層１７ａ上に、蒸着法とパターンエッチングによって金属配線層１８ａを形成する。
　以上により、第２半導体基板９上にＳＧＴ、詳しくは、第２半導体基板９上にＮチャネル型ＳＧＴが形成される。ここで、Ｎチャネル型ＳＧＴのドレインとして機能するＮ＋多結晶シリコン層５５ａは、Ｎチャネル型ＳＧＴにおいてソースとして機能してもよく、ソースとして機能するＮ＋型シリコン層１７ａは、Ｎチャネル型ＳＧＴにおいて、ドレインとして機能してもよい。 Subsequently, a metal wiring layer 18a is formed on the N + type silicon layer 17a by vapor deposition and pattern etching.
As a result, an SGT, specifically, an N-channel SGT is formed on the second semiconductor substrate 9. Here, the N + polycrystalline silicon layer 55a functioning as the drain of the N channel type SGT may function as a source in the N channel type SGT, and the N + type silicon layer 17a functioning as the source may be the N channel type SGT. , It may function as a drain.
　本実施形態によれば、ＳＧＴ（Ｎチャネル型ＳＧＴ）において、ドレインとして機能するＮ＋多結晶シリコン層５５ａの裏面全体に金属層７が接合されている。この構成により、金属層７からＮ＋拡散層６ａまでの電気抵抗が低減するので、高速動作化が実現されたＳＧＴが得られる。 According to the present embodiment, in the SGT (N-channel SGT), the metal layer 7 is bonded to the entire back surface of the N + polycrystalline silicon layer 55a that functions as a drain. With this configuration, the electrical resistance from the metal layer 7 to the N + diffusion layer 6a is reduced, so that an SGT with high speed operation is obtained.
（第３実施形態）
　以下、図３Ａ、図３Ｂを参照して、本発明の第３実施形態に係る、ＳＧＴ（ＭＯＳトランジスタ）を有する半導体装置の製造方法を説明する。本実施形態では、Ｎチャネル型ＳＧＴとＰチャネル型ＳＧＴとを同一の半導体基板上に形成する。本実施形態及びその変形例における半導体装置の製造工程は、以下に特に説明する場合を除いて、第１実施形態と同様である。 (Third embodiment)
Hereinafter, with reference to FIGS. 3A and 3B, a method of manufacturing a semiconductor device having an SGT (MOS transistor) according to a third embodiment of the present invention will be described. In this embodiment, the N channel type SGT and the P channel type SGT are formed on the same semiconductor substrate. The manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
　本実施形態では、図３Ａ、図３Ｂを参照して、第１の半導体基板１上において、Ｎチャネル型ＳＧＴ形成領域１ｎにはＮチャネル型ＳＧＴ、Ｐチャネル型ＳＧＴ形成領域１ｐにはＰチャネル型ＳＧＴをそれぞれ形成する。
　Ｎチャネル型ＳＧＴ形成領域１ｎにおけるＮチャネル型ＳＧＴは、第１実施形態の図１Ａ～図１Ｊ、第２実施形態の図２に示される工程と同様にして形成する。 In the present embodiment, referring to FIGS. 3A and 3B, on the first semiconductor substrate 1, an N channel type SGT formation region 1n is an N channel type SGT, and a P channel type SGT formation region 1p is a P channel type. Each SGT is formed.
The N-channel SGT in the N-channel SGT formation region 1n is formed in the same manner as the steps shown in FIGS. 1A to 1J of the first embodiment and FIG. 2 of the second embodiment.
　一方、Ｐチャネル型ＳＧＴ形成領域１ｐにおけるＰチャネル型ＳＧＴは、第１実施形態の図１Ａ～図１Ｊ、第２実施形態の図２に示される工程とほぼ同様にして形成する。但し、図１Ｃに対応する工程では、Ｎチャネル型ＳＧＴのドレインとして機能するＮ＋多結晶シリコン層５５ａを形成する代わりに、Ｐチャネル型ＳＧＴ形成領域１ｐにおける多結晶シリコン層５に、ボロン（Ｂ）などのアクセプタ不純物をイオンドーピングすることによって、Ｐチャネル型ＳＧＴのソースとして機能するＰ＋多結晶シリコン層５５ｂを形成する。 On the other hand, the P-channel SGT in the P-channel SGT formation region 1p is formed in substantially the same manner as the steps shown in FIGS. 1A to 1J of the first embodiment and FIG. 2 of the second embodiment. However, in the step corresponding to FIG. 1C, instead of forming the N + polycrystalline silicon layer 55a that functions as the drain of the N channel type SGT, boron (B ) Or the like is ion-doped to form a P + polycrystalline silicon layer 55b that functions as a source of the P-channel SGT.
　続いて、図１Ｄ～図１Ｊに対応する工程、図２に対応する工程を経て、図３Ｂに示されるように、シリコン柱１ａによって構成されるＮチャネル型ＳＧＴと、シリコン柱１ｂによって構成されるＰチャネル型ＳＧＴとが形成される。なお、シリコン柱１ｂでは、Ｐチャネル型ＳＧＴのシリコン柱１ｂ（Ｐ型シリコン）に、リン（Ｐ）やヒ素（Ａｓ）などのドナー不純物をイオンドーピングすることでＮ型シリコン層３０ａを形成する。 Subsequently, through steps corresponding to FIGS. 1D to 1J and steps corresponding to FIG. 2, as shown in FIG. 3B, an N channel type SGT constituted by the silicon pillar 1a and a silicon pillar 1b are formed. A P channel type SGT is formed. In the silicon pillar 1b, the N-type silicon layer 30a is formed by ion doping a P-channel SGT silicon pillar 1b (P-type silicon) with a donor impurity such as phosphorus (P) or arsenic (As).
　ここで、図１Ｊに対応する工程では、熱処理によって、シリコン柱１ａ、１ｂ中にＮ＋多結晶シリコン層５５ａ、Ｐ＋多結晶シリコン層５５ｂからドナー不純物、アクセプタ不純物をそれぞれ熱拡散させ、Ｎ＋拡散層６ａ、Ｐ＋拡散層６ｂを形成する。 Here, in the step corresponding to FIG. 1 J, by heat treatment, the silicon pillar 1a, N + polycrystalline silicon layer 55a during 1b, P + polycrystalline silicon layer 55b from the donor impurities, respectively and thermally diffusing the acceptor impurity, N + Diffusion layer 6a and P + diffusion layer 6b are formed.
　また、図２に対応する工程では、熱酸化又はＣＶＤ法によって、シリコン柱１ａ、１ｂの外周部に、ゲート絶縁層１５ａ、１５ｂ、１５ｃ、１５ｄを形成するとともに、ゲート絶縁層１５ａ、１５ｂ、１５ｃ、１５ｄの外周部に、ＣＶＤ法によってゲート導体層１６ａ、１６ｂ、１６ｃ、１６ｄを形成する（図３Ｂ参照）。 In the process corresponding to FIG. 2, the gate insulating layers 15a, 15b, 15c, and 15d are formed on the outer peripheral portions of the silicon pillars 1a and 1b by thermal oxidation or CVD, and the gate insulating layers 15a, 15b, and 15c are formed. , 15d, gate conductor layers 16a, 16b, 16c, 16d are formed by CVD (see FIG. 3B).
　そして、図３Ｂに示される工程では、シリコン柱１ａ、１ｂにおいて、ゲート導体層１６ａ、１６ｂ、１６ｃ、１６ｄの上方部位に、ドナー不純物、アクセプタ不純物をそれぞれイオンドーピングすることによって、Ｎチャネル型ＳＧＴのソースとして機能するＮ＋型シリコン層１７ａ、Ｐチャネル型ＳＧＴのソースとして機能するＰ＋型シリコン層１７ｂをそれぞれ形成する。 In the step shown in FIG. 3B, in the silicon pillars 1a and 1b, donor impurities and acceptor impurities are ion-doped in the upper portions of the gate conductor layers 16a, 16b, 16c, and 16d, respectively. An N + type silicon layer 17a that functions as a source and a P + type silicon layer 17b that functions as a source of a P-channel type SGT are formed.
　続いて、図３Ｂに示される工程において、Ｎチャネル型ＳＧＴにおけるＮ+型シリコン層１７ａ、Ｐチャネル型ＳＧＴにおけるＰ＋型シリコン層１７ｂに電気的に接続されるように、例えば蒸着法及びエッチングによって金属配線層１８ａ、１８ｂを形成する。
　以上により、第２半導体基板９上にＮチャネル型ＳＧＴ及びＰチャネル型ＳＧＴが形成される。 Subsequently, in the step shown in FIG. 3B, for example, by vapor deposition and etching so as to be electrically connected to the N + type silicon layer 17a in the N channel type SGT and the P + type silicon layer 17b in the P channel type SGT. Metal wiring layers 18a and 18b are formed.
Thus, the N channel type SGT and the P channel type SGT are formed on the second semiconductor substrate 9.
　本実施形態では、Ｎチャネル型ＳＧＴにおけるシリコン柱１ａ内のＮ＋多結晶シリコン層５５ａ及びＮ＋拡散層６ａと、Ｎ＋型シリコン層１７ａとは、いずれか一方がドレインであれば、他方はソースとして機能する。また、Ｐチャネル型ＳＧＴにおけるシリコン柱１ｂ内のＰ＋多結晶シリコン層５５ｂ及びＰ＋拡散層６ｂと、Ｐ＋型シリコン層１７ｂとは、いずれか一方がドレインであれば、他方はソースとして機能する。
　本実施形態によれば、第２半導体基板９上に、Ｎチャネル型ＳＧＴとＰチャネル型ＳＧＴとを容易に形成することができる。 In the present embodiment, any one of the N + polycrystalline silicon layer 55a and the N + diffusion layer 6a in the silicon pillar 1a in the N channel type SGT and the N + type silicon layer 17a is a drain, and the other is Act as a source. In addition, if any one of the P + polycrystalline silicon layer 55b and the P + diffusion layer 6b and the P + type silicon layer 17b in the silicon pillar 1b in the P channel type SGT is a drain, the other functions as a source. To do.
According to this embodiment, the N-channel SGT and the P-channel SGT can be easily formed on the second semiconductor substrate 9.
　本実施形態では、Ｎチャネル型ＳＧＴのシリコン柱１ａ（Ｐ型シリコン層３０）を形成した後、Ｐチャネル型ＳＧＴのシリコン柱１ｂ（Ｐ型シリコン）に、リン（Ｐ）やヒ素（Ａｓ）などのドナー不純物をイオンドーピングすることでＮ型シリコン層３０ａを形成した。これに限られず、本実施形態の変形例として、図１Ａにおける第１の半導体基板１を、Ｐ型シリコンに代えて固有半導体であるｉ型シリコンとし、図１Ｉに対応する工程においては、Ｎチャネル型ＳＧＴにおけるシリコン柱１ａにはボロン（Ｂ）などのアクセプタ不純物をイオンドーピングしてＰ型シリコン層３０を形成するとともに、Ｐチャネル型ＳＧＴにおけるシリコン柱１ａには、リン（Ｐ）やヒ素（Ａｓ）などのドナー不純物をイオンドーピングすることでＮ型シリコン層３０ａを形成することも可能である。 In this embodiment, after forming the N-channel SGT silicon pillar 1a (P-type silicon layer 30), the P-channel SGT silicon pillar 1b (P-type silicon) is formed with phosphorus (P), arsenic (As), or the like. The N-type silicon layer 30a was formed by ion doping of the donor impurities. As a modification of this embodiment, the first semiconductor substrate 1 in FIG. 1A is replaced with i-type silicon, which is a unique semiconductor, instead of P-type silicon. In the process corresponding to FIG. The silicon pillar 1a in the type SGT is ion-doped with an acceptor impurity such as boron (B) to form a P-type silicon layer 30, and the silicon pillar 1a in the P-channel type SGT has phosphorus (P) or arsenic (As). It is also possible to form the N-type silicon layer 30a by ion doping with a donor impurity such as
（第４実施形態）
　以下、図４を参照して、本発明の第４実施形態に係る、複数のＳＧＴを有する半導体装置の製造方法を説明する。
　本実施形態では、第３実施形態と同様にして、Ｎチャネル型ＳＧＴ形成領域１ｎにはＮチャネル型ＳＧＴ、Ｐチャネル型ＳＧＴ形成領域１ｐにはＰチャネル型ＳＧＴをそれぞれ形成する（図３Ａ、図３Ｂ参照）。 (Fourth embodiment)
Hereinafter, with reference to FIG. 4, the manufacturing method of the semiconductor device which has several SGT based on 4th Embodiment of this invention is demonstrated.
In this embodiment, as in the third embodiment, an N-channel SGT is formed in the N-channel SGT formation region 1n, and a P-channel SGT is formed in the P-channel SGT formation region 1p (FIG. 3A, FIG. 3). 3B).
　本実施形態では、第１及び第３実施形態とほぼ同様にして、Ｎチャネル型ＳＧＴとＰチャネル型ＳＧＴとを、同一の半導体基板である第２半導体基板９上に形成する（図１Ａ～図１Ｊ、図３Ａ、図３Ｂ参照）。但し、図１Ｅに対応する工程では、図４に示されるように、複数のＮチャネル型ＳＧＴ、Ｐチャネル型ＳＧＴにおいて、ソースとして機能するＮ＋多結晶シリコン層５５ａ、ドレインとして機能するＰ＋多結晶シリコン層５５ｂ同士を金属層７ａａ、７ｂｂ、第１接続用金属層７ａ、第２接続用金属層７ｂによって電気的に接続する。 In the present embodiment, an N channel type SGT and a P channel type SGT are formed on the second semiconductor substrate 9, which is the same semiconductor substrate, in substantially the same manner as in the first and third embodiments (FIGS. 1A to 1D). 1J, see FIGS. 3A and 3B). However, in the step corresponding to FIG. 1E, as shown in FIG. 4, in a plurality of N channel type SGTs and P channel type SGTs, N + polycrystalline silicon layers 55a functioning as sources and P + many functioning as drains. The crystalline silicon layers 55b are electrically connected to each other by the metal layers 7aa and 7bb, the first connection metal layer 7a, and the second connection metal layer 7b.
　即ち、本実施形態では、図１Ｄに対応する工程において、Ｎ＋多結晶シリコン層５５ａ、Ｐ＋多結晶シリコン層５５ｂとなるシリコン層を覆うように、蒸着法とエッチングによって金属層７を形成する。そして、エッチングによって、金属層７、Ｎ＋多結晶シリコン層５５ａ及びＰ＋多結晶シリコン層５５ｂを、所定の形状に成形する。これにより、図４に示されるように、Ｎ＋多結晶シリコン層５５ａ、Ｐ＋多結晶シリコン層５５ｂ、金属層７ａａ、７ｂｂ、第１接続用金属層７ａをそれぞれ形成する。 That is, in the present embodiment, in the step corresponding to FIG. 1D, the metal layer 7 is formed by vapor deposition and etching so as to cover the silicon layers to be the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b. . Then, the metal layer 7, the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b are formed into a predetermined shape by etching. Thereby, as shown in FIG. 4, an N + polycrystalline silicon layer 55a, a P + polycrystalline silicon layer 55b, metal layers 7aa and 7bb, and a first connection metal layer 7a are formed.
　本実施形態では、図３Ｂに対応する工程に続いて、図４を参照して、第１接続用金属層７ａ上に酸化シリコン層２０を形成し、当該酸化シリコン層２０にコンタクトホール２１ｃを形成する。次に、コンタクトホール２１ｃ及び第１接続用金属層７ａを介して、Ｎ＋多結晶シリコン層５５ａ及びＰ＋多結晶シリコン層５５ｂと、酸化シリコン層２０の上部に形成された外部金属配線層２２ｃとを接続する。また、第１接続用金属層７ａを延長した部位に第２接続用金属層７ｂを形成し、この第２接続用金属層７ｂを用いて、所定の場所から図示しないコンタクトホールを介して電気的接点を取り出すようにする。 In the present embodiment, following the step corresponding to FIG. 3B, referring to FIG. 4, a silicon oxide layer 20 is formed on the first connection metal layer 7a, and a contact hole 21c is formed in the silicon oxide layer 20. To do. Next, the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b and the external metal wiring layer 22c formed on the silicon oxide layer 20 through the contact hole 21c and the first connection metal layer 7a. And connect. Further, a second connection metal layer 7b is formed in a portion extending from the first connection metal layer 7a, and the second connection metal layer 7b is used to electrically connect from a predetermined location through a contact hole (not shown). Take out the contact.
　また、本実施形態では、図４を参照して、Ｎチャネル型ＳＧＴのドレインとして機能するＮ＋多結晶シリコン層５５ａ、５５ｂの裏面全体にそれぞれ金属層７ａａ、７ｂｂが接合されている。そして、複数のシリコン柱１ａ、１ｂにおいて、Ｎ＋拡散層６ａ、６ｂ、及び、複数の金属層７ａａ、７ｂｂの内の一方である複数の金属層７ａａ、７ｂｂ同士が互いに接続されている。ここで、Ｎ＋拡散層６ａ、６ｂ、及び、複数の金属層７ａａ、７ｂｂの内の両方が互いに接続されていてもよい。 In the present embodiment, referring to FIG. 4, metal layers 7aa and 7bb are bonded to the entire back surfaces of N + polycrystalline silicon layers 55a and 55b that function as drains of the N-channel SGT, respectively. In the plurality of silicon pillars 1a and 1b, the N + diffusion layers 6a and 6b and the plurality of metal layers 7aa and 7bb which are one of the plurality of metal layers 7aa and 7bb are connected to each other. Here, both of the N + diffusion layers 6a and 6b and the plurality of metal layers 7aa and 7bb may be connected to each other.
　なお、本実施形態において、図４では、Ｎ＋多結晶シリコン層５５ａがＮチャネル型ＳＧＴのソース、Ｐ＋多結晶シリコン層５５ｂがＰチャネル型ＳＧＴのドレインとしてそれぞれ機能した。これに限られず、Ｎ＋多結晶シリコン層５５ａがＮチャネル型ＳＧＴのドレイン、Ｐ＋多結晶シリコン層５５ｂがＰチャネル型ＳＧＴのソースとして機能することもできる。さらには、Ｎ＋多結晶シリコン層５５ａ、Ｐ＋多結晶シリコン層５５ｂがいずれもソース又はドレインとして機能してもよい。 In this embodiment, in FIG. 4, the N + polycrystalline silicon layer 55a functions as an N-channel SGT source, and the P + polycrystalline silicon layer 55b functions as a P-channel SGT drain. However, the present invention is not limited to this, and the N + polycrystalline silicon layer 55a can also function as an N-channel SGT drain and the P + polycrystalline silicon layer 55b can function as a P-channel SGT source. Further, both the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b may function as a source or a drain.
　上述したように、本実施形態によれば、複数のＳＧＴにおいて、Ｎ＋多結晶シリコン層５５ａ、Ｐ＋多結晶シリコン層５５ｂによって構成されるソース、ドレイン同士が、酸化シリコン層２０の上表面において金属配線層２２ａ、２２ｂ、２２ｃが形成されている領域にコンタクトホールなどを介して引き出された上で接続されることなく、第１接続用金属層７ａによって互いに電気的に接続される。これによりＳＧＴを有する回路素子の集積度を高めることができる。 As described above, according to the present embodiment, in the plurality of SGTs, the source and drain constituted by the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b are arranged on the upper surface of the silicon oxide layer 20. The metal wiring layers 22a, 22b, and 22c are electrically connected to each other by the first connection metal layer 7a without being connected after being drawn out through a contact hole or the like. Thereby, the integration degree of the circuit element which has SGT can be raised.
　また、本実施形態に係る半導体装置の製造方法は、固体撮像装置の製造方法に適用することができる。この場合、例えば、非特許文献１に記載されている複数の画素信号を１個の増幅用のＭＯＳトランジスタで読み出す構成の固体撮像装置において、各画素におけるドレイン同士を互いに第１接続用金属層７ａで接続する。この場合も、各画素のドレイン、ソースは、コンタクトホールなどを介して上層部の別の金属配線に接続させた上で互いに接続する必要がない。このため、固体撮像装置の画素の更なる高集積化が実現される。 The semiconductor device manufacturing method according to the present embodiment can be applied to a solid-state imaging device manufacturing method. In this case, for example, in the solid-state imaging device configured to read out a plurality of pixel signals described in Non-Patent Document 1 with a single amplification MOS transistor, the drains of the pixels are connected to each other by the first connection metal layer 7a. Connect with. Also in this case, the drain and source of each pixel need not be connected to each other after being connected to another metal wiring in the upper layer portion via a contact hole or the like. For this reason, further high integration of the pixels of the solid-state imaging device is realized.
（第５実施形態）
　以下、図５Ａ～５Ｃを参照して、本発明の第５実施形態に係る、半導体装置に電気抵抗を形成する方法を説明する。本実施形態及びその変形例における半導体装置の製造工程は、以下に特に説明する場合を除いて、第１実施形態と同様である。
　本実施形態では、図１Ｂに示される、第１の半導体基板１上に形成された多結晶シリコン層５を用いることで、半導体装置の回路素子である電気抵抗を形成する。 (Fifth embodiment)
Hereinafter, a method for forming an electrical resistance in a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 5A to 5C. The manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
In this embodiment, an electrical resistance which is a circuit element of the semiconductor device is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
　本実施形態では、図１Ａに示される工程では、第１の半導体基板１の所定の深さに、この第１の半導体基板１を上下の２つの部分に分離するための分離層２を形成するとともに、第１の半導体基板１上に、絶縁体である第１酸化シリコン層３を形成する。 In the present embodiment, in the step shown in FIG. 1A, a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1. At the same time, a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
　続いて、図１Ｂに示される工程では、その第１酸化シリコン層３上に多結晶シリコン層５を形成し、図１Ｃに示される工程では、この多結晶シリコン層５に、リン（Ｐ）又はヒ素（Ａｓ）などのドナー不純物をイオンドープすることで、Ｎ＋多結晶シリコン層５ａを形成する。 1B, a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3, and in the process shown in FIG. 1C, phosphorus (P) or The N + polycrystalline silicon layer 5a is formed by ion doping with a donor impurity such as arsenic (As).
　本実施形態では、図１Ｂ、図１Ｃに示される工程において、図５Ａに示されるように、第１酸化シリコン層３上の多結晶シリコン層５の所定領域に、リン（Ｐ）又はヒ素（Ａｓ）などのドナー不純物を所定の濃度でイオンドープすることでＮ＋多結晶シリコン層２３ａ、２３ｂを形成する。このＮ＋多結晶シリコン層２３ａ、２３ｂ、ドナー不純物がイオンドープされていない多結晶シリコン層２３によって、多結晶シリコン層５の所定領域（多結晶シリコン層２３）における電気抵抗値が低下し、電気抵抗が形成される。このように、Ｎ＋多結晶シリコン層２３ａ、２３ｂ、多結晶シリコン層２３は、Ｎ＋多結晶シリコン層５ａ（図１Ｃ参照）と同様に、多結晶シリコン層５（図１Ｂ参照）から形成されるので、Ｎ＋多結晶シリコン層５ａと同層に位置する。 In this embodiment, in the steps shown in FIGS. 1B and 1C, phosphorus (P) or arsenic (As) is formed in a predetermined region of the polycrystalline silicon layer 5 on the first silicon oxide layer 3 as shown in FIG. 5A. N + polycrystalline silicon layers 23a and 23b are formed by ion doping with a donor impurity such as) at a predetermined concentration. The N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23 in which the donor impurity is not ion-doped reduce the electric resistance value in a predetermined region (polycrystalline silicon layer 23) of the polycrystalline silicon layer 5 and A resistance is formed. As described above, the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23 are formed from the polycrystalline silicon layer 5 (see FIG. 1B) in the same manner as the N + polycrystalline silicon layer 5a (see FIG. 1C). Therefore, it is located in the same layer as the N + polycrystalline silicon layer 5a.
　続いて、図１Ｄに示される工程では、Ｎ＋多結晶シリコン層２３ａ、２３ｂ上に、金属層７と同層に位置する金属配線層２４ａ、２４ｂを、金属層７と同様にして形成する。 1D, metal wiring layers 24a and 24b located in the same layer as the metal layer 7 are formed in the same manner as the metal layer 7 on the N + polycrystalline silicon layers 23a and 23b.
　本実施形態によれば、多結晶シリコン層５の所定領域に、所定の濃度のドナー不純物をイオンドープすることで、所定の電気抵抗値を有するＮ＋多結晶シリコン層２３ａ、２３ｂ、多結晶シリコン層２３が形成される。また、Ｎ＋多結晶シリコン層２３ａ、２３ｂ、多結晶シリコン層２３は、Ｎ＋多結晶シリコン層５ａと同層に形成される。これにより、同一の半導体基板上に、固体撮像装置、ＳＧＴなどの半導体装置と共に電気抵抗（回路素子）を作成することができるだけでなく、製造工程が簡略化されるようになる。 According to the present embodiment, a predetermined region of the polycrystalline silicon layer 5 is ion-doped with a donor impurity having a predetermined concentration, so that N + polycrystalline silicon layers 23a and 23b having a predetermined electric resistance value, polycrystalline silicon Layer 23 is formed. The N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23 are formed in the same layer as the N + polycrystalline silicon layer 5a. As a result, not only can an electrical resistance (circuit element) be created on the same semiconductor substrate together with a semiconductor device such as a solid-state imaging device or SGT, but also the manufacturing process is simplified.
　また、本実施形態では、図５Ｂを参照して、図１Ｂに示される工程で多結晶シリコン層２５を形成し、エッチングによって所定の形状とした後、蒸着法又はＣＶＤ法によって、その多結晶シリコン層２５に接続する金属配線層２６ａ、２６ｂを形成する。このようにして、多結晶シリコン層２５によっても半導体装置における電気抵抗が形成される。 Further, in the present embodiment, referring to FIG. 5B, after the polycrystalline silicon layer 25 is formed in the step shown in FIG. 1B and formed into a predetermined shape by etching, the polycrystalline silicon layer is formed by vapor deposition or CVD. Metal wiring layers 26 a and 26 b connected to the layer 25 are formed. In this way, electrical resistance in the semiconductor device is also formed by the polycrystalline silicon layer 25.
　また、本実施形態の変形例では、図５Ｃを参照して、第２半導体基板９上に第２酸化シリコン層８を形成し、その第２酸化シリコン層８上に、上述した方法によってＮ＋多結晶シリコン層２３ａ、２３ｂ及び多結晶シリコン層２３を形成する。その後、Ｎ＋多結晶シリコン層２３ａ、２３ｂ及び多結晶シリコン層２３上に第１酸化シリコン層３を形成し、その第１酸化シリコン層３上に、酸化シリコン層２０（図４参照）を形成することも可能である。なお、図５Ｃでは、Ｎ＋多結晶シリコン層２３ａ、２３ｂ及び多結晶シリコン層２３から図５Ａに示される電気抵抗が形成されている。 In the modification of the present embodiment, referring to FIG. 5C, the second silicon oxide layer 8 is formed on the second semiconductor substrate 9, and the N + is formed on the second silicon oxide layer 8 by the method described above. Polycrystalline silicon layers 23a and 23b and a polycrystalline silicon layer 23 are formed. Thereafter, the first silicon oxide layer 3 is formed on the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23, and the silicon oxide layer 20 (see FIG. 4) is formed on the first silicon oxide layer 3. It is also possible to do. In FIG. 5C, the electrical resistance shown in FIG. 5A is formed from the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23.
　また、本実施形態及び図５Ｃに示される変形例では、図４を参照して、第１酸化シリコン層３上には、ＳＧＴを有する回路素子又は金属配線が形成されている。
　さらに、図５Ｃに示される変形例では、電気抵抗を構成する多結晶シリコン層２３は、絶縁体である第１酸化シリコン層３の下方に形成されている。 In the present embodiment and the modification shown in FIG. 5C, referring to FIG. 4, a circuit element or metal wiring having SGT is formed on the first silicon oxide layer 3.
Further, in the modification shown in FIG. 5C, the polycrystalline silicon layer 23 constituting the electric resistance is formed below the first silicon oxide layer 3 which is an insulator.
　本変形例によれば、図５Ｃに示されるように、ＳｉＯ２層（第１酸化シリコン層３）の上下において、電気抵抗を構成する多結晶シリコン層２３と重なるように、図４に示される回路素子の金属配線層２２ａ、２２ｂ、２２ｃを形成することができる。これによって、電気抵抗を有する半導体装置（回路素子）の更なる高集積化が実現される。 According to this modification, as shown in FIG. 5C, the upper and lower sides of the SiO 2 layer (first silicon oxide layer 3) are shown in FIG. 4 so as to overlap with the polycrystalline silicon layer 23 constituting the electric resistance. The metal wiring layers 22a, 22b and 22c of the circuit element can be formed. Thereby, further high integration of the semiconductor device (circuit element) having electric resistance is realized.
（第６実施形態）
　以下、図６Ａ～図６Ｃを参照して、本発明の第６実施形態に係る、半導体装置に容量を形成する方法を説明する。本実施形態における半導体装置の製造工程は、以下に特に説明する場合を除いて、第１実施形態と同様である。
　本実施形態では、図１Ｂに示される、第１の半導体基板１上に形成された多結晶シリコン層５を用いることで、半導体装置の回路素子である容量を形成する。 (Sixth embodiment)
Hereinafter, a method of forming a capacitor in a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 6A to 6C. The manufacturing process of the semiconductor device according to the present embodiment is the same as that of the first embodiment, except as described below.
In this embodiment, a capacitor, which is a circuit element of a semiconductor device, is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
　本実施形態では、図１Ａに示される工程では、第１の半導体基板１の所定の深さに、この第１の半導体基板１を上下の２つの部分に分離するための分離層２を形成するとともに、第１の半導体基板１上に、絶縁体である第１酸化シリコン層３を形成する。 In the present embodiment, in the step shown in FIG. 1A, a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1. At the same time, a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
　続いて、図１Ｂに示される工程では、その第１酸化シリコン層３上に多結晶シリコン層５を形成し、図１Ｃに示される工程では、この多結晶シリコン層５に、リン（Ｐ）又はヒ素（Ａｓ）などのドナー不純物をイオンドープすることで、Ｎ＋多結晶シリコン層５ａを形成する。 1B, a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3, and in the process shown in FIG. 1C, phosphorus (P) or The N + polycrystalline silicon layer 5a is formed by ion doping with a donor impurity such as arsenic (As).
　ここで、図１Ｃに示される工程に続いては、図６Ａを参照して、熱酸化又はＣＶＤ法によって、Ｎ＋多結晶シリコン層５ａの表層部に容量酸化シリコン層２７を形成する。 Here, following the step shown in FIG. 1C, referring to FIG. 6A, capacitive silicon oxide layer 27 is formed on the surface layer portion of N + polycrystalline silicon layer 5a by thermal oxidation or CVD.
　続いて、図６Ｂを参照して、マスクを用いたエッチングによって、容量が形成される容量領域において、容量絶縁膜として機能する容量酸化シリコン層２７を所定の形状に成形する。
　そして、図１Ｄに示される工程では、所定形状に成形された容量酸化シリコン層２７上に、蒸着法又はＣＶＤ法によって、容量電極として機能する金属層２８を形成する。この金属層２８は、第１実施形態の金属層７と同層に形成する。 Subsequently, referring to FIG. 6B, the capacitor silicon oxide layer 27 functioning as a capacitor insulating film is formed into a predetermined shape in the capacitor region where the capacitor is formed by etching using a mask.
In the step shown in FIG. 1D, a metal layer 28 that functions as a capacitor electrode is formed on the capacitor silicon oxide layer 27 formed in a predetermined shape by vapor deposition or CVD. The metal layer 28 is formed in the same layer as the metal layer 7 of the first embodiment.
　続いて、図１Ｅ～図１Ｈ、図４に示される各工程を経ることにより、図６Ｃに示されるような積層構造が形成される。即ち、第２半導体基板９上に第２酸化シリコン層８が形成され、この第２酸化シリコン層８の内部において、容量が形成される容量領域に、容量電極として機能する金属層２８、及び、金属層２８に積層され、容量絶縁膜として機能する容量酸化シリコン層２７が配置されている。そして、容量酸化シリコン層２７及び第２酸化シリコン層８上に、Ｎ＋多結晶シリコン層５ａ、第１酸化シリコン層３及び酸化シリコン層２９（酸化シリコン層２０）がこの順で積層された構造が得られる。この構造では、金属層２８及びＮ＋多結晶シリコン層５ａが容量電極として機能するとともに、容量酸化シリコン層２７が容量絶縁膜として機能する容量が形成されている。 Subsequently, through the respective steps shown in FIGS. 1E to 1H and FIG. 4, a laminated structure as shown in FIG. 6C is formed. That is, a second silicon oxide layer 8 is formed on the second semiconductor substrate 9, and inside the second silicon oxide layer 8, a metal layer 28 functioning as a capacitor electrode is formed in a capacitor region where a capacitor is formed, and A capacitive silicon oxide layer 27 that is stacked on the metal layer 28 and functions as a capacitive insulating film is disposed. Then, the N + polycrystalline silicon layer 5a, the first silicon oxide layer 3 and the silicon oxide layer 29 (silicon oxide layer 20) are stacked in this order on the capacitive silicon oxide layer 27 and the second silicon oxide layer 8. Is obtained. In this structure, the metal layer 28 and the N + polycrystalline silicon layer 5a function as a capacitor electrode, and a capacitor in which the capacitor silicon oxide layer 27 functions as a capacitor insulating film is formed.
　本実施形態では、第１実施形態に係る固体撮像装置の製造方法の図１Ｄ～図１Ｈに示される工程において、Ｎ＋多結晶シリコン層５ａの表層に絶縁層２７を形成する工程（図６Ａ参照）と、容量酸化シリコン層２７、金属層２８を形成する工程（図６Ｂ参照）とが追加される。これにより、同一の半導体基板上に、固体撮像装置の画素、ＳＧＴなどの半導体装置と共に容量（回路素子）を形成することができるだけでなく、製造工程が簡略化されるようになる。 In the present embodiment, in the process shown in FIGS. 1D to 1H of the method for manufacturing the solid-state imaging device according to the first embodiment, the process of forming the insulating layer 27 on the surface layer of the N + polycrystalline silicon layer 5a (see FIG. 6A). ) And a step of forming the capacitive silicon oxide layer 27 and the metal layer 28 (see FIG. 6B). Thereby, not only can a capacitor (circuit element) be formed on the same semiconductor substrate together with a pixel of a solid-state imaging device, a semiconductor device such as SGT, but also the manufacturing process is simplified.
（第７実施形態）
　以下、図７Ａ、図７Ｂを参照して、本発明の第７実施形態に係る、半導体装置に容量を形成する方法を説明する。本実施形態における半導体装置の製造工程は、以下に特に説明する場合を除いて、第１実施形態と同様である。
　本実施形態では、図１Ｂに示される、第１の半導体基板１上に形成された多結晶シリコン層５を用いることで、半導体装置の回路素子である容量を形成する。 (Seventh embodiment)
Hereinafter, with reference to FIGS. 7A and 7B, a method of forming a capacitor in a semiconductor device according to a seventh embodiment of the present invention will be described. The manufacturing process of the semiconductor device according to the present embodiment is the same as that of the first embodiment, except as described below.
In this embodiment, a capacitor, which is a circuit element of a semiconductor device, is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
　本実施形態では、図１Ａに示される工程では、第１の半導体基板１の所定の深さに、この第１の半導体基板１を上下の２つの部分に分離するための分離層２を形成するとともに、第１の半導体基板１上に、絶縁体である第１酸化シリコン層３を形成する。 In the present embodiment, in the step shown in FIG. 1A, a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1. At the same time, a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
　続いて、図１Ｂに示される工程では、多結晶シリコン層５を形成する前に、第１酸化シリコン層３上に図７Ａに示される容量形成領域１００を設定するとともに、この容量形成領域１００における酸化シリコンをエッチングにより除去することで、凹形状の酸化シリコン層除去領域を形成する。即ち、図１Ｂに示される工程では、図７Ａに示されるように、当該酸化シリコン層除去領域の周囲に酸化シリコン層１０１ａ、１０１ｂを残存させるとともに、この酸化シリコン層除去領域には、酸化シリコン層１０１ａ、１０１ｂよりも厚さが薄い酸化シリコン層１０３を残存させる。そして、その酸化シリコン層１０１ａ、１０１ｂをマスクとして用い、ボロン（Ｂ）などのアクセプタ不純物をイオンドーピング又は熱拡散することで、酸化シリコン層１０３を通して容量形成領域１００における第１の半導体基板１の表層にＰ＋拡散層１０２を形成する。そして、図１Ｂを参照して、その第１酸化シリコン層３上に、酸化シリコン層除去領域を埋め込むように多結晶シリコン層５を形成する。 Subsequently, in the step shown in FIG. 1B, before forming the polycrystalline silicon layer 5, the capacitance forming region 100 shown in FIG. 7A is set on the first silicon oxide layer 3, and the capacitance forming region 100 in this capacitance forming region 100 is set. By removing the silicon oxide by etching, a concave silicon oxide layer removal region is formed. That is, in the step shown in FIG. 1B, as shown in FIG. 7A, the silicon oxide layers 101a and 101b are left around the silicon oxide layer removal region, and the silicon oxide layer removal region has a silicon oxide layer. A silicon oxide layer 103 having a thickness smaller than those of 101a and 101b is left. Then, using the silicon oxide layers 101a and 101b as a mask, acceptor impurities such as boron (B) are ion-doped or thermally diffused, whereby the surface layer of the first semiconductor substrate 1 in the capacitor formation region 100 through the silicon oxide layer 103. Then, the P + diffusion layer 102 is formed. Then, referring to FIG. 1B, a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3 so as to embed a silicon oxide layer removal region.
　続いて、図１Ｃに示される工程では、この多結晶シリコン層５に、リン（Ｐ）又はヒ素（Ａｓ）などのドナー不純物をイオンドープすることで、Ｎ＋多結晶シリコン層１０４を形成する（図７Ａ参照）。 1C, the polysilicon layer 5 is ion-doped with a donor impurity such as phosphorus (P) or arsenic (As) to form an N + polycrystalline silicon layer 104 (see FIG. 1C). (See FIG. 7A).
　続いて、図１Ｄに示される工程では、蒸着法又はＣＶＤ法によって、Ｎ＋多結晶シリコン層１０４上に金属層１０５を形成する（図７Ａ参照）。この金属層１０５は、第１実施形態における金属層７と同層に形成する。 1D, a metal layer 105 is formed on the N + polycrystalline silicon layer 104 by vapor deposition or CVD (see FIG. 7A). The metal layer 105 is formed in the same layer as the metal layer 7 in the first embodiment.
　続いて、図１Ｅに示される工程と同様にして、容量が形成される容量形成領域１００において、Ｎ＋多結晶シリコン層１０４と、Ｎ＋多結晶シリコン層１０４上に形成され、容量電極として機能する金属層１０５とを所定の形状に成形する。 Subsequently, in the same manner as the process shown in FIG. 1E, in the capacitor formation region 100 where a capacitor is formed, the N + polycrystalline silicon layer 104 and the N + polycrystalline silicon layer 104 are formed and function as a capacitor electrode. The metal layer 105 to be formed is formed into a predetermined shape.
　続いて、第１実施形態の図１Ｆ～図１Ｉに示される工程を経た後、図７Ｂを参照して、シリコン柱１ａにおいてＰ＋拡散層１０２を残存させるとともに、そのＰ＋拡散層１０２及び酸化シリコン層１０１ａ、１０１ｂを覆うように酸化シリコン層１０７を形成する。 Subsequently, after the steps shown in FIGS. 1F to 1I of the first embodiment, referring to FIG. 7B, the P + diffusion layer 102 is left in the silicon pillar 1a, and the P + diffusion layer 102 and the oxidation layer are oxidized. A silicon oxide layer 107 is formed so as to cover the silicon layers 101a and 101b.
　続いて、図７Ｂを参照して、酸化シリコン層１０７にコンタクトホール１０８を形成し、そのコンタクトホール１０８を介して、酸化シリコン層１０７上の金属配線層１０９とＰ＋拡散層１０２とを電気的に接続する。 7B, a contact hole 108 is formed in the silicon oxide layer 107, and the metal wiring layer 109 and the P + diffusion layer 102 on the silicon oxide layer 107 are electrically connected via the contact hole 108. Connect to.
　以上によって、図７Ｂに示されるように、容量形成領域１００（図７Ａ参照）に、Ｎ＋多結晶シリコン層１０４、金属層１０５、及びＰ＋拡散層１０２が容量電極として機能し、酸化シリコン層１０１ａ、１０１ｂ間の酸化シリコン層１０３が容量絶縁膜として機能する容量が形成される。 As described above, as shown in FIG. 7B, the N + polycrystalline silicon layer 104, the metal layer 105, and the P + diffusion layer 102 function as a capacitor electrode in the capacitor formation region 100 (see FIG. 7A). A capacitor is formed in which the silicon oxide layer 103 between 101a and 101b functions as a capacitor insulating film.
　本実施形態では、Ｐ＋拡散層１０２は、酸化シリコン層１０１ａ、１０１ｂをマスクとして用い、ボロン（Ｂ）などのアクセプタ不純物を第１の半導体基板１にイオンドーピング又は熱拡散することで形成した。これに限られず、Ｐ＋拡散層１０２は、酸化シリコン層１０１ａ、１０１ｂを形成する前に、均一な厚さの第１酸化シリコン層３（図１Ａ参照）上から高加速電圧によるイオンドーピングを行うことで容量形成領域１００以外の所定の領域内に形成することもできる。 In this embodiment, the P + diffusion layer 102 is formed by ion doping or thermal diffusion of acceptor impurities such as boron (B) into the first semiconductor substrate 1 using the silicon oxide layers 101a and 101b as a mask. Without being limited thereto, the P + diffusion layer 102 performs ion doping with a high acceleration voltage on the first silicon oxide layer 3 (see FIG. 1A) having a uniform thickness before the silicon oxide layers 101a and 101b are formed. Thus, it can be formed in a predetermined region other than the capacitance forming region 100.
　本実施形態によれば、図７Ｂに示される構造によって、コンタクトホール１０８によって、半導体装置の任意の場所から各容量間の接続や外部回路への電気信号の取り出しが可能となる。これにより、回路素子の更なる高集積化が実現されるようになる。 7B, according to the structure shown in FIG. 7B, the contact hole 108 enables connection between capacitors and extraction of an electric signal to an external circuit from an arbitrary location of the semiconductor device. As a result, further integration of circuit elements can be realized.
（第８実施形態）
　以下、図８Ａ～図８Ｃを参照して、本発明の第８実施形態に係る、半導体装置にダイオードを形成する方法を説明する。本実施形態及びその変形例における半導体装置の製造工程は、以下に特に説明する場合を除いて、第１実施形態と同様である。
　本実施形態では、図１Ｂに示される、第１の半導体基板１上に形成された多結晶シリコン層５を用いることで、半導体装置の回路素子であるダイオードを形成する。 (Eighth embodiment)
Hereinafter, a method for forming a diode in a semiconductor device according to an eighth embodiment of the present invention will be described with reference to FIGS. 8A to 8C. The manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
In this embodiment, a diode which is a circuit element of a semiconductor device is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
　本実施形態では、第１実施形態の図１Ａ～図１Ｉに示される工程を経ることで、図８Ａに示されるように、第２半導体基板９上に第２酸化シリコン層８が形成されるとともに、ダイオード形成領域１００ａに、金属層７、Ｎ＋多結晶シリコン層５ａ、シリコン柱１ａが下方からこの順で形成される。また、第２酸化シリコン層８上において、Ｎ＋多結晶シリコン層５ａの周囲には第１酸化シリコン層３が形成されている。 In the present embodiment, the second silicon oxide layer 8 is formed on the second semiconductor substrate 9 as shown in FIG. 8A through the steps shown in FIGS. 1A to 1I of the first embodiment. In the diode formation region 100a, the metal layer 7, the N + polycrystalline silicon layer 5a, and the silicon pillar 1a are formed in this order from below. On the second silicon oxide layer 8, a first silicon oxide layer 3 is formed around the N + polycrystalline silicon layer 5a.
　続いて、図８Ａに示される構造において、シリコン柱１ａが真性シリコンで形成されている場合には、ボロン（Ｂ）などのアクセプタ不純物をイオンドーピングすることで、図８Ｂに示されるＰ型シリコン層３０を形成する。なお、シリコン柱１ａが第１実施形態のようにＰ型に形成されている場合には、アクセプタ不純物のイオンドーピングは不要である。 Subsequently, in the structure shown in FIG. 8A, when the silicon pillar 1a is made of intrinsic silicon, an ion impurity is doped with an acceptor impurity such as boron (B) to thereby form a P-type silicon layer shown in FIG. 8B. 30 is formed. When the silicon pillar 1a is formed in the P-type as in the first embodiment, ion doping of acceptor impurities is not necessary.
　続いて、図８Ｂを参照して、熱処理を行い、Ｎ＋多結晶シリコン層５ａからＰ型シリコン層３０中にドナー不純物を熱拡散させ、Ｐ型シリコン層３０（シリコン柱１ａ）の下方部位にＮ＋拡散層６ａを形成する。 Subsequently, referring to FIG. 8B, heat treatment is performed to thermally diffuse donor impurities from the N + polycrystalline silicon layer 5a into the P-type silicon layer 30 and to form a portion below the P-type silicon layer 30 (silicon pillar 1a). N + diffusion layer 6a is formed.
　続いて、図８Ｂを参照して、Ｐ型シリコン層３０（シリコン柱１ａ）の上方部位に、ボロン（Ｂ）などのアクセプタ不純物をイオンドーピングすることにより、Ｐ＋型シリコン層３１を形成するとともに、蒸着法及びエッチングによって、Ｐ＋型シリコン層３１上に金属層３２を形成する。 Subsequently, referring to FIG. 8B, ion implantation of acceptor impurities such as boron (B) is formed on the upper portion of the P-type silicon layer 30 (silicon pillar 1 a), thereby forming a P + -type silicon layer 31. Then, the metal layer 32 is formed on the P + type silicon layer 31 by vapor deposition and etching.
　続いて、図８Ｂを参照して、Ｐ型シリコン層３０及び金属層３２を覆うように、酸化シリコン層３３を形成し、その酸化シリコン層３３において、金属層３２上の領域にコンタクトホール３４、金属配線層３５をこの順に形成する。これにより、金属配線層３５と金属層３２とをコンタクトホール３４を介して電気的に接続する。 8B, a silicon oxide layer 33 is formed so as to cover the P-type silicon layer 30 and the metal layer 32. In the silicon oxide layer 33, contact holes 34, The metal wiring layer 35 is formed in this order. Thereby, the metal wiring layer 35 and the metal layer 32 are electrically connected via the contact hole 34.
　本実施形態では、Ｐ＋型シリコン層３１とＰ型シリコン層３０とによってｐｎ接合ダイオードが形成されている。 In this embodiment, a pn junction diode is formed by the P + type silicon layer 31 and the P type silicon layer 30.
　本実施形態によれば、同一の半導体基板上に、固体撮像装置の画素、ＳＧＴなどの半導体装置と共にダイオード（回路素子）を形成することができるだけでなく、製造工程が簡略化されるようになる。 According to the present embodiment, not only a diode (circuit element) can be formed on the same semiconductor substrate together with a pixel of a solid-state imaging device and a semiconductor device such as SGT, but also the manufacturing process is simplified. .
　図８Ｃに、シリコン柱１ａにＰＩＮフォトダイオードが形成されている本実施形態の変形例を示す。この変形例では、第８実施形態に示されるシリコン柱１ａには、Ｐ型シリコン層３０に代えて、固有半導体であるｉ型シリコン層３０ｂが形成されている。そして、ｉ型シリコン層３０ｂ上には、Ｐ＋型シリコン層３１が形成されている。そして、ｉ型シリコン層３０ｂと、Ｐ＋型シリコン層３１とによってＰＩＮフォトダイオードが形成されている。 FIG. 8C shows a modification of this embodiment in which a PIN photodiode is formed on the silicon pillar 1a. In this modification, an i-type silicon layer 30b, which is a unique semiconductor, is formed on the silicon pillar 1a shown in the eighth embodiment instead of the P-type silicon layer 30. A P + type silicon layer 31 is formed on the i type silicon layer 30b. A PIN photodiode is formed by the i-type silicon layer 30 b and the P + -type silicon layer 31.
　このＰＩＮフォトダイオードにおいては、図８Ｃを参照して、Ｐ＋型シリコン層３１の上部から光が入射する。このため、その光の入射を妨害しないように、Ｐ＋型シリコン層３１と外部回路とを接続するための金属層３２が、Ｐ＋型シリコン層３１の外周領域に形成されている。 In this PIN photodiode, referring to FIG. 8C, light enters from the upper part of the P + -type silicon layer 31. Therefore, the so incident light does not interfere, the metal layer 32 for connecting the P + -type silicon layer 31 and the external circuit are formed on the outer peripheral region of the P + -type silicon layer 31.
　本変形例のＰＩＮフォトダイオードによれば、ｉ型シリコン層３０ｂの全体又は広範囲の領域に空乏層が形成されるので、広い光電変換領域を確保することができるとともに、容量形成領域の厚さに相当する空乏層の厚さが大きくなるため、低容量化が図られる。そして、このＰＩＮフォトダイオードは、光コネクション受光素子として、半導体装置の回路素子と同一の半導体基板上に形成すされる。 According to the PIN photodiode of this modification, the depletion layer is formed in the entire i-type silicon layer 30b or in a wide area, so that a wide photoelectric conversion area can be secured and the thickness of the capacitance formation area can be increased. Since the thickness of the corresponding depletion layer is increased, the capacity can be reduced. The PIN photodiode is formed as an optical connection light receiving element on the same semiconductor substrate as the circuit element of the semiconductor device.
　本変形例のＰＩＮフォトダイオードは、光スイッチとして機能するため、入力回路配線の抵抗・容量によるＲＣ遅延がなく、回路入力部の高速化及び、回路全体の高速化が実現される。 Since the PIN photodiode of this modification functions as an optical switch, there is no RC delay due to the resistance / capacitance of the input circuit wiring, and the speed of the circuit input section and the speed of the entire circuit can be increased.
　本変形例によれば、同一の半導体基板上に、固体撮像装置の画素、ＳＧＴなどの半導体装置と共にＰＩＮフォトダイオード（回路素子）を形成することができるだけでなく、製造工程が簡略化されるようになる。 According to this modification, a PIN photodiode (circuit element) can be formed on the same semiconductor substrate together with a pixel of a solid-state imaging device, a semiconductor device such as SGT, and the manufacturing process can be simplified. become.
（第９実施形態）
　以下、図９Ａ～図９Ｃを参照して、本発明の第９実施形態に係る、ＣＭＯＳインバータ回路について説明する。
　図９Ａに、本実施形態で用いるＣＭＯＳインバータ回路を示す。図９Ａに示されるように、Ｐチャネル型ＭＯＳトランジスタ３７ａとＮチャネル型ＭＯＳトランジスタ３７ｂとが直列に接続されている。Ｐチャネル型ＭＯＳトランジスタ３７ａとＮチャネル型ＭＯＳトランジスタ３７ｂのゲート同士がゲート接続配線３８を介して接続され、ゲート接続配線３８は入力端子配線Ｖｉに接続されている。Ｐチャネル型ＭＯＳトランジスタ３７ａのソースは、電源端子配線Ｖｄｄに接続されている。Ｐチャネル型ＭＯＳトランジスタ３７ａのドレインとＮチャネル型トランジスタ３７ｂのドレインとはドレイン接続配線３９を介して出力端子配線Ｖｏに接続されるとともに、Ｎチャネル型ＭＯＳトランジスタ３７ｂのソースはグランド電位となっているグランド端子配線Ｖｓｓに接続されている。 (Ninth embodiment)
A CMOS inverter circuit according to the ninth embodiment of the present invention will be described below with reference to FIGS. 9A to 9C.
FIG. 9A shows a CMOS inverter circuit used in this embodiment. As shown in FIG. 9A, a P-channel MOS transistor 37a and an N-channel MOS transistor 37b are connected in series. The gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b are connected through a gate connection wiring 38, and the gate connection wiring 38 is connected to the input terminal wiring Vi. The source of the P-channel MOS transistor 37a is connected to the power supply terminal wiring Vdd. The drain of the P-channel MOS transistor 37a and the drain of the N-channel transistor 37b are connected to the output terminal wiring Vo via the drain connection wiring 39, and the source of the N-channel MOS transistor 37b is at the ground potential. It is connected to the ground terminal wiring Vss.
　図９Ｂに、このＣＭＯＳインバータ回路の平面配置図を示す。
　図９Ｂに示されるように、コンタクトホール４１ｃ、シリコン柱４０ａ、コンタクトホール４１ａ、コンタクトホール４１ｂ、及びコンタクトホール４１ｄ、が直線状に並んで配置されている。 FIG. 9B shows a plan layout of this CMOS inverter circuit.
As shown in FIG. 9B, the contact hole 41c, the silicon pillar 40a, the contact hole 41a, the contact hole 41b, and the contact hole 41d are arranged in a straight line.
　入力端子配線Ｖｉは、コンタクトホール４１ｃから電気信号（ゲート電圧）を入力するためのものである。電源端子配線Ｖｄｄは、コンタクトホール４１ａから電源電圧を供給するためのものである。グランド端子配線Ｖｓｓは、コンタクトホール４１ｂを介してグランドに接続するためのものである。出力端子配線Ｖｏは、コンタクトホール４１ｄから電気信号を出力するためのものである。 The input terminal wiring Vi is for inputting an electric signal (gate voltage) from the contact hole 41c. The power supply terminal wiring Vdd is for supplying a power supply voltage from the contact hole 41a. The ground terminal wiring Vss is for connecting to the ground via the contact hole 41b. The output terminal wiring Vo is for outputting an electrical signal from the contact hole 41d.
　コンタクトホール４１ｃは、Ｐチャネル型ＭＯＳトランジスタ３７ａとＮチャネル型ＭＯＳトランジスタ３７ｂのゲート同士を接続するゲート接続配線３８上に形成されている。シリコン柱４０ａは、Ｐチャネル型ＭＯＳトランジスタ３７ａを構成している。コンタクトホール４１ａは、シリコン柱４０ａ上に形成されている。シリコン柱４０ｂは、Ｎチャネル型ＭＯＳトランジスタ３７ｂを構成している。コンタクトホール４１ｂはシリコン柱４０ｂ上に形成されている。コンタクトホール４１ｄは、Ｐチャネル型ＭＯＳトランジスタ３７ａのドレインとＮチャネル型ＭＯＳトランジスタ３７ｂのドレインとを互いに接続したドレイン接続配線３９上に形成されている。 The contact hole 41c is formed on the gate connection wiring 38 that connects the gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b. The silicon pillar 40a constitutes a P channel type MOS transistor 37a. The contact hole 41a is formed on the silicon pillar 40a. The silicon pillar 40b constitutes an N channel type MOS transistor 37b. The contact hole 41b is formed on the silicon pillar 40b. The contact hole 41d is formed on a drain connection wiring 39 that connects the drain of the P-channel MOS transistor 37a and the drain of the N-channel MOS transistor 37b to each other.
　そして、このコンタクトホール４１ｂ及びコンタクトホール４１ｄの列方向と直交する行方向に延びるように、それぞれ、入力端子配線Ｖｉ、電源端子配線Ｖｄｄ、グランド端子配線Ｖｓｓ、及び出力端子配線Ｖｏが配置されている（図９Ａ参照）。 The input terminal wiring Vi, the power supply terminal wiring Vdd, the ground terminal wiring Vss, and the output terminal wiring Vo are arranged so as to extend in the row direction orthogonal to the column direction of the contact holes 41b and 41d, respectively. (See FIG. 9A).
　図９Ｃは、図９ＢのＢ－Ｂ’線での断面構造図である。以下、図９Ｃを参照して、上述したＣＭＯＳインバータ回路を形成する方法を説明する。本実施形態において、ＣＭＯＳインバータ回路の形成工程は、以下に特に説明する場合を除いて、第１実施形態と同様である。 FIG. 9C is a sectional structural view taken along line B-B ′ of FIG. 9B. Hereinafter, a method of forming the above-described CMOS inverter circuit will be described with reference to FIG. 9C. In the present embodiment, the process of forming the CMOS inverter circuit is the same as that of the first embodiment, except as specifically described below.
　本実施形態において、図９Ｃに示される、Ｐチャネル型ＭＯＳトランジスタ３７ａ、Ｎチャネル型ＭＯＳトランジスタ３７ｂを有するＣＭＯＳインバータ回路は、図３Ｂに示されるＣＭＯＳインバータ回路における、Ｎチャネル型ＭＯＳトランジスタとＰチャネル型ＭＯＳトランジスタとの左右の位置関係が入れ替わっているが、図３Ａ、図３Ｂに示される第３実施形態と同様にして形成される。以下、上記実施形態と共通又は対応する符号で示される部分の説明は省略する。 In this embodiment, the CMOS inverter circuit having the P-channel MOS transistor 37a and the N-channel MOS transistor 37b shown in FIG. 9C is the same as the N-channel MOS transistor and the P-channel type in the CMOS inverter circuit shown in FIG. 3B. Although the left and right positional relationship with the MOS transistor is switched, it is formed in the same manner as the third embodiment shown in FIGS. 3A and 3B. Hereinafter, the description of the parts indicated by the same or corresponding symbols as those of the above embodiment will be omitted.
　図９Ｃに示されるように、Ｐチャネル型ＭＯＳトランジスタ３７ａにおいてドレインとして機能するＰ＋多結晶シリコン層５５ｂと、Ｎチャネル型ＭＯＳトランジスタ３７ｂにおいてドレインとして機能するＮ＋多結晶シリコン層５５ａとの下方にドレイン接続配線３９が形成されている。Ｎ＋多結晶シリコン層５５ａ及びＰ＋多結晶シリコン層５５ｂの下面にはドレイン接続配線３９が接合されている。Ｎ＋多結晶シリコン層５５ａ及びＰ＋多結晶シリコン層５５ｂは、ドレイン接続配線３９を介して接続されている。そして、ドレイン接続配線３９は、絶縁層４３ｂ上に形成され、酸化シリコン層４５を貫通するコンタクトホール４１ｄを介して出力端子配線層Ｖｏに接続されている。 As shown in FIG. 9C, below the P + polycrystalline silicon layer 55b functioning as the drain in the P-channel MOS transistor 37a and the N + polycrystalline silicon layer 55a functioning as the drain in the N-channel MOS transistor 37b. A drain connection wiring 39 is formed. A drain connection wiring 39 is bonded to the lower surfaces of the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b. The N + polycrystalline silicon layer 55 a and the P + polycrystalline silicon layer 55 b are connected via the drain connection wiring 39. The drain connection wiring 39 is formed on the insulating layer 43 b and is connected to the output terminal wiring layer Vo through a contact hole 41 d penetrating the silicon oxide layer 45.
　また、Ｐチャネル型ＭＯＳトランジスタ３７ａのゲート導体層１６ｂａ、１６ｂｂと、Ｎチャネル型ＭＯＳトランジスタ３７ｂのゲート導体層１６ａａ、１６ａｂとは、絶縁層４３ａ上に形成されたゲート接続配線３８を介して接続されている。 The gate conductor layers 16ba and 16bb of the P-channel MOS transistor 37a and the gate conductor layers 16aa and 16ab of the N-channel MOS transistor 37b are connected through a gate connection wiring 38 formed on the insulating layer 43a. ing.
　また、ゲート接続配線３８と、Ｐチャネル型ＭＯＳトランジスタ３７ａのドレインとなるＰ＋型シリコン層１７ｂ上に形成された金属配線層１８ｂ、Ｎチャネル型ＭＯＳトランジスタ３７ｂのドレインとなるＮ＋型シリコン層１７ａ上に形成された金属配線層１８ａ、ドレイン接続配線３９は、それぞれ、酸化シリコン層４５を貫通するコンタクトホール４１ｃ、４１ａ、４１ｂ、４１ｄを介して、酸化シリコン層４５上に形成された入力端子配線層Ｖｉ、電源端子配線層Ｖｄｄ、グランド端子配線層Ｖｓｓ、出力端子配線層Ｖｏに接続されている。入力端子配線層Ｖｉ、電源端子配線層Ｖｄｄ、グランド端子配線層Ｖｓｓ、出力端子配線層Ｖｏとは、互いに平行に配線されている（図９Ｃ参照）。 Further, the gate connection wiring 38, the metal wiring layer 18b formed on the P + type silicon layer 17b serving as the drain of the P channel type MOS transistor 37a, and the N + type silicon layer 17a serving as the drain of the N channel type MOS transistor 37b. The metal wiring layer 18a and the drain connection wiring 39 formed above are input terminal wirings formed on the silicon oxide layer 45 through contact holes 41c, 41a, 41b and 41d penetrating the silicon oxide layer 45, respectively. The layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vo are connected. The input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vo are wired in parallel to each other (see FIG. 9C).
　本実施形態によれば、Ｐチャネル型ＭＯＳトランジスタ３７ａにおいてドレインとして機能するＰ＋多結晶シリコン層５５ｂと、Ｎチャネル型ＭＯＳトランジスタ３７ｂにおいてドレインとして機能するＮ＋多結晶シリコン層５５ａとが、互いに近接した状態で接続されるとともに、低い電気抵抗を有するドレイン接続配線３９によって電気的に接続されている。この構造によって、高速かつ高集積度が実現されたＣＭＯＳインバータ回路を有する集積回路が得られる。 According to this embodiment, the P + polycrystalline silicon layer 55b functioning as a drain in the P-channel MOS transistor 37a and the N + polycrystalline silicon layer 55a functioning as a drain in the N-channel MOS transistor 37b are close to each other. In addition, the drain connection wiring 39 having a low electric resistance is electrically connected. With this structure, an integrated circuit having a CMOS inverter circuit that achieves high speed and high integration can be obtained.
（第１０実施形態）
　以下、図１０Ａ～図１０Ｄを参照して、本発明の第１０実施形態に係る２段構造のＣＭＯＳインバータ回路について説明する。以下、上記第９実施形態と共通又は対応する符号で示される部分及び構造の説明は省略する。
　図１０Ａに、本実施形態で用いる２段構造のＣＭＯＳインバータ回路を示す。
　図１０Ａに示されるように、Ｐチャネル型ＭＯＳトランジスタ３７ａ、３７ｃと、Ｎチャネル型ＭＯＳトランジスタ３７ｂ、３７ｄとが、それぞれ、１段目、２段目において直列に接続されている。１段目のＰチャネル型ＭＯＳトランジスタ３７ａとＮチャネル型ＭＯＳトランジスタ３７ｂの各ゲートは、ゲート接続配線３８ａを介して入力端子配線Ｖｉに接続されている。２段目のＰチャネル型ＭＯＳトランジスタ３７ｃとＮチャネル型ＭＯＳトランジスタ３７ｄの各ゲートは、ゲート接続配線３８ｂを介して１段目の出力端子配線Ｖｏに接続されている。１段目及び２段目のＰチャネル型ＭＯＳトランジスタ３７ａ、３７ｃの各ドレインは、電源端子配線Ｖｄｄに接続されている。１段目及び２段目のＰチャネル型ＭＯＳトランジスタ３７ｂ、３７ｄの各ソースは、グランド端子配線Ｖｓｓに接続されている。 (10th Embodiment)
A two-stage CMOS inverter circuit according to a tenth embodiment of the present invention will be described below with reference to FIGS. 10A to 10D. Hereinafter, description of portions and structures indicated by reference numerals common or corresponding to those of the ninth embodiment will be omitted.
FIG. 10A shows a CMOS inverter circuit having a two-stage structure used in this embodiment.
As shown in FIG. 10A, P- channel MOS transistors 37a and 37c and N- channel MOS transistors 37b and 37d are connected in series at the first and second stages, respectively. The gates of the first-stage P-channel MOS transistor 37a and N-channel MOS transistor 37b are connected to the input terminal wiring Vi through the gate connection wiring 38a. The gates of the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37d are connected to the first-stage output terminal wiring Vo through the gate connection wiring 38b. The drains of the first-stage and second-stage P- channel MOS transistors 37a and 37c are connected to the power supply terminal wiring Vdd. The sources of the first-stage and second-stage P- channel MOS transistors 37b and 37d are connected to the ground terminal wiring Vss.
　１段目において、Ｐチャネル型ＭＯＳトランジスタ３７ａのドレインとＮチャネル型トランジスタ３７ｂのドレインとは、ドレイン接続配線３９ａを介して１段目の出力端子配線Ｖｏに接続されている。
　２段目において、Ｐチャネル型トランジスタ３７ｃのドレインとＮチャネル型トランジスタ３７ｄのドレインとは、ドレイン接続配線３９ｂを介して出力端子配線Ｖｏｕｔに接続されている。 In the first stage, the drain of the P-channel MOS transistor 37a and the drain of the N-channel transistor 37b are connected to the first-stage output terminal wiring Vo via the drain connection wiring 39a.
In the second stage, the drain of the P-channel transistor 37c and the drain of the N-channel transistor 37d are connected to the output terminal wiring Vout via the drain connection wiring 39b.
　図１０Ｂに、このＣＭＯＳインバータ回路の平面配置図を示す。
　図１０Ｂに示されるように、１段目のＰチャネル型ＭＯＳトランジスタ３７ａを構成するシリコン柱４０ａ及びＮチャネル型ＭＯＳトランジスタ３７ｂを構成するシリコン柱４０ｂに形成されたゲート接続配線３８ａ上にコンタクトホール４１ｃが形成され、コンタクトホール４１ｃは、入力端子配線Ｖｉと接続されている。ゲート接続配線３８ａは、Ｐチャネル型ＭＯＳトランジスタ３７ａ及びＮチャネル型ＭＯＳトランジスタ３７ｂのゲート同士を接続する。 FIG. 10B shows a plan layout of this CMOS inverter circuit.
As shown in FIG. 10B, a contact hole 41c is formed on the gate connection wiring 38a formed on the silicon pillar 40a constituting the first-stage P-channel MOS transistor 37a and the silicon pillar 40b constituting the N-channel MOS transistor 37b. The contact hole 41c is connected to the input terminal wiring Vi. The gate connection wiring 38a connects the gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b.
　１段目において、Ｐチャネル型ＭＯＳトランジスタ３７ａのドレインとＮチャネル型ＭＯＳトランジスタ３７ｂのドレインとは、１段目のドレイン接続配線３９ａを介して接続されている。 In the first stage, the drain of the P-channel MOS transistor 37a and the drain of the N-channel MOS transistor 37b are connected via the first-stage drain connection wiring 39a.
　２段目のＰチャネル型ＭＯＳトランジスタ３７ｃを構成するシリコン柱４０ｃ及びＮチャネル型ＭＯＳトランジスタ３７ｄを構成するシリコン柱４０ｄに形成されたゲート接続配線３８ｂ上にコンタクトホール４１ｅが形成され、コンタクトホール４１ｅは、１段目の出力端子配線Ｖｏ（図１０Ａ参照）に接続されている。 A contact hole 41e is formed on the gate connection wiring 38b formed in the silicon pillar 40c constituting the second-stage P-channel MOS transistor 37c and the silicon pillar 40d constituting the N-channel MOS transistor 37d. It is connected to the first-stage output terminal wiring Vo (see FIG. 10A).
　１段目のドレイン接続配線３９ａは、コンタクトホール４１ｅ（図１０Ｃ参照）を介してゲート接続配線３８ｂと接続されている。ゲート接続配線３８ｂは、２段目のＰチャネル型ＭＯＳトランジスタ３７ｃとＮチャネル型ＭＯＳトランジスタ３７ｄのゲート同士を接続する。 The first-stage drain connection wiring 39a is connected to the gate connection wiring 38b through the contact hole 41e (see FIG. 10C). The gate connection wiring 38b connects the gates of the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37d.
　１段目及び２段目のＰチャネル型ＭＯＳトランジスタ３７ａ、３７ｃのシリコン柱４０ａ、４０ｃ上にそれぞれコンタクトホール４１ａ、４１ｃが形成されている。コンタクトホール４１ａ、４１ｃは、いずれも電源端子配線層Ｖｄｄに接続されている。 Contact holes 41a and 41c are formed on the silicon pillars 40a and 40c of the first-stage and second-stage P- channel MOS transistors 37a and 37c, respectively. The contact holes 41a and 41c are both connected to the power supply terminal wiring layer Vdd.
　１段目及び２段目のＰチャネル型ＭＯＳトランジスタ３７ｂ、３７ｄのシリコン柱４０ｂ、４０ｄ上にそれぞれコンタクトホール４１ｂ、４１ｄが形成され、コンタクトホール４１ｂ、４１ｄは、いずれもグランド端子配線層Ｖｓｓに接続されている。 Contact holes 41b and 41d are formed on the silicon pillars 40b and 40d of the first-stage and second-stage P- channel MOS transistors 37b and 37d, respectively, and both of the contact holes 41b and 41d are connected to the ground terminal wiring layer Vss. Has been.
　２段目のドレイン接続配線３９ｂ上にコンタクトホール４１ｆが形成され、コンタクトホール４１ｆは、出力端子配線層Ｖｏｕｔに接続されている。
　また、入力端子配線層Ｖｉ、電源端子配線層Ｖｄｄ、グランド端子配線層Ｖｓｓ、出力端子配線層Ｖｏｕｔは、互いに平行に配線されている。 A contact hole 41f is formed on the second-stage drain connection wiring 39b, and the contact hole 41f is connected to the output terminal wiring layer Vout.
The input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout are wired in parallel to each other.
　図１０Ｃは、図１０ＢのＣ－Ｃ’線での断面構造図であり、以下、図１０Ｃを参照して、上述した２段構造のＣＭＯＳインバータ回路について説明する。本実施形態において、２段構造のＣＭＯＳインバータ回路は、第１実施形態と同様にして形成されたものである。 FIG. 10C is a cross-sectional structural view taken along the line C-C ′ of FIG. 10B. Hereinafter, the above-described two-stage CMOS inverter circuit will be described with reference to FIG. 10C. In the present embodiment, the two-stage CMOS inverter circuit is formed in the same manner as in the first embodiment.
　図１０Ｃに示される、Ｐチャネル型ＭＯＳトランジスタ３７ａ、Ｎチャネル型ＭＯＳトランジスタ３７ｂを有するＣＭＯＳインバータ回路は、図３Ｂに示されるＣＭＯＳインバータ回路における、Ｎチャネル型ＭＯＳトランジスタとＰチャネル型ＭＯＳトランジスタとの左右の位置関係が入れ替わっているが、図３Ａ、図３Ｂに示される第３実施形態と同様にして形成される。 The CMOS inverter circuit having the P-channel MOS transistor 37a and the N-channel MOS transistor 37b shown in FIG. 10C is the same as the CMOS inverter circuit shown in FIG. 3B in terms of the left and right sides of the N-channel MOS transistor and the P-channel MOS transistor. However, they are formed in the same manner as the third embodiment shown in FIGS. 3A and 3B.
　図１０Ｃに示されるように、１段目において、Ｐチャネル型ＭＯＳトランジスタ３７ａのシリコン柱４０ａの外周を囲むゲート導体層１６ｂａ、１６ｂｂと、Ｎチャネル型ＭＯＳトランジスタ３７ｂのシリコン柱４０ｂの外周を囲むゲート導体層１６ａａ、１６ａｂとが、ゲート接続配線３８ａを介して接続されている。ゲート接続配線３８ａ上に形成された酸化シリコン層４５に、Ｎチャネル型ＭＯＳトランジスタ３７ｂ上の金属配線層１８ａと接続されたコンタクトホール４１ｂが形成されている。コンタクトホール４１ｂは、Ｎチャネル型ＭＯＳトランジスタ３７ｂのグランド端子配線Ｖｓｓに接続されている。なお、図１０Ｃでは、第１酸化シリコン層３とゲート接続配線３８ａとの間に酸化シリコン層４３が形成されている。 As shown in FIG. 10C, in the first stage, gate conductor layers 16ba and 16bb surrounding the outer periphery of the silicon column 40a of the P-channel MOS transistor 37a and the gate surrounding the outer periphery of the silicon column 40b of the N-channel MOS transistor 37b. The conductor layers 16aa and 16ab are connected via the gate connection wiring 38a. A contact hole 41b connected to the metal wiring layer 18a on the N-channel MOS transistor 37b is formed in the silicon oxide layer 45 formed on the gate connection wiring 38a. The contact hole 41b is connected to the ground terminal wiring Vss of the N channel type MOS transistor 37b. In FIG. 10C, a silicon oxide layer 43 is formed between the first silicon oxide layer 3 and the gate connection wiring 38a.
　１段目において、Ｐチャネル型ＭＯＳトランジスタ３７ａのシリコン柱４０ａの下端部に形成され、ドレインとして機能するＰ＋多結晶シリコン層５５ｂと、Ｎチャネル型ＭＯＳトランジスタ３７ｂのシリコン柱４０ｂの下端部に形成され、ドレインとして機能するＮ＋多結晶シリコン層５５ａとは、１段目のドレイン接続配線３９ａである金属配線層４２を介して互いに電気的に接続されている。 In the first stage, formed at the lower end portion of the silicon column 40a of the P-channel MOS transistor 37a and formed at the lower end portion of the P + polycrystalline silicon layer 55b functioning as the drain and the silicon column 40b of the N-channel MOS transistor 37b. The N + polycrystalline silicon layer 55a functioning as the drain is electrically connected to each other through the metal wiring layer 42 which is the first-stage drain connection wiring 39a.
　そして、金属配線層４２は、２段目のＰチャネル型ＭＯＳトランジスタ３７ｃとＮチャネル型ＭＯＳトランジスタ３７ｄのゲート同士を接続するゲート接続配線３８ｂと、酸化シリコン層４５に形成されたコンタクトホール４１ｅを介して接続されている（図１０Ａ、図１０Ｂ参照）。 The metal wiring layer 42 is connected via a gate connection wiring 38b that connects the gates of the second-stage P-channel MOS transistor 37c and the N-channel MOS transistor 37d, and a contact hole 41e formed in the silicon oxide layer 45. Are connected (see FIGS. 10A and 10B).
　１段目のＰチャネル型ＭＯＳトランジスタ３７ａのシリコン柱４０ａ上にコンタクトホール４１ａが形成され、コンタクトホール４１ａは電源端子配線層Ｖｄｄに接続されている。１段目のＮチャネル型ＭＯＳトランジスタ３７ｂのシリコン柱４０ｂ上にコンタクトホール４１ｂが形成され、コンタクトホール４１ｂはグランド端子配線層Ｖｓｓに接続されている。 A contact hole 41a is formed on the silicon pillar 40a of the first-stage P-channel MOS transistor 37a, and the contact hole 41a is connected to the power supply terminal wiring layer Vdd. A contact hole 41b is formed on the silicon pillar 40b of the first-stage N-channel MOS transistor 37b, and the contact hole 41b is connected to the ground terminal wiring layer Vss.
　２段目のドレイン接続配線３９ｂ上にコンタクトホール４１ｆが形成され、酸化シリコン層４５上において、コンタクトホール４１ｆに出力端子配線層Ｖｏｕｔが接続されている（図１０Ａ、図１０Ｂ参照）。
　また、入力端子配線層Ｖｉ、電源端子配線層Ｖｄｄ、グランド端子配線層Ｖｓｓ、出力端子配線層Ｖｏｕｔは互いに平行に配線されている（図１０Ｂ参照）。 A contact hole 41f is formed on the second-stage drain connection wiring 39b, and the output terminal wiring layer Vout is connected to the contact hole 41f on the silicon oxide layer 45 (see FIGS. 10A and 10B).
Further, the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout are wired in parallel to each other (see FIG. 10B).
　本実施形態によれば、１段目のＰチャネル型ＭＯＳトランジスタ３７ａ及びＮチャネル型ＭＯＳトランジスタ３７ｂのドレイン接続配線３９ａとして機能する金属配線層４２が、２段目のＰチャネル型ＭＯＳトランジスタ３７ｃ及びＮチャネル型ＭＯＳトランジスタ３７ｄのゲート接続配線３８ｂに、コンタクトホール４１ｅを介して直接的に接続される。この構成では、金属配線層４２（３９ａ）は、酸化シリコン層４５に形成したコンタクトホールを介して入力端子配線層Ｖｉ、電源端子配線層Ｖｄｄ、グランド端子配線層Ｖｓｓ、出力端子配線層Ｖｏｕｔ（図１０Ｂ参照）と同層まで引き上げる必要がないので、回路素子の高集積度化が実現される。 According to the present embodiment, the metal wiring layer 42 functioning as the drain connection wiring 39a of the first-stage P-channel MOS transistor 37a and N-channel MOS transistor 37b is replaced with the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37c. The channel type MOS transistor 37d is directly connected to the gate connection wiring 38b via the contact hole 41e. In this configuration, the metal wiring layer 42 (39a) is connected to the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout through the contact holes formed in the silicon oxide layer 45 (FIG. 10B), it is not necessary to pull up to the same layer as that, so that high integration of circuit elements is realized.
（第１１実施形態）
　以下、図１１Ａ、図１１Ｂを参照して、本発明の第１１実施形態に係る、半導体基板にマスク合わせマークを形成する方法を説明する。
　図１１Ａで示される工程は、第１実施形態における図１Ｈで示される工程に対応するものである。その他の工程は、以下に特に説明する場合を除いて、第１実施形態と同様である。 (Eleventh embodiment)
Hereinafter, a method for forming a mask alignment mark on a semiconductor substrate according to an eleventh embodiment of the present invention will be described with reference to FIGS. 11A and 11B.
The process shown in FIG. 11A corresponds to the process shown in FIG. 1H in the first embodiment. The other steps are the same as those in the first embodiment except for the case specifically described below.
　図１１Ａに示されるように、第２半導体基板９上には、第２酸化シリコン層８が形成されている。第２酸化シリコン層８上には、第１酸化シリコン層３、第１の半導体基板１がこの順で形成されている。 As shown in FIG. 11A, a second silicon oxide layer 8 is formed on the second semiconductor substrate 9. On the second silicon oxide layer 8, the first silicon oxide layer 3 and the first semiconductor substrate 1 are formed in this order.
　図１１Ａに示されるように、第１の半導体基板１上の所定の位置に、マスク合わせのためのマスク合わせマーク形成領域４７ａと、回路を形成するための回路形成領域４７ｂとを設定する。 As shown in FIG. 11A, a mask alignment mark formation region 47a for mask alignment and a circuit formation region 47b for forming a circuit are set at predetermined positions on the first semiconductor substrate 1.
　図１１Ａに示されるマスク合わせマーク形成領域４７ａにおいては、第１酸化シリコン層３に酸化シリコン層除去領域４８が形成されている（図１Ｂ参照）。酸化シリコン層除去領域４８の中央部には、マーク金属層４９ａ、マーク多結晶シリコン層４９ｂが積層状態で形成されている。 In the mask alignment mark formation region 47a shown in FIG. 11A, a silicon oxide layer removal region 48 is formed in the first silicon oxide layer 3 (see FIG. 1B). At the center of the silicon oxide layer removal region 48, a mark metal layer 49a and a mark polycrystalline silicon layer 49b are formed in a laminated state.
　酸化シリコン層除去領域４８は、図１Ｂに示されるように、固体撮像装置の画素における接合トランジスタのソース又はドレインが形成される孔４と同時に形成される。 As shown in FIG. 1B, the silicon oxide layer removal region 48 is formed simultaneously with the hole 4 in which the source or drain of the junction transistor in the pixel of the solid-state imaging device is formed.
　一方、図１１Ａに示されるように、回路形成領域４７ｂの中央部には、金属層７、Ｎ＋多結晶シリコン層５ａが積層状態で形成されている（図１Ｈ参照）。 On the other hand, as shown in FIG. 11A, a metal layer 7 and an N + polycrystalline silicon layer 5a are formed in a laminated state in the center of the circuit formation region 47b (see FIG. 1H).
　図１１Ａに示される状態から、マスク合わせマーク形成領域４７ａにおける第１の半導体基板１をエッチングすることにより、図１１Ｂに示されるように、所定の位置にマスク合わせ孔５０を形成する。これにより、マスク合わせ孔５０を通して、マーク金属層４９ａ、マーク多結晶シリコン層４９ｂ及び酸化シリコン層除去領域４８が露出する。
　続いて、マスク合わせ孔５０内における、マーク金属層４９ａ、マーク多結晶シリコン層４９ｂ及び酸化シリコン層除去領域４８の内のいずれか１つを基準となるマスク合わせマークとして、フォトマスクのマスク合わせを行う。
　続いて、フォトレジストが形成された領域にフォトマスクを重ねて光を照射し、回路を転写する。 By etching the first semiconductor substrate 1 in the mask alignment mark formation region 47a from the state shown in FIG. 11A, a mask alignment hole 50 is formed at a predetermined position as shown in FIG. 11B. As a result, the mark metal layer 49 a, the mark polycrystalline silicon layer 49 b, and the silicon oxide layer removal region 48 are exposed through the mask alignment hole 50.
Subsequently, the mask alignment of the photomask is performed using any one of the mark metal layer 49a, the mark polycrystalline silicon layer 49b, and the silicon oxide layer removal region 48 in the mask alignment hole 50 as a reference mask alignment mark. Do.
Subsequently, a photomask is overlaid on the region where the photoresist is formed, and light is irradiated to transfer the circuit.
　これに対し、マスク合わせ孔５０が存在しない場合には、第１の半導体基板１上にフォトレジストを被覆し、第１の半導体基板１の下方に位置するマーク金属層４９ａ、マーク多結晶シリコン層４９ｂ、酸化シリコン層除去領域４８のいずれかをマークとしてマスク合わせを行うことになる。この場合には、第１の半導体基板１は、シリコンからなり、青色光、紫外線光の吸収が大きいので、マスク合わせには透過率の高い赤色波長光又は赤外線光が用いられる。このため、マーク像の解像度が低下するとともに、マスク合わせ精度が低下する。 On the other hand, when the mask alignment hole 50 does not exist, the first semiconductor substrate 1 is covered with a photoresist, and the mark metal layer 49a and the mark polycrystalline silicon layer located below the first semiconductor substrate 1 are covered. Mask alignment is performed using either of 49b and the silicon oxide layer removal region 48 as a mark. In this case, the first semiconductor substrate 1 is made of silicon and absorbs blue light and ultraviolet light. Therefore, red wavelength light or infrared light having high transmittance is used for mask alignment. For this reason, the resolution of the mark image is lowered and the mask alignment accuracy is lowered.
　これに対して、本実施形態によれば、マスク合わせマーク形成領域４７ａには、青色光、紫外線光の吸収が大きいシリコン層が存在しないので、マーク金属層４９ａ、マーク多結晶シリコン層４９ｂ、酸化シリコン層除去領域４８上に直接フォトレジストを形成することができる。このため、高い解像度のマーク像が得られ、マスク合わせ精度が向上する。 On the other hand, according to the present embodiment, the mask alignment mark formation region 47a does not include a silicon layer that absorbs a large amount of blue light and ultraviolet light, so the mark metal layer 49a, the mark polycrystalline silicon layer 49b, the oxidation layer A photoresist can be formed directly on the silicon layer removal region 48. For this reason, a high-resolution mark image is obtained, and the mask alignment accuracy is improved.
　また、本実施形態によれば、酸化シリコン層除去領域４８上に直接フォトレジストが形成されるので、図１Ｉに示されるＮ＋多結晶シリコン層５ａとシリコン柱１ａとの位置合わせ精度が高められる。 In addition, according to the present embodiment, since the photoresist is directly formed on the silicon oxide layer removal region 48, the alignment accuracy between the N + polycrystalline silicon layer 5a and the silicon pillar 1a shown in FIG. .
　以下、図１２を参照して、図１１Ａ～図１１Ｂに示される態様と比較して、フォトマスクのマスク合わせ精度をさらに向上させる本実施形態の変形例について説明する。以下に特に説明する場合を除いて、第１１実施形態と同様とする。 Hereinafter, with reference to FIG. 12, a modification of the present embodiment that further improves the mask alignment accuracy of the photomask as compared with the mode shown in FIGS. 11A to 11B will be described. The process is the same as that of the eleventh embodiment except for the case specifically described below.
　図１２に示されるように、図１１Ｂに示されるマスク合わせ孔５０内に青色光又は紫外線光を透過する透明絶縁層５０ａを埋め込む。この透明絶縁層５０ａには、ＳｉＯ２膜を用いる。
　その後、ＣＭＰによって、そのＳｉＯ２膜及び第１の半導体基板１の表面を平坦化する。このマスク合わせ孔５０のＳｉＯ２膜による埋め込み工程は、図１Ｉを参照して、接合トランジスタが形成されるシリコン柱１ａが形成される前に行われる。 As shown in FIG. 12, a transparent insulating layer 50a that transmits blue light or ultraviolet light is embedded in the mask alignment hole 50 shown in FIG. 11B. An SiO 2 film is used for the transparent insulating layer 50a.
Thereafter, the SiO 2 film and the surface of the first semiconductor substrate 1 are planarized by CMP. The step of filling the mask alignment hole 50 with the SiO 2 film is performed before the silicon pillar 1a on which the junction transistor is formed is formed with reference to FIG. 1I.
　この変形例によれば、マスク合わせ孔５０内の透明絶縁層５０ａによって、マスク合わせマーク形成領域４７ａと回路形成領域４７ｂとに被覆するフォトレジストを薄く均一なものとすることができるので、第１１実施形態と比較して、マスク合わせ精度がさらに向上するようになる。 According to this modification, the transparent insulating layer 50a in the mask alignment hole 50 can make the photoresist covering the mask alignment mark formation region 47a and the circuit formation region 47b thin and uniform. Compared with the embodiment, the mask alignment accuracy is further improved.
（第１２実施形態）
　以下、図１３Ａ、図１３Ｂを参照して、本発明の第１２実施形態に係る半導体装置の製造方法を説明する。
　図１３Ａは、第１実施形態における図１Ｂに示される工程に対応するものである。その他の工程は、以下に特に説明する場合を除いて、第１実施形態と同様である。 (Twelfth embodiment)
A method for manufacturing a semiconductor device according to the twelfth embodiment of the present invention will be described below with reference to FIGS. 13A and 13B.
FIG. 13A corresponds to the step shown in FIG. 1B in the first embodiment. The other steps are the same as those in the first embodiment except for the case specifically described below.
　本実施形態では、図１３Ａに示される工程では、第１の半導体基板１の所定の深さに、この第１の半導体基板１を上下の２つの部分に分離するための分離層２を形成するとともに、第１の半導体基板１上に、絶縁体である第１酸化シリコン層３を形成する。 In the present embodiment, in the step shown in FIG. 13A, the separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1. At the same time, a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
　続いて、図１３Ａに示されるように、第１酸化シリコン層３において、所定の領域の酸化シリコン（ＳｉＯ２）を除去することで孔４を形成する。 Subsequently, as shown in FIG. 13A, holes 4 are formed in the first silicon oxide layer 3 by removing silicon oxide (SiO 2 ) in a predetermined region.
　続いて、図１３Ａに示されるように、この孔４（酸化シリコン層除去領域４８）を埋め込むように、第１酸化シリコン層３及び第１の半導体基板１の上に、ＣＶＤ法によって多結晶シリコン層１１１を形成する。この多結晶シリコン層１１１にはドナー不純物又はアクセプタ不純物がドープされていない。 Subsequently, as shown in FIG. 13A, polycrystalline silicon is formed on the first silicon oxide layer 3 and the first semiconductor substrate 1 by the CVD method so as to fill the hole 4 (silicon oxide layer removal region 48). Layer 111 is formed. This polycrystalline silicon layer 111 is not doped with donor impurities or acceptor impurities.
　続いて、図１３Ｂに示されるように、多結晶シリコン層１１１上に、ＣＶＤ法及びドナー不純物のイオンドープによって、ドナー不純物がドープされたＮ＋多結晶シリコン層１０６を形成する。 Subsequently, as shown in FIG. 13B, an N + polycrystalline silicon layer 106 doped with donor impurities is formed on the polycrystalline silicon layer 111 by CVD and ion doping of donor impurities.
　続いて、このＮ＋多結晶シリコン層１０６上に、図１Ｄに示される工程と同様にして金属層７を形成する。さらに、図１Ｅ～１Ｌで示された工程と同様にして半導体装置を形成する。 Subsequently, a metal layer 7 is formed on the N + polycrystalline silicon layer 106 in the same manner as the step shown in FIG. 1D. Further, a semiconductor device is formed in the same manner as the steps shown in FIGS. 1E to 1L.
　本実施形態によれば、第１の半導体基板１とＮ＋多結晶シリコン層１０６の間に、不純物がドープされていない多結晶シリコン層１１１が形成されている。この多結晶シリコン層１１１の存在により、図１Ｊに示される工程における熱処理によってＮ＋多結晶シリコン層１０６を拡散源とした場合における、シリコン柱１ａへのドナー不純物の拡散深さを調整することができる。 According to the present embodiment, the polycrystalline silicon layer 111 which is not doped with impurities is formed between the first semiconductor substrate 1 and the N + polycrystalline silicon layer 106. Due to the presence of the polycrystalline silicon layer 111, the diffusion depth of the donor impurity to the silicon pillar 1a when the N + polycrystalline silicon layer 106 is used as a diffusion source by the heat treatment in the step shown in FIG. 1J can be adjusted. it can.
　即ち、まず、熱処理によって、Ｎ＋多結晶シリコン層１０６からドナー不純物を拡散させ、多結晶シリコン層１１１をＮ＋多結晶シリコン層にする。その後、Ｎ＋多結晶シリコン層１１１からシリコン柱１ａ内に熱処理によってドナー不純物を拡散してＮ＋拡散層６ａを形成する。このように熱処理によってドナー不純物がドープされていない多結晶シリコン層１１１をＮ＋多結晶シリコン層とすることで、Ｎ＋多結晶シリコン層１０６から外部へのドナー不純物の拡散性能が減弱される。 That is, first, the donor impurity is diffused from the N + polycrystalline silicon layer 106 by heat treatment, so that the polycrystalline silicon layer 111 becomes an N + polycrystalline silicon layer. Then, by diffusing donor impurities by heat treatment of N + polysilicon layer 111 in the silicon pillar 1a to form the N + diffusion layer 6a. Thus, by making the polycrystalline silicon layer 111 not doped with donor impurities by heat treatment into an N + polycrystalline silicon layer, the diffusion performance of donor impurities from the N + polycrystalline silicon layer 106 to the outside is reduced.
　これにより、図１Ｇに示される工程において、第１の半導体基板１上で、第２の半導体基板９と第２酸化シリコン層８とを接着した後の熱処理の条件（温度、時間）によって、Ｎ＋拡散層６ａが所望の深さを超えて拡散することが想定される場合に、かかる拡散の深さを抑制するために有効となる。 Thereby, in the process shown in FIG. 1G, N 2 is changed depending on the heat treatment conditions (temperature, time) after bonding the second semiconductor substrate 9 and the second silicon oxide layer 8 on the first semiconductor substrate 1. When the + diffusion layer 6a is assumed to diffuse beyond a desired depth, this is effective for suppressing the diffusion depth.
　一方、アプセプタ不純物を拡散させる場合は、Ｎ＋多結晶シリコン層１０６に代えてＰ＋多結晶シリコン層を用いることができる。ドナー不純物又はアクセプタ不純物がドープされていない多結晶シリコン層１１１には、積極的に不純物がドープされていなくとも微量の不純物は含有されていることは、本実施形態の効果に影響しない。 On the other hand, in the case of diffusing the acceptor impurity, a P + polycrystalline silicon layer can be used in place of the N + polycrystalline silicon layer 106. Even if the polycrystalline silicon layer 111 that is not doped with donor impurities or acceptor impurities contains a small amount of impurities even if they are not actively doped, the effect of this embodiment is not affected.
　なお、第１実施形態と、第１実施形態に関連する実施形態では、第１酸化シリコン層３は、第１酸化シリコン層３は、熱酸化、陽極酸化、又はＣＶＤ（Chemical Vapor Deposition）などで形成した。これに限られず、窒化シリコン（ＳｉＮ）膜など他の絶縁膜との多層構造で構成してもよい。 In the first embodiment and the embodiment related to the first embodiment, the first silicon oxide layer 3 is formed by thermal oxidation, anodization, CVD (Chemical Vapor Deposition), or the like. Formed. However, the present invention is not limited to this, and a multilayer structure with another insulating film such as a silicon nitride (SiN) film may be used.
　なお、本発明は上述した第１～第１２実施形態で説明した実施態様に限定されず、種種の変形が可能である。
　上記実施形態では、第１の半導体基板１はＰ型の導電型とした。これに限られず、第１の半導体基板１は、固有半導体であるｉ型（イントリンシック型）でもよい。また、第１の半導体基板１に形成する回路素子に応じて、Ｎ型の導電型とすることもできる。 The present invention is not limited to the embodiments described in the first to twelfth embodiments described above, and various modifications can be made.
In the above embodiment, the first semiconductor substrate 1 is P-type conductivity. The first semiconductor substrate 1 is not limited to this, and may be i-type (intrinsic type) which is a unique semiconductor. Further, depending on the circuit element formed on the first semiconductor substrate 1, an N-type conductivity type may be used.
　同様に、図３Ｂ，図４、図９Ｃ、図１０Ｃを用いた実施形態では、Ｐチャネル型ＭＯＳトランジスタのチャネルはＮ型シリコン層３０ａに形成され、Ｎチャネル型ＭＯＳトランジスタのチャネルはＰ型シリコン層３０に形成されるものとしたが、いずれも固有半導体であるｉ型シリコンに形成されてもよい。 Similarly, in the embodiment using FIGS. 3B, 4, 9C, and 10C, the channel of the P-channel MOS transistor is formed in the N-type silicon layer 30a, and the channel of the N-channel MOS transistor is the P-type silicon layer. However, it may be formed on i-type silicon which is a unique semiconductor.
　上記実施形態では、図１Ｋにおいて、シリコン柱１ａに形成した固体撮像装置の画素において、Ｎ＋多結晶シリコン層５ａ、金属層７、Ｎ＋拡散層６ａを個別の材料層としているが、図１Ｄ～図１Ｋの間の工程で行う熱処理によって、金属層７の金属材料（Ｎｉ，Ｗなど）と、Ｎ＋多結晶シリコン層５ａ、又はＮ＋拡散層６ａの一部との反応により、金属層７、Ｎ＋多結晶シリコン層５ａ、又はＮ＋拡散層６ａの全部又は一部がシリサイド層（ＮｉＳｉ、ＷＳｉなど）に変化していてもよい。また、図１Ｌ、図２、図３Ｂ、図４、図８Ａ、図８Ｂ、図８Ｃ、図９Ｃ、図１０Ｃ、図１１Ｂ、図１２で示される各工程での熱処理によって、金属層７の金属材料とＮ＋多結晶シリコン層５ａ、又はＮ＋拡散層６ａの一部との反応により、金属層７、Ｎ＋多結晶シリコン層５ａ、又はＮ＋拡散層６ａの全部又は一部がシリサイド層（ＮｉＳｉ、ＷＳｉなど）に変化していてもよい。これらによっても、信号線（電気配線）となる部分の電気抵抗値が低下する効果が得られる。 In the above embodiment, in FIG. 1K, in the pixel of the solid-state imaging device formed on the silicon pillar 1a, the N + polycrystalline silicon layer 5a, the metal layer 7, and the N + diffusion layer 6a are used as individual material layers. Through the heat treatment performed in the steps between FIG. 1K, the metal layer 7 is reacted with the metal material (Ni, W, etc.) of the metal layer 7 and a part of the N + polycrystalline silicon layer 5a or the N + diffusion layer 6a. 7. All or part of the N + polycrystalline silicon layer 5a or the N + diffusion layer 6a may be changed to a silicide layer (NiSi, WSi, etc.). 1L, 2, 3B, 4, 8A, 8B, 8C, 9C, 10C, 11B, and 12 by the heat treatment in each step shown in FIG. And the N + polycrystalline silicon layer 5a or a part of the N + diffusion layer 6a, the metal layer 7, the N + polycrystalline silicon layer 5a, or the N + diffusion layer 6a all or part of the silicide layer ( NiSi, WSi, etc.). Also by these, the effect that the electrical resistance value of the part used as a signal line (electrical wiring) falls is acquired.
　上記実施形態では、図１Ｈに示されるように、第１の半導体基板１の所定の深さに高濃度水素イオン（Ｈ＋）をイオン注入して形成した分離層２から、４００～６００℃の熱処理により、第１の半導体基板１を上下に分離し、第１の半導体基板１を所定の厚さまで薄くした。これに限られず、第１の半導体基板１を所定の厚さまで薄くするには、例えば、非特許文献３に示される分離層２に多孔質層を形成する方法を採用してもよい。その他、第１の半導体基板１を上下に分離する方法も採用できる。 In the above embodiment, as shown in FIG. 1H, from the separation layer 2 formed by ion-implanting high-concentration hydrogen ions (H + ) to a predetermined depth of the first semiconductor substrate 1, the temperature is 400 to 600 ° C. The first semiconductor substrate 1 was separated into a top and bottom by heat treatment, and the first semiconductor substrate 1 was thinned to a predetermined thickness. For example, a method of forming a porous layer in the separation layer 2 shown in Non-Patent Document 3 may be employed to reduce the thickness of the first semiconductor substrate 1 to a predetermined thickness. In addition, a method of separating the first semiconductor substrate 1 vertically can be employed.
　また、第２半導体基板９は、シリコンとは異種の半導体、例えば、炭化シリコン（ＳｉＣ）などの化合物半導体、絶縁体又は有機樹脂体であってもよい。この構成によっても、第１の半導体基板１に形成される回路素子を保持することができる。 The second semiconductor substrate 9 may be a semiconductor different from silicon, for example, a compound semiconductor such as silicon carbide (SiC), an insulator, or an organic resin body. Also with this configuration, the circuit elements formed on the first semiconductor substrate 1 can be held.
　また、第２酸化シリコン層８、酸化シリコン層２０、２９、４５は、窒化シリコン（ＳｉＮ）膜などその他の絶縁膜との多層構成であってもよい。 Further, the second silicon oxide layer 8 and the silicon oxide layers 20, 29, 45 may have a multilayer structure with other insulating films such as a silicon nitride (SiN) film.
　また、Ｎ＋多結晶シリコン層５ａ、５５ａ、Ｐ＋多結晶シリコン層５５ｂは、イオンドープによって形成した。これに限られず、不純物の熱拡散、不純物を混入したドープド多結晶シリコン層によって形成してもよい。 The N + polycrystalline silicon layers 5a and 55a and the P + polycrystalline silicon layer 55b were formed by ion doping. However, the present invention is not limited to this, and it may be formed by thermal diffusion of impurities or a doped polycrystalline silicon layer mixed with impurities.
　また、図１Ｂにおいて、多結晶シリコン層５は、ＣＶＤ法によって形成した。これに限られず、多結晶シリコン層５は、エピタキシャル成長によって形成してもよい。この場合、第１の半導体基板１上には単結晶シリコン層が成長し、その成長条件により第１酸化シリコン層３上には多結晶シリコン層が形成される。この場合、単結晶シリコン層がドナー又はアクセプタのシリコン柱１ａへの拡散源となる。また、単結晶シリコン層の成長条件（温度など）により第１酸化シリコン層３上にはシリコン層が形成されないようにすることもできる。 In FIG. 1B, the polycrystalline silicon layer 5 was formed by a CVD method. However, the present invention is not limited to this, and the polycrystalline silicon layer 5 may be formed by epitaxial growth. In this case, a single crystal silicon layer is grown on the first semiconductor substrate 1, and a polycrystalline silicon layer is formed on the first silicon oxide layer 3 depending on the growth conditions. In this case, the single crystal silicon layer becomes a diffusion source to the silicon pillar 1a of the donor or acceptor. Further, the silicon layer can be prevented from being formed on the first silicon oxide layer 3 depending on the growth conditions (temperature, etc.) of the single crystal silicon layer.
　また、図１Ｇにおいて、シリコンからなる第２半導体基板９と、ＣＭＰで平坦化した第２酸化シリコン層８とを貼り合わせたが、第２半導体基板９の表面に、酸化又はＣＶＤ法によって酸化層又は絶縁層を形成した後に第２半導体基板９と第２酸化シリコン層８とを貼り合わせることもできる。 In FIG. 1G, the second semiconductor substrate 9 made of silicon and the second silicon oxide layer 8 flattened by CMP are bonded together, and an oxide layer is formed on the surface of the second semiconductor substrate 9 by oxidation or CVD. Alternatively, the second semiconductor substrate 9 and the second silicon oxide layer 8 can be bonded after the insulating layer is formed.
　また、図９Ｃにおいて、ドレイン接続配線３９と出力端子配線Ｖｏとはコンタクトホール４１ｄを介して接続した。これに限られず、ドレイン接続配線３９と出力端子配線Ｖｏとは、コンタクトホール４１ｄの底部がドレイン接続配線３９上のＮ＋多結晶シリコン層５５ａに接するようにして接続することもできる。この構成によっても、Ｎ＋多結晶シリコン層５５ａの電気抵抗は十分に小さいので、回路素子の高速動作が実現される。 In FIG. 9C, the drain connection wiring 39 and the output terminal wiring Vo are connected via the contact hole 41d. The drain connection wiring 39 and the output terminal wiring Vo can be connected so that the bottom of the contact hole 41 d is in contact with the N + polycrystalline silicon layer 55 a on the drain connection wiring 39. Also with this configuration, the electrical resistance of the N + polycrystalline silicon layer 55a is sufficiently small, so that high-speed operation of the circuit element is realized.
　また、図１０Ｃにおいて、ドレイン接続配線として機能する金属配線層４２（３９ａ）と２段目のゲート接続配線３８ｂとは、コンタクトホール４１ｅを介して接続した。これに限られず、コンタクトホール４１ｅの底部が金属配線層４２上のＮ＋多結晶シリコン層５５ａに接するようにして接続することもできる。この構成によっても、Ｎ＋多結晶シリコン層５５ａの電気抵抗は十分に小さいので、回路素子の高速動作が実現される。 In FIG. 10C, the metal wiring layer 42 (39a) functioning as the drain connection wiring and the second-stage gate connection wiring 38b are connected via the contact hole 41e. The connection is not limited to this, and the contact hole 41 e can be connected so that the bottom thereof is in contact with the N + polycrystalline silicon layer 55 a on the metal wiring layer 42. Also with this configuration, the electrical resistance of the N + polycrystalline silicon layer 55a is sufficiently small, so that high-speed operation of the circuit element is realized.
　また、図１Ｌ、図２、図３Ｂに示されるような、ゲート導体層１１ａ、１１ｂ、１１ｃ、１１ｄ、１６ａ、１６ｂ、１６ｃ、１６ｄ、図１０Ｃに示されるような、ゲート接続配線３８、３８ａ、３８ｂは、蒸着法又はＣＶＤ法によって形成した。これに限られず、単層又は異なる種類の複数の金属層から構成したり、不純物をドープした多結晶シリコン層又はその多結晶シリコン層と金属層との多層構成とすることもできる。または、ゲート接続配線３８、３８ａ、３８ｂは、Ｎチャネル型とＰチャネル型で異なる材料を使用してもよい。 Further, gate conductor layers 11a, 11b, 11c, 11d, 16a, 16b, 16c, 16d, and gate connection wirings 38, 38a, as shown in FIG. 10C, as shown in FIG. 1L, FIG. 2, and FIG. 38b was formed by a vapor deposition method or a CVD method. However, the present invention is not limited to this, and a single layer or a plurality of different types of metal layers, a polycrystalline silicon layer doped with impurities, or a multilayer configuration of the polycrystalline silicon layer and the metal layer may be used. Alternatively, the gate connection wirings 38, 38a, and 38b may use different materials for the N channel type and the P channel type.
　また、図１０Ｂ、図１０Ｃに示される２段ＣＭＯＳインバータ回路において、以下のように構成することも可能である。即ち、Ｐチャネル型ＭＯＳトランジスタ３７ａのシリコン柱４０ａと、Ｎチャネル型ＭＯＳトランジスタ３７ｂのシリコン柱４０ｂのそれぞれの上方部位のＰ＋型シリコン層１７ｂ、Ｎ＋型シリコン層１７ａを、酸化シリコン層４５に形成したコンタクトホール４１ａ、４１ｂを介して１段目の出力端子配線層Ｖｏｕｔに接続する。そして、Ｐチャネル型ＭＯＳトランジスタ３７ａのシリコン柱４０ａの下方部位のＰ＋多結晶シリコン層５５ｂと、Ｐ＋拡散層６ｂとに接続された金属層４６ｂを電源端子配線層Ｖｄｄとするとともに、Ｎチャネル型ＭＯＳトランジスタ３７ｂのシリコン柱４０ｂの下方部位のＮ＋多結晶シリコン層５５ａと、Ｎ＋拡散層６ａとに接続された金属層４６ａをグランド端子配線層Ｖｓｓとする。この構造においても、図１０Ｃで示した構造と同様な効果が得られる。 Further, the two-stage CMOS inverter circuit shown in FIGS. 10B and 10C can be configured as follows. That is, the P + -type silicon layer 17b and the N + -type silicon layer 17a in the upper part of the silicon pillar 40a of the P-channel MOS transistor 37a and the silicon pillar 40b of the N-channel MOS transistor 37b are formed in the silicon oxide layer 45. It is connected to the first-stage output terminal wiring layer Vout through the formed contact holes 41a and 41b. The metal layer 46b connected to the P + polycrystalline silicon layer 55b and the P + diffusion layer 6b below the silicon pillar 40a of the P channel MOS transistor 37a is used as a power supply terminal wiring layer Vdd, and N channel The metal layer 46a connected to the N + polycrystalline silicon layer 55a and the N + diffusion layer 6a below the silicon pillar 40b of the type MOS transistor 37b is defined as a ground terminal wiring layer Vss. Also in this structure, the same effect as the structure shown in FIG. 10C can be obtained.
　また、図１Ｋに示される画素構造において、ゲート導体層１１ａ、１１ｂと信号線となるＮ＋拡散層６ａとの自己整合を行うために、ゲート導体層１１ａ、１１ｂを形成した後に、ヒ素（Ａｓ）のイオンドーピング、又は、堆積Ａｓドープ酸化シリコン層を拡散源として、ゲート導体層１１ａ，１１ｂとＮ＋拡散層６ａ間のシリコン柱１ａ内にＮ＋型シリコン層を形成してもよい。 Further, in the pixel structure shown in FIG. 1K, arsenic (As) is formed after the gate conductor layers 11a and 11b are formed in order to perform self-alignment between the gate conductor layers 11a and 11b and the N + diffusion layer 6a serving as a signal line. The N + -type silicon layer may be formed in the silicon pillar 1a between the gate conductor layers 11a and 11b and the N + diffusion layer 6a by using the ion doping or the deposited As-doped silicon oxide layer as a diffusion source.
　また、図１Ｉの第１の実施形態において、第１の半導体基板１を第１酸化シリコン層３の表面までエッチングしてシリコン柱１ａを形成しているが、このエッチング処理は、第１酸化シリコン層３の表面に至る前で停止するようにしてもよい。例えば、図１４Ａに示されるように、エッチングされずに残存したシリコン層にドナー不純物をドープすることでＮ＋型シリコン層を形成してもよい。 In addition, in the first embodiment of FIG. 1I, the first semiconductor substrate 1 is etched to the surface of the first silicon oxide layer 3 to form the silicon pillar 1a. It may be stopped before reaching the surface of the layer 3. For example, as shown in FIG. 14A, an N + type silicon layer may be formed by doping a remaining silicon layer without being etched with a donor impurity.
　また、図２に示されるＳＧＴにおいても、ゲート導体層１６ａ，１６ｂとソース又はドレインとなるＮ＋拡散層６ａとの自己整合を行うために、ヒ素（Ａｓ）のイオンドーピング、又は、堆積Ａｓドープ酸化シリコン層を拡散源として、ゲート導体層１６ａ，１６ｂとＮ＋拡散層６ａ間のシリコン柱１ａ内にＮ＋型シリコン層を形成してもよい。 Also in the SGT shown in FIG. 2, arsenic (As) ion doping or deposition As doping is performed in order to perform self-alignment between the gate conductor layers 16a and 16b and the N + diffusion layer 6a serving as the source or drain. An N + type silicon layer may be formed in the silicon pillar 1a between the gate conductor layers 16a and 16b and the N + diffusion layer 6a using the silicon oxide layer as a diffusion source.
　また、図１Ｋに示される第１の実施形態の製造方法で形成された固体撮像装置の画素にはフォトダイオードを構成するＮ型シリコン層１２ａ、１２ｂの外周部に、第３酸化シリコン層１０ａ、１０ｂを介して光を反射する導体層が形成されてもよい。これにより混色が防止される。また、Ｎ型シリコン層１２ａ、１２ｂの外周部のシリコン柱１ａ内にＰ＋型シリコン層１３ａと接続されたＰ＋型シリコン層を形成することで低残像・低ノイズが実現される構造としてもよい。このように、シリコン柱１ａに固体撮像装置の機能がより高められる構造を適宜形成することができる。 Further, in the pixel of the solid-state imaging device formed by the manufacturing method of the first embodiment shown in FIG. 1K, the third silicon oxide layer 10a, on the outer peripheral portion of the N-type silicon layers 12a and 12b constituting the photodiode, A conductor layer that reflects light through 10b may be formed. This prevents color mixing. Further, by forming a P + -type silicon layer connected to the P + -type silicon layer 13 a in the silicon pillar 1 a on the outer periphery of the N-type silicon layers 12 a and 12 b, it is possible to realize a low afterimage and low noise. Good. As described above, a structure in which the function of the solid-state imaging device is further enhanced can be appropriately formed in the silicon pillar 1a.
　また、本発明の技術的思想は、同一基板上に１つの実施形態における回路素子だけでなく、複数の実施形態における回路素子が形成されるものにも適用されることは言うまでもない。また、各実施形態における各製造工程は、同一の構成が製造される場合には、順序を適宜変更することができる。 Further, it goes without saying that the technical idea of the present invention is applied not only to the circuit elements in one embodiment but also to those in which circuit elements in a plurality of embodiments are formed on the same substrate. Further, the order of the manufacturing steps in each embodiment can be appropriately changed when the same configuration is manufactured.
　なお、本発明は、本発明の広義の精神と範囲を逸脱することなく、様々な実施形態及び変形が可能とされるものである。また、上述した実施形態は、本発明の一実施例を説明するためのものであり、本発明の範囲を限定するものではない。 It should be noted that the present invention can be variously modified and modified without departing from the broad spirit and scope of the present invention. Further, the above-described embodiment is for explaining an example of the present invention, and does not limit the scope of the present invention.
　本発明は、柱状構造を有する半導体内にチャネル領域が形成されているトランジスタを備える半導体装置に適用できる。 The present invention can be applied to a semiconductor device including a transistor in which a channel region is formed in a semiconductor having a columnar structure.
　１　第１の半導体基板
　１ａ、１ｂ、４０ａ、４０ｂ、４０ｃ、４０ｄ　シリコン柱
　１ｎ　Ｎチャネル型ＳＧＴ形成領域
　１ｐ　Ｐチャネル型ＳＧＴ形成領域
　２　分離層
　３　第１酸化シリコン層
　４　孔
　５、２３　多結晶シリコン層
　５ａ、５ｂ、２３ａ、２３ｂ、５５ａ、１０４　Ｎ＋多結晶シリコン層
　５５ｂ　Ｐ＋多結晶シリコン層
　６ａ、６ａｂ　Ｎ＋拡散層
　６ｂ、１０２　Ｐ＋拡散層
　７、２８、３２、５９、１０５　金属層
　７ａ、７ｂ、７ａａ、７ｂｂ　第１接続用金属層
　８　第２酸化シリコン層
　９　第２半導体基板
　１０ａ、１０ｂ　第３酸化シリコン層
　１１ａ、１１ｂ、１１ｃ、１１ｄ、１６ａ、１６ｂ、１６ｃ、１６ｄ、１６ａａ、１６ａｂ、１６ｂａ、１６ｂｂ、５４ａ、５４ｂ　ゲート導体層
　１２ａ、１２ｂ、１２ｃ、１２ｄ　Ｎ型シリコン層
　１３ａ、１３ｂ、１７ｂ、３１、５６　Ｐ＋型シリコン層
　１４ａ、１４ｂ、１４ｃ、１４ｄ　画素選択金属配線層
　１５ａ、１５ｂ、１５ｃ、１５ｄ、７１　ゲート絶縁層
　１７ａ、５１　Ｎ＋型シリコン層
　１８ａ、１８ｂ、２２ａ、２２ｂ、２２ｃ、２４ａ、２４ｂ、２６ａ、２６ｂ、３５、４２、１０９　金属配線層
　２０、２９、３３、４３、４５、６２、１０１ａ、１０１ｂ、１０３、１０７　酸化シリコン層
　２１ｃ、３４、４１ａ、４１ｂ、４１ｃ、４１ｄ、４１ｅ、４１ｆ、７５、１０８　コンタクトホール
　２７　容量酸化シリコン層
　３０、５２　Ｐ型シリコン層
　３０ａ、５８ａ、５８ｂ　Ｎ型シリコン層
　３０ｂ　ｉ型シリコン層
　３７ａ、３７ｃ　Ｐチャネル型ＭＯＳトランジスタ
　３７ｂ、３７ｄ　Ｎチャネル型ＭＯＳトランジスタ
　３８、３８ａ、３８ｂ　ゲート接続配線
　３９、３９ａ、３９ｂ　ドレイン接続配線
　４７ａ　マスク合わせマーク形成領域
　４７ｂ　回路形成領域
　４８　酸化シリコン層除去領域
　４９ａ　マーク金属層
　４９ｂ　マーク多結晶シリコン層
　５０　マスク合わせ孔
　５０ａ　透明絶縁層
　５３ａ、５３ｂ　絶縁膜
　５７ａ、５７ｂ　画素選択線
　６０　基板
　６１、６４　半導体基板
　６６　埋め込み酸化膜基板
　６７　平面状シリコン膜
　６８　ＰＭＯＳ柱状シリコン層
　６９、７０　Ｐ＋型シリコン拡散層
　７１　ゲート絶縁層
　７２　ゲート電極
　７３　窒化シリコン（ＳｉＮ）膜
　７４　酸化シリコン（ＳｉＯ２）膜
　７６　ソース金属配線
　１００　容量形成領域
　１０６　（ドナー不純物がドープされた）Ｎ＋多結晶シリコン層
　１１０　柱状半導体
　１１１　（ドナー不純物又はアクセプタ不純物がドープされていない）多結晶シリコン層
　Ｖｉ　入力端子配線（層）
　Ｖｄｄ　電源端子配線（層）
　Ｖｓｓ　グランド端子配線（層）
　Ｖｏ、Ｖｏｕｔ　出力端子配線（層） DESCRIPTION OF SYMBOLS 1 1st semiconductor substrate 1a, 1b, 40a, 40b, 40c, 40d Silicon pillar 1n N channel type SGT formation region 1p P channel type SGT formation region 2 Separation layer 3 First silicon oxide layer 4 Hole 5, 23 Polycrystalline silicon layers 5a, 5b, 23a, 23b, 55a, 104 N + polycrystalline silicon layer 55b P + polycrystalline silicon layer 6a, 6ab N + diffusion layer 6b, 102 P + diffusion layer 7,28,32,59,105 metal layer 7a, 7b, 7aa, 7bb First connection metal layer 8 Second silicon oxide layer 9 Second semiconductor substrate 10a, 10b Third silicon oxide layer 11a, 11b, 11c, 11d, 16a, 16b, 16c, 16d, 16aa, 16ab, 16ba, 16bb, 54a, 54b Gate conductor layer 12a, 12b, 12c, 12d N-type silicon layer 1 a, 13b, 17b, 31,56 P + -type silicon layer 14a, 14b, 14c, 14d pixel selection metal wiring layers 15a, 15b, 15c, 15d, 71 a gate insulating layer 17a, 51 N + -type silicon layer 18a, 18b, 22a, 22b, 22c, 24a, 24b, 26a, 26b, 35, 42, 109 Metal wiring layer 20, 29, 33, 43, 45, 62, 101a, 101b, 103, 107 Silicon oxide layer 21c, 34, 41a, 41b, 41c, 41d, 41e, 41f, 75, 108 Contact hole 27 Capacitance silicon oxide layer 30, 52 P-type silicon layer 30a, 58a, 58b N-type silicon layer 30b i-type silicon layer 37a, 37c P-channel MOS transistor 37b 37d N-channel MOS transistors 38, 38a 38b Gate connection wiring 39, 39a, 39b Drain connection wiring 47a Mask alignment mark formation region 47b Circuit formation region 48 Silicon oxide layer removal region 49a Mark metal layer 49b Mark polycrystalline silicon layer 50 Mask alignment hole 50a Transparent insulating layer 53a, 53b Insulation Films 57a, 57b Pixel selection line 60 Substrate 61, 64 Semiconductor substrate 66 Embedded oxide film substrate 67 Planar silicon film 68 PMOS columnar silicon layer 69, 70 P + type silicon diffusion layer 71 Gate insulating layer 72 Gate electrode 73 Silicon nitride (SiN) ) film 74 of silicon oxide (SiO 2) film 76 source metal wiring 100 capacitor forming region 106 (donor impurities are doped) N + polycrystalline silicon layer 110 columnar semiconductor 111 (donor impurity or an acceptor impurity doping of I have not) polycrystalline silicon layer Vi input terminal wiring (layer)
Vdd Power supply terminal wiring (layer)
Vss ground terminal wiring (layer)
Vo, Vout Output terminal wiring (layer)

Claims (17)

  1. 　半導体基板上に第１の絶縁層を形成する第１絶縁層形成工程と、
    　前記第１の絶縁層の所定の部分を除去し、絶縁層除去領域を形成する絶縁層除去工程と、
    　少なくとも前記絶縁層除去領域を覆うように、前記半導体基板上にドナー不純物又はアクセプタ不純物を含む第１の半導体層を形成する第１半導体層形成工程と、
    　前記第１の半導体層上に導電層を形成する導電層形成工程と、
    　前記導電層及び前記第１の半導体層を所定の形状に成形する成形工程と、
    　前記所定の形状に形成した導電層及び第１の半導体層を覆うように、第２の絶縁層を形成する第２絶縁層形成工程と、
    　前記第２の絶縁層の表面を平坦化する平坦化工程と、
    　前記平坦化された前記第２の絶縁層の表面に、基板を接着する接着工程と、
    　前記半導体基板を所定の厚さまで薄くする薄膜化工程と、
    　前記第１の半導体層上に、前記半導体基板から柱状構造を有する柱状半導体を形成する柱状半導体形成工程と、
    　前記柱状半導体に前記回路素子を形成する回路素子形成工程と、を備え、
    　少なくとも前記第１半導体層形成工程以後に、前記ドナー不純物又はアクセプタ不純物を含む前記第１の半導体層から当該不純物を拡散させることで前記柱状半導体に第１の半導体領域を形成する第１半導体領域形成工程をさらに備える、
    　ことを特徴とする半導体装置の製造方法。     A first insulating layer forming step of forming a first insulating layer on the semiconductor substrate;
    An insulating layer removing step of removing a predetermined portion of the first insulating layer to form an insulating layer removal region;
    A first semiconductor layer forming step of forming a first semiconductor layer containing a donor impurity or an acceptor impurity on the semiconductor substrate so as to cover at least the insulating layer removal region;
    A conductive layer forming step of forming a conductive layer on the first semiconductor layer;
    A molding step of molding the conductive layer and the first semiconductor layer into a predetermined shape;
    A second insulating layer forming step of forming a second insulating layer so as to cover the conductive layer and the first semiconductor layer formed in the predetermined shape;
    A planarization step of planarizing the surface of the second insulating layer;
    An adhesion step of adhering a substrate to the flattened surface of the second insulating layer;
    A thinning process for thinning the semiconductor substrate to a predetermined thickness;
    Forming a columnar semiconductor having a columnar structure from the semiconductor substrate on the first semiconductor layer; and
    A circuit element forming step of forming the circuit element on the columnar semiconductor,
    Forming a first semiconductor region in the columnar semiconductor by diffusing the impurity from the first semiconductor layer containing the donor impurity or acceptor impurity at least after the first semiconductor layer forming step The process further includes
    A method for manufacturing a semiconductor device.
  2. 　前記回路素子形成工程は、
    　前記柱状半導体の外周部に第３の絶縁層を形成するとともに、前記第３の絶縁層の外周部にゲート導体層を形成する工程と、
    　前記ゲート導体層の上方部位かつ前記柱状半導体の表層部に、前記第１の半導体領域と同一導電型である第４の半導体領域を形成する工程と、
    　前記柱状半導体において、前記第３の絶縁層の上方部位に、前記第１の半導体領域と反対導電型の第３の半導体領域を形成する工程と、を含む、ことを特徴とする請求項１に記載の半導体装置の製造方法。     The circuit element forming step includes
    Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer;
    Forming a fourth semiconductor region having the same conductivity type as the first semiconductor region in a portion above the gate conductor layer and in a surface layer portion of the columnar semiconductor;
    Forming a third semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the third insulating layer in the columnar semiconductor. The manufacturing method of the semiconductor device of description.
  3. 　前記回路素子形成工程は、
    　前記柱状半導体の外周部に第３の絶縁層を形成するとともに、前記第３の絶縁層の外周部にゲート導体層を形成する工程と、
    　前記柱状半導体における前記第３の絶縁層の上方部位に、前記第１の半導体領域と同一導電型の第５の半導体領域を形成する工程と、を含む、ことを特徴とする請求項１に記載の半導体装置の製造方法。     The circuit element forming step includes
    Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer;
    Forming a fifth semiconductor region having the same conductivity type as that of the first semiconductor region at a position above the third insulating layer in the columnar semiconductor. Semiconductor device manufacturing method.
  4. 　前記回路素子形成工程は、
    　前記柱状半導体の上方部位に、前記第１の半導体領域と反対導電型の第６の半導体領域を形成する工程を含む、ことを特徴とする請求項１に記載の半導体装置の製造方法。     The circuit element forming step includes
    2. The method of manufacturing a semiconductor device according to claim 1, comprising a step of forming a sixth semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the columnar semiconductor.
  5. 　前記第１半導体層形成工程は、前記第１の半導体層と同層に、電気抵抗として機能する第２の半導体層を形成する工程を含む、ことを特徴とする請求項１乃至４のいずれか１項に記載の半導体装置の製造方法。 5. The method according to claim 1, wherein the first semiconductor layer forming step includes a step of forming a second semiconductor layer functioning as an electric resistance in the same layer as the first semiconductor layer. 2. A method for manufacturing a semiconductor device according to item 1.
  6. 　前記第１半導体層形成工程は、容量電極として機能する前記第１の半導体層上の所定の領域に容量絶縁膜として機能する絶縁膜を形成する工程を含み、
    　前記導電層形成工程は、前記絶縁膜上に、前記第１の半導体層と共に容量電極として機能する導電層を形成する工程を含む、ことを特徴とする請求項１乃至５のいずれか１項に記載の半導体装置の製造方法。     The first semiconductor layer forming step includes a step of forming an insulating film functioning as a capacitor insulating film in a predetermined region on the first semiconductor layer functioning as a capacitor electrode;
    The said conductive layer formation process includes the process of forming the conductive layer which functions as a capacitive electrode with the said 1st semiconductor layer on the said insulating film, The any one of Claim 1 thru | or 5 characterized by the above-mentioned. The manufacturing method of the semiconductor device of description.
  7. 　前記第１絶縁層形成工程は、前記半導体基板上に、第１の絶縁層と共に第４の絶縁層を形成するとともに、予め設定した容量形成領域に、前記第４の絶縁層よりも厚さが薄く、容量絶縁膜として機能する第５の絶縁層を形成する工程を含み、
    　前記導電層形成工程は、前記第５の絶縁層上に、容量電極として機能する導電層を形成する工程を含み、
    　前記絶縁層除去工程は、前記容量形成領域に、ドナー不純物又はアクセプタ不純物を有し、容量電極として機能する不純物層を形成する容量形成工程を含む、ことを特徴とする請求項１乃至６のいずれか１項に記載の半導体装置の製造方法。     The first insulating layer forming step forms a fourth insulating layer together with the first insulating layer on the semiconductor substrate, and has a thickness larger than that of the fourth insulating layer in a preset capacitance forming region. Forming a thin fifth insulating layer functioning as a capacitive insulating film,
    The conductive layer forming step includes a step of forming a conductive layer functioning as a capacitor electrode on the fifth insulating layer,
    The said insulating layer removal process includes the capacity | capacitance formation process which forms the impurity layer which has a donor impurity or an acceptor impurity in the said capacity | capacitance formation area | region, and functions as a capacity | capacitance electrode. A method for manufacturing a semiconductor device according to claim 1.
  8. 　前記半導体基板上にマスク合わせマーク形成領域を設定するマスク合わせマーク形成領域設定工程と、
    　前記マスク合わせマーク形成領域に、マスク合わせ孔を形成し、前記絶縁層除去領域、前記第１の絶縁層及び前記導電層の少なくとも一つを露出させる工程と、
    　前記マスク合わせ孔を通して、前記絶縁層除去領域、前記第１の絶縁層及び前記導電層の内の少なくとも一つからなるマスク合わせマークを形成するマスク合わせマーク形成工程と、
    　前記マスク合わせマークを基準として、フォトマスクのマスク合わせを行うマスク合わせ工程と、をさらに備える、ことを特徴とする請求項１乃至７のいずれか１項に記載の半導体装置の製造方法。     A mask alignment mark formation region setting step for setting a mask alignment mark formation region on the semiconductor substrate;
    Forming a mask alignment hole in the mask alignment mark formation region to expose at least one of the insulating layer removal region, the first insulating layer, and the conductive layer;
    A mask alignment mark forming step of forming a mask alignment mark comprising at least one of the insulating layer removal region, the first insulating layer, and the conductive layer through the mask alignment hole;
    The method of manufacturing a semiconductor device according to claim 1, further comprising: a mask alignment step of performing mask alignment of a photomask with the mask alignment mark as a reference.
  9. 　前記マスク合わせ孔に透明絶縁体を埋め込む工程をさらに備え、
    　前記マスク合わせマーク形成工程では、前記透明絶縁体を通して、前記絶縁層除去領域、前記第１の絶縁層及び前記導電層の内の少なくとも一つからなるマスク合わせマークを形成し、
    　前記マスク合わせ工程では、前記マスク合わせマークを基準として、フォトマスクのマスク合わせを行う、ことを特徴とする請求項８に記載の半導体装置の製造方法。     A step of embedding a transparent insulator in the mask alignment hole;
    In the mask alignment mark forming step, a mask alignment mark comprising at least one of the insulating layer removal region, the first insulating layer, and the conductive layer is formed through the transparent insulator,
    9. The method of manufacturing a semiconductor device according to claim 8, wherein in the mask alignment step, mask alignment of a photomask is performed with reference to the mask alignment mark.
  10. 　前記絶縁層除去工程と、前記第１半導体層形成工程との間に、前記絶縁層除去領域を覆うように、ドナー不純物及びアクセプタ不純物がドープされていない第２の半導体層を形成する工程をさらに備える、ことを特徴とする請求項１乃至９のいずれか１項に記載の半導体装置の製造方法。 Forming a second semiconductor layer not doped with donor impurities and acceptor impurities so as to cover the insulating layer removal region between the insulating layer removing step and the first semiconductor layer forming step; The method for manufacturing a semiconductor device according to claim 1, wherein the method is provided.
  11. 　請求項２に記載の半導体装置の製造方法によって製造される半導体装置であって、
    　前記柱状半導体は、
    　前記第１の半導体領域上に形成された当該第１の半導体領域と反対導電型の半導体又は固有半導体からなる第２の半導体領域を備え、
    　前記第２の半導体領域と前記第４の半導体領域とから電磁エネルギー波の照射により発生する信号電荷を蓄積するダイオードが形成され、
    　前記ダイオードがゲートとして機能し、前記第１の半導体領域と前記第３の半導体領域のいずれか一方がソース、他方がドレインとしてそれぞれ機能し、かつ、前記第２の半導体領域に形成されたチャネルを流れるとともに前記ダイオードに蓄積された信号電荷量に応じて変化する電流を信号取り出し手段によって取り出し可能とされた接合トランジスタが形成され、
    　前記ゲート導体層がゲートとして機能するとともに、前記第１の半導体領域及び前記第４の半導体領域の一方がソースとして機能し、他方がドレインとして機能するＭＯＳトランジスタによって、前記ゲート導体層に電圧が印加されることで、前記ダイオードに蓄積された信号電荷を前記第１の半導体領域に除去する信号電荷除去手段が形成されている、ことを特徴とする半導体装置。     A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 2,
    The columnar semiconductor is
    A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor;
    A diode that accumulates signal charges generated by irradiation of electromagnetic energy waves from the second semiconductor region and the fourth semiconductor region is formed,
    The diode functions as a gate, one of the first semiconductor region and the third semiconductor region functions as a source, the other functions as a drain, and a channel formed in the second semiconductor region. A junction transistor is formed that is capable of taking out a current that flows and changes in accordance with the amount of signal charge accumulated in the diode by a signal taking-out means,
    The gate conductor layer functions as a gate, and a voltage is applied to the gate conductor layer by a MOS transistor in which one of the first semiconductor region and the fourth semiconductor region functions as a source and the other functions as a drain. Thus, a signal charge removing means for removing signal charges accumulated in the diode in the first semiconductor region is formed.
  12. 　請求項３に記載の半導体装置の製造方法によって製造される半導体装置であって、
    　前記柱状半導体は、
    　前記第１の半導体領域上に形成された当該第１の半導体領域と反対導電型又は固有半導体からなる第２の半導体領域を備え、
    　前記ゲート導体層がゲートとして機能するとともに、前記第１の半導体領域及び前記第５の半導体領域の一方がソースとして機能し、他方がドレインとして機能するＭＯＳトランジスタが形成されている、ことを特徴とする半導体装置。     A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 3,
    The columnar semiconductor is
    A second semiconductor region formed on the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region or an intrinsic semiconductor;
    The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain. Semiconductor device.
  13. 　請求項４に記載の半導体装置の製造方法によって製造される半導体装置であって、
    　前記柱状半導体は、
    　前記第１の半導体領域と第６の半導体領域との間に、前記第１の半導体領域と反対導電型又は固有半導体からなる第２の半導体領域を備え、
    　前記第２の半導体領域と、前記第６の半導体領域と、からダイオードが形成されている、ことを特徴とする半導体装置。     A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 4,
    The columnar semiconductor is
    Between the first semiconductor region and the sixth semiconductor region, a second semiconductor region made of a conductive type or a specific semiconductor opposite to the first semiconductor region is provided,
    2. A semiconductor device, wherein a diode is formed from the second semiconductor region and the sixth semiconductor region.
  14. 　請求項１又は３に記載の半導体装置の製造方法によって製造される半導体装置であって、
    　前記第１の半導体層上に複数の前記柱状半導体が形成されており、
    　前記複数の柱状半導体は、前記第１の半導体領域にアクセプタ不純物がドープされている複数の第１の柱状半導体と、前記第１の半導体領域にドナー不純物がドープされている複数の第２の柱状半導体とからなる、ことを特徴とする半導体装置。     A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1 or 3,
    A plurality of the columnar semiconductors are formed on the first semiconductor layer;
    The plurality of columnar semiconductors include a plurality of first columnar semiconductors in which the first semiconductor region is doped with an acceptor impurity, and a plurality of second columnar semiconductors in which the first semiconductor region is doped with a donor impurity. A semiconductor device comprising a semiconductor.
  15. 　請求項１乃至３のいずれか１項に記載の半導体装置の製造方法によって製造される半導体装置であって、
    　前記第１の半導体層上に複数の前記柱状半導体が形成されており、
    　前記複数の柱状半導体における、複数の前記第１の半導体領域、及び、複数の前記導電層の内の両方、又は、一方が互いに接続されている、ことを特徴とする半導体装置。     A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1,
    A plurality of the columnar semiconductors are formed on the first semiconductor layer;
    In the plurality of columnar semiconductors, both or one of the plurality of first semiconductor regions and the plurality of conductive layers are connected to each other.
  16. 　請求項３に記載の半導体装置の製造方法によって製造される半導体装置であって、
    　前記第１の半導体層上に複数の前記柱状半導体が形成されており、
    　前記各柱状半導体は、
    　前記第１の半導体領域上に形成された当該第１の半導体領域と反対導電型の半導体又は固有半導体からなる第２の半導体領域と、
    　前記第２の半導体領域上に形成された第５の半導体領域と、
    　前記第２の半導体領域の外周部に形成された第３の絶縁層と、
    　前記第３の絶縁層の外周部に形成されたゲート導体層と、を備え、
    　前記ゲート導体層がゲートとして機能するとともに、前記第１の半導体領域及び前記第５の半導体領域の一方がソースとして機能し、他方がドレインとして機能するＭＯＳトランジスタが形成され、
    　前記第１の半導体層は、前記複数の柱状半導体に亘って連続して繋がるように形成されているとともに、前記繋がるように形成された前記第１の半導体層は、絶縁層に形成されたコンタクトホールを介して、外部回路に接続するための配線層に接続されている、ことを特徴とする半導体装置。     A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 3,
    A plurality of the columnar semiconductors are formed on the first semiconductor layer;
    Each of the columnar semiconductors is
    A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor;
    A fifth semiconductor region formed on the second semiconductor region;
    A third insulating layer formed on the outer periphery of the second semiconductor region;
    A gate conductor layer formed on the outer periphery of the third insulating layer,
    The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
    The first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer formed so as to be connected is a contact formed on an insulating layer. A semiconductor device which is connected to a wiring layer for connecting to an external circuit through a hole.
  17. 　請求項３に記載の半導体装置の製造方法によって製造される半導体装置であって、
    　前記第１の半導体層上に複数の前記柱状半導体が形成されており、
    　前記各柱状半導体は、
    　前記第１の半導体領域上に形成された当該第１の半導体領域と反対導電型の半導体又は固有半導体からなる第２の半導体領域と、
    　前記第２の半導体領域上に形成された第５の半導体領域と、
    　前記第２の半導体領域の外周部に形成された第３の絶縁層と、
    　前記第３の絶縁層の外周部に形成されたゲート導体層と、を備え、
    　前記ゲート導体層がゲートとして機能するとともに、前記第１の半導体領域及び前記第５の半導体領域の一方がソースとして機能し、他方がドレインとして機能するＭＯＳトランジスタが形成され、
    　前記第１の半導体層は、前記複数の柱状半導体に亘って連続して繋がるように形成されているとともに、前記第１の半導体層は、絶縁層に形成されたコンタクトホールを介して、所定のトランジスタのゲートに接続するための配線層に接続されている、ことを特徴とする半導体装置。     A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 3,
    A plurality of the columnar semiconductors are formed on the first semiconductor layer;
    Each of the columnar semiconductors is
    A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor;
    A fifth semiconductor region formed on the second semiconductor region;
    A third insulating layer formed on the outer periphery of the second semiconductor region;
    A gate conductor layer formed on the outer periphery of the third insulating layer,
    The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
    The first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer is connected to a predetermined hole via a contact hole formed in the insulating layer. A semiconductor device, wherein the semiconductor device is connected to a wiring layer for connecting to a gate of a transistor.
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