WO2012106929A1 - 计算机系统及其配置时钟的方法 - Google Patents

计算机系统及其配置时钟的方法 Download PDF

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Publication number
WO2012106929A1
WO2012106929A1 PCT/CN2011/077625 CN2011077625W WO2012106929A1 WO 2012106929 A1 WO2012106929 A1 WO 2012106929A1 CN 2011077625 W CN2011077625 W CN 2011077625W WO 2012106929 A1 WO2012106929 A1 WO 2012106929A1
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WO
WIPO (PCT)
Prior art keywords
node
clock
nodes
selection module
computer system
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Application number
PCT/CN2011/077625
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English (en)
French (fr)
Inventor
吴登奔
张羽
俞柏峰
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP11858207.1A priority Critical patent/EP2573643B1/en
Priority to PCT/CN2011/077625 priority patent/WO2012106929A1/zh
Priority to CN201180001193.7A priority patent/CN102317885B/zh
Publication of WO2012106929A1 publication Critical patent/WO2012106929A1/zh
Priority to US13/717,205 priority patent/US9026835B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1604—Error detection or correction of the data by redundancy in hardware where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Definitions

  • the present invention relates to computer system technology, and in particular, to a computer system and a clock configuration method for realizing node clock synchronization of a computer system of the same partition system. Background technique
  • a computer system such as a minicomputer that requires high computational and fault-tolerant performance, is composed of a plurality of different nodes, wherein the nodes are the smallest units of the hard partition, and each node can be composed of a single partition or other nodes.
  • the interconnections form a partition, and each partition can run an independent operating system.
  • several independent nodes in the computer system form a whole partition system through the CPU interconnection technology, and an operating system can be run in the whole.
  • the system can access any valid device on the node to which the partition belongs.
  • Each node in a partitioned system requires not only a clock, but each node requires a clock from the same source. This is because the clock is very important in digital circuits. Once there is no clock, the digital logic is not working at all. If the nodes in the partition system do not use the clock from the same source, the entire partition will not work properly.
  • the partition system uses a single clock synchronization scheme to implement clock synchronization within the partition system. That is, there is only one clock in a partition system, which is the clock source of each node in the partition system.
  • the clock is placed on a node of the partition system, or is separated from each node and set separately.
  • a partition system has only one clock as a clock source. When the clock is abnormal, the partition system has no clock source available, and the clock synchronization of each node of the partition system cannot be realized.
  • Summary of the invention The purpose of the embodiments of the present invention is to provide a computer system and a clock configuration method for realizing node clock synchronization of the same partition system of the computer system, so that the same partition system in the computer system can still be realized when the clock source in the partition system fails. Each node clock is synchronized.
  • An embodiment of the present invention provides a computer system, including at least two nodes, where the at least two nodes each include a selection module and a CPU, and the input of the selection module is a clock of the node and a clock output by other nodes. The output end is connected to the input end of the selection module of the CPU and other nodes;
  • the computer system further includes a clock control module, and an output end of the clock control module is connected to a control end of the selection module, and is configured to control clocks of the at least two nodes to be the same clock.
  • the input terminal of the selection module of each node has a clock source of the node, and the clock output of other nodes is also used, and the third party controls the selection module to select a clock input through a third-party clock control module.
  • the clock input of the node and can provide clocks for other nodes to ensure that each node uses the same clock source, when the clock of multiple nodes is abnormal, as long as the computer system still has a normal clock, the computer system Still working.
  • the embodiment of the invention further provides a clock configuration method for realizing node clock synchronization of the same partition system in the above computer system, including:
  • each node in the same partition system using the computer system has multiple clocks and optional structural features, and is the same partition.
  • the two connected nodes of the system select a connection channel to ensure that the clock sources of the nodes in the same partition system are unified, thereby realizing each in the same partition system.
  • the clock of the node is synchronized, and the clock channel is abnormal.
  • Other connection channels can be selected, and the clock sources of the nodes in the same partition system are still unified, and the clock synchronization of each node in the same partition system is realized.
  • FIG. 1 is a schematic structural diagram of a node in a computer system according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a clock connection of two nodes in a computer system according to an embodiment of the present invention
  • FIG. 3A is a schematic diagram of a clock connection of four nodes in a computer system according to an embodiment of the present invention
  • FIG. 3B is a schematic diagram of a frame of FIG.
  • 4A is a schematic diagram of a clock connection framework of eight nodes in a computer system according to an embodiment of the present invention
  • 4B is a schematic diagram of a clock connection framework of 16 nodes in a computer system according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a clock connection frame of 32 nodes in a computer system according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of an 8-node computer system according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a clock configuration method for implementing node clock synchronization of the same partition system in the foregoing computer system according to an embodiment of the present invention
  • FIG. 8A is a clock path diagram after the clock is configured in FIG. 7; FIG.
  • 8B is a schematic diagram of remaining nodes that are not configured during the configuration process of FIG. 7;
  • 8C is a diagram showing a replacement clock path after the clock channel between node 0 and node 1 is abnormal in the computer system shown in FIG. 6;
  • FIG. 8D is a schematic diagram of remaining nodes that are not configured during the formation of FIG. 8C;
  • FIG. 9 is a schematic diagram of another clock connection of eight nodes in the computer system shown in FIG. 6.
  • the computer system provided by the embodiment of the present invention includes at least two nodes, wherein, as shown in FIG. 1, the at least two nodes each include a selection module 11 and a CPU 12, and an input Input 1 Input of the selection module 11 N is the clock of the src and other nodes of the node, and the output is
  • output is connected to the input terminals of the CPU 12 and other nodes of the selection module;
  • the computer system further includes a clock control module 13.
  • the output end of the clock control module 13 is connected to the control end of the selection module, and is configured to control the output clock of the output module of the at least two nodes to be the same clock.
  • the input terminal of the selection module of each node has a clock source of the node, and the clock output of the other node, and the third party controls the selection module to select a clock input as the clock of the node through a third-party clock control module.
  • Input and can provide clocks for other nodes to ensure that each node uses the same clock source.
  • the computer system can still work normally as long as the computer system still has a normal clock.
  • the two nodes are directly connected.
  • the output of the selection module 211 in the node 21 is directly connected to the input of the selection module 221 of the node 22, and the output of the selection module 221 of the node 22 is connected to the input of the selection module 211 of the node 21.
  • the other input of the selection module is the clock src of the node.
  • the output of the selection module 211 in the node 21 is connected to the CPU 212 of the node, and the output of the selection module 221 in the node 22 is connected to the CPU 222 of the node.
  • Node 21 and node 22 are bidirectional connections, which can be used to close a connection. When the open connection is abnormal, the closed connection is enabled.
  • the control terminals of the selection module 211 and the selection module 221 are all controlled by the clock control module 23.
  • the input of the selected module in each node is the clock of the node and the clock of other nodes.
  • the clock src of one node is taken as a common clock source, thereby ensuring the Clock synchronization.
  • connection mode is similar to that of FIG. 2, and the four nodes are connected.
  • the selection modules are connected in a ring shape, and the input of each node's selection module is the output of the node's clock and the connected modules of the two nodes.
  • the common node 31, the node 32, the node 33, and the node 34 have four nodes, and the selection modules of the four nodes are sequentially connected in a ring shape, as shown in FIG. 3B.
  • the output end of the selection module 311 is connected to the input terminal of the selection module 321 and the node 34 of the node 32, and is connected to the CPU 312 of the node; in the node 32, the output of the module 321 is selected.
  • the terminal is connected to the input terminal of the selection module 311 and the node 33 of the node 31, and is connected to the CPU 332 of the node; in the node 33, the output of the selection module 331 and the selection module 321 and the node 34 of the node 32 are The input end of the selection module 341 is connected and connected to the CPU 322 of the node; in the node 34, the output end of the selection module 341 is connected to the input module of the selection module 311 and the node 33 of the node 31, and is connected to the node.
  • the CPU 342 is connected.
  • the control terminals of all the selected modules are connected to the clock control module 35.
  • the connection between any two nodes is a bidirectional connection, that is, there are two connection channels, that is, clock channels, between the two connected nodes, and the unenabled connection channel needs to be closed when used.
  • the clock channel is reselected according to the normal condition of the clock channel.
  • 8 nodes When there are 8 nodes in the computer system, 8 nodes are located at each vertex of a cuboid, and 4 nodes in each surface of the cuboid are connected by a selection module or connected by a selection module, and each node is connected. Connect with three nodes through the selection module.
  • FIG. 4A four nodes of each surface of the rectangular parallelepiped are sequentially connected into a ring by a selection module, wherein the ring connection is similar to that of FIG. 3A, and each node is connected to three nodes through a selection module, any two.
  • the connections between the nodes are two-way connections. That is, there are two connection channels, that is, clock channels, between the two nodes connected.
  • connection channels When using, one of the connection channels can be closed, and the other connection channel can be used. When the connection channel used is abnormal, the closed connection channel is enabled.
  • the obtained cuboid connection is different from that of FIG. 3A in that each node is connected to three nodes. Specifically, the input of each node's selection module is the clock of the node and the output of the selected module of the three connected nodes. .
  • every 8 nodes are located at each vertex of one cuboid, and 4 nodes in each surface of the cuboid are connected by a selection module or sequentially connected through a selection module, and each node Connected to the 3+n nodes through the selection module, the connection of the cuboid is similar to that of FIG. 4A, and the nodes at the same position of each of the cuboids are connected by the selection module, and the input of the selection module of each node is connected to the clock of the node.
  • the connection between any two nodes is a two-way connection. That is, there are two connection channels, that is, clock channels, between the two nodes connected. When using, one of the connection channels can be closed, and the other connection channel can be used. When the connection used is abnormal, the closed connection channel is enabled.
  • the structure shown in Fig. 4B is obtained after the connection.
  • the structure shown in Fig. 5 is obtained after the connection.
  • the node connections of a 64-node, 128-node, etc. computer system are similar. Eight nodes are located at each vertices of one cuboid, and each node is associated with three adjacent nodes. When there are eight integer multiples in the system, each of the eight nodes connected in the above manner can be regarded as a single point as a whole, and each point is connected by the above connection method. For example, 16 nodes are located at each vertex of two cuboids, and the same position of the two cuboids are connected again, and so on, to achieve a connection of 32 nodes and 64 nodes, which is not enumerated here.
  • the node with the most connections should be selected as possible to form a partition, for example, two directly connected nodes are created as one partition system, or Create 4 nodes that are connected as a ring to create a partition system.
  • two directly connected nodes are created as one partition system, or Create 4 nodes that are connected as a ring to create a partition system.
  • 8 nodes connected as a single cuboid can also be created as a partition system. This is because clock synchronization is only required for the same partition system.
  • the most connected nodes are combined into one partition system, which can ensure that the replacement path is found in the case that some nodes in the partition system are abnormal. Affect other partition systems.
  • the partition system when there is an abnormality in the node clock, the partition system should be created to ensure that at least one of the node clocks in the partition is normal. Otherwise, the partition system can only use the clocks of other partition systems.
  • a partition is created in a computer system, nodes belonging to the same partition system in the computer system are directly connected to each other Connected or indirectly connected, the intermediate node of the indirect connection and the two nodes of the indirect connection are located in the same partition system. For example, in an n X 8 node computer system, 8 nodes connected as a single cuboid are created as a partition system.
  • the partition system After the computer system provided by the above embodiment is partitioned, if the clock source is abnormal in a certain partition system, as long as the normal clock is present in the partition system, the operation of the partition system is not affected. If a certain clock channel of the partition system is abnormal, the downstream node of the clock channel can work normally, and only the other normal channels exist, and the partition system can still work normally. If a node in the partition system is abnormal in function, after the culling, the partition system can work normally as long as the clock between the remaining nodes can be routed. In this way, if there are too many abnormal nodes in the partition system, and the clock channels between the remaining nodes cannot be routed, the remaining nodes cannot form one partition, but several independent partitions can be re-established according to the partition conditions.
  • node 0 and node 1 are connected by a selection module, and represent a rectangular parallelepiped.
  • nodes 0 to 7 are located at respective vertices of the cube, on the front and rear surfaces of the cube, and on the lower surface. Sequentially connected as a ring, the four nodes on the upper surface are cross-connected, and are synchronized as a backup clock. For example, the front and back surfaces are sequentially connected, and the upper surface is cross-joined. This is because when multiple node errors occur, they are directly connected. The probability that several nodes appear at the same time will be relatively large. Therefore, some cross-connections are used in the clock connection. In general, the number of connected nodes does not change.
  • Figure 6 shows how to find the corresponding clock channel when a node clock is abnormal, so that the clock chain is normal.
  • the two nodes directly connected are selected to form a partition system.
  • the clocks of each node in the partition system are provided by the nodes in the partition to avoid interaction between the partition systems. If all nodes in a partitioned system have abnormal clocks, one node of the associated partitioning system can provide clocks for all nodes of the partitioned system, but the partitioned system clock is working normally and is controlled by another partition. In this case, the two nodes can be separated and re-partitioned, and the other connected nodes form two independent 2P partitions.
  • the clock configuration of the partition system is described below by taking the 8P partition system as an example.
  • the configuration process includes:
  • Step 701 Create a clock relationship connection table according to the clock connection manner.
  • each row of Table 1 is a layer, and each layer has a start point and an end point.
  • the connection between the start point and the end point is a two-way connection channel, which has a connection channel from the start point to the end point, and a connection channel from the end point to the start point.
  • node 0 is the starting point
  • node 1 is the ending point
  • the third line Node 1 is the starting point and node 0 is the ending point.
  • the subsequent steps are to simplify the direct or indirect multiple-connected nodes into one-way and non-repetitive connections, and select the two-way connection channels between directly connected nodes, and select one connection channel as the directly connected nodes.
  • the clock channel, another connection channel is used as a backup to reconfigure the partition system in case of clock anomalies, channel anomalies or node anomalies.
  • Step 702 Detect whether the clock of each node is normal.
  • Step 703 Select and turn on the clock source. Specifically, according to the order of the master node clock ⁇ the partition node clock ⁇ the other partition node clocks, a normal node clock is selected as the clock source from the master node clock, the partition node clock, and other partition node clocks, and the clock is turned on.
  • the clock of the master node is selected as the clock source. If there is no abnormality, the master node is selected as the clock. If an abnormality occurs, the node clock directly connected to the master node is selected as the clock source. Assume that in Figure 6, if an 8P partition is created and node 0 is the master node, but the clock of node 0 is abnormal, then any normal clock of the node connected to node 0, that is, node 1, node 2 or node 6, is selected as the clock source. .
  • Step 704 Add the node where the clock source is located to the clock relationship routing table, and set the node to be The starting point of the front layer.
  • the clock relationship routing table is similar to that in Table 1. The entry contains the start and end points. The difference is that when the clock relationship routing table starts, the start column and the end column are empty, and are added gradually by performing subsequent steps. Taking the computer system shown in FIG. 6 as an example, if the clock of the node 0 is the clock source, the node 0 is added to the starting point of the first layer in the clock relation routing table.
  • Step 705 Determine whether all nodes in the partition system have been added to the clock relationship routing table. If all the nodes have been added to the clock relationship routing table, complete the clock configuration. Otherwise, go to step 706.
  • Step 706 Determine whether nodes in the partition system directly connected to the starting point of the current layer are all in the clock relationship routing table. If it is already in the clock relationship routing table, step 709 is performed; otherwise, step 707 is performed.
  • Step 707 Directly connected to the starting point of the current layer and the clock channel is normal, and is not added to the node of the clock relation routing table, and select a node directly connected to the starting point of the current layer;
  • Step 708 Add the node selected in step 707 as the end point of the current layer, add the end point item of the current layer of the clock relation routing table, and open the clock channel of the current layer node to the node direction selected in step 707, and select The node is added to the new row of the clock relation routing table as the starting point of the next layer. Then, step 706 is performed again.
  • Step 709 Determine whether there is a node that is the same level as the starting point of the current layer, such as a node that is N-hopped from the clock source. If a node that is at the same level as the starting point of the current layer is not added to the clock relationship routing table, and the node is If the clock channel between the upper layer and the starting point of the upper layer is normal, step 712 is performed; otherwise, step 710 is performed.
  • Step 710 Determine whether there is a starting point of the next layer. If there is a starting point of the next layer, perform step 711; otherwise, complete the clock configuration.
  • Step 711 Set the first starting point of the next layer to the starting point of the current layer, and continue the steps.
  • Step 712 Select the node as the starting point of the current layer, and continue to step 705.
  • node 0 is the master node in the computer system, and the section The clock at point 0 is normal.
  • Table 2 Clock relationship routing table The remaining nodes that are not configured in the system are shown in the first mullion in Figure 8B.
  • connection channel between the node 1, the node 2, and the node 6 directly connected to the node 0 is normal. If the connection channel between the node 0 and the node 1, the node 2, and the node 6 are normal, the node 0 is opened or selected.
  • the connection channel in the direction of node 1, node 2, and node 6 serves as a clock channel between node 0 and node 1, node 2, and node 6, and adds node 1, node 2, and node 6 as the end point of the first layer to The clock relationship is in the routing table.
  • node 1, the node 2, and the node 6 are used as the starting point of the next layer, and it is determined whether the connection channel between the node 3 and the node 7 directly connected to the node 1 is normal, if between the node 1 and the node 3 and the node 7, If the connection channel is normal, the connection channel in the direction of node 1 to node 3 and node 7 is turned on or selected as the clock channel between node 1 and node 3 and node 7, and node 1 and node 3 and node 7 are used as a layer. That is, node 1 is the starting point of the layer, node 3 and node 7 are the end points of the layer, and are added to the clock relationship routing table; as shown in Table 4.
  • Node 7 determines whether the connection channel between the remaining nodes 5 directly connected to Node 2 is normal. If the connection channel between Node 2 and Node 5 is normal, the connection from Node 2 to Node 5 is made.
  • the channel acts as the clock channel between node 2 and node 5, and takes node 2 and node 5 as a layer, that is, the starting point of node 2 as a layer, and node 5 is the end point of the layer, added to the clock relationship routing table; Table 5 shows.
  • connection channel between the nodes 4 directly connected to the node 6 is normal. If the connection channel between the node 6 and the node 4 is normal, the connection channel in the direction from the node 6 to the node 4 is taken as the node 6 and the node 4.
  • the clock channel between them, and node 6 and node 4 as a layer, that is, the starting point of node 6 as a layer, node 4 is the end point of the layer, added to the clock relationship routing table, as shown in Table 6.
  • FIG. 8A The corresponding clock routing is shown in Figure 8A.
  • the table 1 can be connected according to the clock relationship, and node 3 is known.
  • Node 2 also backs up the connection channel, and node 1 is directly connected to node 3. Therefore, the connection channel in the direction of node 2 to node 3 can be opened or selected as the clock channel between node 2 and node 3, and node 1 is closed. To the connection channel in the direction of node 3, the connection channel from node 3 to node 1 is opened as the clock channel between node 3 and node 1, as shown in FIG.
  • node 1 node 3 can still be provided by the clock source. clock.
  • the remaining nodes that are not configured during the configuration process are shown in Figure 8D.
  • the connection channel is also backed up between the node 7 and the node 6, and the connection channel in the direction of the node 6 to the node 7 is opened as the clock channel between the node 6 and the node 7, as shown in FIG. 8C. As shown, node 7 can still get the clock provided by the clock source.
  • FIG. 9 is a schematic diagram of another clock connection of eight nodes in the computer system shown in FIG. 6. Its performance is also a rectangular parallelepiped. The up, down, left, and right are sequential rings, which do not cross.
  • the clock relationship connection table is shown in Table 7.
  • the foregoing device and method embodiments ensure clock synchronization of each node in the partition system by using a clock connection channel and a clock configuration method between nodes; and, when some nodes are abnormal in clock, they do not affect the system, that is, the system also If it is not up, if some nodes have abnormal clocks, you can also set up a partition to run the system normally.
  • the partition system is guaranteed to be unaffected.
  • the maximum degree is It ensures that the partition system composed of the remaining nodes is not affected.
  • a node cannot be set up when there are too many node anomalies, it is also possible to build several independent partition systems into the remaining nodes.
  • the clock connection between the nodes in the above apparatus and method embodiments can also be applied to the Quick Path Interconnect (QPI) connection of the partition, and similarly the connection between the nodes in other systems.
  • QPI Quick Path Interconnect

Description

计算机系统及其配置时钟的方法 技术领域
本发明涉及计算机系统技术， 尤其涉及一种计算机系统及用于实现计算 机系统同一分区系统的节点时钟同步的时钟配置方法。 背景技术
通常， 计算机系统， 如对计算以及容错性能要求较高的小型机， 由多个 不同的节点构成， 其中， 节点为硬分区的最小单元， 每个节点可以单独组成 一个分区， 也可以与其他节点互联组成一个分区， 每个分区上都可以运行独 立的操作系统具体地，计算机系统中几个独立的节点通过 CPU互联技术形成 一个整体即分区系统， 在该整体下可以运行一个操作系统， 该操作系统可以 访问任何该分区所属节点上的有效设备。
一个分区系统中的每个节点不仅需要时钟， 而且每个节点需要相同来源 的时钟。 这是因为时钟在数字电路中非常重要， 一旦没有了时钟， 数字逻辑 完全无法正常工作， 而分区系统中的各个节点若不使用相同来源的时钟， 则 整个分区也无法正常工作。
现有技术中， 分区系统采用单一式时钟同步方案实现分区系统内的时钟 同步。 即一个分区系统内只有一个时钟， 作为该分区系统内各节点的时钟源， 该时钟放在该分区系统的某一节点上， 或者与各节点分开， 单独设置。
现有技术存在的缺陷在于： 一个分区系统只有一个时钟可作为时钟源， 当该时钟异常时， 该分区系统无时钟源可用， 无法实现该分区系统的各节点 的时钟同步。 发明内容 本发明实施例的目的在于提出一种计算机系统及用于实现计算机系统同 一分区系统的节点时钟同步的时钟配置方法， 以在分区系统内的时钟源故障 时， 仍然能够实现计算机系统中同一分区系统的各节点时钟同步。
本发明实施例提供了一种计算机系统， 包括至少两个节点， 其中， 所述 至少两个节点均包括选择模块及 CPU, 所述选择模块的输入为本节点的时钟 及其他节点输出的时钟，输出端与所述 CPU及其他节点的选择模块的输入端 相连；
所述计算机系统还包括时钟控制模块， 所述时钟控制模块的输出端与所 述选择模块的控制端相连，用于控制所述至少两个节点的时钟为同一个时钟。
本发明实施例提供的计算机系统中， 每个节点的选择模块的输入端有本 节点的时钟源， 也有其他节点的时钟输出， 通过第三方如上述的时钟控制模 块来控制选择模块选择一个时钟输入作为该节点的时钟输入， 并且可以为其 他的节点提供时钟， 以保证每个节点使用同一个时钟源， 当多个节点的时钟 异常时， 只要该计算机系统还存在一个正常的时钟， 该计算机系统仍能正常 工作。
本发明实施例还提供了一种用于实现上述计算机系统中同一分区系统的 节点时钟同步的时钟配置方法， 包括：
选择一节点的时钟作为所属分区系统的时钟源的选择步骤；
开通所述节点作为起点， 与所述节点之间相连的节点作为终点的连接通 道作为所述节点及与之直接相连的节点之间的时钟通道的开通步骤；
判断作为终点的节点是否与所述分区系统中剩余的节点相连， 若是， 则 执行所述开通步骤； 否则， 完成所述分区系统的时钟配置。
本发明实施例提供的用于实现计算机系统同一分区系统的节点时钟同步 的时钟配置方法中， 利用计算机系统的同一分区系统中每个节点都有多个时 钟可选的结构特点， 通过为同一分区系统的相连两个节点选择一条连接通道 保证同一分区系统内的各节点的时钟源统一， 从而实现同一分区系统内的各 节点的时钟同步， 并且在时钟通道异常， 可选择其他连接通道， 仍然保证了 同一分区系统内的各节点的时钟源统一， 实现了同一分区系统内的各节点的 时钟同步。 附图说明
图 1为本发明实施例提供的计算机系统中节点的结构示意图；
图 2为本发明实施例提供的计算机系统中两个节点的时钟连接示意图； 图 3A为本发明实施例提供的计算机系统中四个节点的时钟连接示意图； 图 3B为图 3A的框架示意图；
图 4A为本发明实施例提供的计算机系统中 8个节点的时钟连接框架示 意图；
图 4B为本发明实施例提供的计算机系统中 16个节点的时钟连接框架示 意图；
图 5为本发明实施例提供的计算机系统中 32个节点的时钟连接框架示意 图；
图 6为本发明实施例提供的 8节点计算机系统的结构示意图；
图 7为本发明实施例提供的用于实现上述计算机系统中同一分区系统的 节点时钟同步的时钟配置方法流程图；
图 8A为图 7配置完时钟后的时钟路径图；
图 8B为图 7配置过程中未被配置的剩余节点示意图；
图 8C为图 6所示计算机系统中节点 0与节点 1之间时钟通道异常后的替 换时钟路径图；
图 8D为图 8C形成过程中未被配置的剩余节点示意图；
图 9为图 6所示计算机系统中 8个节点的另外一种时钟连接示意图。 具体实施方式 为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本发 明作进一步地详细描述。
本发明实施例提供的计算机系统， 包括至少两个节点， 其中， 如图 1 所 示， 所述至少两个节点均包括选 4奪模块 11及 CPU 12, 所述选择模块 11的输 入 Input 1 Input N为本节点的时钟 src及其他节点输出的时钟， 输出端
( output )与所述 CPU 12及其他节点的选择模块的输入端相连；
所述计算机系统还包括时钟控制模块 13 ,所述时钟控制模块 13的输出端 与所述选择模块的控制端相连， 用于控制所述至少两个节点的选择模块输出 端输出的时钟为同一个时钟。
上述技术方案中， 每个节点的选择模块的输入端有本节点的时钟源， 也 有其他节点的时钟输出， 通过第三方如上述的时钟控制模块来控制选择模块 选择一个时钟输入作为该节点的时钟输入，并且可以为其他的节点提供时钟， 以保证每个节点使用同一个时钟源， 当多个节点的时钟异常时， 只要该计算 机系统还存在一个正常的时钟， 该计算机系统仍能正常工作。
当计算机系统中有两个节点时， 两节点直接相连。 如图 2所示， 节点 21 中选择模块 211的输出端， 与节点 22中选择模块 221的输入端直接连接， 节 点 22中选择模块 221的输出端与节点 21中选择模块 211的输入端相连。 并 且， 节点 21及节点 22中， 选择模块的另一个输入为本节点的时钟 src。 节点 21中选择模块 211的输出端与本节点的 CPU 212相连， 节点 22中选择模块 221的输出端与本节点的 CPU 222相连。 节点 21与节点 22为双向连接， 使 用时可关闭一条连接， 当开启的连接异常时， 启用关闭的连接。
选择模块 211及选择模块 221的控制端均由时钟控制模块 23控制输出。 换句话说 , 每个节点中选择模块的输入为本节点的时钟与其他节点的时钟 , 在时钟控制模块 23的控制下，将一个节点的时钟 src作为共同的时钟源， 从 而保证每个节点的时钟同步。
当计算机系统中有四个节点时， 连接方式与图 2类似， 所述四个节点通 过选择模块连接为环形， 每个节点的选择模块的输入为本节点的时钟及相连 的两个节点的选择模块的输出。 如图 3A、 图 3B所示， 计算机系统中共有节 点 31、 节点 32、 节点 33及节点 34共四个节点， 四个节点的选择模块依次相 连为一个环形， 如图 3B所示。 具体地， 节点 31中， 选择模块 311的输出端 与节点 32中选择模块 321及节点 34中选择模块 341的输入端相连， 并与本 节点的 CPU 312相连； 节点 32中， 选择模块 321的输出端与节点 31中选择 模块 311及节点 33 中选择模块 331的输入端相连， 并与本节点的 CPU 332 相连； 节点 33中， 选择模块 331的输出端与节点 32中选择模块 321及节点 34中选择模块 341的输入端相连， 并与本节点的 CPU 322相连； 节点 34中， 选择模块 341的输出端与节点 31中选择模块 311及节点 33 中选择模块 331 的输入端相连， 并与本节点的 CPU 342相连。 且所有选 4奪模块的控制端均与 时钟控制模块 35相连， 在时钟控制模块 35的控制下， 所有节点选择同一个 节点的时钟源 src作为共同的时钟源。 同样， 图 3A中， 任意两个节点之间的 连接均为双向连接， 即相连的两个节点之间有两个连接通道也即时钟通道， 使用时需关闭未启用的连接通道，。 当使用的时钟通路异常时， 则根据时钟通 道正常情况重新选择时钟通道。
当计算机系统中有 8个节点时， 8个节点位于一个长方体的各个顶点处， 所述长方体各个表面内的 4个节点通过选择模块交叉连接或通过选择模块两 两相邻连接， 且每个节点与三个节点通过选择模块连接。 如图 4A所示， 长 方体的各个表面的 4个节点通过选择模块顺次连接为一个环形， 其中， 环形 的连接与图 3A类似， 每个节点均与三个节点通过选择模块相连， 任意两个 节点之间的连接均为双向连接即相连的两个节点之间有两条连接通道也即时 钟通道， 使用时可关闭其中一条连接通道， 使用另一条连接通道。 当使用的 连接通道异常时， 启用关闭的连接通道。 得到的长方体连接方式与图 3A 的 不同之处在于， 每个节点与三个节点相连， 具体地， 每个节点的选择模块的 输入为本节点的时钟及相连的三个节点的选择模块的输出。 当计算机系统中有 n x 8个节点时， 每 8个节点位于一个长方体的各个顶 点处， 所述长方体各个表面内的 4个节点通过选择模块交叉连接或通过选择 模块顺次连接， 且每个节点与 3+n个节点通过选择模块连接， 长方体的连接 与图 4A类似， 每个所述长方体相同位置上的节点通过选择模块相连， 每个 节点的选择模块的输入为本节点的时钟与相连的 3+n个节点的选择模块的输 出， 其中， n 为自然数。 同样， 任意两个节点之间的连接均为双向连接即相 连的两个节点之间有两条连接通道也即时钟通道， 使用时可关闭其中一条连 接通道， 使用另一条连接通道。 当使用的连接异常时， 启用关闭的连接通道。
例如， 当计算机系统中有 16个节点时， 连接后得到如图 4B所示的结构， 当计算机系统中有 32个节点时， 连接后得到如图 5所示的结构。 64节点、 128节点等等计算机系统的节点连接类似。 8个节点位于一个长方体的各个顶 点处， 每个节点与相邻的 3个节点相联。 当系统中有 8的整数倍个节点时， 以上述方式连接的各个 8个节点整体又可以分别看成一个点， 再利用上述连 接方式将各个点连接。 如， 16个节点位于两个长方体的各个顶点处， 两个长 方体的同一个位置点再相联， 以此类推， 实现 32个节点、 64个节点的联接， 这里不——列举。
对上述实施例提供的计算机系统进行分区时， 为了保证分区系统容错率 达到最高， 应尽可能选择连接最多的几个节点组成一个分区， 如将直接相连 的两个节点创建为一个分区系统， 或将连接为一个环形的 4个节点创建为一 个分区系统。如对于 n 8节点计算机系统还可将连接为一个长方体的 8个节 点创建为一个分区系统。 这是因为时钟同步仅仅是对同一分区系统有要求， 将连接最多的几个节点组成一个分区系统， 可以最大程度上保证在该分区系 统内某些节点异常的情况下， 找到替换路径， 且不影响其他分区系统。
并且， 当节点时钟存在异常， 创建分区系统时应保证分区内的节点时钟 至少有一个正常， 否则该分区系统只能使用其他分区系统的时钟。 计算机系 统中创建分区后， 所述计算机系统中属于同一个分区系统的节点相互之间直 接连接或间接连接， 所述间接连接的中间节点与所述间接连接的两端节点位 于同一个分区系统内。 例如对于 n X 8节点计算机系统中， 连接为一个长方体 的 8个节点创建为一个分区系统。
上述实施例提供的计算机系统进行分区后， 某一分区系统内若时钟源异 常， 只要该分区系统内存在正常时钟， 则该分区系统的运行不受影响。 若该 分区系统的某一时钟通道异常， 该时钟通道的下游节点可以正常工作， 则只 要存在其他正常通道， 该分区系统仍然可以正常工作。 若该分区系统内某一 节点功能异常， 剔除后， 只要剩余节点间的时钟可以路由互联， 则该分区系 统还可以正常工作。 这样， 若该分区系统内节点异常个数过多， 造成剩余节 点间时钟通道无法路由互联， 则剩余节点无法组建一个分区， 但可以根据分 区情况重新组建几个独立的分区。
下面以 8节点小机型为例做进一步详细说明。
如图 6所示， 节点 0、 节点 1 节点 7通过选择模块连接， 表现为一 个长方体， 或者说， 节点 0〜节点 7位于立方体的各个顶点处， 立方体的前后 表面及下表面上， 4节点各顺次连接为一个环形， 上表面的 4个节点交叉相 连， 作为备份时钟同步路由， 如： 前后表面顺次联接， 上表面交叉联接， 这 是因为当出现多个节点错误时， 直接相联的几个节点同时出现的概率会相对 较大， 因此时钟连接中采用一些交叉联接的方式， 总体上每个节点的相联个 数都不会变。 通过图 6可以直观的说明某个节点时钟异常时， 如何找到相应 的时钟通道， 从而保证时钟链正常。
根据图 6所示的连接关系， 生成如下表 1所示的时钟关系路由表。
表 1 时钟关系连接表 起点 终 ^> 占、、
0 1、 2、 6 2 0、 3、 5
3 1、 2、 4
4 3、 5、 6
5 2、 4、 7
6 0、 4、 7
7 1、 5、 6
当任意有限个时钟及时钟通道异常时 , 都可以从尝试从时钟关系路由表 中找到其他替代的时钟通道， 用找到的替代时钟通道替代异常的时钟通道。 另外时钟选择时， 不仅需要选择是否使用该节点的时钟， 还需要选择启用的 时钟通路， 保证所有节点的时钟来源唯一。
由于不是任意两个节点之间都存在时钟连接， 部分时钟通道需要通过其 他节点路由形成通道， 为了减少出错概率及提高设置速度， 在创建分区时， 按照上述分区方式进行分区。
假设创建 2P分区系统， 则选择直接联接的 2个节点组成一个分区系统。 一般情况下， 分区系统中各节点时钟都由分区内的节点提供， 以免分区系统 之间相互影响。 若某分区系统内的所有节点时钟都异常， 此时可以由相联分 区系统的一个节点为该分区系统的所有节点提供时钟， 但该分区系统时钟是 否正常工作， 受控于另一分区。 这种情况下， 可以将这两节点分开， 进行重 新分区， 与其他相联的节点分别组成两个独立的 2P分区。
假设创建 4P分区系统， 正常情况下， 任意选择上下或前后相互连接构成 环形的 4个节点组建一个分区系统， 此时容错概率最高。 但若创建分区时， 多个节点时钟已存在异常， 则应该根据上述分区原则合理创建分区， 保证所 有分区系统可以正常工作。
假设创建 6P分区系统， 则按照创建 4P分区的方式先选择 4个节点， 然 后再任意选择相邻的可以组成 2P的两个节点，即直接相连的两个节点一起创 建为 6P分区系统。
假设创建 8P分区系统， 则该计算机系统中的所有节点可以组成一个 8P 分区系统。
下面以 8P分区系统为例对分区系统的时钟配置进行说明。
如图 7所示， 配置流程包括：
步骤 701、 根据时钟联接方式创建时钟关系连接表， 如表 1 所示， 表 1 的每一行都即一层， 每层均有起点和终点。 起点与终点之间的连接为双向连 接通道， 既有起点到终点的连接通道， 也有终点到起点的连接通道， 如在表 1的第 2行节点 0为起点， 节点 1为终点， 第 3行节点 1为起点， 节点 0为 终点。 后续的步骤就是对直接或间接的多次连接的节点简化为单向且不重复 地连接， 且对直接相连的节点之间的双向连接通道进行选择， 选择一条连接 通道作为直接相连的节点之间的时钟通道， 另一条连接通道作为备份， 以在 时钟异常、 通道异常或节点异常的情况下重新对分区系统进行时钟配置。
步骤 702、 检测各节点时钟是否正常；
步骤 703、 选择并开启时钟源。 具体地， 按照主节点时钟→本分区节点时 钟→其他分区节点时钟的顺序， 从主节点时钟、 本分区节点时钟、 其他分区 节点时钟中选择一个正常的节点时钟作为时钟源， 并开启该时钟。
一般选择主节点的时钟为时钟源， 若没有异常， 则选择主节点为时钟， 若出现异常， 则选择同一分区与主节点直接相联的节点时钟作为时钟源。 假 设图 6中， 若创建 8P分区， 节点 0为主节点， 但节点 0的时钟异常， 则选择 与节点 0相连的节点即节点 1、 节点 2或节点 6的时钟的任意一个正常时钟 作为时钟源。
步骤 704、将时钟源所在节点添加到时钟关系路由表中，设置该节点为当 前层起点。 时钟关系路由表与表 1类似， 表项包含起点和终点， 不同之处在 于时钟关系路由表开始时， 起点列和终点列均为空， 通过执行后续步骤逐渐 添加。 以图 6所示计算机系统为例， 若节点 0的时钟为时钟源， 则将节点 0 添加到时钟关系路由表中第一层的起点项。
步骤 705、 判断该分区系统中所有节点是否都已添加到时钟关系路由表 中。 若所有节点已添加到时钟关系路由表中， 完成时钟配置， 否则， 执行步 骤 706。
步骤 706、判断该分区系统中与当前层起点直接相联的节点是否都已在时 钟关系路由表中。 若已在时钟关系路由表中， 则执行步骤 709, 否则， 执行 步骤 707。
步骤 707、从与当前层起点直接相连且时钟通道正常， 并未被添加到时钟 关系路由表的节点中， 选择一个与当前层起点直接相连的节点；
步骤 708、将步骤 707中选择的节点作为当前层的终点， 添加到时钟关系 路由表的当前层的终点项中， 开启当前层节点到步骤 707中选择的节点方向 上的时钟通道， 并将选择的节点作为下一层起点添加到时钟关系路由表的新 一行表项中。 然后， 再次执行步骤 706。
步骤 709、判断是否还存在与当前层起点同级的节点如与时钟源之间均为 N跳的节点， 若存在与当前层起点同级的节点未加入到时钟关系路由表， 且 该节点作为上一层终点时与该上一层起点之间的时钟通道正常， 则执行步骤 712, 否则， 执行步骤 710。
步骤 710、 判断是否存在下一层起点， 若存在下一层起点， 则执行步骤 711 , 否则完成时钟配置。
步骤 711、将存在的第一个下一层起点设置为当前层起点， 继续执行步骤
705„
步骤 712、 选择该节点为当前层起点， 继续执行步骤 705。
以图 6所示计算机系统为例， 假设计算机系统中节点 0为主节点， 且节 点 0的时钟正常。
则选择节点 0的时钟为时钟源， 将节点 0添加到时钟关系路由表中。 如 表 2所示。
表 2 时钟关系路由表
Figure imgf000013_0001
系统中未被配置的剩余节点如图 8B中的第一个竖框所示。
然后判断与节点 0直接相连的节点 1、节点 2及节点 6之间的连接通道是 否正常， 若节点 0与节点 1、 节点 2及节点 6之间的连接通道均正常， 则开 通或选择节点 0到节点 1、 节点 2及节点 6方向上的连接通道作为节点 0与 节点 1、 节点 2及节点 6之间的时钟通道， 并将节点 1、 节点 2及节点 6作为 第一层的终点添加到时钟关系路由表中。
表 3
Figure imgf000013_0002
系统中未被配置的剩余节点如图 8B中的第二个竖框所示。
进一步地， 将节点 1、 节点 2及节点 6作为下一层起点， 判断与节点 1 直接连接的节点 3、 节点 7之间的连接通道是否正常， 若节点 1与节点 3、 节 点 7之间的连接通道均正常， 则开通或选择节点 1到节点 3、 节点 7方向上 的连接通道作为节点 1与节点 3、 节点 7之间的时钟通道， 并将节点 1及节 点 3、 节点 7作为一层即以节点 1为一层的起点， 节点 3、 节点 7为该层的终 点， 添加到时钟关系路由表中； 如表 4所示。
表 4
起点 终点 节点 0 节点 1、 节点 2、 节点 6
节点 1 节点 3、 节点 7 判断剩余的与节点 2直接连接的节点 5之间的连接通道是否正常， 若节 点 2与节点 5之间的连接通道正常， 则将节点 2到节点 5方向上的连接通道 作为节点 2与节点 5之间的时钟通道， 并将节 2及节点 5作为一层即以节点 2为一层的起点， 节点 5 为一层的终点， 添加到时钟关系路由表中； 如表 5 所示。
表 5
Figure imgf000014_0001
判断剩余的于节点 6直接连接的节点 4之间的连接通道是否正常， 若节 点 6与节点 4之间的连接通道正常， 则将节点 6到节点 4方向上的连接通道 作为节点 6与节点 4之间的时钟通道， 并将节点 6及节点 4作为一层即以节 点 6为一层的起点， 节点 4为该层的终点， 添加到时钟关系路由表中， 如表 6所示。
表 6
Figure imgf000014_0002
相应的时钟路由如图 8A所示。 当配置的节点 0与节点 1之间的时钟通道发生异常， 则节点 1、 节点 3 及节点 7将无法得到时钟源提供的时钟， 此时， 可根据时钟关系连接表表 1 , 获知节点 3与节点 2之间还备份有连接通道， 而节点 1与节点 3直接相连， 因此可开通或选择节点 2到节点 3方向上的连接通道作为节点 2与节点 3之 间的时钟通道， 并关闭节点 1到节点 3方向上的连接通道， 开通节点 3到节 点 1上的连接通道作为节点 3与节点 1之间的时钟通道，如图 8C所示，从而 节点 1、 节点 3仍可得到时钟源提供的时钟。 配置过程中未被配置的剩余节 点如图 8D所示。 并且， 根据时钟连接表表 1还可获知节点 7与节点 6之间 还备份有连接通道， 开通节点 6到节点 7方向上的连接通道作为节点 6与节 点 7之间的时钟通道， 如图 8C所示， 这样， 节点 7仍可得到时钟源提供的时 钟。
图 9为图 6所示计算机系统中 8个节点的另外一种时钟连接示意图。 其 表现也是一个长方体， 上下前后左右都为顺序环， 不交叉， 其时钟关系连接 表如表 7所示。
表 7
Figure imgf000015_0001
上述装置及方法实施例通过节点之间的时钟连接通道及时钟配置方法， 保证了分区系统内各节点的时钟同步； 并且， 当部分节点时钟异常时， 不会 对系统有所影响， 即系统还没起来时， 若部分节点时钟异常时， 也可以组建 一个分区， 正常的把系统运行起来； 当部分节点时钟通道异常， 最大程度地 保证了分区系统不受影响； 当部分节点异常时， 最大程度地保证了剩余节点 所组成的分区系统不受影响； 当节点异常数过多时无法组建一个分区时， 还 可以将剩余节点组建几个独立的分区系统。
上述装置及方法实施例中的节点之间的时钟连接方式也可应用于分区的 快速通道互联（ Quick Path Interconnect, QPI )联接， 及类似地其他系统中节 点之间的联接。
本领域普通技术人员可以理解： 实现上述方法实施例的全部或部分步骤 可以通过程序指令相关的硬件来完成， 前述的程序可以存储于一计算机可读 取存储介质中， 该程序在执行时， 执行包括上述方法实施例的步骤； 而前述 的存储介质包括： ROM、 RAM, 磁碟或者光盘等各种可以存储程序代码的介 质。
最后应说明的是： 以上实施例仅用以说明本发明的技术方案， 而非对其 限制； 尽管参照前述实施例对本发明进行了详细的说明， 本领域的普通技术 人员应当理解： 其依然可以对前述各实施例所记载的技术方案进行修改， 或 者对其中部分技术特征进行等同替换； 而这些修改或者替换， 并不使相应技 术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims

权 利 要求 书
1、 一种计算机系统， 包括至少两个节点， 其特征在于， 所述至少两个节 点均包括选择模块及 CPU, 所述选择模块的输入为本节点的时钟及其他节点 输出的时钟， 输出端与所述 CPU及其他节点的选择模块的输入端相连；
所述计算机系统还包括时钟控制模块， 所述时钟控制模块的输出端与所 述选择模块的控制端相连，用于控制所述至少两个节点的时钟为同一个时钟。
2、 根据权利要求 1所述的计算机系统， 其特征在于， 所述至少两个节点 为四个节点， 所述四个节点通过选择模块连接为环形， 每个节点的选择模块 的输入为本节点的时钟及相连的两个节点的选择模块的输出。
3、 根据权利要求 1所述的计算机系统， 其特征在于， 所述至少两个节点 为 8个节点， 位于一个长方体的各个顶点处， 所述长方体各个表面内的 4个 节点通过选择模块交叉连接或通过选择模块两两相邻连接， 且每个节点与三 个节点通过选择模块连接， 每一节点的选择模块的输入为该节点的时钟及相 连的三个节点的选择模块的输出。
4、 根据权利要求 1所述的计算机系统， 其特征在于， 所述至少两个节点 为 n x 8个节点， 其中， 每 8个节点位于一个长方体的各个顶点处， 所述长方 体各个表面内的 4个节点通过选择模块交叉连接或通过选择模块顺次连接， 且每个节点与 3+n个节点通过选 4奪模块连接， 每个所述长方体相同位置上的 节点通过选择模块相连， 每个节点的选择模块的输入为本节点的时钟与相连 的 3+n个节点的选择模块的输出， 其中， n为大于 0的自然数。
5、 根据权利要求 2-4任一项所述的计算机系统， 其特征在于， 所述计算 机系统中属于同一个分区系统的节点相互之间直接连接或间接连接， 所述间 接连接的中间节点与所述间接连接的两端节点位于同一个分区系统内。
6、 根据权利要求 1-4任一项所述的计算机系统， 其特征在于， 所述选择 模块的输出端与其他节点的选择模块的输入端的连接通过 CPU互联线缆实 现。
7、 一种用于实现权利要求 1-6任一项所述的计算机系统中同一分区系统 的节点时钟同步的时钟配置方法， 其特征在于， 包括：
选择一节点的时钟作为所属分区系统的时钟源的选择步骤；
开通所述节点作为起点， 与所述节点之间相连的节点作为终点的连接通 道作为所述节点及与之直接相连的节点之间的时钟通道的开通步骤；
判断作为终点的节点是否与所述分区系统中剩余的节点相连， 若是， 则 执行所述开通步骤； 否则， 完成所述分区系统的时钟配置。
8、 根据权利要求 7所述的时钟配置方法， 其特征在于， 还包括： 根据所 述计算机系统中节点之间的时钟连接关系建立时钟关系连接表；
所述开通步骤根据所述时钟关系连接表得到节点之间的连接关系。
9、 根据权利要求 7或 8所述的时钟配置方法， 其特征在于， 执行所述开 通步骤时或之后， 还包括：
建立时钟关系路由表， 将所述起点及终点添加到所述时钟关系路由表中。
10、 根据权利要求 9所述的时钟配置方法， 其特征在于， 根据所述时钟 关系路由表， 重新开通由于时钟异常、 时钟通道异常或节点异常导致时钟通 道断开的节点与时钟源所在节点之间的时钟通道。
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